mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
cmsis/TARGET_CORTEX_M/core_cm33.h@181:96ed750bd169, 2018-01-17 (annotated)
- Committer:
- Anna Bridge
- Date:
- Wed Jan 17 15:23:54 2018 +0000
- Revision:
- 181:96ed750bd169
mbed-dev libray. Release version 158
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Anna Bridge |
181:96ed750bd169 | 1 | /**************************************************************************//** |
Anna Bridge |
181:96ed750bd169 | 2 | * @file core_cm33.h |
Anna Bridge |
181:96ed750bd169 | 3 | * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File |
Anna Bridge |
181:96ed750bd169 | 4 | * @version V5.0.3 |
Anna Bridge |
181:96ed750bd169 | 5 | * @date 09. August 2017 |
Anna Bridge |
181:96ed750bd169 | 6 | ******************************************************************************/ |
Anna Bridge |
181:96ed750bd169 | 7 | /* |
Anna Bridge |
181:96ed750bd169 | 8 | * Copyright (c) 2009-2017 ARM Limited. All rights reserved. |
Anna Bridge |
181:96ed750bd169 | 9 | * |
Anna Bridge |
181:96ed750bd169 | 10 | * SPDX-License-Identifier: Apache-2.0 |
Anna Bridge |
181:96ed750bd169 | 11 | * |
Anna Bridge |
181:96ed750bd169 | 12 | * Licensed under the Apache License, Version 2.0 (the License); you may |
Anna Bridge |
181:96ed750bd169 | 13 | * not use this file except in compliance with the License. |
Anna Bridge |
181:96ed750bd169 | 14 | * You may obtain a copy of the License at |
Anna Bridge |
181:96ed750bd169 | 15 | * |
Anna Bridge |
181:96ed750bd169 | 16 | * www.apache.org/licenses/LICENSE-2.0 |
Anna Bridge |
181:96ed750bd169 | 17 | * |
Anna Bridge |
181:96ed750bd169 | 18 | * Unless required by applicable law or agreed to in writing, software |
Anna Bridge |
181:96ed750bd169 | 19 | * distributed under the License is distributed on an AS IS BASIS, WITHOUT |
Anna Bridge |
181:96ed750bd169 | 20 | * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
Anna Bridge |
181:96ed750bd169 | 21 | * See the License for the specific language governing permissions and |
Anna Bridge |
181:96ed750bd169 | 22 | * limitations under the License. |
Anna Bridge |
181:96ed750bd169 | 23 | */ |
Anna Bridge |
181:96ed750bd169 | 24 | |
Anna Bridge |
181:96ed750bd169 | 25 | #if defined ( __ICCARM__ ) |
Anna Bridge |
181:96ed750bd169 | 26 | #pragma system_include /* treat file as system include file for MISRA check */ |
Anna Bridge |
181:96ed750bd169 | 27 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
Anna Bridge |
181:96ed750bd169 | 28 | #pragma clang system_header /* treat file as system include file */ |
Anna Bridge |
181:96ed750bd169 | 29 | #endif |
Anna Bridge |
181:96ed750bd169 | 30 | |
Anna Bridge |
181:96ed750bd169 | 31 | #ifndef __CORE_CM33_H_GENERIC |
Anna Bridge |
181:96ed750bd169 | 32 | #define __CORE_CM33_H_GENERIC |
Anna Bridge |
181:96ed750bd169 | 33 | |
Anna Bridge |
181:96ed750bd169 | 34 | #include <stdint.h> |
Anna Bridge |
181:96ed750bd169 | 35 | |
Anna Bridge |
181:96ed750bd169 | 36 | #ifdef __cplusplus |
Anna Bridge |
181:96ed750bd169 | 37 | extern "C" { |
Anna Bridge |
181:96ed750bd169 | 38 | #endif |
Anna Bridge |
181:96ed750bd169 | 39 | |
Anna Bridge |
181:96ed750bd169 | 40 | /** |
Anna Bridge |
181:96ed750bd169 | 41 | \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
Anna Bridge |
181:96ed750bd169 | 42 | CMSIS violates the following MISRA-C:2004 rules: |
Anna Bridge |
181:96ed750bd169 | 43 | |
Anna Bridge |
181:96ed750bd169 | 44 | \li Required Rule 8.5, object/function definition in header file.<br> |
Anna Bridge |
181:96ed750bd169 | 45 | Function definitions in header files are used to allow 'inlining'. |
Anna Bridge |
181:96ed750bd169 | 46 | |
Anna Bridge |
181:96ed750bd169 | 47 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
Anna Bridge |
181:96ed750bd169 | 48 | Unions are used for effective representation of core registers. |
Anna Bridge |
181:96ed750bd169 | 49 | |
Anna Bridge |
181:96ed750bd169 | 50 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
Anna Bridge |
181:96ed750bd169 | 51 | Function-like macros are used to allow more efficient code. |
Anna Bridge |
181:96ed750bd169 | 52 | */ |
Anna Bridge |
181:96ed750bd169 | 53 | |
Anna Bridge |
181:96ed750bd169 | 54 | |
Anna Bridge |
181:96ed750bd169 | 55 | /******************************************************************************* |
Anna Bridge |
181:96ed750bd169 | 56 | * CMSIS definitions |
Anna Bridge |
181:96ed750bd169 | 57 | ******************************************************************************/ |
Anna Bridge |
181:96ed750bd169 | 58 | /** |
Anna Bridge |
181:96ed750bd169 | 59 | \ingroup Cortex_M33 |
Anna Bridge |
181:96ed750bd169 | 60 | @{ |
Anna Bridge |
181:96ed750bd169 | 61 | */ |
Anna Bridge |
181:96ed750bd169 | 62 | |
Anna Bridge |
181:96ed750bd169 | 63 | #include "cmsis_version.h" |
Anna Bridge |
181:96ed750bd169 | 64 | |
Anna Bridge |
181:96ed750bd169 | 65 | /* CMSIS CM33 definitions */ |
Anna Bridge |
181:96ed750bd169 | 66 | #define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ |
Anna Bridge |
181:96ed750bd169 | 67 | #define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ |
Anna Bridge |
181:96ed750bd169 | 68 | #define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ |
Anna Bridge |
181:96ed750bd169 | 69 | __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ |
Anna Bridge |
181:96ed750bd169 | 70 | |
Anna Bridge |
181:96ed750bd169 | 71 | #define __CORTEX_M (33U) /*!< Cortex-M Core */ |
Anna Bridge |
181:96ed750bd169 | 72 | |
Anna Bridge |
181:96ed750bd169 | 73 | /** __FPU_USED indicates whether an FPU is used or not. |
Anna Bridge |
181:96ed750bd169 | 74 | For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. |
Anna Bridge |
181:96ed750bd169 | 75 | */ |
Anna Bridge |
181:96ed750bd169 | 76 | #if defined ( __CC_ARM ) |
Anna Bridge |
181:96ed750bd169 | 77 | #if defined __TARGET_FPU_VFP |
Anna Bridge |
181:96ed750bd169 | 78 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 79 | #define __FPU_USED 1U |
Anna Bridge |
181:96ed750bd169 | 80 | #else |
Anna Bridge |
181:96ed750bd169 | 81 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 82 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 83 | #endif |
Anna Bridge |
181:96ed750bd169 | 84 | #else |
Anna Bridge |
181:96ed750bd169 | 85 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 86 | #endif |
Anna Bridge |
181:96ed750bd169 | 87 | |
Anna Bridge |
181:96ed750bd169 | 88 | #if defined(__ARM_FEATURE_DSP) |
Anna Bridge |
181:96ed750bd169 | 89 | #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 90 | #define __DSP_USED 1U |
Anna Bridge |
181:96ed750bd169 | 91 | #else |
Anna Bridge |
181:96ed750bd169 | 92 | #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 93 | #define __DSP_USED 0U |
Anna Bridge |
181:96ed750bd169 | 94 | #endif |
Anna Bridge |
181:96ed750bd169 | 95 | #else |
Anna Bridge |
181:96ed750bd169 | 96 | #define __DSP_USED 0U |
Anna Bridge |
181:96ed750bd169 | 97 | #endif |
Anna Bridge |
181:96ed750bd169 | 98 | |
Anna Bridge |
181:96ed750bd169 | 99 | #elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
Anna Bridge |
181:96ed750bd169 | 100 | #if defined __ARM_PCS_VFP |
Anna Bridge |
181:96ed750bd169 | 101 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 102 | #define __FPU_USED 1U |
Anna Bridge |
181:96ed750bd169 | 103 | #else |
Anna Bridge |
181:96ed750bd169 | 104 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 105 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 106 | #endif |
Anna Bridge |
181:96ed750bd169 | 107 | #else |
Anna Bridge |
181:96ed750bd169 | 108 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 109 | #endif |
Anna Bridge |
181:96ed750bd169 | 110 | |
Anna Bridge |
181:96ed750bd169 | 111 | #if defined(__ARM_FEATURE_DSP) |
Anna Bridge |
181:96ed750bd169 | 112 | #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 113 | #define __DSP_USED 1U |
Anna Bridge |
181:96ed750bd169 | 114 | #else |
Anna Bridge |
181:96ed750bd169 | 115 | #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 116 | #define __DSP_USED 0U |
Anna Bridge |
181:96ed750bd169 | 117 | #endif |
Anna Bridge |
181:96ed750bd169 | 118 | #else |
Anna Bridge |
181:96ed750bd169 | 119 | #define __DSP_USED 0U |
Anna Bridge |
181:96ed750bd169 | 120 | #endif |
Anna Bridge |
181:96ed750bd169 | 121 | |
Anna Bridge |
181:96ed750bd169 | 122 | #elif defined ( __GNUC__ ) |
Anna Bridge |
181:96ed750bd169 | 123 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
Anna Bridge |
181:96ed750bd169 | 124 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 125 | #define __FPU_USED 1U |
Anna Bridge |
181:96ed750bd169 | 126 | #else |
Anna Bridge |
181:96ed750bd169 | 127 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 128 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 129 | #endif |
Anna Bridge |
181:96ed750bd169 | 130 | #else |
Anna Bridge |
181:96ed750bd169 | 131 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 132 | #endif |
Anna Bridge |
181:96ed750bd169 | 133 | |
Anna Bridge |
181:96ed750bd169 | 134 | #if defined(__ARM_FEATURE_DSP) |
Anna Bridge |
181:96ed750bd169 | 135 | #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 136 | #define __DSP_USED 1U |
Anna Bridge |
181:96ed750bd169 | 137 | #else |
Anna Bridge |
181:96ed750bd169 | 138 | #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 139 | #define __DSP_USED 0U |
Anna Bridge |
181:96ed750bd169 | 140 | #endif |
Anna Bridge |
181:96ed750bd169 | 141 | #else |
Anna Bridge |
181:96ed750bd169 | 142 | #define __DSP_USED 0U |
Anna Bridge |
181:96ed750bd169 | 143 | #endif |
Anna Bridge |
181:96ed750bd169 | 144 | |
Anna Bridge |
181:96ed750bd169 | 145 | #elif defined ( __ICCARM__ ) |
Anna Bridge |
181:96ed750bd169 | 146 | #if defined __ARMVFP__ |
Anna Bridge |
181:96ed750bd169 | 147 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 148 | #define __FPU_USED 1U |
Anna Bridge |
181:96ed750bd169 | 149 | #else |
Anna Bridge |
181:96ed750bd169 | 150 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 151 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 152 | #endif |
Anna Bridge |
181:96ed750bd169 | 153 | #else |
Anna Bridge |
181:96ed750bd169 | 154 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 155 | #endif |
Anna Bridge |
181:96ed750bd169 | 156 | |
Anna Bridge |
181:96ed750bd169 | 157 | #if defined(__ARM_FEATURE_DSP) |
Anna Bridge |
181:96ed750bd169 | 158 | #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 159 | #define __DSP_USED 1U |
Anna Bridge |
181:96ed750bd169 | 160 | #else |
Anna Bridge |
181:96ed750bd169 | 161 | #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 162 | #define __DSP_USED 0U |
Anna Bridge |
181:96ed750bd169 | 163 | #endif |
Anna Bridge |
181:96ed750bd169 | 164 | #else |
Anna Bridge |
181:96ed750bd169 | 165 | #define __DSP_USED 0U |
Anna Bridge |
181:96ed750bd169 | 166 | #endif |
Anna Bridge |
181:96ed750bd169 | 167 | |
Anna Bridge |
181:96ed750bd169 | 168 | #elif defined ( __TI_ARM__ ) |
Anna Bridge |
181:96ed750bd169 | 169 | #if defined __TI_VFP_SUPPORT__ |
Anna Bridge |
181:96ed750bd169 | 170 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 171 | #define __FPU_USED 1U |
Anna Bridge |
181:96ed750bd169 | 172 | #else |
Anna Bridge |
181:96ed750bd169 | 173 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 174 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 175 | #endif |
Anna Bridge |
181:96ed750bd169 | 176 | #else |
Anna Bridge |
181:96ed750bd169 | 177 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 178 | #endif |
Anna Bridge |
181:96ed750bd169 | 179 | |
Anna Bridge |
181:96ed750bd169 | 180 | #elif defined ( __TASKING__ ) |
Anna Bridge |
181:96ed750bd169 | 181 | #if defined __FPU_VFP__ |
Anna Bridge |
181:96ed750bd169 | 182 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 183 | #define __FPU_USED 1U |
Anna Bridge |
181:96ed750bd169 | 184 | #else |
Anna Bridge |
181:96ed750bd169 | 185 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 186 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 187 | #endif |
Anna Bridge |
181:96ed750bd169 | 188 | #else |
Anna Bridge |
181:96ed750bd169 | 189 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 190 | #endif |
Anna Bridge |
181:96ed750bd169 | 191 | |
Anna Bridge |
181:96ed750bd169 | 192 | #elif defined ( __CSMC__ ) |
Anna Bridge |
181:96ed750bd169 | 193 | #if ( __CSMC__ & 0x400U) |
Anna Bridge |
181:96ed750bd169 | 194 | #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 195 | #define __FPU_USED 1U |
Anna Bridge |
181:96ed750bd169 | 196 | #else |
Anna Bridge |
181:96ed750bd169 | 197 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Anna Bridge |
181:96ed750bd169 | 198 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 199 | #endif |
Anna Bridge |
181:96ed750bd169 | 200 | #else |
Anna Bridge |
181:96ed750bd169 | 201 | #define __FPU_USED 0U |
Anna Bridge |
181:96ed750bd169 | 202 | #endif |
Anna Bridge |
181:96ed750bd169 | 203 | |
Anna Bridge |
181:96ed750bd169 | 204 | #endif |
Anna Bridge |
181:96ed750bd169 | 205 | |
Anna Bridge |
181:96ed750bd169 | 206 | #include "cmsis_compiler.h" /* CMSIS compiler specific defines */ |
Anna Bridge |
181:96ed750bd169 | 207 | |
Anna Bridge |
181:96ed750bd169 | 208 | |
Anna Bridge |
181:96ed750bd169 | 209 | #ifdef __cplusplus |
Anna Bridge |
181:96ed750bd169 | 210 | } |
Anna Bridge |
181:96ed750bd169 | 211 | #endif |
Anna Bridge |
181:96ed750bd169 | 212 | |
Anna Bridge |
181:96ed750bd169 | 213 | #endif /* __CORE_CM33_H_GENERIC */ |
Anna Bridge |
181:96ed750bd169 | 214 | |
Anna Bridge |
181:96ed750bd169 | 215 | #ifndef __CMSIS_GENERIC |
Anna Bridge |
181:96ed750bd169 | 216 | |
Anna Bridge |
181:96ed750bd169 | 217 | #ifndef __CORE_CM33_H_DEPENDANT |
Anna Bridge |
181:96ed750bd169 | 218 | #define __CORE_CM33_H_DEPENDANT |
Anna Bridge |
181:96ed750bd169 | 219 | |
Anna Bridge |
181:96ed750bd169 | 220 | #ifdef __cplusplus |
Anna Bridge |
181:96ed750bd169 | 221 | extern "C" { |
Anna Bridge |
181:96ed750bd169 | 222 | #endif |
Anna Bridge |
181:96ed750bd169 | 223 | |
Anna Bridge |
181:96ed750bd169 | 224 | /* check device defines and use defaults */ |
Anna Bridge |
181:96ed750bd169 | 225 | #if defined __CHECK_DEVICE_DEFINES |
Anna Bridge |
181:96ed750bd169 | 226 | #ifndef __CM33_REV |
Anna Bridge |
181:96ed750bd169 | 227 | #define __CM33_REV 0x0000U |
Anna Bridge |
181:96ed750bd169 | 228 | #warning "__CM33_REV not defined in device header file; using default!" |
Anna Bridge |
181:96ed750bd169 | 229 | #endif |
Anna Bridge |
181:96ed750bd169 | 230 | |
Anna Bridge |
181:96ed750bd169 | 231 | #ifndef __FPU_PRESENT |
Anna Bridge |
181:96ed750bd169 | 232 | #define __FPU_PRESENT 0U |
Anna Bridge |
181:96ed750bd169 | 233 | #warning "__FPU_PRESENT not defined in device header file; using default!" |
Anna Bridge |
181:96ed750bd169 | 234 | #endif |
Anna Bridge |
181:96ed750bd169 | 235 | |
Anna Bridge |
181:96ed750bd169 | 236 | #ifndef __MPU_PRESENT |
Anna Bridge |
181:96ed750bd169 | 237 | #define __MPU_PRESENT 0U |
Anna Bridge |
181:96ed750bd169 | 238 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
Anna Bridge |
181:96ed750bd169 | 239 | #endif |
Anna Bridge |
181:96ed750bd169 | 240 | |
Anna Bridge |
181:96ed750bd169 | 241 | #ifndef __SAUREGION_PRESENT |
Anna Bridge |
181:96ed750bd169 | 242 | #define __SAUREGION_PRESENT 0U |
Anna Bridge |
181:96ed750bd169 | 243 | #warning "__SAUREGION_PRESENT not defined in device header file; using default!" |
Anna Bridge |
181:96ed750bd169 | 244 | #endif |
Anna Bridge |
181:96ed750bd169 | 245 | |
Anna Bridge |
181:96ed750bd169 | 246 | #ifndef __DSP_PRESENT |
Anna Bridge |
181:96ed750bd169 | 247 | #define __DSP_PRESENT 0U |
Anna Bridge |
181:96ed750bd169 | 248 | #warning "__DSP_PRESENT not defined in device header file; using default!" |
Anna Bridge |
181:96ed750bd169 | 249 | #endif |
Anna Bridge |
181:96ed750bd169 | 250 | |
Anna Bridge |
181:96ed750bd169 | 251 | #ifndef __NVIC_PRIO_BITS |
Anna Bridge |
181:96ed750bd169 | 252 | #define __NVIC_PRIO_BITS 3U |
Anna Bridge |
181:96ed750bd169 | 253 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
Anna Bridge |
181:96ed750bd169 | 254 | #endif |
Anna Bridge |
181:96ed750bd169 | 255 | |
Anna Bridge |
181:96ed750bd169 | 256 | #ifndef __Vendor_SysTickConfig |
Anna Bridge |
181:96ed750bd169 | 257 | #define __Vendor_SysTickConfig 0U |
Anna Bridge |
181:96ed750bd169 | 258 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
Anna Bridge |
181:96ed750bd169 | 259 | #endif |
Anna Bridge |
181:96ed750bd169 | 260 | #endif |
Anna Bridge |
181:96ed750bd169 | 261 | |
Anna Bridge |
181:96ed750bd169 | 262 | /* IO definitions (access restrictions to peripheral registers) */ |
Anna Bridge |
181:96ed750bd169 | 263 | /** |
Anna Bridge |
181:96ed750bd169 | 264 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
Anna Bridge |
181:96ed750bd169 | 265 | |
Anna Bridge |
181:96ed750bd169 | 266 | <strong>IO Type Qualifiers</strong> are used |
Anna Bridge |
181:96ed750bd169 | 267 | \li to specify the access to peripheral variables. |
Anna Bridge |
181:96ed750bd169 | 268 | \li for automatic generation of peripheral register debug information. |
Anna Bridge |
181:96ed750bd169 | 269 | */ |
Anna Bridge |
181:96ed750bd169 | 270 | #ifdef __cplusplus |
Anna Bridge |
181:96ed750bd169 | 271 | #define __I volatile /*!< Defines 'read only' permissions */ |
Anna Bridge |
181:96ed750bd169 | 272 | #else |
Anna Bridge |
181:96ed750bd169 | 273 | #define __I volatile const /*!< Defines 'read only' permissions */ |
Anna Bridge |
181:96ed750bd169 | 274 | #endif |
Anna Bridge |
181:96ed750bd169 | 275 | #define __O volatile /*!< Defines 'write only' permissions */ |
Anna Bridge |
181:96ed750bd169 | 276 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
Anna Bridge |
181:96ed750bd169 | 277 | |
Anna Bridge |
181:96ed750bd169 | 278 | /* following defines should be used for structure members */ |
Anna Bridge |
181:96ed750bd169 | 279 | #define __IM volatile const /*! Defines 'read only' structure member permissions */ |
Anna Bridge |
181:96ed750bd169 | 280 | #define __OM volatile /*! Defines 'write only' structure member permissions */ |
Anna Bridge |
181:96ed750bd169 | 281 | #define __IOM volatile /*! Defines 'read / write' structure member permissions */ |
Anna Bridge |
181:96ed750bd169 | 282 | |
Anna Bridge |
181:96ed750bd169 | 283 | /*@} end of group Cortex_M33 */ |
Anna Bridge |
181:96ed750bd169 | 284 | |
Anna Bridge |
181:96ed750bd169 | 285 | |
Anna Bridge |
181:96ed750bd169 | 286 | |
Anna Bridge |
181:96ed750bd169 | 287 | /******************************************************************************* |
Anna Bridge |
181:96ed750bd169 | 288 | * Register Abstraction |
Anna Bridge |
181:96ed750bd169 | 289 | Core Register contain: |
Anna Bridge |
181:96ed750bd169 | 290 | - Core Register |
Anna Bridge |
181:96ed750bd169 | 291 | - Core NVIC Register |
Anna Bridge |
181:96ed750bd169 | 292 | - Core SCB Register |
Anna Bridge |
181:96ed750bd169 | 293 | - Core SysTick Register |
Anna Bridge |
181:96ed750bd169 | 294 | - Core Debug Register |
Anna Bridge |
181:96ed750bd169 | 295 | - Core MPU Register |
Anna Bridge |
181:96ed750bd169 | 296 | - Core SAU Register |
Anna Bridge |
181:96ed750bd169 | 297 | - Core FPU Register |
Anna Bridge |
181:96ed750bd169 | 298 | ******************************************************************************/ |
Anna Bridge |
181:96ed750bd169 | 299 | /** |
Anna Bridge |
181:96ed750bd169 | 300 | \defgroup CMSIS_core_register Defines and Type Definitions |
Anna Bridge |
181:96ed750bd169 | 301 | \brief Type definitions and defines for Cortex-M processor based devices. |
Anna Bridge |
181:96ed750bd169 | 302 | */ |
Anna Bridge |
181:96ed750bd169 | 303 | |
Anna Bridge |
181:96ed750bd169 | 304 | /** |
Anna Bridge |
181:96ed750bd169 | 305 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 306 | \defgroup CMSIS_CORE Status and Control Registers |
Anna Bridge |
181:96ed750bd169 | 307 | \brief Core Register type definitions. |
Anna Bridge |
181:96ed750bd169 | 308 | @{ |
Anna Bridge |
181:96ed750bd169 | 309 | */ |
Anna Bridge |
181:96ed750bd169 | 310 | |
Anna Bridge |
181:96ed750bd169 | 311 | /** |
Anna Bridge |
181:96ed750bd169 | 312 | \brief Union type to access the Application Program Status Register (APSR). |
Anna Bridge |
181:96ed750bd169 | 313 | */ |
Anna Bridge |
181:96ed750bd169 | 314 | typedef union |
Anna Bridge |
181:96ed750bd169 | 315 | { |
Anna Bridge |
181:96ed750bd169 | 316 | struct |
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181:96ed750bd169 | 317 | { |
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181:96ed750bd169 | 318 | uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ |
Anna Bridge |
181:96ed750bd169 | 319 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
Anna Bridge |
181:96ed750bd169 | 320 | uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ |
Anna Bridge |
181:96ed750bd169 | 321 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
Anna Bridge |
181:96ed750bd169 | 322 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
Anna Bridge |
181:96ed750bd169 | 323 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
Anna Bridge |
181:96ed750bd169 | 324 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
Anna Bridge |
181:96ed750bd169 | 325 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
Anna Bridge |
181:96ed750bd169 | 326 | } b; /*!< Structure used for bit access */ |
Anna Bridge |
181:96ed750bd169 | 327 | uint32_t w; /*!< Type used for word access */ |
Anna Bridge |
181:96ed750bd169 | 328 | } APSR_Type; |
Anna Bridge |
181:96ed750bd169 | 329 | |
Anna Bridge |
181:96ed750bd169 | 330 | /* APSR Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 331 | #define APSR_N_Pos 31U /*!< APSR: N Position */ |
Anna Bridge |
181:96ed750bd169 | 332 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
Anna Bridge |
181:96ed750bd169 | 333 | |
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181:96ed750bd169 | 334 | #define APSR_Z_Pos 30U /*!< APSR: Z Position */ |
Anna Bridge |
181:96ed750bd169 | 335 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
Anna Bridge |
181:96ed750bd169 | 336 | |
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181:96ed750bd169 | 337 | #define APSR_C_Pos 29U /*!< APSR: C Position */ |
Anna Bridge |
181:96ed750bd169 | 338 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
Anna Bridge |
181:96ed750bd169 | 339 | |
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181:96ed750bd169 | 340 | #define APSR_V_Pos 28U /*!< APSR: V Position */ |
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181:96ed750bd169 | 341 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
Anna Bridge |
181:96ed750bd169 | 342 | |
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181:96ed750bd169 | 343 | #define APSR_Q_Pos 27U /*!< APSR: Q Position */ |
Anna Bridge |
181:96ed750bd169 | 344 | #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ |
Anna Bridge |
181:96ed750bd169 | 345 | |
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181:96ed750bd169 | 346 | #define APSR_GE_Pos 16U /*!< APSR: GE Position */ |
Anna Bridge |
181:96ed750bd169 | 347 | #define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ |
Anna Bridge |
181:96ed750bd169 | 348 | |
Anna Bridge |
181:96ed750bd169 | 349 | |
Anna Bridge |
181:96ed750bd169 | 350 | /** |
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181:96ed750bd169 | 351 | \brief Union type to access the Interrupt Program Status Register (IPSR). |
Anna Bridge |
181:96ed750bd169 | 352 | */ |
Anna Bridge |
181:96ed750bd169 | 353 | typedef union |
Anna Bridge |
181:96ed750bd169 | 354 | { |
Anna Bridge |
181:96ed750bd169 | 355 | struct |
Anna Bridge |
181:96ed750bd169 | 356 | { |
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181:96ed750bd169 | 357 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
Anna Bridge |
181:96ed750bd169 | 358 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
Anna Bridge |
181:96ed750bd169 | 359 | } b; /*!< Structure used for bit access */ |
Anna Bridge |
181:96ed750bd169 | 360 | uint32_t w; /*!< Type used for word access */ |
Anna Bridge |
181:96ed750bd169 | 361 | } IPSR_Type; |
Anna Bridge |
181:96ed750bd169 | 362 | |
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181:96ed750bd169 | 363 | /* IPSR Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 364 | #define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ |
Anna Bridge |
181:96ed750bd169 | 365 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
Anna Bridge |
181:96ed750bd169 | 366 | |
Anna Bridge |
181:96ed750bd169 | 367 | |
Anna Bridge |
181:96ed750bd169 | 368 | /** |
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181:96ed750bd169 | 369 | \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
Anna Bridge |
181:96ed750bd169 | 370 | */ |
Anna Bridge |
181:96ed750bd169 | 371 | typedef union |
Anna Bridge |
181:96ed750bd169 | 372 | { |
Anna Bridge |
181:96ed750bd169 | 373 | struct |
Anna Bridge |
181:96ed750bd169 | 374 | { |
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181:96ed750bd169 | 375 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
Anna Bridge |
181:96ed750bd169 | 376 | uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ |
Anna Bridge |
181:96ed750bd169 | 377 | uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ |
Anna Bridge |
181:96ed750bd169 | 378 | uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ |
Anna Bridge |
181:96ed750bd169 | 379 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
Anna Bridge |
181:96ed750bd169 | 380 | uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ |
Anna Bridge |
181:96ed750bd169 | 381 | uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ |
Anna Bridge |
181:96ed750bd169 | 382 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
Anna Bridge |
181:96ed750bd169 | 383 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
Anna Bridge |
181:96ed750bd169 | 384 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
Anna Bridge |
181:96ed750bd169 | 385 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
Anna Bridge |
181:96ed750bd169 | 386 | } b; /*!< Structure used for bit access */ |
Anna Bridge |
181:96ed750bd169 | 387 | uint32_t w; /*!< Type used for word access */ |
Anna Bridge |
181:96ed750bd169 | 388 | } xPSR_Type; |
Anna Bridge |
181:96ed750bd169 | 389 | |
Anna Bridge |
181:96ed750bd169 | 390 | /* xPSR Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 391 | #define xPSR_N_Pos 31U /*!< xPSR: N Position */ |
Anna Bridge |
181:96ed750bd169 | 392 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
Anna Bridge |
181:96ed750bd169 | 393 | |
Anna Bridge |
181:96ed750bd169 | 394 | #define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ |
Anna Bridge |
181:96ed750bd169 | 395 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
Anna Bridge |
181:96ed750bd169 | 396 | |
Anna Bridge |
181:96ed750bd169 | 397 | #define xPSR_C_Pos 29U /*!< xPSR: C Position */ |
Anna Bridge |
181:96ed750bd169 | 398 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
Anna Bridge |
181:96ed750bd169 | 399 | |
Anna Bridge |
181:96ed750bd169 | 400 | #define xPSR_V_Pos 28U /*!< xPSR: V Position */ |
Anna Bridge |
181:96ed750bd169 | 401 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
Anna Bridge |
181:96ed750bd169 | 402 | |
Anna Bridge |
181:96ed750bd169 | 403 | #define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ |
Anna Bridge |
181:96ed750bd169 | 404 | #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ |
Anna Bridge |
181:96ed750bd169 | 405 | |
Anna Bridge |
181:96ed750bd169 | 406 | #define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ |
Anna Bridge |
181:96ed750bd169 | 407 | #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ |
Anna Bridge |
181:96ed750bd169 | 408 | |
Anna Bridge |
181:96ed750bd169 | 409 | #define xPSR_T_Pos 24U /*!< xPSR: T Position */ |
Anna Bridge |
181:96ed750bd169 | 410 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
Anna Bridge |
181:96ed750bd169 | 411 | |
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181:96ed750bd169 | 412 | #define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ |
Anna Bridge |
181:96ed750bd169 | 413 | #define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ |
Anna Bridge |
181:96ed750bd169 | 414 | |
Anna Bridge |
181:96ed750bd169 | 415 | #define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ |
Anna Bridge |
181:96ed750bd169 | 416 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
Anna Bridge |
181:96ed750bd169 | 417 | |
Anna Bridge |
181:96ed750bd169 | 418 | |
Anna Bridge |
181:96ed750bd169 | 419 | /** |
Anna Bridge |
181:96ed750bd169 | 420 | \brief Union type to access the Control Registers (CONTROL). |
Anna Bridge |
181:96ed750bd169 | 421 | */ |
Anna Bridge |
181:96ed750bd169 | 422 | typedef union |
Anna Bridge |
181:96ed750bd169 | 423 | { |
Anna Bridge |
181:96ed750bd169 | 424 | struct |
Anna Bridge |
181:96ed750bd169 | 425 | { |
Anna Bridge |
181:96ed750bd169 | 426 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
Anna Bridge |
181:96ed750bd169 | 427 | uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ |
Anna Bridge |
181:96ed750bd169 | 428 | uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ |
Anna Bridge |
181:96ed750bd169 | 429 | uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ |
Anna Bridge |
181:96ed750bd169 | 430 | uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ |
Anna Bridge |
181:96ed750bd169 | 431 | } b; /*!< Structure used for bit access */ |
Anna Bridge |
181:96ed750bd169 | 432 | uint32_t w; /*!< Type used for word access */ |
Anna Bridge |
181:96ed750bd169 | 433 | } CONTROL_Type; |
Anna Bridge |
181:96ed750bd169 | 434 | |
Anna Bridge |
181:96ed750bd169 | 435 | /* CONTROL Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 436 | #define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ |
Anna Bridge |
181:96ed750bd169 | 437 | #define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ |
Anna Bridge |
181:96ed750bd169 | 438 | |
Anna Bridge |
181:96ed750bd169 | 439 | #define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ |
Anna Bridge |
181:96ed750bd169 | 440 | #define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ |
Anna Bridge |
181:96ed750bd169 | 441 | |
Anna Bridge |
181:96ed750bd169 | 442 | #define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ |
Anna Bridge |
181:96ed750bd169 | 443 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
Anna Bridge |
181:96ed750bd169 | 444 | |
Anna Bridge |
181:96ed750bd169 | 445 | #define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ |
Anna Bridge |
181:96ed750bd169 | 446 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
Anna Bridge |
181:96ed750bd169 | 447 | |
Anna Bridge |
181:96ed750bd169 | 448 | /*@} end of group CMSIS_CORE */ |
Anna Bridge |
181:96ed750bd169 | 449 | |
Anna Bridge |
181:96ed750bd169 | 450 | |
Anna Bridge |
181:96ed750bd169 | 451 | /** |
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181:96ed750bd169 | 452 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 453 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
Anna Bridge |
181:96ed750bd169 | 454 | \brief Type definitions for the NVIC Registers |
Anna Bridge |
181:96ed750bd169 | 455 | @{ |
Anna Bridge |
181:96ed750bd169 | 456 | */ |
Anna Bridge |
181:96ed750bd169 | 457 | |
Anna Bridge |
181:96ed750bd169 | 458 | /** |
Anna Bridge |
181:96ed750bd169 | 459 | \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
Anna Bridge |
181:96ed750bd169 | 460 | */ |
Anna Bridge |
181:96ed750bd169 | 461 | typedef struct |
Anna Bridge |
181:96ed750bd169 | 462 | { |
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181:96ed750bd169 | 463 | __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
Anna Bridge |
181:96ed750bd169 | 464 | uint32_t RESERVED0[16U]; |
Anna Bridge |
181:96ed750bd169 | 465 | __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
Anna Bridge |
181:96ed750bd169 | 466 | uint32_t RSERVED1[16U]; |
Anna Bridge |
181:96ed750bd169 | 467 | __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
Anna Bridge |
181:96ed750bd169 | 468 | uint32_t RESERVED2[16U]; |
Anna Bridge |
181:96ed750bd169 | 469 | __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
Anna Bridge |
181:96ed750bd169 | 470 | uint32_t RESERVED3[16U]; |
Anna Bridge |
181:96ed750bd169 | 471 | __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ |
Anna Bridge |
181:96ed750bd169 | 472 | uint32_t RESERVED4[16U]; |
Anna Bridge |
181:96ed750bd169 | 473 | __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ |
Anna Bridge |
181:96ed750bd169 | 474 | uint32_t RESERVED5[16U]; |
Anna Bridge |
181:96ed750bd169 | 475 | __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ |
Anna Bridge |
181:96ed750bd169 | 476 | uint32_t RESERVED6[580U]; |
Anna Bridge |
181:96ed750bd169 | 477 | __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ |
Anna Bridge |
181:96ed750bd169 | 478 | } NVIC_Type; |
Anna Bridge |
181:96ed750bd169 | 479 | |
Anna Bridge |
181:96ed750bd169 | 480 | /* Software Triggered Interrupt Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 481 | #define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ |
Anna Bridge |
181:96ed750bd169 | 482 | #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ |
Anna Bridge |
181:96ed750bd169 | 483 | |
Anna Bridge |
181:96ed750bd169 | 484 | /*@} end of group CMSIS_NVIC */ |
Anna Bridge |
181:96ed750bd169 | 485 | |
Anna Bridge |
181:96ed750bd169 | 486 | |
Anna Bridge |
181:96ed750bd169 | 487 | /** |
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181:96ed750bd169 | 488 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 489 | \defgroup CMSIS_SCB System Control Block (SCB) |
Anna Bridge |
181:96ed750bd169 | 490 | \brief Type definitions for the System Control Block Registers |
Anna Bridge |
181:96ed750bd169 | 491 | @{ |
Anna Bridge |
181:96ed750bd169 | 492 | */ |
Anna Bridge |
181:96ed750bd169 | 493 | |
Anna Bridge |
181:96ed750bd169 | 494 | /** |
Anna Bridge |
181:96ed750bd169 | 495 | \brief Structure type to access the System Control Block (SCB). |
Anna Bridge |
181:96ed750bd169 | 496 | */ |
Anna Bridge |
181:96ed750bd169 | 497 | typedef struct |
Anna Bridge |
181:96ed750bd169 | 498 | { |
Anna Bridge |
181:96ed750bd169 | 499 | __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
Anna Bridge |
181:96ed750bd169 | 500 | __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
Anna Bridge |
181:96ed750bd169 | 501 | __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
Anna Bridge |
181:96ed750bd169 | 502 | __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
Anna Bridge |
181:96ed750bd169 | 503 | __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
Anna Bridge |
181:96ed750bd169 | 504 | __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
Anna Bridge |
181:96ed750bd169 | 505 | __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ |
Anna Bridge |
181:96ed750bd169 | 506 | __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
Anna Bridge |
181:96ed750bd169 | 507 | __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ |
Anna Bridge |
181:96ed750bd169 | 508 | __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ |
Anna Bridge |
181:96ed750bd169 | 509 | __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ |
Anna Bridge |
181:96ed750bd169 | 510 | __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ |
Anna Bridge |
181:96ed750bd169 | 511 | __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ |
Anna Bridge |
181:96ed750bd169 | 512 | __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ |
Anna Bridge |
181:96ed750bd169 | 513 | __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ |
Anna Bridge |
181:96ed750bd169 | 514 | __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ |
Anna Bridge |
181:96ed750bd169 | 515 | __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ |
Anna Bridge |
181:96ed750bd169 | 516 | __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ |
Anna Bridge |
181:96ed750bd169 | 517 | __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ |
Anna Bridge |
181:96ed750bd169 | 518 | __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ |
Anna Bridge |
181:96ed750bd169 | 519 | __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ |
Anna Bridge |
181:96ed750bd169 | 520 | __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ |
Anna Bridge |
181:96ed750bd169 | 521 | __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ |
Anna Bridge |
181:96ed750bd169 | 522 | __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ |
Anna Bridge |
181:96ed750bd169 | 523 | __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ |
Anna Bridge |
181:96ed750bd169 | 524 | uint32_t RESERVED3[92U]; |
Anna Bridge |
181:96ed750bd169 | 525 | __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ |
Anna Bridge |
181:96ed750bd169 | 526 | uint32_t RESERVED4[15U]; |
Anna Bridge |
181:96ed750bd169 | 527 | __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ |
Anna Bridge |
181:96ed750bd169 | 528 | __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ |
Anna Bridge |
181:96ed750bd169 | 529 | __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ |
Anna Bridge |
181:96ed750bd169 | 530 | uint32_t RESERVED5[1U]; |
Anna Bridge |
181:96ed750bd169 | 531 | __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ |
Anna Bridge |
181:96ed750bd169 | 532 | uint32_t RESERVED6[1U]; |
Anna Bridge |
181:96ed750bd169 | 533 | __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ |
Anna Bridge |
181:96ed750bd169 | 534 | __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ |
Anna Bridge |
181:96ed750bd169 | 535 | __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ |
Anna Bridge |
181:96ed750bd169 | 536 | __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ |
Anna Bridge |
181:96ed750bd169 | 537 | __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ |
Anna Bridge |
181:96ed750bd169 | 538 | __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ |
Anna Bridge |
181:96ed750bd169 | 539 | __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ |
Anna Bridge |
181:96ed750bd169 | 540 | __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ |
Anna Bridge |
181:96ed750bd169 | 541 | uint32_t RESERVED7[6U]; |
Anna Bridge |
181:96ed750bd169 | 542 | __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ |
Anna Bridge |
181:96ed750bd169 | 543 | __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ |
Anna Bridge |
181:96ed750bd169 | 544 | __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ |
Anna Bridge |
181:96ed750bd169 | 545 | __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ |
Anna Bridge |
181:96ed750bd169 | 546 | __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ |
Anna Bridge |
181:96ed750bd169 | 547 | uint32_t RESERVED8[1U]; |
Anna Bridge |
181:96ed750bd169 | 548 | __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ |
Anna Bridge |
181:96ed750bd169 | 549 | } SCB_Type; |
Anna Bridge |
181:96ed750bd169 | 550 | |
Anna Bridge |
181:96ed750bd169 | 551 | /* SCB CPUID Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 552 | #define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ |
Anna Bridge |
181:96ed750bd169 | 553 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
Anna Bridge |
181:96ed750bd169 | 554 | |
Anna Bridge |
181:96ed750bd169 | 555 | #define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ |
Anna Bridge |
181:96ed750bd169 | 556 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
Anna Bridge |
181:96ed750bd169 | 557 | |
Anna Bridge |
181:96ed750bd169 | 558 | #define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ |
Anna Bridge |
181:96ed750bd169 | 559 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
Anna Bridge |
181:96ed750bd169 | 560 | |
Anna Bridge |
181:96ed750bd169 | 561 | #define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ |
Anna Bridge |
181:96ed750bd169 | 562 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
Anna Bridge |
181:96ed750bd169 | 563 | |
Anna Bridge |
181:96ed750bd169 | 564 | #define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ |
Anna Bridge |
181:96ed750bd169 | 565 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
Anna Bridge |
181:96ed750bd169 | 566 | |
Anna Bridge |
181:96ed750bd169 | 567 | /* SCB Interrupt Control State Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 568 | #define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ |
Anna Bridge |
181:96ed750bd169 | 569 | #define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ |
Anna Bridge |
181:96ed750bd169 | 570 | |
Anna Bridge |
181:96ed750bd169 | 571 | #define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ |
Anna Bridge |
181:96ed750bd169 | 572 | #define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ |
Anna Bridge |
181:96ed750bd169 | 573 | |
Anna Bridge |
181:96ed750bd169 | 574 | #define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ |
Anna Bridge |
181:96ed750bd169 | 575 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
Anna Bridge |
181:96ed750bd169 | 576 | |
Anna Bridge |
181:96ed750bd169 | 577 | #define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ |
Anna Bridge |
181:96ed750bd169 | 578 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
Anna Bridge |
181:96ed750bd169 | 579 | |
Anna Bridge |
181:96ed750bd169 | 580 | #define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ |
Anna Bridge |
181:96ed750bd169 | 581 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
Anna Bridge |
181:96ed750bd169 | 582 | |
Anna Bridge |
181:96ed750bd169 | 583 | #define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ |
Anna Bridge |
181:96ed750bd169 | 584 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
Anna Bridge |
181:96ed750bd169 | 585 | |
Anna Bridge |
181:96ed750bd169 | 586 | #define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ |
Anna Bridge |
181:96ed750bd169 | 587 | #define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ |
Anna Bridge |
181:96ed750bd169 | 588 | |
Anna Bridge |
181:96ed750bd169 | 589 | #define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ |
Anna Bridge |
181:96ed750bd169 | 590 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
Anna Bridge |
181:96ed750bd169 | 591 | |
Anna Bridge |
181:96ed750bd169 | 592 | #define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ |
Anna Bridge |
181:96ed750bd169 | 593 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
Anna Bridge |
181:96ed750bd169 | 594 | |
Anna Bridge |
181:96ed750bd169 | 595 | #define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ |
Anna Bridge |
181:96ed750bd169 | 596 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
Anna Bridge |
181:96ed750bd169 | 597 | |
Anna Bridge |
181:96ed750bd169 | 598 | #define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ |
Anna Bridge |
181:96ed750bd169 | 599 | #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ |
Anna Bridge |
181:96ed750bd169 | 600 | |
Anna Bridge |
181:96ed750bd169 | 601 | #define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ |
Anna Bridge |
181:96ed750bd169 | 602 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
Anna Bridge |
181:96ed750bd169 | 603 | |
Anna Bridge |
181:96ed750bd169 | 604 | /* SCB Vector Table Offset Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 605 | #define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ |
Anna Bridge |
181:96ed750bd169 | 606 | #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
Anna Bridge |
181:96ed750bd169 | 607 | |
Anna Bridge |
181:96ed750bd169 | 608 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 609 | #define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ |
Anna Bridge |
181:96ed750bd169 | 610 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
Anna Bridge |
181:96ed750bd169 | 611 | |
Anna Bridge |
181:96ed750bd169 | 612 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ |
Anna Bridge |
181:96ed750bd169 | 613 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
Anna Bridge |
181:96ed750bd169 | 614 | |
Anna Bridge |
181:96ed750bd169 | 615 | #define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ |
Anna Bridge |
181:96ed750bd169 | 616 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
Anna Bridge |
181:96ed750bd169 | 617 | |
Anna Bridge |
181:96ed750bd169 | 618 | #define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ |
Anna Bridge |
181:96ed750bd169 | 619 | #define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ |
Anna Bridge |
181:96ed750bd169 | 620 | |
Anna Bridge |
181:96ed750bd169 | 621 | #define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ |
Anna Bridge |
181:96ed750bd169 | 622 | #define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ |
Anna Bridge |
181:96ed750bd169 | 623 | |
Anna Bridge |
181:96ed750bd169 | 624 | #define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ |
Anna Bridge |
181:96ed750bd169 | 625 | #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ |
Anna Bridge |
181:96ed750bd169 | 626 | |
Anna Bridge |
181:96ed750bd169 | 627 | #define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ |
Anna Bridge |
181:96ed750bd169 | 628 | #define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ |
Anna Bridge |
181:96ed750bd169 | 629 | |
Anna Bridge |
181:96ed750bd169 | 630 | #define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ |
Anna Bridge |
181:96ed750bd169 | 631 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
Anna Bridge |
181:96ed750bd169 | 632 | |
Anna Bridge |
181:96ed750bd169 | 633 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
Anna Bridge |
181:96ed750bd169 | 634 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
Anna Bridge |
181:96ed750bd169 | 635 | |
Anna Bridge |
181:96ed750bd169 | 636 | /* SCB System Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 637 | #define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ |
Anna Bridge |
181:96ed750bd169 | 638 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
Anna Bridge |
181:96ed750bd169 | 639 | |
Anna Bridge |
181:96ed750bd169 | 640 | #define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ |
Anna Bridge |
181:96ed750bd169 | 641 | #define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ |
Anna Bridge |
181:96ed750bd169 | 642 | |
Anna Bridge |
181:96ed750bd169 | 643 | #define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ |
Anna Bridge |
181:96ed750bd169 | 644 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
Anna Bridge |
181:96ed750bd169 | 645 | |
Anna Bridge |
181:96ed750bd169 | 646 | #define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ |
Anna Bridge |
181:96ed750bd169 | 647 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
Anna Bridge |
181:96ed750bd169 | 648 | |
Anna Bridge |
181:96ed750bd169 | 649 | /* SCB Configuration Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 650 | #define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ |
Anna Bridge |
181:96ed750bd169 | 651 | #define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ |
Anna Bridge |
181:96ed750bd169 | 652 | |
Anna Bridge |
181:96ed750bd169 | 653 | #define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ |
Anna Bridge |
181:96ed750bd169 | 654 | #define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ |
Anna Bridge |
181:96ed750bd169 | 655 | |
Anna Bridge |
181:96ed750bd169 | 656 | #define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ |
Anna Bridge |
181:96ed750bd169 | 657 | #define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ |
Anna Bridge |
181:96ed750bd169 | 658 | |
Anna Bridge |
181:96ed750bd169 | 659 | #define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ |
Anna Bridge |
181:96ed750bd169 | 660 | #define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ |
Anna Bridge |
181:96ed750bd169 | 661 | |
Anna Bridge |
181:96ed750bd169 | 662 | #define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ |
Anna Bridge |
181:96ed750bd169 | 663 | #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ |
Anna Bridge |
181:96ed750bd169 | 664 | |
Anna Bridge |
181:96ed750bd169 | 665 | #define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ |
Anna Bridge |
181:96ed750bd169 | 666 | #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ |
Anna Bridge |
181:96ed750bd169 | 667 | |
Anna Bridge |
181:96ed750bd169 | 668 | #define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ |
Anna Bridge |
181:96ed750bd169 | 669 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
Anna Bridge |
181:96ed750bd169 | 670 | |
Anna Bridge |
181:96ed750bd169 | 671 | #define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ |
Anna Bridge |
181:96ed750bd169 | 672 | #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ |
Anna Bridge |
181:96ed750bd169 | 673 | |
Anna Bridge |
181:96ed750bd169 | 674 | /* SCB System Handler Control and State Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 675 | #define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ |
Anna Bridge |
181:96ed750bd169 | 676 | #define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ |
Anna Bridge |
181:96ed750bd169 | 677 | |
Anna Bridge |
181:96ed750bd169 | 678 | #define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ |
Anna Bridge |
181:96ed750bd169 | 679 | #define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ |
Anna Bridge |
181:96ed750bd169 | 680 | |
Anna Bridge |
181:96ed750bd169 | 681 | #define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ |
Anna Bridge |
181:96ed750bd169 | 682 | #define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ |
Anna Bridge |
181:96ed750bd169 | 683 | |
Anna Bridge |
181:96ed750bd169 | 684 | #define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ |
Anna Bridge |
181:96ed750bd169 | 685 | #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ |
Anna Bridge |
181:96ed750bd169 | 686 | |
Anna Bridge |
181:96ed750bd169 | 687 | #define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ |
Anna Bridge |
181:96ed750bd169 | 688 | #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ |
Anna Bridge |
181:96ed750bd169 | 689 | |
Anna Bridge |
181:96ed750bd169 | 690 | #define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ |
Anna Bridge |
181:96ed750bd169 | 691 | #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ |
Anna Bridge |
181:96ed750bd169 | 692 | |
Anna Bridge |
181:96ed750bd169 | 693 | #define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ |
Anna Bridge |
181:96ed750bd169 | 694 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
Anna Bridge |
181:96ed750bd169 | 695 | |
Anna Bridge |
181:96ed750bd169 | 696 | #define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ |
Anna Bridge |
181:96ed750bd169 | 697 | #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ |
Anna Bridge |
181:96ed750bd169 | 698 | |
Anna Bridge |
181:96ed750bd169 | 699 | #define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ |
Anna Bridge |
181:96ed750bd169 | 700 | #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ |
Anna Bridge |
181:96ed750bd169 | 701 | |
Anna Bridge |
181:96ed750bd169 | 702 | #define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ |
Anna Bridge |
181:96ed750bd169 | 703 | #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ |
Anna Bridge |
181:96ed750bd169 | 704 | |
Anna Bridge |
181:96ed750bd169 | 705 | #define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ |
Anna Bridge |
181:96ed750bd169 | 706 | #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 707 | |
Anna Bridge |
181:96ed750bd169 | 708 | #define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ |
Anna Bridge |
181:96ed750bd169 | 709 | #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 710 | |
Anna Bridge |
181:96ed750bd169 | 711 | #define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ |
Anna Bridge |
181:96ed750bd169 | 712 | #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 713 | |
Anna Bridge |
181:96ed750bd169 | 714 | #define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ |
Anna Bridge |
181:96ed750bd169 | 715 | #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 716 | |
Anna Bridge |
181:96ed750bd169 | 717 | #define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ |
Anna Bridge |
181:96ed750bd169 | 718 | #define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 719 | |
Anna Bridge |
181:96ed750bd169 | 720 | #define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ |
Anna Bridge |
181:96ed750bd169 | 721 | #define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 722 | |
Anna Bridge |
181:96ed750bd169 | 723 | #define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ |
Anna Bridge |
181:96ed750bd169 | 724 | #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 725 | |
Anna Bridge |
181:96ed750bd169 | 726 | #define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ |
Anna Bridge |
181:96ed750bd169 | 727 | #define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 728 | |
Anna Bridge |
181:96ed750bd169 | 729 | #define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ |
Anna Bridge |
181:96ed750bd169 | 730 | #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 731 | |
Anna Bridge |
181:96ed750bd169 | 732 | #define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ |
Anna Bridge |
181:96ed750bd169 | 733 | #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ |
Anna Bridge |
181:96ed750bd169 | 734 | |
Anna Bridge |
181:96ed750bd169 | 735 | /* SCB Configurable Fault Status Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 736 | #define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ |
Anna Bridge |
181:96ed750bd169 | 737 | #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ |
Anna Bridge |
181:96ed750bd169 | 738 | |
Anna Bridge |
181:96ed750bd169 | 739 | #define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ |
Anna Bridge |
181:96ed750bd169 | 740 | #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ |
Anna Bridge |
181:96ed750bd169 | 741 | |
Anna Bridge |
181:96ed750bd169 | 742 | #define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ |
Anna Bridge |
181:96ed750bd169 | 743 | #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ |
Anna Bridge |
181:96ed750bd169 | 744 | |
Anna Bridge |
181:96ed750bd169 | 745 | /* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ |
Anna Bridge |
181:96ed750bd169 | 746 | #define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 747 | #define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 748 | |
Anna Bridge |
181:96ed750bd169 | 749 | #define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ |
Anna Bridge |
181:96ed750bd169 | 750 | #define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 751 | |
Anna Bridge |
181:96ed750bd169 | 752 | #define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ |
Anna Bridge |
181:96ed750bd169 | 753 | #define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 754 | |
Anna Bridge |
181:96ed750bd169 | 755 | #define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ |
Anna Bridge |
181:96ed750bd169 | 756 | #define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 757 | |
Anna Bridge |
181:96ed750bd169 | 758 | #define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ |
Anna Bridge |
181:96ed750bd169 | 759 | #define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ |
Anna Bridge |
181:96ed750bd169 | 760 | |
Anna Bridge |
181:96ed750bd169 | 761 | #define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ |
Anna Bridge |
181:96ed750bd169 | 762 | #define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ |
Anna Bridge |
181:96ed750bd169 | 763 | |
Anna Bridge |
181:96ed750bd169 | 764 | /* BusFault Status Register (part of SCB Configurable Fault Status Register) */ |
Anna Bridge |
181:96ed750bd169 | 765 | #define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 766 | #define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 767 | |
Anna Bridge |
181:96ed750bd169 | 768 | #define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ |
Anna Bridge |
181:96ed750bd169 | 769 | #define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 770 | |
Anna Bridge |
181:96ed750bd169 | 771 | #define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ |
Anna Bridge |
181:96ed750bd169 | 772 | #define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 773 | |
Anna Bridge |
181:96ed750bd169 | 774 | #define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ |
Anna Bridge |
181:96ed750bd169 | 775 | #define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 776 | |
Anna Bridge |
181:96ed750bd169 | 777 | #define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ |
Anna Bridge |
181:96ed750bd169 | 778 | #define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 779 | |
Anna Bridge |
181:96ed750bd169 | 780 | #define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ |
Anna Bridge |
181:96ed750bd169 | 781 | #define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 782 | |
Anna Bridge |
181:96ed750bd169 | 783 | #define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ |
Anna Bridge |
181:96ed750bd169 | 784 | #define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 785 | |
Anna Bridge |
181:96ed750bd169 | 786 | /* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ |
Anna Bridge |
181:96ed750bd169 | 787 | #define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ |
Anna Bridge |
181:96ed750bd169 | 788 | #define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ |
Anna Bridge |
181:96ed750bd169 | 789 | |
Anna Bridge |
181:96ed750bd169 | 790 | #define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ |
Anna Bridge |
181:96ed750bd169 | 791 | #define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ |
Anna Bridge |
181:96ed750bd169 | 792 | |
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181:96ed750bd169 | 793 | #define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ |
Anna Bridge |
181:96ed750bd169 | 794 | #define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ |
Anna Bridge |
181:96ed750bd169 | 795 | |
Anna Bridge |
181:96ed750bd169 | 796 | #define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ |
Anna Bridge |
181:96ed750bd169 | 797 | #define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ |
Anna Bridge |
181:96ed750bd169 | 798 | |
Anna Bridge |
181:96ed750bd169 | 799 | #define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ |
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181:96ed750bd169 | 800 | #define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ |
Anna Bridge |
181:96ed750bd169 | 801 | |
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181:96ed750bd169 | 802 | #define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ |
Anna Bridge |
181:96ed750bd169 | 803 | #define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ |
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181:96ed750bd169 | 804 | |
Anna Bridge |
181:96ed750bd169 | 805 | #define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ |
Anna Bridge |
181:96ed750bd169 | 806 | #define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ |
Anna Bridge |
181:96ed750bd169 | 807 | |
Anna Bridge |
181:96ed750bd169 | 808 | /* SCB Hard Fault Status Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 809 | #define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ |
Anna Bridge |
181:96ed750bd169 | 810 | #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ |
Anna Bridge |
181:96ed750bd169 | 811 | |
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181:96ed750bd169 | 812 | #define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ |
Anna Bridge |
181:96ed750bd169 | 813 | #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ |
Anna Bridge |
181:96ed750bd169 | 814 | |
Anna Bridge |
181:96ed750bd169 | 815 | #define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ |
Anna Bridge |
181:96ed750bd169 | 816 | #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ |
Anna Bridge |
181:96ed750bd169 | 817 | |
Anna Bridge |
181:96ed750bd169 | 818 | /* SCB Debug Fault Status Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 819 | #define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ |
Anna Bridge |
181:96ed750bd169 | 820 | #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ |
Anna Bridge |
181:96ed750bd169 | 821 | |
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181:96ed750bd169 | 822 | #define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ |
Anna Bridge |
181:96ed750bd169 | 823 | #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ |
Anna Bridge |
181:96ed750bd169 | 824 | |
Anna Bridge |
181:96ed750bd169 | 825 | #define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ |
Anna Bridge |
181:96ed750bd169 | 826 | #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ |
Anna Bridge |
181:96ed750bd169 | 827 | |
Anna Bridge |
181:96ed750bd169 | 828 | #define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ |
Anna Bridge |
181:96ed750bd169 | 829 | #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ |
Anna Bridge |
181:96ed750bd169 | 830 | |
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181:96ed750bd169 | 831 | #define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ |
Anna Bridge |
181:96ed750bd169 | 832 | #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ |
Anna Bridge |
181:96ed750bd169 | 833 | |
Anna Bridge |
181:96ed750bd169 | 834 | /* SCB Non-Secure Access Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 835 | #define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ |
Anna Bridge |
181:96ed750bd169 | 836 | #define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ |
Anna Bridge |
181:96ed750bd169 | 837 | |
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181:96ed750bd169 | 838 | #define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ |
Anna Bridge |
181:96ed750bd169 | 839 | #define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ |
Anna Bridge |
181:96ed750bd169 | 840 | |
Anna Bridge |
181:96ed750bd169 | 841 | #define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ |
Anna Bridge |
181:96ed750bd169 | 842 | #define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ |
Anna Bridge |
181:96ed750bd169 | 843 | |
Anna Bridge |
181:96ed750bd169 | 844 | /* SCB Cache Level ID Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 845 | #define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ |
Anna Bridge |
181:96ed750bd169 | 846 | #define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ |
Anna Bridge |
181:96ed750bd169 | 847 | |
Anna Bridge |
181:96ed750bd169 | 848 | #define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ |
Anna Bridge |
181:96ed750bd169 | 849 | #define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ |
Anna Bridge |
181:96ed750bd169 | 850 | |
Anna Bridge |
181:96ed750bd169 | 851 | /* SCB Cache Type Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 852 | #define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ |
Anna Bridge |
181:96ed750bd169 | 853 | #define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ |
Anna Bridge |
181:96ed750bd169 | 854 | |
Anna Bridge |
181:96ed750bd169 | 855 | #define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ |
Anna Bridge |
181:96ed750bd169 | 856 | #define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ |
Anna Bridge |
181:96ed750bd169 | 857 | |
Anna Bridge |
181:96ed750bd169 | 858 | #define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ |
Anna Bridge |
181:96ed750bd169 | 859 | #define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ |
Anna Bridge |
181:96ed750bd169 | 860 | |
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181:96ed750bd169 | 861 | #define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ |
Anna Bridge |
181:96ed750bd169 | 862 | #define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ |
Anna Bridge |
181:96ed750bd169 | 863 | |
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181:96ed750bd169 | 864 | #define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ |
Anna Bridge |
181:96ed750bd169 | 865 | #define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ |
Anna Bridge |
181:96ed750bd169 | 866 | |
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181:96ed750bd169 | 867 | /* SCB Cache Size ID Register Definitions */ |
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181:96ed750bd169 | 868 | #define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ |
Anna Bridge |
181:96ed750bd169 | 869 | #define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ |
Anna Bridge |
181:96ed750bd169 | 870 | |
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181:96ed750bd169 | 871 | #define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ |
Anna Bridge |
181:96ed750bd169 | 872 | #define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ |
Anna Bridge |
181:96ed750bd169 | 873 | |
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181:96ed750bd169 | 874 | #define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ |
Anna Bridge |
181:96ed750bd169 | 875 | #define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ |
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181:96ed750bd169 | 876 | |
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181:96ed750bd169 | 877 | #define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ |
Anna Bridge |
181:96ed750bd169 | 878 | #define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ |
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181:96ed750bd169 | 879 | |
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181:96ed750bd169 | 880 | #define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ |
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181:96ed750bd169 | 881 | #define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ |
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181:96ed750bd169 | 882 | |
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181:96ed750bd169 | 883 | #define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ |
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181:96ed750bd169 | 884 | #define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ |
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181:96ed750bd169 | 885 | |
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181:96ed750bd169 | 886 | #define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ |
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181:96ed750bd169 | 887 | #define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ |
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181:96ed750bd169 | 888 | |
Anna Bridge |
181:96ed750bd169 | 889 | /* SCB Cache Size Selection Register Definitions */ |
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181:96ed750bd169 | 890 | #define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ |
Anna Bridge |
181:96ed750bd169 | 891 | #define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ |
Anna Bridge |
181:96ed750bd169 | 892 | |
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181:96ed750bd169 | 893 | #define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ |
Anna Bridge |
181:96ed750bd169 | 894 | #define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ |
Anna Bridge |
181:96ed750bd169 | 895 | |
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181:96ed750bd169 | 896 | /* SCB Software Triggered Interrupt Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 897 | #define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ |
Anna Bridge |
181:96ed750bd169 | 898 | #define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ |
Anna Bridge |
181:96ed750bd169 | 899 | |
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181:96ed750bd169 | 900 | /* SCB D-Cache Invalidate by Set-way Register Definitions */ |
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181:96ed750bd169 | 901 | #define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ |
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181:96ed750bd169 | 902 | #define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ |
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181:96ed750bd169 | 903 | |
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181:96ed750bd169 | 904 | #define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ |
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181:96ed750bd169 | 905 | #define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ |
Anna Bridge |
181:96ed750bd169 | 906 | |
Anna Bridge |
181:96ed750bd169 | 907 | /* SCB D-Cache Clean by Set-way Register Definitions */ |
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181:96ed750bd169 | 908 | #define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ |
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181:96ed750bd169 | 909 | #define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ |
Anna Bridge |
181:96ed750bd169 | 910 | |
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181:96ed750bd169 | 911 | #define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ |
Anna Bridge |
181:96ed750bd169 | 912 | #define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ |
Anna Bridge |
181:96ed750bd169 | 913 | |
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181:96ed750bd169 | 914 | /* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ |
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181:96ed750bd169 | 915 | #define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ |
Anna Bridge |
181:96ed750bd169 | 916 | #define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ |
Anna Bridge |
181:96ed750bd169 | 917 | |
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181:96ed750bd169 | 918 | #define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ |
Anna Bridge |
181:96ed750bd169 | 919 | #define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ |
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181:96ed750bd169 | 920 | |
Anna Bridge |
181:96ed750bd169 | 921 | /* Instruction Tightly-Coupled Memory Control Register Definitions */ |
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181:96ed750bd169 | 922 | #define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ |
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181:96ed750bd169 | 923 | #define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ |
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181:96ed750bd169 | 924 | |
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181:96ed750bd169 | 925 | #define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ |
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181:96ed750bd169 | 926 | #define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ |
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181:96ed750bd169 | 927 | |
Anna Bridge |
181:96ed750bd169 | 928 | #define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ |
Anna Bridge |
181:96ed750bd169 | 929 | #define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ |
Anna Bridge |
181:96ed750bd169 | 930 | |
Anna Bridge |
181:96ed750bd169 | 931 | #define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ |
Anna Bridge |
181:96ed750bd169 | 932 | #define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ |
Anna Bridge |
181:96ed750bd169 | 933 | |
Anna Bridge |
181:96ed750bd169 | 934 | /* Data Tightly-Coupled Memory Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 935 | #define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ |
Anna Bridge |
181:96ed750bd169 | 936 | #define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ |
Anna Bridge |
181:96ed750bd169 | 937 | |
Anna Bridge |
181:96ed750bd169 | 938 | #define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ |
Anna Bridge |
181:96ed750bd169 | 939 | #define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ |
Anna Bridge |
181:96ed750bd169 | 940 | |
Anna Bridge |
181:96ed750bd169 | 941 | #define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ |
Anna Bridge |
181:96ed750bd169 | 942 | #define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ |
Anna Bridge |
181:96ed750bd169 | 943 | |
Anna Bridge |
181:96ed750bd169 | 944 | #define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ |
Anna Bridge |
181:96ed750bd169 | 945 | #define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ |
Anna Bridge |
181:96ed750bd169 | 946 | |
Anna Bridge |
181:96ed750bd169 | 947 | /* AHBP Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 948 | #define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ |
Anna Bridge |
181:96ed750bd169 | 949 | #define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ |
Anna Bridge |
181:96ed750bd169 | 950 | |
Anna Bridge |
181:96ed750bd169 | 951 | #define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ |
Anna Bridge |
181:96ed750bd169 | 952 | #define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ |
Anna Bridge |
181:96ed750bd169 | 953 | |
Anna Bridge |
181:96ed750bd169 | 954 | /* L1 Cache Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 955 | #define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ |
Anna Bridge |
181:96ed750bd169 | 956 | #define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ |
Anna Bridge |
181:96ed750bd169 | 957 | |
Anna Bridge |
181:96ed750bd169 | 958 | #define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ |
Anna Bridge |
181:96ed750bd169 | 959 | #define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ |
Anna Bridge |
181:96ed750bd169 | 960 | |
Anna Bridge |
181:96ed750bd169 | 961 | #define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ |
Anna Bridge |
181:96ed750bd169 | 962 | #define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ |
Anna Bridge |
181:96ed750bd169 | 963 | |
Anna Bridge |
181:96ed750bd169 | 964 | /* AHBS Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 965 | #define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ |
Anna Bridge |
181:96ed750bd169 | 966 | #define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ |
Anna Bridge |
181:96ed750bd169 | 967 | |
Anna Bridge |
181:96ed750bd169 | 968 | #define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ |
Anna Bridge |
181:96ed750bd169 | 969 | #define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ |
Anna Bridge |
181:96ed750bd169 | 970 | |
Anna Bridge |
181:96ed750bd169 | 971 | #define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ |
Anna Bridge |
181:96ed750bd169 | 972 | #define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ |
Anna Bridge |
181:96ed750bd169 | 973 | |
Anna Bridge |
181:96ed750bd169 | 974 | /* Auxiliary Bus Fault Status Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 975 | #define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ |
Anna Bridge |
181:96ed750bd169 | 976 | #define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ |
Anna Bridge |
181:96ed750bd169 | 977 | |
Anna Bridge |
181:96ed750bd169 | 978 | #define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ |
Anna Bridge |
181:96ed750bd169 | 979 | #define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ |
Anna Bridge |
181:96ed750bd169 | 980 | |
Anna Bridge |
181:96ed750bd169 | 981 | #define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ |
Anna Bridge |
181:96ed750bd169 | 982 | #define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ |
Anna Bridge |
181:96ed750bd169 | 983 | |
Anna Bridge |
181:96ed750bd169 | 984 | #define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ |
Anna Bridge |
181:96ed750bd169 | 985 | #define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ |
Anna Bridge |
181:96ed750bd169 | 986 | |
Anna Bridge |
181:96ed750bd169 | 987 | #define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ |
Anna Bridge |
181:96ed750bd169 | 988 | #define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ |
Anna Bridge |
181:96ed750bd169 | 989 | |
Anna Bridge |
181:96ed750bd169 | 990 | #define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ |
Anna Bridge |
181:96ed750bd169 | 991 | #define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ |
Anna Bridge |
181:96ed750bd169 | 992 | |
Anna Bridge |
181:96ed750bd169 | 993 | /*@} end of group CMSIS_SCB */ |
Anna Bridge |
181:96ed750bd169 | 994 | |
Anna Bridge |
181:96ed750bd169 | 995 | |
Anna Bridge |
181:96ed750bd169 | 996 | /** |
Anna Bridge |
181:96ed750bd169 | 997 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 998 | \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) |
Anna Bridge |
181:96ed750bd169 | 999 | \brief Type definitions for the System Control and ID Register not in the SCB |
Anna Bridge |
181:96ed750bd169 | 1000 | @{ |
Anna Bridge |
181:96ed750bd169 | 1001 | */ |
Anna Bridge |
181:96ed750bd169 | 1002 | |
Anna Bridge |
181:96ed750bd169 | 1003 | /** |
Anna Bridge |
181:96ed750bd169 | 1004 | \brief Structure type to access the System Control and ID Register not in the SCB. |
Anna Bridge |
181:96ed750bd169 | 1005 | */ |
Anna Bridge |
181:96ed750bd169 | 1006 | typedef struct |
Anna Bridge |
181:96ed750bd169 | 1007 | { |
Anna Bridge |
181:96ed750bd169 | 1008 | uint32_t RESERVED0[1U]; |
Anna Bridge |
181:96ed750bd169 | 1009 | __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ |
Anna Bridge |
181:96ed750bd169 | 1010 | __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ |
Anna Bridge |
181:96ed750bd169 | 1011 | __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ |
Anna Bridge |
181:96ed750bd169 | 1012 | } SCnSCB_Type; |
Anna Bridge |
181:96ed750bd169 | 1013 | |
Anna Bridge |
181:96ed750bd169 | 1014 | /* Interrupt Controller Type Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1015 | #define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ |
Anna Bridge |
181:96ed750bd169 | 1016 | #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ |
Anna Bridge |
181:96ed750bd169 | 1017 | |
Anna Bridge |
181:96ed750bd169 | 1018 | /*@} end of group CMSIS_SCnotSCB */ |
Anna Bridge |
181:96ed750bd169 | 1019 | |
Anna Bridge |
181:96ed750bd169 | 1020 | |
Anna Bridge |
181:96ed750bd169 | 1021 | /** |
Anna Bridge |
181:96ed750bd169 | 1022 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 1023 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
Anna Bridge |
181:96ed750bd169 | 1024 | \brief Type definitions for the System Timer Registers. |
Anna Bridge |
181:96ed750bd169 | 1025 | @{ |
Anna Bridge |
181:96ed750bd169 | 1026 | */ |
Anna Bridge |
181:96ed750bd169 | 1027 | |
Anna Bridge |
181:96ed750bd169 | 1028 | /** |
Anna Bridge |
181:96ed750bd169 | 1029 | \brief Structure type to access the System Timer (SysTick). |
Anna Bridge |
181:96ed750bd169 | 1030 | */ |
Anna Bridge |
181:96ed750bd169 | 1031 | typedef struct |
Anna Bridge |
181:96ed750bd169 | 1032 | { |
Anna Bridge |
181:96ed750bd169 | 1033 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
Anna Bridge |
181:96ed750bd169 | 1034 | __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
Anna Bridge |
181:96ed750bd169 | 1035 | __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
Anna Bridge |
181:96ed750bd169 | 1036 | __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
Anna Bridge |
181:96ed750bd169 | 1037 | } SysTick_Type; |
Anna Bridge |
181:96ed750bd169 | 1038 | |
Anna Bridge |
181:96ed750bd169 | 1039 | /* SysTick Control / Status Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1040 | #define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ |
Anna Bridge |
181:96ed750bd169 | 1041 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
Anna Bridge |
181:96ed750bd169 | 1042 | |
Anna Bridge |
181:96ed750bd169 | 1043 | #define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ |
Anna Bridge |
181:96ed750bd169 | 1044 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
Anna Bridge |
181:96ed750bd169 | 1045 | |
Anna Bridge |
181:96ed750bd169 | 1046 | #define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ |
Anna Bridge |
181:96ed750bd169 | 1047 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
Anna Bridge |
181:96ed750bd169 | 1048 | |
Anna Bridge |
181:96ed750bd169 | 1049 | #define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ |
Anna Bridge |
181:96ed750bd169 | 1050 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
Anna Bridge |
181:96ed750bd169 | 1051 | |
Anna Bridge |
181:96ed750bd169 | 1052 | /* SysTick Reload Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1053 | #define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ |
Anna Bridge |
181:96ed750bd169 | 1054 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
Anna Bridge |
181:96ed750bd169 | 1055 | |
Anna Bridge |
181:96ed750bd169 | 1056 | /* SysTick Current Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1057 | #define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ |
Anna Bridge |
181:96ed750bd169 | 1058 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
Anna Bridge |
181:96ed750bd169 | 1059 | |
Anna Bridge |
181:96ed750bd169 | 1060 | /* SysTick Calibration Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1061 | #define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ |
Anna Bridge |
181:96ed750bd169 | 1062 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
Anna Bridge |
181:96ed750bd169 | 1063 | |
Anna Bridge |
181:96ed750bd169 | 1064 | #define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ |
Anna Bridge |
181:96ed750bd169 | 1065 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
Anna Bridge |
181:96ed750bd169 | 1066 | |
Anna Bridge |
181:96ed750bd169 | 1067 | #define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ |
Anna Bridge |
181:96ed750bd169 | 1068 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
Anna Bridge |
181:96ed750bd169 | 1069 | |
Anna Bridge |
181:96ed750bd169 | 1070 | /*@} end of group CMSIS_SysTick */ |
Anna Bridge |
181:96ed750bd169 | 1071 | |
Anna Bridge |
181:96ed750bd169 | 1072 | |
Anna Bridge |
181:96ed750bd169 | 1073 | /** |
Anna Bridge |
181:96ed750bd169 | 1074 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 1075 | \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) |
Anna Bridge |
181:96ed750bd169 | 1076 | \brief Type definitions for the Instrumentation Trace Macrocell (ITM) |
Anna Bridge |
181:96ed750bd169 | 1077 | @{ |
Anna Bridge |
181:96ed750bd169 | 1078 | */ |
Anna Bridge |
181:96ed750bd169 | 1079 | |
Anna Bridge |
181:96ed750bd169 | 1080 | /** |
Anna Bridge |
181:96ed750bd169 | 1081 | \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). |
Anna Bridge |
181:96ed750bd169 | 1082 | */ |
Anna Bridge |
181:96ed750bd169 | 1083 | typedef struct |
Anna Bridge |
181:96ed750bd169 | 1084 | { |
Anna Bridge |
181:96ed750bd169 | 1085 | __OM union |
Anna Bridge |
181:96ed750bd169 | 1086 | { |
Anna Bridge |
181:96ed750bd169 | 1087 | __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ |
Anna Bridge |
181:96ed750bd169 | 1088 | __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ |
Anna Bridge |
181:96ed750bd169 | 1089 | __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ |
Anna Bridge |
181:96ed750bd169 | 1090 | } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ |
Anna Bridge |
181:96ed750bd169 | 1091 | uint32_t RESERVED0[864U]; |
Anna Bridge |
181:96ed750bd169 | 1092 | __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ |
Anna Bridge |
181:96ed750bd169 | 1093 | uint32_t RESERVED1[15U]; |
Anna Bridge |
181:96ed750bd169 | 1094 | __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ |
Anna Bridge |
181:96ed750bd169 | 1095 | uint32_t RESERVED2[15U]; |
Anna Bridge |
181:96ed750bd169 | 1096 | __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ |
Anna Bridge |
181:96ed750bd169 | 1097 | uint32_t RESERVED3[29U]; |
Anna Bridge |
181:96ed750bd169 | 1098 | __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ |
Anna Bridge |
181:96ed750bd169 | 1099 | __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ |
Anna Bridge |
181:96ed750bd169 | 1100 | __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ |
Anna Bridge |
181:96ed750bd169 | 1101 | uint32_t RESERVED4[43U]; |
Anna Bridge |
181:96ed750bd169 | 1102 | __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ |
Anna Bridge |
181:96ed750bd169 | 1103 | __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ |
Anna Bridge |
181:96ed750bd169 | 1104 | uint32_t RESERVED5[1U]; |
Anna Bridge |
181:96ed750bd169 | 1105 | __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ |
Anna Bridge |
181:96ed750bd169 | 1106 | uint32_t RESERVED6[4U]; |
Anna Bridge |
181:96ed750bd169 | 1107 | __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ |
Anna Bridge |
181:96ed750bd169 | 1108 | __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ |
Anna Bridge |
181:96ed750bd169 | 1109 | __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ |
Anna Bridge |
181:96ed750bd169 | 1110 | __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ |
Anna Bridge |
181:96ed750bd169 | 1111 | __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ |
Anna Bridge |
181:96ed750bd169 | 1112 | __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ |
Anna Bridge |
181:96ed750bd169 | 1113 | __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ |
Anna Bridge |
181:96ed750bd169 | 1114 | __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ |
Anna Bridge |
181:96ed750bd169 | 1115 | __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ |
Anna Bridge |
181:96ed750bd169 | 1116 | __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ |
Anna Bridge |
181:96ed750bd169 | 1117 | __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ |
Anna Bridge |
181:96ed750bd169 | 1118 | __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ |
Anna Bridge |
181:96ed750bd169 | 1119 | } ITM_Type; |
Anna Bridge |
181:96ed750bd169 | 1120 | |
Anna Bridge |
181:96ed750bd169 | 1121 | /* ITM Stimulus Port Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1122 | #define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ |
Anna Bridge |
181:96ed750bd169 | 1123 | #define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ |
Anna Bridge |
181:96ed750bd169 | 1124 | |
Anna Bridge |
181:96ed750bd169 | 1125 | #define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ |
Anna Bridge |
181:96ed750bd169 | 1126 | #define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ |
Anna Bridge |
181:96ed750bd169 | 1127 | |
Anna Bridge |
181:96ed750bd169 | 1128 | /* ITM Trace Privilege Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1129 | #define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ |
Anna Bridge |
181:96ed750bd169 | 1130 | #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ |
Anna Bridge |
181:96ed750bd169 | 1131 | |
Anna Bridge |
181:96ed750bd169 | 1132 | /* ITM Trace Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1133 | #define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ |
Anna Bridge |
181:96ed750bd169 | 1134 | #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ |
Anna Bridge |
181:96ed750bd169 | 1135 | |
Anna Bridge |
181:96ed750bd169 | 1136 | #define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ |
Anna Bridge |
181:96ed750bd169 | 1137 | #define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1138 | |
Anna Bridge |
181:96ed750bd169 | 1139 | #define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ |
Anna Bridge |
181:96ed750bd169 | 1140 | #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ |
Anna Bridge |
181:96ed750bd169 | 1141 | |
Anna Bridge |
181:96ed750bd169 | 1142 | #define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ |
Anna Bridge |
181:96ed750bd169 | 1143 | #define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ |
Anna Bridge |
181:96ed750bd169 | 1144 | |
Anna Bridge |
181:96ed750bd169 | 1145 | #define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ |
Anna Bridge |
181:96ed750bd169 | 1146 | #define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ |
Anna Bridge |
181:96ed750bd169 | 1147 | |
Anna Bridge |
181:96ed750bd169 | 1148 | #define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ |
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181:96ed750bd169 | 1149 | #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ |
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181:96ed750bd169 | 1150 | |
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181:96ed750bd169 | 1151 | #define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ |
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181:96ed750bd169 | 1152 | #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ |
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181:96ed750bd169 | 1153 | |
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181:96ed750bd169 | 1154 | #define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ |
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181:96ed750bd169 | 1155 | #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ |
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181:96ed750bd169 | 1156 | |
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181:96ed750bd169 | 1157 | #define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ |
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181:96ed750bd169 | 1158 | #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ |
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181:96ed750bd169 | 1159 | |
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181:96ed750bd169 | 1160 | #define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ |
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181:96ed750bd169 | 1161 | #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ |
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181:96ed750bd169 | 1162 | |
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181:96ed750bd169 | 1163 | /* ITM Integration Write Register Definitions */ |
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181:96ed750bd169 | 1164 | #define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ |
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181:96ed750bd169 | 1165 | #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ |
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181:96ed750bd169 | 1166 | |
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181:96ed750bd169 | 1167 | /* ITM Integration Read Register Definitions */ |
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181:96ed750bd169 | 1168 | #define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ |
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181:96ed750bd169 | 1169 | #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ |
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181:96ed750bd169 | 1170 | |
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181:96ed750bd169 | 1171 | /* ITM Integration Mode Control Register Definitions */ |
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181:96ed750bd169 | 1172 | #define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ |
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181:96ed750bd169 | 1173 | #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ |
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181:96ed750bd169 | 1174 | |
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181:96ed750bd169 | 1175 | /* ITM Lock Status Register Definitions */ |
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181:96ed750bd169 | 1176 | #define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ |
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181:96ed750bd169 | 1177 | #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ |
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181:96ed750bd169 | 1178 | |
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181:96ed750bd169 | 1179 | #define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ |
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181:96ed750bd169 | 1180 | #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ |
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181:96ed750bd169 | 1181 | |
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181:96ed750bd169 | 1182 | #define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ |
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181:96ed750bd169 | 1183 | #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ |
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181:96ed750bd169 | 1184 | |
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181:96ed750bd169 | 1185 | /*@}*/ /* end of group CMSIS_ITM */ |
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181:96ed750bd169 | 1186 | |
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181:96ed750bd169 | 1187 | |
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181:96ed750bd169 | 1188 | /** |
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181:96ed750bd169 | 1189 | \ingroup CMSIS_core_register |
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181:96ed750bd169 | 1190 | \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) |
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181:96ed750bd169 | 1191 | \brief Type definitions for the Data Watchpoint and Trace (DWT) |
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181:96ed750bd169 | 1192 | @{ |
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181:96ed750bd169 | 1193 | */ |
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181:96ed750bd169 | 1194 | |
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181:96ed750bd169 | 1195 | /** |
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181:96ed750bd169 | 1196 | \brief Structure type to access the Data Watchpoint and Trace Register (DWT). |
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181:96ed750bd169 | 1197 | */ |
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181:96ed750bd169 | 1198 | typedef struct |
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181:96ed750bd169 | 1199 | { |
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181:96ed750bd169 | 1200 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ |
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181:96ed750bd169 | 1201 | __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ |
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181:96ed750bd169 | 1202 | __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ |
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181:96ed750bd169 | 1203 | __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ |
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181:96ed750bd169 | 1204 | __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ |
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181:96ed750bd169 | 1205 | __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ |
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181:96ed750bd169 | 1206 | __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ |
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181:96ed750bd169 | 1207 | __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ |
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181:96ed750bd169 | 1208 | __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ |
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181:96ed750bd169 | 1209 | uint32_t RESERVED1[1U]; |
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181:96ed750bd169 | 1210 | __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ |
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181:96ed750bd169 | 1211 | uint32_t RESERVED2[1U]; |
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181:96ed750bd169 | 1212 | __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ |
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181:96ed750bd169 | 1213 | uint32_t RESERVED3[1U]; |
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181:96ed750bd169 | 1214 | __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ |
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181:96ed750bd169 | 1215 | uint32_t RESERVED4[1U]; |
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181:96ed750bd169 | 1216 | __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ |
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181:96ed750bd169 | 1217 | uint32_t RESERVED5[1U]; |
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181:96ed750bd169 | 1218 | __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ |
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181:96ed750bd169 | 1219 | uint32_t RESERVED6[1U]; |
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181:96ed750bd169 | 1220 | __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ |
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181:96ed750bd169 | 1221 | uint32_t RESERVED7[1U]; |
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181:96ed750bd169 | 1222 | __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ |
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181:96ed750bd169 | 1223 | uint32_t RESERVED8[1U]; |
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181:96ed750bd169 | 1224 | __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ |
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181:96ed750bd169 | 1225 | uint32_t RESERVED9[1U]; |
Anna Bridge |
181:96ed750bd169 | 1226 | __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ |
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181:96ed750bd169 | 1227 | uint32_t RESERVED10[1U]; |
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181:96ed750bd169 | 1228 | __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ |
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181:96ed750bd169 | 1229 | uint32_t RESERVED11[1U]; |
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181:96ed750bd169 | 1230 | __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ |
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181:96ed750bd169 | 1231 | uint32_t RESERVED12[1U]; |
Anna Bridge |
181:96ed750bd169 | 1232 | __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ |
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181:96ed750bd169 | 1233 | uint32_t RESERVED13[1U]; |
Anna Bridge |
181:96ed750bd169 | 1234 | __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ |
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181:96ed750bd169 | 1235 | uint32_t RESERVED14[1U]; |
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181:96ed750bd169 | 1236 | __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ |
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181:96ed750bd169 | 1237 | uint32_t RESERVED15[1U]; |
Anna Bridge |
181:96ed750bd169 | 1238 | __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ |
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181:96ed750bd169 | 1239 | uint32_t RESERVED16[1U]; |
Anna Bridge |
181:96ed750bd169 | 1240 | __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ |
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181:96ed750bd169 | 1241 | uint32_t RESERVED17[1U]; |
Anna Bridge |
181:96ed750bd169 | 1242 | __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ |
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181:96ed750bd169 | 1243 | uint32_t RESERVED18[1U]; |
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181:96ed750bd169 | 1244 | __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ |
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181:96ed750bd169 | 1245 | uint32_t RESERVED19[1U]; |
Anna Bridge |
181:96ed750bd169 | 1246 | __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ |
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181:96ed750bd169 | 1247 | uint32_t RESERVED20[1U]; |
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181:96ed750bd169 | 1248 | __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ |
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181:96ed750bd169 | 1249 | uint32_t RESERVED21[1U]; |
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181:96ed750bd169 | 1250 | __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ |
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181:96ed750bd169 | 1251 | uint32_t RESERVED22[1U]; |
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181:96ed750bd169 | 1252 | __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ |
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181:96ed750bd169 | 1253 | uint32_t RESERVED23[1U]; |
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181:96ed750bd169 | 1254 | __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ |
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181:96ed750bd169 | 1255 | uint32_t RESERVED24[1U]; |
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181:96ed750bd169 | 1256 | __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ |
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181:96ed750bd169 | 1257 | uint32_t RESERVED25[1U]; |
Anna Bridge |
181:96ed750bd169 | 1258 | __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ |
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181:96ed750bd169 | 1259 | uint32_t RESERVED26[1U]; |
Anna Bridge |
181:96ed750bd169 | 1260 | __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ |
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181:96ed750bd169 | 1261 | uint32_t RESERVED27[1U]; |
Anna Bridge |
181:96ed750bd169 | 1262 | __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ |
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181:96ed750bd169 | 1263 | uint32_t RESERVED28[1U]; |
Anna Bridge |
181:96ed750bd169 | 1264 | __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ |
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181:96ed750bd169 | 1265 | uint32_t RESERVED29[1U]; |
Anna Bridge |
181:96ed750bd169 | 1266 | __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ |
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181:96ed750bd169 | 1267 | uint32_t RESERVED30[1U]; |
Anna Bridge |
181:96ed750bd169 | 1268 | __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ |
Anna Bridge |
181:96ed750bd169 | 1269 | uint32_t RESERVED31[1U]; |
Anna Bridge |
181:96ed750bd169 | 1270 | __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ |
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181:96ed750bd169 | 1271 | uint32_t RESERVED32[934U]; |
Anna Bridge |
181:96ed750bd169 | 1272 | __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ |
Anna Bridge |
181:96ed750bd169 | 1273 | uint32_t RESERVED33[1U]; |
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181:96ed750bd169 | 1274 | __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ |
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181:96ed750bd169 | 1275 | } DWT_Type; |
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181:96ed750bd169 | 1276 | |
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181:96ed750bd169 | 1277 | /* DWT Control Register Definitions */ |
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181:96ed750bd169 | 1278 | #define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ |
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181:96ed750bd169 | 1279 | #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ |
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181:96ed750bd169 | 1280 | |
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181:96ed750bd169 | 1281 | #define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ |
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181:96ed750bd169 | 1282 | #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ |
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181:96ed750bd169 | 1283 | |
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181:96ed750bd169 | 1284 | #define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ |
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181:96ed750bd169 | 1285 | #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ |
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181:96ed750bd169 | 1286 | |
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181:96ed750bd169 | 1287 | #define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ |
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181:96ed750bd169 | 1288 | #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ |
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181:96ed750bd169 | 1289 | |
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181:96ed750bd169 | 1290 | #define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ |
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181:96ed750bd169 | 1291 | #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ |
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181:96ed750bd169 | 1292 | |
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181:96ed750bd169 | 1293 | #define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ |
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181:96ed750bd169 | 1294 | #define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ |
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181:96ed750bd169 | 1295 | |
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181:96ed750bd169 | 1296 | #define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ |
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181:96ed750bd169 | 1297 | #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ |
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181:96ed750bd169 | 1298 | |
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181:96ed750bd169 | 1299 | #define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ |
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181:96ed750bd169 | 1300 | #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ |
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181:96ed750bd169 | 1301 | |
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181:96ed750bd169 | 1302 | #define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ |
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181:96ed750bd169 | 1303 | #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ |
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181:96ed750bd169 | 1304 | |
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181:96ed750bd169 | 1305 | #define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ |
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181:96ed750bd169 | 1306 | #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ |
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181:96ed750bd169 | 1307 | |
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181:96ed750bd169 | 1308 | #define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ |
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181:96ed750bd169 | 1309 | #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ |
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181:96ed750bd169 | 1310 | |
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181:96ed750bd169 | 1311 | #define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ |
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181:96ed750bd169 | 1312 | #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ |
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181:96ed750bd169 | 1313 | |
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181:96ed750bd169 | 1314 | #define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ |
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181:96ed750bd169 | 1315 | #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ |
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181:96ed750bd169 | 1316 | |
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181:96ed750bd169 | 1317 | #define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ |
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181:96ed750bd169 | 1318 | #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ |
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181:96ed750bd169 | 1319 | |
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181:96ed750bd169 | 1320 | #define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ |
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181:96ed750bd169 | 1321 | #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ |
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181:96ed750bd169 | 1322 | |
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181:96ed750bd169 | 1323 | #define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ |
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181:96ed750bd169 | 1324 | #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ |
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181:96ed750bd169 | 1325 | |
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181:96ed750bd169 | 1326 | #define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ |
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181:96ed750bd169 | 1327 | #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ |
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181:96ed750bd169 | 1328 | |
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181:96ed750bd169 | 1329 | #define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ |
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181:96ed750bd169 | 1330 | #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ |
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181:96ed750bd169 | 1331 | |
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181:96ed750bd169 | 1332 | #define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ |
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181:96ed750bd169 | 1333 | #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ |
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181:96ed750bd169 | 1334 | |
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181:96ed750bd169 | 1335 | /* DWT CPI Count Register Definitions */ |
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181:96ed750bd169 | 1336 | #define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ |
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181:96ed750bd169 | 1337 | #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ |
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181:96ed750bd169 | 1338 | |
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181:96ed750bd169 | 1339 | /* DWT Exception Overhead Count Register Definitions */ |
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181:96ed750bd169 | 1340 | #define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ |
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181:96ed750bd169 | 1341 | #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ |
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181:96ed750bd169 | 1342 | |
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181:96ed750bd169 | 1343 | /* DWT Sleep Count Register Definitions */ |
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181:96ed750bd169 | 1344 | #define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ |
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181:96ed750bd169 | 1345 | #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ |
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181:96ed750bd169 | 1346 | |
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181:96ed750bd169 | 1347 | /* DWT LSU Count Register Definitions */ |
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181:96ed750bd169 | 1348 | #define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ |
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181:96ed750bd169 | 1349 | #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ |
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181:96ed750bd169 | 1350 | |
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181:96ed750bd169 | 1351 | /* DWT Folded-instruction Count Register Definitions */ |
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181:96ed750bd169 | 1352 | #define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ |
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181:96ed750bd169 | 1353 | #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ |
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181:96ed750bd169 | 1354 | |
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181:96ed750bd169 | 1355 | /* DWT Comparator Function Register Definitions */ |
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181:96ed750bd169 | 1356 | #define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ |
Anna Bridge |
181:96ed750bd169 | 1357 | #define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1358 | |
Anna Bridge |
181:96ed750bd169 | 1359 | #define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ |
Anna Bridge |
181:96ed750bd169 | 1360 | #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ |
Anna Bridge |
181:96ed750bd169 | 1361 | |
Anna Bridge |
181:96ed750bd169 | 1362 | #define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ |
Anna Bridge |
181:96ed750bd169 | 1363 | #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ |
Anna Bridge |
181:96ed750bd169 | 1364 | |
Anna Bridge |
181:96ed750bd169 | 1365 | #define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ |
Anna Bridge |
181:96ed750bd169 | 1366 | #define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ |
Anna Bridge |
181:96ed750bd169 | 1367 | |
Anna Bridge |
181:96ed750bd169 | 1368 | #define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ |
Anna Bridge |
181:96ed750bd169 | 1369 | #define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ |
Anna Bridge |
181:96ed750bd169 | 1370 | |
Anna Bridge |
181:96ed750bd169 | 1371 | /*@}*/ /* end of group CMSIS_DWT */ |
Anna Bridge |
181:96ed750bd169 | 1372 | |
Anna Bridge |
181:96ed750bd169 | 1373 | |
Anna Bridge |
181:96ed750bd169 | 1374 | /** |
Anna Bridge |
181:96ed750bd169 | 1375 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 1376 | \defgroup CMSIS_TPI Trace Port Interface (TPI) |
Anna Bridge |
181:96ed750bd169 | 1377 | \brief Type definitions for the Trace Port Interface (TPI) |
Anna Bridge |
181:96ed750bd169 | 1378 | @{ |
Anna Bridge |
181:96ed750bd169 | 1379 | */ |
Anna Bridge |
181:96ed750bd169 | 1380 | |
Anna Bridge |
181:96ed750bd169 | 1381 | /** |
Anna Bridge |
181:96ed750bd169 | 1382 | \brief Structure type to access the Trace Port Interface Register (TPI). |
Anna Bridge |
181:96ed750bd169 | 1383 | */ |
Anna Bridge |
181:96ed750bd169 | 1384 | typedef struct |
Anna Bridge |
181:96ed750bd169 | 1385 | { |
Anna Bridge |
181:96ed750bd169 | 1386 | __IOM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ |
Anna Bridge |
181:96ed750bd169 | 1387 | __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ |
Anna Bridge |
181:96ed750bd169 | 1388 | uint32_t RESERVED0[2U]; |
Anna Bridge |
181:96ed750bd169 | 1389 | __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ |
Anna Bridge |
181:96ed750bd169 | 1390 | uint32_t RESERVED1[55U]; |
Anna Bridge |
181:96ed750bd169 | 1391 | __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ |
Anna Bridge |
181:96ed750bd169 | 1392 | uint32_t RESERVED2[131U]; |
Anna Bridge |
181:96ed750bd169 | 1393 | __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ |
Anna Bridge |
181:96ed750bd169 | 1394 | __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ |
Anna Bridge |
181:96ed750bd169 | 1395 | __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ |
Anna Bridge |
181:96ed750bd169 | 1396 | uint32_t RESERVED3[759U]; |
Anna Bridge |
181:96ed750bd169 | 1397 | __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ |
Anna Bridge |
181:96ed750bd169 | 1398 | __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ |
Anna Bridge |
181:96ed750bd169 | 1399 | __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ |
Anna Bridge |
181:96ed750bd169 | 1400 | uint32_t RESERVED4[1U]; |
Anna Bridge |
181:96ed750bd169 | 1401 | __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ |
Anna Bridge |
181:96ed750bd169 | 1402 | __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ |
Anna Bridge |
181:96ed750bd169 | 1403 | __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ |
Anna Bridge |
181:96ed750bd169 | 1404 | uint32_t RESERVED5[39U]; |
Anna Bridge |
181:96ed750bd169 | 1405 | __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ |
Anna Bridge |
181:96ed750bd169 | 1406 | __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ |
Anna Bridge |
181:96ed750bd169 | 1407 | uint32_t RESERVED7[8U]; |
Anna Bridge |
181:96ed750bd169 | 1408 | __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ |
Anna Bridge |
181:96ed750bd169 | 1409 | __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ |
Anna Bridge |
181:96ed750bd169 | 1410 | } TPI_Type; |
Anna Bridge |
181:96ed750bd169 | 1411 | |
Anna Bridge |
181:96ed750bd169 | 1412 | /* TPI Asynchronous Clock Prescaler Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1413 | #define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ |
Anna Bridge |
181:96ed750bd169 | 1414 | #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ |
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181:96ed750bd169 | 1415 | |
Anna Bridge |
181:96ed750bd169 | 1416 | /* TPI Selected Pin Protocol Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1417 | #define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ |
Anna Bridge |
181:96ed750bd169 | 1418 | #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ |
Anna Bridge |
181:96ed750bd169 | 1419 | |
Anna Bridge |
181:96ed750bd169 | 1420 | /* TPI Formatter and Flush Status Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1421 | #define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ |
Anna Bridge |
181:96ed750bd169 | 1422 | #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ |
Anna Bridge |
181:96ed750bd169 | 1423 | |
Anna Bridge |
181:96ed750bd169 | 1424 | #define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ |
Anna Bridge |
181:96ed750bd169 | 1425 | #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ |
Anna Bridge |
181:96ed750bd169 | 1426 | |
Anna Bridge |
181:96ed750bd169 | 1427 | #define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ |
Anna Bridge |
181:96ed750bd169 | 1428 | #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ |
Anna Bridge |
181:96ed750bd169 | 1429 | |
Anna Bridge |
181:96ed750bd169 | 1430 | #define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ |
Anna Bridge |
181:96ed750bd169 | 1431 | #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ |
Anna Bridge |
181:96ed750bd169 | 1432 | |
Anna Bridge |
181:96ed750bd169 | 1433 | /* TPI Formatter and Flush Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1434 | #define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ |
Anna Bridge |
181:96ed750bd169 | 1435 | #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ |
Anna Bridge |
181:96ed750bd169 | 1436 | |
Anna Bridge |
181:96ed750bd169 | 1437 | #define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ |
Anna Bridge |
181:96ed750bd169 | 1438 | #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ |
Anna Bridge |
181:96ed750bd169 | 1439 | |
Anna Bridge |
181:96ed750bd169 | 1440 | /* TPI TRIGGER Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1441 | #define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ |
Anna Bridge |
181:96ed750bd169 | 1442 | #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ |
Anna Bridge |
181:96ed750bd169 | 1443 | |
Anna Bridge |
181:96ed750bd169 | 1444 | /* TPI Integration ETM Data Register Definitions (FIFO0) */ |
Anna Bridge |
181:96ed750bd169 | 1445 | #define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 1446 | #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1447 | |
Anna Bridge |
181:96ed750bd169 | 1448 | #define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ |
Anna Bridge |
181:96ed750bd169 | 1449 | #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ |
Anna Bridge |
181:96ed750bd169 | 1450 | |
Anna Bridge |
181:96ed750bd169 | 1451 | #define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 1452 | #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1453 | |
Anna Bridge |
181:96ed750bd169 | 1454 | #define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ |
Anna Bridge |
181:96ed750bd169 | 1455 | #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ |
Anna Bridge |
181:96ed750bd169 | 1456 | |
Anna Bridge |
181:96ed750bd169 | 1457 | #define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ |
Anna Bridge |
181:96ed750bd169 | 1458 | #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1459 | |
Anna Bridge |
181:96ed750bd169 | 1460 | #define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ |
Anna Bridge |
181:96ed750bd169 | 1461 | #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1462 | |
Anna Bridge |
181:96ed750bd169 | 1463 | #define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ |
Anna Bridge |
181:96ed750bd169 | 1464 | #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1465 | |
Anna Bridge |
181:96ed750bd169 | 1466 | /* TPI ITATBCTR2 Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1467 | #define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ |
Anna Bridge |
181:96ed750bd169 | 1468 | #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ |
Anna Bridge |
181:96ed750bd169 | 1469 | |
Anna Bridge |
181:96ed750bd169 | 1470 | /* TPI Integration ITM Data Register Definitions (FIFO1) */ |
Anna Bridge |
181:96ed750bd169 | 1471 | #define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 1472 | #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1473 | |
Anna Bridge |
181:96ed750bd169 | 1474 | #define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ |
Anna Bridge |
181:96ed750bd169 | 1475 | #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ |
Anna Bridge |
181:96ed750bd169 | 1476 | |
Anna Bridge |
181:96ed750bd169 | 1477 | #define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 1478 | #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1479 | |
Anna Bridge |
181:96ed750bd169 | 1480 | #define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ |
Anna Bridge |
181:96ed750bd169 | 1481 | #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ |
Anna Bridge |
181:96ed750bd169 | 1482 | |
Anna Bridge |
181:96ed750bd169 | 1483 | #define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ |
Anna Bridge |
181:96ed750bd169 | 1484 | #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1485 | |
Anna Bridge |
181:96ed750bd169 | 1486 | #define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ |
Anna Bridge |
181:96ed750bd169 | 1487 | #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1488 | |
Anna Bridge |
181:96ed750bd169 | 1489 | #define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ |
Anna Bridge |
181:96ed750bd169 | 1490 | #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1491 | |
Anna Bridge |
181:96ed750bd169 | 1492 | /* TPI ITATBCTR0 Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1493 | #define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ |
Anna Bridge |
181:96ed750bd169 | 1494 | #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ |
Anna Bridge |
181:96ed750bd169 | 1495 | |
Anna Bridge |
181:96ed750bd169 | 1496 | /* TPI Integration Mode Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1497 | #define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ |
Anna Bridge |
181:96ed750bd169 | 1498 | #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ |
Anna Bridge |
181:96ed750bd169 | 1499 | |
Anna Bridge |
181:96ed750bd169 | 1500 | /* TPI DEVID Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1501 | #define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 1502 | #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1503 | |
Anna Bridge |
181:96ed750bd169 | 1504 | #define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 1505 | #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1506 | |
Anna Bridge |
181:96ed750bd169 | 1507 | #define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 1508 | #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1509 | |
Anna Bridge |
181:96ed750bd169 | 1510 | #define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ |
Anna Bridge |
181:96ed750bd169 | 1511 | #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ |
Anna Bridge |
181:96ed750bd169 | 1512 | |
Anna Bridge |
181:96ed750bd169 | 1513 | #define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ |
Anna Bridge |
181:96ed750bd169 | 1514 | #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ |
Anna Bridge |
181:96ed750bd169 | 1515 | |
Anna Bridge |
181:96ed750bd169 | 1516 | #define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ |
Anna Bridge |
181:96ed750bd169 | 1517 | #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ |
Anna Bridge |
181:96ed750bd169 | 1518 | |
Anna Bridge |
181:96ed750bd169 | 1519 | /* TPI DEVTYPE Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1520 | #define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ |
Anna Bridge |
181:96ed750bd169 | 1521 | #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ |
Anna Bridge |
181:96ed750bd169 | 1522 | |
Anna Bridge |
181:96ed750bd169 | 1523 | #define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ |
Anna Bridge |
181:96ed750bd169 | 1524 | #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ |
Anna Bridge |
181:96ed750bd169 | 1525 | |
Anna Bridge |
181:96ed750bd169 | 1526 | /*@}*/ /* end of group CMSIS_TPI */ |
Anna Bridge |
181:96ed750bd169 | 1527 | |
Anna Bridge |
181:96ed750bd169 | 1528 | |
Anna Bridge |
181:96ed750bd169 | 1529 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 1530 | /** |
Anna Bridge |
181:96ed750bd169 | 1531 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 1532 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
Anna Bridge |
181:96ed750bd169 | 1533 | \brief Type definitions for the Memory Protection Unit (MPU) |
Anna Bridge |
181:96ed750bd169 | 1534 | @{ |
Anna Bridge |
181:96ed750bd169 | 1535 | */ |
Anna Bridge |
181:96ed750bd169 | 1536 | |
Anna Bridge |
181:96ed750bd169 | 1537 | /** |
Anna Bridge |
181:96ed750bd169 | 1538 | \brief Structure type to access the Memory Protection Unit (MPU). |
Anna Bridge |
181:96ed750bd169 | 1539 | */ |
Anna Bridge |
181:96ed750bd169 | 1540 | typedef struct |
Anna Bridge |
181:96ed750bd169 | 1541 | { |
Anna Bridge |
181:96ed750bd169 | 1542 | __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
Anna Bridge |
181:96ed750bd169 | 1543 | __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
Anna Bridge |
181:96ed750bd169 | 1544 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ |
Anna Bridge |
181:96ed750bd169 | 1545 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
Anna Bridge |
181:96ed750bd169 | 1546 | __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ |
Anna Bridge |
181:96ed750bd169 | 1547 | __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ |
Anna Bridge |
181:96ed750bd169 | 1548 | __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ |
Anna Bridge |
181:96ed750bd169 | 1549 | __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ |
Anna Bridge |
181:96ed750bd169 | 1550 | __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ |
Anna Bridge |
181:96ed750bd169 | 1551 | __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ |
Anna Bridge |
181:96ed750bd169 | 1552 | __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ |
Anna Bridge |
181:96ed750bd169 | 1553 | uint32_t RESERVED0[1]; |
Anna Bridge |
181:96ed750bd169 | 1554 | union { |
Anna Bridge |
181:96ed750bd169 | 1555 | __IOM uint32_t MAIR[2]; |
Anna Bridge |
181:96ed750bd169 | 1556 | struct { |
Anna Bridge |
181:96ed750bd169 | 1557 | __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ |
Anna Bridge |
181:96ed750bd169 | 1558 | __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ |
Anna Bridge |
181:96ed750bd169 | 1559 | }; |
Anna Bridge |
181:96ed750bd169 | 1560 | }; |
Anna Bridge |
181:96ed750bd169 | 1561 | } MPU_Type; |
Anna Bridge |
181:96ed750bd169 | 1562 | |
Anna Bridge |
181:96ed750bd169 | 1563 | #define MPU_TYPE_RALIASES 4U |
Anna Bridge |
181:96ed750bd169 | 1564 | |
Anna Bridge |
181:96ed750bd169 | 1565 | /* MPU Type Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1566 | #define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ |
Anna Bridge |
181:96ed750bd169 | 1567 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
Anna Bridge |
181:96ed750bd169 | 1568 | |
Anna Bridge |
181:96ed750bd169 | 1569 | #define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ |
Anna Bridge |
181:96ed750bd169 | 1570 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
Anna Bridge |
181:96ed750bd169 | 1571 | |
Anna Bridge |
181:96ed750bd169 | 1572 | #define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ |
Anna Bridge |
181:96ed750bd169 | 1573 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
Anna Bridge |
181:96ed750bd169 | 1574 | |
Anna Bridge |
181:96ed750bd169 | 1575 | /* MPU Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1576 | #define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ |
Anna Bridge |
181:96ed750bd169 | 1577 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
Anna Bridge |
181:96ed750bd169 | 1578 | |
Anna Bridge |
181:96ed750bd169 | 1579 | #define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ |
Anna Bridge |
181:96ed750bd169 | 1580 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
Anna Bridge |
181:96ed750bd169 | 1581 | |
Anna Bridge |
181:96ed750bd169 | 1582 | #define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ |
Anna Bridge |
181:96ed750bd169 | 1583 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
Anna Bridge |
181:96ed750bd169 | 1584 | |
Anna Bridge |
181:96ed750bd169 | 1585 | /* MPU Region Number Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1586 | #define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ |
Anna Bridge |
181:96ed750bd169 | 1587 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
Anna Bridge |
181:96ed750bd169 | 1588 | |
Anna Bridge |
181:96ed750bd169 | 1589 | /* MPU Region Base Address Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1590 | #define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: ADDR Position */ |
Anna Bridge |
181:96ed750bd169 | 1591 | #define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: ADDR Mask */ |
Anna Bridge |
181:96ed750bd169 | 1592 | |
Anna Bridge |
181:96ed750bd169 | 1593 | #define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ |
Anna Bridge |
181:96ed750bd169 | 1594 | #define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ |
Anna Bridge |
181:96ed750bd169 | 1595 | |
Anna Bridge |
181:96ed750bd169 | 1596 | #define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ |
Anna Bridge |
181:96ed750bd169 | 1597 | #define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ |
Anna Bridge |
181:96ed750bd169 | 1598 | |
Anna Bridge |
181:96ed750bd169 | 1599 | #define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ |
Anna Bridge |
181:96ed750bd169 | 1600 | #define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ |
Anna Bridge |
181:96ed750bd169 | 1601 | |
Anna Bridge |
181:96ed750bd169 | 1602 | /* MPU Region Limit Address Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1603 | #define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ |
Anna Bridge |
181:96ed750bd169 | 1604 | #define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ |
Anna Bridge |
181:96ed750bd169 | 1605 | |
Anna Bridge |
181:96ed750bd169 | 1606 | #define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ |
Anna Bridge |
181:96ed750bd169 | 1607 | #define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ |
Anna Bridge |
181:96ed750bd169 | 1608 | |
Anna Bridge |
181:96ed750bd169 | 1609 | #define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ |
Anna Bridge |
181:96ed750bd169 | 1610 | #define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ |
Anna Bridge |
181:96ed750bd169 | 1611 | |
Anna Bridge |
181:96ed750bd169 | 1612 | /* MPU Memory Attribute Indirection Register 0 Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1613 | #define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ |
Anna Bridge |
181:96ed750bd169 | 1614 | #define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1615 | |
Anna Bridge |
181:96ed750bd169 | 1616 | #define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ |
Anna Bridge |
181:96ed750bd169 | 1617 | #define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1618 | |
Anna Bridge |
181:96ed750bd169 | 1619 | #define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ |
Anna Bridge |
181:96ed750bd169 | 1620 | #define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1621 | |
Anna Bridge |
181:96ed750bd169 | 1622 | #define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ |
Anna Bridge |
181:96ed750bd169 | 1623 | #define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1624 | |
Anna Bridge |
181:96ed750bd169 | 1625 | /* MPU Memory Attribute Indirection Register 1 Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1626 | #define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ |
Anna Bridge |
181:96ed750bd169 | 1627 | #define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1628 | |
Anna Bridge |
181:96ed750bd169 | 1629 | #define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ |
Anna Bridge |
181:96ed750bd169 | 1630 | #define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1631 | |
Anna Bridge |
181:96ed750bd169 | 1632 | #define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ |
Anna Bridge |
181:96ed750bd169 | 1633 | #define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1634 | |
Anna Bridge |
181:96ed750bd169 | 1635 | #define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ |
Anna Bridge |
181:96ed750bd169 | 1636 | #define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ |
Anna Bridge |
181:96ed750bd169 | 1637 | |
Anna Bridge |
181:96ed750bd169 | 1638 | /*@} end of group CMSIS_MPU */ |
Anna Bridge |
181:96ed750bd169 | 1639 | #endif |
Anna Bridge |
181:96ed750bd169 | 1640 | |
Anna Bridge |
181:96ed750bd169 | 1641 | |
Anna Bridge |
181:96ed750bd169 | 1642 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
Anna Bridge |
181:96ed750bd169 | 1643 | /** |
Anna Bridge |
181:96ed750bd169 | 1644 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 1645 | \defgroup CMSIS_SAU Security Attribution Unit (SAU) |
Anna Bridge |
181:96ed750bd169 | 1646 | \brief Type definitions for the Security Attribution Unit (SAU) |
Anna Bridge |
181:96ed750bd169 | 1647 | @{ |
Anna Bridge |
181:96ed750bd169 | 1648 | */ |
Anna Bridge |
181:96ed750bd169 | 1649 | |
Anna Bridge |
181:96ed750bd169 | 1650 | /** |
Anna Bridge |
181:96ed750bd169 | 1651 | \brief Structure type to access the Security Attribution Unit (SAU). |
Anna Bridge |
181:96ed750bd169 | 1652 | */ |
Anna Bridge |
181:96ed750bd169 | 1653 | typedef struct |
Anna Bridge |
181:96ed750bd169 | 1654 | { |
Anna Bridge |
181:96ed750bd169 | 1655 | __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ |
Anna Bridge |
181:96ed750bd169 | 1656 | __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ |
Anna Bridge |
181:96ed750bd169 | 1657 | #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 1658 | __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ |
Anna Bridge |
181:96ed750bd169 | 1659 | __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ |
Anna Bridge |
181:96ed750bd169 | 1660 | __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ |
Anna Bridge |
181:96ed750bd169 | 1661 | #else |
Anna Bridge |
181:96ed750bd169 | 1662 | uint32_t RESERVED0[3]; |
Anna Bridge |
181:96ed750bd169 | 1663 | #endif |
Anna Bridge |
181:96ed750bd169 | 1664 | __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ |
Anna Bridge |
181:96ed750bd169 | 1665 | __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ |
Anna Bridge |
181:96ed750bd169 | 1666 | } SAU_Type; |
Anna Bridge |
181:96ed750bd169 | 1667 | |
Anna Bridge |
181:96ed750bd169 | 1668 | /* SAU Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1669 | #define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ |
Anna Bridge |
181:96ed750bd169 | 1670 | #define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ |
Anna Bridge |
181:96ed750bd169 | 1671 | |
Anna Bridge |
181:96ed750bd169 | 1672 | #define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ |
Anna Bridge |
181:96ed750bd169 | 1673 | #define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ |
Anna Bridge |
181:96ed750bd169 | 1674 | |
Anna Bridge |
181:96ed750bd169 | 1675 | /* SAU Type Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1676 | #define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ |
Anna Bridge |
181:96ed750bd169 | 1677 | #define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ |
Anna Bridge |
181:96ed750bd169 | 1678 | |
Anna Bridge |
181:96ed750bd169 | 1679 | #if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 1680 | /* SAU Region Number Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1681 | #define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ |
Anna Bridge |
181:96ed750bd169 | 1682 | #define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ |
Anna Bridge |
181:96ed750bd169 | 1683 | |
Anna Bridge |
181:96ed750bd169 | 1684 | /* SAU Region Base Address Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1685 | #define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ |
Anna Bridge |
181:96ed750bd169 | 1686 | #define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ |
Anna Bridge |
181:96ed750bd169 | 1687 | |
Anna Bridge |
181:96ed750bd169 | 1688 | /* SAU Region Limit Address Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1689 | #define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ |
Anna Bridge |
181:96ed750bd169 | 1690 | #define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ |
Anna Bridge |
181:96ed750bd169 | 1691 | |
Anna Bridge |
181:96ed750bd169 | 1692 | #define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ |
Anna Bridge |
181:96ed750bd169 | 1693 | #define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ |
Anna Bridge |
181:96ed750bd169 | 1694 | |
Anna Bridge |
181:96ed750bd169 | 1695 | #define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ |
Anna Bridge |
181:96ed750bd169 | 1696 | #define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ |
Anna Bridge |
181:96ed750bd169 | 1697 | |
Anna Bridge |
181:96ed750bd169 | 1698 | #endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ |
Anna Bridge |
181:96ed750bd169 | 1699 | |
Anna Bridge |
181:96ed750bd169 | 1700 | /* Secure Fault Status Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1701 | #define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ |
Anna Bridge |
181:96ed750bd169 | 1702 | #define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 1703 | |
Anna Bridge |
181:96ed750bd169 | 1704 | #define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ |
Anna Bridge |
181:96ed750bd169 | 1705 | #define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ |
Anna Bridge |
181:96ed750bd169 | 1706 | |
Anna Bridge |
181:96ed750bd169 | 1707 | #define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ |
Anna Bridge |
181:96ed750bd169 | 1708 | #define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ |
Anna Bridge |
181:96ed750bd169 | 1709 | |
Anna Bridge |
181:96ed750bd169 | 1710 | #define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ |
Anna Bridge |
181:96ed750bd169 | 1711 | #define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ |
Anna Bridge |
181:96ed750bd169 | 1712 | |
Anna Bridge |
181:96ed750bd169 | 1713 | #define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ |
Anna Bridge |
181:96ed750bd169 | 1714 | #define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ |
Anna Bridge |
181:96ed750bd169 | 1715 | |
Anna Bridge |
181:96ed750bd169 | 1716 | #define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ |
Anna Bridge |
181:96ed750bd169 | 1717 | #define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ |
Anna Bridge |
181:96ed750bd169 | 1718 | |
Anna Bridge |
181:96ed750bd169 | 1719 | #define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ |
Anna Bridge |
181:96ed750bd169 | 1720 | #define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ |
Anna Bridge |
181:96ed750bd169 | 1721 | |
Anna Bridge |
181:96ed750bd169 | 1722 | #define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ |
Anna Bridge |
181:96ed750bd169 | 1723 | #define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ |
Anna Bridge |
181:96ed750bd169 | 1724 | |
Anna Bridge |
181:96ed750bd169 | 1725 | /*@} end of group CMSIS_SAU */ |
Anna Bridge |
181:96ed750bd169 | 1726 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
Anna Bridge |
181:96ed750bd169 | 1727 | |
Anna Bridge |
181:96ed750bd169 | 1728 | |
Anna Bridge |
181:96ed750bd169 | 1729 | /** |
Anna Bridge |
181:96ed750bd169 | 1730 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 1731 | \defgroup CMSIS_FPU Floating Point Unit (FPU) |
Anna Bridge |
181:96ed750bd169 | 1732 | \brief Type definitions for the Floating Point Unit (FPU) |
Anna Bridge |
181:96ed750bd169 | 1733 | @{ |
Anna Bridge |
181:96ed750bd169 | 1734 | */ |
Anna Bridge |
181:96ed750bd169 | 1735 | |
Anna Bridge |
181:96ed750bd169 | 1736 | /** |
Anna Bridge |
181:96ed750bd169 | 1737 | \brief Structure type to access the Floating Point Unit (FPU). |
Anna Bridge |
181:96ed750bd169 | 1738 | */ |
Anna Bridge |
181:96ed750bd169 | 1739 | typedef struct |
Anna Bridge |
181:96ed750bd169 | 1740 | { |
Anna Bridge |
181:96ed750bd169 | 1741 | uint32_t RESERVED0[1U]; |
Anna Bridge |
181:96ed750bd169 | 1742 | __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ |
Anna Bridge |
181:96ed750bd169 | 1743 | __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ |
Anna Bridge |
181:96ed750bd169 | 1744 | __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ |
Anna Bridge |
181:96ed750bd169 | 1745 | __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ |
Anna Bridge |
181:96ed750bd169 | 1746 | __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ |
Anna Bridge |
181:96ed750bd169 | 1747 | } FPU_Type; |
Anna Bridge |
181:96ed750bd169 | 1748 | |
Anna Bridge |
181:96ed750bd169 | 1749 | /* Floating-Point Context Control Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1750 | #define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ |
Anna Bridge |
181:96ed750bd169 | 1751 | #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1752 | |
Anna Bridge |
181:96ed750bd169 | 1753 | #define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ |
Anna Bridge |
181:96ed750bd169 | 1754 | #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1755 | |
Anna Bridge |
181:96ed750bd169 | 1756 | #define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ |
Anna Bridge |
181:96ed750bd169 | 1757 | #define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1758 | |
Anna Bridge |
181:96ed750bd169 | 1759 | #define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ |
Anna Bridge |
181:96ed750bd169 | 1760 | #define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1761 | |
Anna Bridge |
181:96ed750bd169 | 1762 | #define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ |
Anna Bridge |
181:96ed750bd169 | 1763 | #define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1764 | |
Anna Bridge |
181:96ed750bd169 | 1765 | #define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ |
Anna Bridge |
181:96ed750bd169 | 1766 | #define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1767 | |
Anna Bridge |
181:96ed750bd169 | 1768 | #define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ |
Anna Bridge |
181:96ed750bd169 | 1769 | #define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1770 | |
Anna Bridge |
181:96ed750bd169 | 1771 | #define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ |
Anna Bridge |
181:96ed750bd169 | 1772 | #define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1773 | |
Anna Bridge |
181:96ed750bd169 | 1774 | #define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ |
Anna Bridge |
181:96ed750bd169 | 1775 | #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1776 | |
Anna Bridge |
181:96ed750bd169 | 1777 | #define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ |
Anna Bridge |
181:96ed750bd169 | 1778 | #define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1779 | |
Anna Bridge |
181:96ed750bd169 | 1780 | #define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ |
Anna Bridge |
181:96ed750bd169 | 1781 | #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ |
Anna Bridge |
181:96ed750bd169 | 1782 | |
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181:96ed750bd169 | 1783 | #define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ |
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181:96ed750bd169 | 1784 | #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ |
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181:96ed750bd169 | 1785 | |
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181:96ed750bd169 | 1786 | #define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ |
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181:96ed750bd169 | 1787 | #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ |
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181:96ed750bd169 | 1788 | |
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181:96ed750bd169 | 1789 | #define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ |
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181:96ed750bd169 | 1790 | #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ |
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181:96ed750bd169 | 1791 | |
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181:96ed750bd169 | 1792 | #define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ |
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181:96ed750bd169 | 1793 | #define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ |
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181:96ed750bd169 | 1794 | |
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181:96ed750bd169 | 1795 | #define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ |
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181:96ed750bd169 | 1796 | #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ |
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181:96ed750bd169 | 1797 | |
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181:96ed750bd169 | 1798 | #define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ |
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181:96ed750bd169 | 1799 | #define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ |
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181:96ed750bd169 | 1800 | |
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181:96ed750bd169 | 1801 | /* Floating-Point Context Address Register Definitions */ |
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181:96ed750bd169 | 1802 | #define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ |
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181:96ed750bd169 | 1803 | #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ |
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181:96ed750bd169 | 1804 | |
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181:96ed750bd169 | 1805 | /* Floating-Point Default Status Control Register Definitions */ |
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181:96ed750bd169 | 1806 | #define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ |
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181:96ed750bd169 | 1807 | #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ |
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181:96ed750bd169 | 1808 | |
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181:96ed750bd169 | 1809 | #define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ |
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181:96ed750bd169 | 1810 | #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ |
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181:96ed750bd169 | 1811 | |
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181:96ed750bd169 | 1812 | #define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ |
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181:96ed750bd169 | 1813 | #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ |
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181:96ed750bd169 | 1814 | |
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181:96ed750bd169 | 1815 | #define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ |
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181:96ed750bd169 | 1816 | #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ |
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181:96ed750bd169 | 1817 | |
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181:96ed750bd169 | 1818 | /* Media and FP Feature Register 0 Definitions */ |
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181:96ed750bd169 | 1819 | #define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ |
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181:96ed750bd169 | 1820 | #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ |
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181:96ed750bd169 | 1821 | |
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181:96ed750bd169 | 1822 | #define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ |
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181:96ed750bd169 | 1823 | #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ |
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181:96ed750bd169 | 1824 | |
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181:96ed750bd169 | 1825 | #define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ |
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181:96ed750bd169 | 1826 | #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ |
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181:96ed750bd169 | 1827 | |
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181:96ed750bd169 | 1828 | #define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ |
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181:96ed750bd169 | 1829 | #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ |
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181:96ed750bd169 | 1830 | |
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181:96ed750bd169 | 1831 | #define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ |
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181:96ed750bd169 | 1832 | #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ |
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181:96ed750bd169 | 1833 | |
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181:96ed750bd169 | 1834 | #define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ |
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181:96ed750bd169 | 1835 | #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ |
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181:96ed750bd169 | 1836 | |
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181:96ed750bd169 | 1837 | #define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ |
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181:96ed750bd169 | 1838 | #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ |
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181:96ed750bd169 | 1839 | |
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181:96ed750bd169 | 1840 | #define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ |
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181:96ed750bd169 | 1841 | #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ |
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181:96ed750bd169 | 1842 | |
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181:96ed750bd169 | 1843 | /* Media and FP Feature Register 1 Definitions */ |
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181:96ed750bd169 | 1844 | #define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ |
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181:96ed750bd169 | 1845 | #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ |
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181:96ed750bd169 | 1846 | |
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181:96ed750bd169 | 1847 | #define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ |
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181:96ed750bd169 | 1848 | #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ |
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181:96ed750bd169 | 1849 | |
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181:96ed750bd169 | 1850 | #define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ |
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181:96ed750bd169 | 1851 | #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ |
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181:96ed750bd169 | 1852 | |
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181:96ed750bd169 | 1853 | #define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ |
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181:96ed750bd169 | 1854 | #define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ |
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181:96ed750bd169 | 1855 | |
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181:96ed750bd169 | 1856 | /*@} end of group CMSIS_FPU */ |
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181:96ed750bd169 | 1857 | |
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181:96ed750bd169 | 1858 | |
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181:96ed750bd169 | 1859 | /** |
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181:96ed750bd169 | 1860 | \ingroup CMSIS_core_register |
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181:96ed750bd169 | 1861 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
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181:96ed750bd169 | 1862 | \brief Type definitions for the Core Debug Registers |
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181:96ed750bd169 | 1863 | @{ |
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181:96ed750bd169 | 1864 | */ |
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181:96ed750bd169 | 1865 | |
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181:96ed750bd169 | 1866 | /** |
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181:96ed750bd169 | 1867 | \brief Structure type to access the Core Debug Register (CoreDebug). |
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181:96ed750bd169 | 1868 | */ |
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181:96ed750bd169 | 1869 | typedef struct |
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181:96ed750bd169 | 1870 | { |
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181:96ed750bd169 | 1871 | __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ |
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181:96ed750bd169 | 1872 | __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ |
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181:96ed750bd169 | 1873 | __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ |
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181:96ed750bd169 | 1874 | __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ |
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181:96ed750bd169 | 1875 | uint32_t RESERVED4[1U]; |
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181:96ed750bd169 | 1876 | __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ |
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181:96ed750bd169 | 1877 | __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ |
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181:96ed750bd169 | 1878 | } CoreDebug_Type; |
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181:96ed750bd169 | 1879 | |
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181:96ed750bd169 | 1880 | /* Debug Halting Control and Status Register Definitions */ |
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181:96ed750bd169 | 1881 | #define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ |
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181:96ed750bd169 | 1882 | #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ |
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181:96ed750bd169 | 1883 | |
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181:96ed750bd169 | 1884 | #define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ |
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181:96ed750bd169 | 1885 | #define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ |
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181:96ed750bd169 | 1886 | |
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181:96ed750bd169 | 1887 | #define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ |
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181:96ed750bd169 | 1888 | #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ |
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181:96ed750bd169 | 1889 | |
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181:96ed750bd169 | 1890 | #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ |
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181:96ed750bd169 | 1891 | #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ |
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181:96ed750bd169 | 1892 | |
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181:96ed750bd169 | 1893 | #define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ |
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181:96ed750bd169 | 1894 | #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ |
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181:96ed750bd169 | 1895 | |
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181:96ed750bd169 | 1896 | #define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ |
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181:96ed750bd169 | 1897 | #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ |
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181:96ed750bd169 | 1898 | |
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181:96ed750bd169 | 1899 | #define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ |
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181:96ed750bd169 | 1900 | #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ |
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181:96ed750bd169 | 1901 | |
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181:96ed750bd169 | 1902 | #define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ |
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181:96ed750bd169 | 1903 | #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ |
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181:96ed750bd169 | 1904 | |
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181:96ed750bd169 | 1905 | #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ |
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181:96ed750bd169 | 1906 | #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ |
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181:96ed750bd169 | 1907 | |
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181:96ed750bd169 | 1908 | #define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ |
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181:96ed750bd169 | 1909 | #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ |
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181:96ed750bd169 | 1910 | |
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181:96ed750bd169 | 1911 | #define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ |
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181:96ed750bd169 | 1912 | #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ |
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181:96ed750bd169 | 1913 | |
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181:96ed750bd169 | 1914 | #define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ |
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181:96ed750bd169 | 1915 | #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ |
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181:96ed750bd169 | 1916 | |
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181:96ed750bd169 | 1917 | #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ |
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181:96ed750bd169 | 1918 | #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ |
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181:96ed750bd169 | 1919 | |
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181:96ed750bd169 | 1920 | /* Debug Core Register Selector Register Definitions */ |
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181:96ed750bd169 | 1921 | #define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ |
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181:96ed750bd169 | 1922 | #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ |
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181:96ed750bd169 | 1923 | |
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181:96ed750bd169 | 1924 | #define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ |
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181:96ed750bd169 | 1925 | #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ |
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181:96ed750bd169 | 1926 | |
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181:96ed750bd169 | 1927 | /* Debug Exception and Monitor Control Register Definitions */ |
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181:96ed750bd169 | 1928 | #define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ |
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181:96ed750bd169 | 1929 | #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ |
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181:96ed750bd169 | 1930 | |
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181:96ed750bd169 | 1931 | #define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ |
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181:96ed750bd169 | 1932 | #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ |
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181:96ed750bd169 | 1933 | |
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181:96ed750bd169 | 1934 | #define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ |
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181:96ed750bd169 | 1935 | #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ |
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181:96ed750bd169 | 1936 | |
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181:96ed750bd169 | 1937 | #define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ |
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181:96ed750bd169 | 1938 | #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ |
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181:96ed750bd169 | 1939 | |
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181:96ed750bd169 | 1940 | #define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ |
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181:96ed750bd169 | 1941 | #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ |
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181:96ed750bd169 | 1942 | |
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181:96ed750bd169 | 1943 | #define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ |
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181:96ed750bd169 | 1944 | #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ |
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181:96ed750bd169 | 1945 | |
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181:96ed750bd169 | 1946 | #define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ |
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181:96ed750bd169 | 1947 | #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ |
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181:96ed750bd169 | 1948 | |
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181:96ed750bd169 | 1949 | #define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ |
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181:96ed750bd169 | 1950 | #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ |
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181:96ed750bd169 | 1951 | |
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181:96ed750bd169 | 1952 | #define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ |
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181:96ed750bd169 | 1953 | #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ |
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181:96ed750bd169 | 1954 | |
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181:96ed750bd169 | 1955 | #define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ |
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181:96ed750bd169 | 1956 | #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ |
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181:96ed750bd169 | 1957 | |
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181:96ed750bd169 | 1958 | #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ |
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181:96ed750bd169 | 1959 | #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ |
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181:96ed750bd169 | 1960 | |
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181:96ed750bd169 | 1961 | #define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ |
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181:96ed750bd169 | 1962 | #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ |
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181:96ed750bd169 | 1963 | |
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181:96ed750bd169 | 1964 | #define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ |
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181:96ed750bd169 | 1965 | #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ |
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181:96ed750bd169 | 1966 | |
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181:96ed750bd169 | 1967 | /* Debug Authentication Control Register Definitions */ |
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181:96ed750bd169 | 1968 | #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ |
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181:96ed750bd169 | 1969 | #define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ |
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181:96ed750bd169 | 1970 | |
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181:96ed750bd169 | 1971 | #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ |
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181:96ed750bd169 | 1972 | #define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ |
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181:96ed750bd169 | 1973 | |
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181:96ed750bd169 | 1974 | #define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ |
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181:96ed750bd169 | 1975 | #define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ |
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181:96ed750bd169 | 1976 | |
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181:96ed750bd169 | 1977 | #define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ |
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181:96ed750bd169 | 1978 | #define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ |
Anna Bridge |
181:96ed750bd169 | 1979 | |
Anna Bridge |
181:96ed750bd169 | 1980 | /* Debug Security Control and Status Register Definitions */ |
Anna Bridge |
181:96ed750bd169 | 1981 | #define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ |
Anna Bridge |
181:96ed750bd169 | 1982 | #define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ |
Anna Bridge |
181:96ed750bd169 | 1983 | |
Anna Bridge |
181:96ed750bd169 | 1984 | #define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ |
Anna Bridge |
181:96ed750bd169 | 1985 | #define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ |
Anna Bridge |
181:96ed750bd169 | 1986 | |
Anna Bridge |
181:96ed750bd169 | 1987 | #define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ |
Anna Bridge |
181:96ed750bd169 | 1988 | #define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ |
Anna Bridge |
181:96ed750bd169 | 1989 | |
Anna Bridge |
181:96ed750bd169 | 1990 | /*@} end of group CMSIS_CoreDebug */ |
Anna Bridge |
181:96ed750bd169 | 1991 | |
Anna Bridge |
181:96ed750bd169 | 1992 | |
Anna Bridge |
181:96ed750bd169 | 1993 | /** |
Anna Bridge |
181:96ed750bd169 | 1994 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 1995 | \defgroup CMSIS_core_bitfield Core register bit field macros |
Anna Bridge |
181:96ed750bd169 | 1996 | \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). |
Anna Bridge |
181:96ed750bd169 | 1997 | @{ |
Anna Bridge |
181:96ed750bd169 | 1998 | */ |
Anna Bridge |
181:96ed750bd169 | 1999 | |
Anna Bridge |
181:96ed750bd169 | 2000 | /** |
Anna Bridge |
181:96ed750bd169 | 2001 | \brief Mask and shift a bit field value for use in a register bit range. |
Anna Bridge |
181:96ed750bd169 | 2002 | \param[in] field Name of the register bit field. |
Anna Bridge |
181:96ed750bd169 | 2003 | \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. |
Anna Bridge |
181:96ed750bd169 | 2004 | \return Masked and shifted value. |
Anna Bridge |
181:96ed750bd169 | 2005 | */ |
Anna Bridge |
181:96ed750bd169 | 2006 | #define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) |
Anna Bridge |
181:96ed750bd169 | 2007 | |
Anna Bridge |
181:96ed750bd169 | 2008 | /** |
Anna Bridge |
181:96ed750bd169 | 2009 | \brief Mask and shift a register value to extract a bit filed value. |
Anna Bridge |
181:96ed750bd169 | 2010 | \param[in] field Name of the register bit field. |
Anna Bridge |
181:96ed750bd169 | 2011 | \param[in] value Value of register. This parameter is interpreted as an uint32_t type. |
Anna Bridge |
181:96ed750bd169 | 2012 | \return Masked and shifted bit field value. |
Anna Bridge |
181:96ed750bd169 | 2013 | */ |
Anna Bridge |
181:96ed750bd169 | 2014 | #define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) |
Anna Bridge |
181:96ed750bd169 | 2015 | |
Anna Bridge |
181:96ed750bd169 | 2016 | /*@} end of group CMSIS_core_bitfield */ |
Anna Bridge |
181:96ed750bd169 | 2017 | |
Anna Bridge |
181:96ed750bd169 | 2018 | |
Anna Bridge |
181:96ed750bd169 | 2019 | /** |
Anna Bridge |
181:96ed750bd169 | 2020 | \ingroup CMSIS_core_register |
Anna Bridge |
181:96ed750bd169 | 2021 | \defgroup CMSIS_core_base Core Definitions |
Anna Bridge |
181:96ed750bd169 | 2022 | \brief Definitions for base addresses, unions, and structures. |
Anna Bridge |
181:96ed750bd169 | 2023 | @{ |
Anna Bridge |
181:96ed750bd169 | 2024 | */ |
Anna Bridge |
181:96ed750bd169 | 2025 | |
Anna Bridge |
181:96ed750bd169 | 2026 | /* Memory mapping of Core Hardware */ |
Anna Bridge |
181:96ed750bd169 | 2027 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
Anna Bridge |
181:96ed750bd169 | 2028 | #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ |
Anna Bridge |
181:96ed750bd169 | 2029 | #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ |
Anna Bridge |
181:96ed750bd169 | 2030 | #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ |
Anna Bridge |
181:96ed750bd169 | 2031 | #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ |
Anna Bridge |
181:96ed750bd169 | 2032 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
Anna Bridge |
181:96ed750bd169 | 2033 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
Anna Bridge |
181:96ed750bd169 | 2034 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
Anna Bridge |
181:96ed750bd169 | 2035 | |
Anna Bridge |
181:96ed750bd169 | 2036 | #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ |
Anna Bridge |
181:96ed750bd169 | 2037 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
Anna Bridge |
181:96ed750bd169 | 2038 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
Anna Bridge |
181:96ed750bd169 | 2039 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
Anna Bridge |
181:96ed750bd169 | 2040 | #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ |
Anna Bridge |
181:96ed750bd169 | 2041 | #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ |
Anna Bridge |
181:96ed750bd169 | 2042 | #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ |
Anna Bridge |
181:96ed750bd169 | 2043 | #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ |
Anna Bridge |
181:96ed750bd169 | 2044 | |
Anna Bridge |
181:96ed750bd169 | 2045 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 2046 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
Anna Bridge |
181:96ed750bd169 | 2047 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
Anna Bridge |
181:96ed750bd169 | 2048 | #endif |
Anna Bridge |
181:96ed750bd169 | 2049 | |
Anna Bridge |
181:96ed750bd169 | 2050 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
Anna Bridge |
181:96ed750bd169 | 2051 | #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ |
Anna Bridge |
181:96ed750bd169 | 2052 | #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ |
Anna Bridge |
181:96ed750bd169 | 2053 | #endif |
Anna Bridge |
181:96ed750bd169 | 2054 | |
Anna Bridge |
181:96ed750bd169 | 2055 | #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ |
Anna Bridge |
181:96ed750bd169 | 2056 | #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ |
Anna Bridge |
181:96ed750bd169 | 2057 | |
Anna Bridge |
181:96ed750bd169 | 2058 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
Anna Bridge |
181:96ed750bd169 | 2059 | #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2060 | #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2061 | #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2062 | #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2063 | #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2064 | |
Anna Bridge |
181:96ed750bd169 | 2065 | #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2066 | #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2067 | #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2068 | #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2069 | #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2070 | |
Anna Bridge |
181:96ed750bd169 | 2071 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 2072 | #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2073 | #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2074 | #endif |
Anna Bridge |
181:96ed750bd169 | 2075 | |
Anna Bridge |
181:96ed750bd169 | 2076 | #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2077 | #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ |
Anna Bridge |
181:96ed750bd169 | 2078 | |
Anna Bridge |
181:96ed750bd169 | 2079 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
Anna Bridge |
181:96ed750bd169 | 2080 | /*@} */ |
Anna Bridge |
181:96ed750bd169 | 2081 | |
Anna Bridge |
181:96ed750bd169 | 2082 | |
Anna Bridge |
181:96ed750bd169 | 2083 | |
Anna Bridge |
181:96ed750bd169 | 2084 | /******************************************************************************* |
Anna Bridge |
181:96ed750bd169 | 2085 | * Hardware Abstraction Layer |
Anna Bridge |
181:96ed750bd169 | 2086 | Core Function Interface contains: |
Anna Bridge |
181:96ed750bd169 | 2087 | - Core NVIC Functions |
Anna Bridge |
181:96ed750bd169 | 2088 | - Core SysTick Functions |
Anna Bridge |
181:96ed750bd169 | 2089 | - Core Debug Functions |
Anna Bridge |
181:96ed750bd169 | 2090 | - Core Register Access Functions |
Anna Bridge |
181:96ed750bd169 | 2091 | ******************************************************************************/ |
Anna Bridge |
181:96ed750bd169 | 2092 | /** |
Anna Bridge |
181:96ed750bd169 | 2093 | \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
Anna Bridge |
181:96ed750bd169 | 2094 | */ |
Anna Bridge |
181:96ed750bd169 | 2095 | |
Anna Bridge |
181:96ed750bd169 | 2096 | |
Anna Bridge |
181:96ed750bd169 | 2097 | |
Anna Bridge |
181:96ed750bd169 | 2098 | /* ########################## NVIC functions #################################### */ |
Anna Bridge |
181:96ed750bd169 | 2099 | /** |
Anna Bridge |
181:96ed750bd169 | 2100 | \ingroup CMSIS_Core_FunctionInterface |
Anna Bridge |
181:96ed750bd169 | 2101 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
Anna Bridge |
181:96ed750bd169 | 2102 | \brief Functions that manage interrupts and exceptions via the NVIC. |
Anna Bridge |
181:96ed750bd169 | 2103 | @{ |
Anna Bridge |
181:96ed750bd169 | 2104 | */ |
Anna Bridge |
181:96ed750bd169 | 2105 | |
Anna Bridge |
181:96ed750bd169 | 2106 | #ifdef CMSIS_NVIC_VIRTUAL |
Anna Bridge |
181:96ed750bd169 | 2107 | #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE |
Anna Bridge |
181:96ed750bd169 | 2108 | #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" |
Anna Bridge |
181:96ed750bd169 | 2109 | #endif |
Anna Bridge |
181:96ed750bd169 | 2110 | #include CMSIS_NVIC_VIRTUAL_HEADER_FILE |
Anna Bridge |
181:96ed750bd169 | 2111 | #else |
Anna Bridge |
181:96ed750bd169 | 2112 | #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping |
Anna Bridge |
181:96ed750bd169 | 2113 | #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping |
Anna Bridge |
181:96ed750bd169 | 2114 | #define NVIC_EnableIRQ __NVIC_EnableIRQ |
Anna Bridge |
181:96ed750bd169 | 2115 | #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ |
Anna Bridge |
181:96ed750bd169 | 2116 | #define NVIC_DisableIRQ __NVIC_DisableIRQ |
Anna Bridge |
181:96ed750bd169 | 2117 | #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ |
Anna Bridge |
181:96ed750bd169 | 2118 | #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ |
Anna Bridge |
181:96ed750bd169 | 2119 | #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ |
Anna Bridge |
181:96ed750bd169 | 2120 | #define NVIC_GetActive __NVIC_GetActive |
Anna Bridge |
181:96ed750bd169 | 2121 | #define NVIC_SetPriority __NVIC_SetPriority |
Anna Bridge |
181:96ed750bd169 | 2122 | #define NVIC_GetPriority __NVIC_GetPriority |
Anna Bridge |
181:96ed750bd169 | 2123 | #define NVIC_SystemReset __NVIC_SystemReset |
Anna Bridge |
181:96ed750bd169 | 2124 | #endif /* CMSIS_NVIC_VIRTUAL */ |
Anna Bridge |
181:96ed750bd169 | 2125 | |
Anna Bridge |
181:96ed750bd169 | 2126 | #ifdef CMSIS_VECTAB_VIRTUAL |
Anna Bridge |
181:96ed750bd169 | 2127 | #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
Anna Bridge |
181:96ed750bd169 | 2128 | #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" |
Anna Bridge |
181:96ed750bd169 | 2129 | #endif |
Anna Bridge |
181:96ed750bd169 | 2130 | #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE |
Anna Bridge |
181:96ed750bd169 | 2131 | #else |
Anna Bridge |
181:96ed750bd169 | 2132 | #define NVIC_SetVector __NVIC_SetVector |
Anna Bridge |
181:96ed750bd169 | 2133 | #define NVIC_GetVector __NVIC_GetVector |
Anna Bridge |
181:96ed750bd169 | 2134 | #endif /* (CMSIS_VECTAB_VIRTUAL) */ |
Anna Bridge |
181:96ed750bd169 | 2135 | |
Anna Bridge |
181:96ed750bd169 | 2136 | #define NVIC_USER_IRQ_OFFSET 16 |
Anna Bridge |
181:96ed750bd169 | 2137 | |
Anna Bridge |
181:96ed750bd169 | 2138 | |
Anna Bridge |
181:96ed750bd169 | 2139 | |
Anna Bridge |
181:96ed750bd169 | 2140 | /** |
Anna Bridge |
181:96ed750bd169 | 2141 | \brief Set Priority Grouping |
Anna Bridge |
181:96ed750bd169 | 2142 | \details Sets the priority grouping field using the required unlock sequence. |
Anna Bridge |
181:96ed750bd169 | 2143 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
Anna Bridge |
181:96ed750bd169 | 2144 | Only values from 0..7 are used. |
Anna Bridge |
181:96ed750bd169 | 2145 | In case of a conflict between priority grouping and available |
Anna Bridge |
181:96ed750bd169 | 2146 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
Anna Bridge |
181:96ed750bd169 | 2147 | \param [in] PriorityGroup Priority grouping field. |
Anna Bridge |
181:96ed750bd169 | 2148 | */ |
Anna Bridge |
181:96ed750bd169 | 2149 | __STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) |
Anna Bridge |
181:96ed750bd169 | 2150 | { |
Anna Bridge |
181:96ed750bd169 | 2151 | uint32_t reg_value; |
Anna Bridge |
181:96ed750bd169 | 2152 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
Anna Bridge |
181:96ed750bd169 | 2153 | |
Anna Bridge |
181:96ed750bd169 | 2154 | reg_value = SCB->AIRCR; /* read old register configuration */ |
Anna Bridge |
181:96ed750bd169 | 2155 | reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ |
Anna Bridge |
181:96ed750bd169 | 2156 | reg_value = (reg_value | |
Anna Bridge |
181:96ed750bd169 | 2157 | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
Anna Bridge |
181:96ed750bd169 | 2158 | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ |
Anna Bridge |
181:96ed750bd169 | 2159 | SCB->AIRCR = reg_value; |
Anna Bridge |
181:96ed750bd169 | 2160 | } |
Anna Bridge |
181:96ed750bd169 | 2161 | |
Anna Bridge |
181:96ed750bd169 | 2162 | |
Anna Bridge |
181:96ed750bd169 | 2163 | /** |
Anna Bridge |
181:96ed750bd169 | 2164 | \brief Get Priority Grouping |
Anna Bridge |
181:96ed750bd169 | 2165 | \details Reads the priority grouping field from the NVIC Interrupt Controller. |
Anna Bridge |
181:96ed750bd169 | 2166 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
Anna Bridge |
181:96ed750bd169 | 2167 | */ |
Anna Bridge |
181:96ed750bd169 | 2168 | __STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) |
Anna Bridge |
181:96ed750bd169 | 2169 | { |
Anna Bridge |
181:96ed750bd169 | 2170 | return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); |
Anna Bridge |
181:96ed750bd169 | 2171 | } |
Anna Bridge |
181:96ed750bd169 | 2172 | |
Anna Bridge |
181:96ed750bd169 | 2173 | |
Anna Bridge |
181:96ed750bd169 | 2174 | /** |
Anna Bridge |
181:96ed750bd169 | 2175 | \brief Enable Interrupt |
Anna Bridge |
181:96ed750bd169 | 2176 | \details Enables a device specific interrupt in the NVIC interrupt controller. |
Anna Bridge |
181:96ed750bd169 | 2177 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2178 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2179 | */ |
Anna Bridge |
181:96ed750bd169 | 2180 | __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2181 | { |
Anna Bridge |
181:96ed750bd169 | 2182 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2183 | { |
Anna Bridge |
181:96ed750bd169 | 2184 | NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
Anna Bridge |
181:96ed750bd169 | 2185 | } |
Anna Bridge |
181:96ed750bd169 | 2186 | } |
Anna Bridge |
181:96ed750bd169 | 2187 | |
Anna Bridge |
181:96ed750bd169 | 2188 | |
Anna Bridge |
181:96ed750bd169 | 2189 | /** |
Anna Bridge |
181:96ed750bd169 | 2190 | \brief Get Interrupt Enable status |
Anna Bridge |
181:96ed750bd169 | 2191 | \details Returns a device specific interrupt enable status from the NVIC interrupt controller. |
Anna Bridge |
181:96ed750bd169 | 2192 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2193 | \return 0 Interrupt is not enabled. |
Anna Bridge |
181:96ed750bd169 | 2194 | \return 1 Interrupt is enabled. |
Anna Bridge |
181:96ed750bd169 | 2195 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2196 | */ |
Anna Bridge |
181:96ed750bd169 | 2197 | __STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2198 | { |
Anna Bridge |
181:96ed750bd169 | 2199 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2200 | { |
Anna Bridge |
181:96ed750bd169 | 2201 | return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
Anna Bridge |
181:96ed750bd169 | 2202 | } |
Anna Bridge |
181:96ed750bd169 | 2203 | else |
Anna Bridge |
181:96ed750bd169 | 2204 | { |
Anna Bridge |
181:96ed750bd169 | 2205 | return(0U); |
Anna Bridge |
181:96ed750bd169 | 2206 | } |
Anna Bridge |
181:96ed750bd169 | 2207 | } |
Anna Bridge |
181:96ed750bd169 | 2208 | |
Anna Bridge |
181:96ed750bd169 | 2209 | |
Anna Bridge |
181:96ed750bd169 | 2210 | /** |
Anna Bridge |
181:96ed750bd169 | 2211 | \brief Disable Interrupt |
Anna Bridge |
181:96ed750bd169 | 2212 | \details Disables a device specific interrupt in the NVIC interrupt controller. |
Anna Bridge |
181:96ed750bd169 | 2213 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2214 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2215 | */ |
Anna Bridge |
181:96ed750bd169 | 2216 | __STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2217 | { |
Anna Bridge |
181:96ed750bd169 | 2218 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2219 | { |
Anna Bridge |
181:96ed750bd169 | 2220 | NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
Anna Bridge |
181:96ed750bd169 | 2221 | __DSB(); |
Anna Bridge |
181:96ed750bd169 | 2222 | __ISB(); |
Anna Bridge |
181:96ed750bd169 | 2223 | } |
Anna Bridge |
181:96ed750bd169 | 2224 | } |
Anna Bridge |
181:96ed750bd169 | 2225 | |
Anna Bridge |
181:96ed750bd169 | 2226 | |
Anna Bridge |
181:96ed750bd169 | 2227 | /** |
Anna Bridge |
181:96ed750bd169 | 2228 | \brief Get Pending Interrupt |
Anna Bridge |
181:96ed750bd169 | 2229 | \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. |
Anna Bridge |
181:96ed750bd169 | 2230 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2231 | \return 0 Interrupt status is not pending. |
Anna Bridge |
181:96ed750bd169 | 2232 | \return 1 Interrupt status is pending. |
Anna Bridge |
181:96ed750bd169 | 2233 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2234 | */ |
Anna Bridge |
181:96ed750bd169 | 2235 | __STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2236 | { |
Anna Bridge |
181:96ed750bd169 | 2237 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2238 | { |
Anna Bridge |
181:96ed750bd169 | 2239 | return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
Anna Bridge |
181:96ed750bd169 | 2240 | } |
Anna Bridge |
181:96ed750bd169 | 2241 | else |
Anna Bridge |
181:96ed750bd169 | 2242 | { |
Anna Bridge |
181:96ed750bd169 | 2243 | return(0U); |
Anna Bridge |
181:96ed750bd169 | 2244 | } |
Anna Bridge |
181:96ed750bd169 | 2245 | } |
Anna Bridge |
181:96ed750bd169 | 2246 | |
Anna Bridge |
181:96ed750bd169 | 2247 | |
Anna Bridge |
181:96ed750bd169 | 2248 | /** |
Anna Bridge |
181:96ed750bd169 | 2249 | \brief Set Pending Interrupt |
Anna Bridge |
181:96ed750bd169 | 2250 | \details Sets the pending bit of a device specific interrupt in the NVIC pending register. |
Anna Bridge |
181:96ed750bd169 | 2251 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2252 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2253 | */ |
Anna Bridge |
181:96ed750bd169 | 2254 | __STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2255 | { |
Anna Bridge |
181:96ed750bd169 | 2256 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2257 | { |
Anna Bridge |
181:96ed750bd169 | 2258 | NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
Anna Bridge |
181:96ed750bd169 | 2259 | } |
Anna Bridge |
181:96ed750bd169 | 2260 | } |
Anna Bridge |
181:96ed750bd169 | 2261 | |
Anna Bridge |
181:96ed750bd169 | 2262 | |
Anna Bridge |
181:96ed750bd169 | 2263 | /** |
Anna Bridge |
181:96ed750bd169 | 2264 | \brief Clear Pending Interrupt |
Anna Bridge |
181:96ed750bd169 | 2265 | \details Clears the pending bit of a device specific interrupt in the NVIC pending register. |
Anna Bridge |
181:96ed750bd169 | 2266 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2267 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2268 | */ |
Anna Bridge |
181:96ed750bd169 | 2269 | __STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2270 | { |
Anna Bridge |
181:96ed750bd169 | 2271 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2272 | { |
Anna Bridge |
181:96ed750bd169 | 2273 | NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
Anna Bridge |
181:96ed750bd169 | 2274 | } |
Anna Bridge |
181:96ed750bd169 | 2275 | } |
Anna Bridge |
181:96ed750bd169 | 2276 | |
Anna Bridge |
181:96ed750bd169 | 2277 | |
Anna Bridge |
181:96ed750bd169 | 2278 | /** |
Anna Bridge |
181:96ed750bd169 | 2279 | \brief Get Active Interrupt |
Anna Bridge |
181:96ed750bd169 | 2280 | \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. |
Anna Bridge |
181:96ed750bd169 | 2281 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2282 | \return 0 Interrupt status is not active. |
Anna Bridge |
181:96ed750bd169 | 2283 | \return 1 Interrupt status is active. |
Anna Bridge |
181:96ed750bd169 | 2284 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2285 | */ |
Anna Bridge |
181:96ed750bd169 | 2286 | __STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2287 | { |
Anna Bridge |
181:96ed750bd169 | 2288 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2289 | { |
Anna Bridge |
181:96ed750bd169 | 2290 | return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
Anna Bridge |
181:96ed750bd169 | 2291 | } |
Anna Bridge |
181:96ed750bd169 | 2292 | else |
Anna Bridge |
181:96ed750bd169 | 2293 | { |
Anna Bridge |
181:96ed750bd169 | 2294 | return(0U); |
Anna Bridge |
181:96ed750bd169 | 2295 | } |
Anna Bridge |
181:96ed750bd169 | 2296 | } |
Anna Bridge |
181:96ed750bd169 | 2297 | |
Anna Bridge |
181:96ed750bd169 | 2298 | |
Anna Bridge |
181:96ed750bd169 | 2299 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
Anna Bridge |
181:96ed750bd169 | 2300 | /** |
Anna Bridge |
181:96ed750bd169 | 2301 | \brief Get Interrupt Target State |
Anna Bridge |
181:96ed750bd169 | 2302 | \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. |
Anna Bridge |
181:96ed750bd169 | 2303 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2304 | \return 0 if interrupt is assigned to Secure |
Anna Bridge |
181:96ed750bd169 | 2305 | \return 1 if interrupt is assigned to Non Secure |
Anna Bridge |
181:96ed750bd169 | 2306 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2307 | */ |
Anna Bridge |
181:96ed750bd169 | 2308 | __STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2309 | { |
Anna Bridge |
181:96ed750bd169 | 2310 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2311 | { |
Anna Bridge |
181:96ed750bd169 | 2312 | return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
Anna Bridge |
181:96ed750bd169 | 2313 | } |
Anna Bridge |
181:96ed750bd169 | 2314 | else |
Anna Bridge |
181:96ed750bd169 | 2315 | { |
Anna Bridge |
181:96ed750bd169 | 2316 | return(0U); |
Anna Bridge |
181:96ed750bd169 | 2317 | } |
Anna Bridge |
181:96ed750bd169 | 2318 | } |
Anna Bridge |
181:96ed750bd169 | 2319 | |
Anna Bridge |
181:96ed750bd169 | 2320 | |
Anna Bridge |
181:96ed750bd169 | 2321 | /** |
Anna Bridge |
181:96ed750bd169 | 2322 | \brief Set Interrupt Target State |
Anna Bridge |
181:96ed750bd169 | 2323 | \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. |
Anna Bridge |
181:96ed750bd169 | 2324 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2325 | \return 0 if interrupt is assigned to Secure |
Anna Bridge |
181:96ed750bd169 | 2326 | 1 if interrupt is assigned to Non Secure |
Anna Bridge |
181:96ed750bd169 | 2327 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2328 | */ |
Anna Bridge |
181:96ed750bd169 | 2329 | __STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2330 | { |
Anna Bridge |
181:96ed750bd169 | 2331 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2332 | { |
Anna Bridge |
181:96ed750bd169 | 2333 | NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); |
Anna Bridge |
181:96ed750bd169 | 2334 | return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
Anna Bridge |
181:96ed750bd169 | 2335 | } |
Anna Bridge |
181:96ed750bd169 | 2336 | else |
Anna Bridge |
181:96ed750bd169 | 2337 | { |
Anna Bridge |
181:96ed750bd169 | 2338 | return(0U); |
Anna Bridge |
181:96ed750bd169 | 2339 | } |
Anna Bridge |
181:96ed750bd169 | 2340 | } |
Anna Bridge |
181:96ed750bd169 | 2341 | |
Anna Bridge |
181:96ed750bd169 | 2342 | |
Anna Bridge |
181:96ed750bd169 | 2343 | /** |
Anna Bridge |
181:96ed750bd169 | 2344 | \brief Clear Interrupt Target State |
Anna Bridge |
181:96ed750bd169 | 2345 | \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. |
Anna Bridge |
181:96ed750bd169 | 2346 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2347 | \return 0 if interrupt is assigned to Secure |
Anna Bridge |
181:96ed750bd169 | 2348 | 1 if interrupt is assigned to Non Secure |
Anna Bridge |
181:96ed750bd169 | 2349 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2350 | */ |
Anna Bridge |
181:96ed750bd169 | 2351 | __STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2352 | { |
Anna Bridge |
181:96ed750bd169 | 2353 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2354 | { |
Anna Bridge |
181:96ed750bd169 | 2355 | NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))); |
Anna Bridge |
181:96ed750bd169 | 2356 | return((uint32_t)(((NVIC->ITNS[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
Anna Bridge |
181:96ed750bd169 | 2357 | } |
Anna Bridge |
181:96ed750bd169 | 2358 | else |
Anna Bridge |
181:96ed750bd169 | 2359 | { |
Anna Bridge |
181:96ed750bd169 | 2360 | return(0U); |
Anna Bridge |
181:96ed750bd169 | 2361 | } |
Anna Bridge |
181:96ed750bd169 | 2362 | } |
Anna Bridge |
181:96ed750bd169 | 2363 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
Anna Bridge |
181:96ed750bd169 | 2364 | |
Anna Bridge |
181:96ed750bd169 | 2365 | |
Anna Bridge |
181:96ed750bd169 | 2366 | /** |
Anna Bridge |
181:96ed750bd169 | 2367 | \brief Set Interrupt Priority |
Anna Bridge |
181:96ed750bd169 | 2368 | \details Sets the priority of a device specific interrupt or a processor exception. |
Anna Bridge |
181:96ed750bd169 | 2369 | The interrupt number can be positive to specify a device specific interrupt, |
Anna Bridge |
181:96ed750bd169 | 2370 | or negative to specify a processor exception. |
Anna Bridge |
181:96ed750bd169 | 2371 | \param [in] IRQn Interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2372 | \param [in] priority Priority to set. |
Anna Bridge |
181:96ed750bd169 | 2373 | \note The priority cannot be set for every processor exception. |
Anna Bridge |
181:96ed750bd169 | 2374 | */ |
Anna Bridge |
181:96ed750bd169 | 2375 | __STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
Anna Bridge |
181:96ed750bd169 | 2376 | { |
Anna Bridge |
181:96ed750bd169 | 2377 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2378 | { |
Anna Bridge |
181:96ed750bd169 | 2379 | NVIC->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
Anna Bridge |
181:96ed750bd169 | 2380 | } |
Anna Bridge |
181:96ed750bd169 | 2381 | else |
Anna Bridge |
181:96ed750bd169 | 2382 | { |
Anna Bridge |
181:96ed750bd169 | 2383 | SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
Anna Bridge |
181:96ed750bd169 | 2384 | } |
Anna Bridge |
181:96ed750bd169 | 2385 | } |
Anna Bridge |
181:96ed750bd169 | 2386 | |
Anna Bridge |
181:96ed750bd169 | 2387 | |
Anna Bridge |
181:96ed750bd169 | 2388 | /** |
Anna Bridge |
181:96ed750bd169 | 2389 | \brief Get Interrupt Priority |
Anna Bridge |
181:96ed750bd169 | 2390 | \details Reads the priority of a device specific interrupt or a processor exception. |
Anna Bridge |
181:96ed750bd169 | 2391 | The interrupt number can be positive to specify a device specific interrupt, |
Anna Bridge |
181:96ed750bd169 | 2392 | or negative to specify a processor exception. |
Anna Bridge |
181:96ed750bd169 | 2393 | \param [in] IRQn Interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2394 | \return Interrupt Priority. |
Anna Bridge |
181:96ed750bd169 | 2395 | Value is aligned automatically to the implemented priority bits of the microcontroller. |
Anna Bridge |
181:96ed750bd169 | 2396 | */ |
Anna Bridge |
181:96ed750bd169 | 2397 | __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2398 | { |
Anna Bridge |
181:96ed750bd169 | 2399 | |
Anna Bridge |
181:96ed750bd169 | 2400 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2401 | { |
Anna Bridge |
181:96ed750bd169 | 2402 | return(((uint32_t)NVIC->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); |
Anna Bridge |
181:96ed750bd169 | 2403 | } |
Anna Bridge |
181:96ed750bd169 | 2404 | else |
Anna Bridge |
181:96ed750bd169 | 2405 | { |
Anna Bridge |
181:96ed750bd169 | 2406 | return(((uint32_t)SCB->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); |
Anna Bridge |
181:96ed750bd169 | 2407 | } |
Anna Bridge |
181:96ed750bd169 | 2408 | } |
Anna Bridge |
181:96ed750bd169 | 2409 | |
Anna Bridge |
181:96ed750bd169 | 2410 | |
Anna Bridge |
181:96ed750bd169 | 2411 | /** |
Anna Bridge |
181:96ed750bd169 | 2412 | \brief Encode Priority |
Anna Bridge |
181:96ed750bd169 | 2413 | \details Encodes the priority for an interrupt with the given priority group, |
Anna Bridge |
181:96ed750bd169 | 2414 | preemptive priority value, and subpriority value. |
Anna Bridge |
181:96ed750bd169 | 2415 | In case of a conflict between priority grouping and available |
Anna Bridge |
181:96ed750bd169 | 2416 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
Anna Bridge |
181:96ed750bd169 | 2417 | \param [in] PriorityGroup Used priority group. |
Anna Bridge |
181:96ed750bd169 | 2418 | \param [in] PreemptPriority Preemptive priority value (starting from 0). |
Anna Bridge |
181:96ed750bd169 | 2419 | \param [in] SubPriority Subpriority value (starting from 0). |
Anna Bridge |
181:96ed750bd169 | 2420 | \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). |
Anna Bridge |
181:96ed750bd169 | 2421 | */ |
Anna Bridge |
181:96ed750bd169 | 2422 | __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) |
Anna Bridge |
181:96ed750bd169 | 2423 | { |
Anna Bridge |
181:96ed750bd169 | 2424 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
Anna Bridge |
181:96ed750bd169 | 2425 | uint32_t PreemptPriorityBits; |
Anna Bridge |
181:96ed750bd169 | 2426 | uint32_t SubPriorityBits; |
Anna Bridge |
181:96ed750bd169 | 2427 | |
Anna Bridge |
181:96ed750bd169 | 2428 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
Anna Bridge |
181:96ed750bd169 | 2429 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
Anna Bridge |
181:96ed750bd169 | 2430 | |
Anna Bridge |
181:96ed750bd169 | 2431 | return ( |
Anna Bridge |
181:96ed750bd169 | 2432 | ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | |
Anna Bridge |
181:96ed750bd169 | 2433 | ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) |
Anna Bridge |
181:96ed750bd169 | 2434 | ); |
Anna Bridge |
181:96ed750bd169 | 2435 | } |
Anna Bridge |
181:96ed750bd169 | 2436 | |
Anna Bridge |
181:96ed750bd169 | 2437 | |
Anna Bridge |
181:96ed750bd169 | 2438 | /** |
Anna Bridge |
181:96ed750bd169 | 2439 | \brief Decode Priority |
Anna Bridge |
181:96ed750bd169 | 2440 | \details Decodes an interrupt priority value with a given priority group to |
Anna Bridge |
181:96ed750bd169 | 2441 | preemptive priority value and subpriority value. |
Anna Bridge |
181:96ed750bd169 | 2442 | In case of a conflict between priority grouping and available |
Anna Bridge |
181:96ed750bd169 | 2443 | priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. |
Anna Bridge |
181:96ed750bd169 | 2444 | \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). |
Anna Bridge |
181:96ed750bd169 | 2445 | \param [in] PriorityGroup Used priority group. |
Anna Bridge |
181:96ed750bd169 | 2446 | \param [out] pPreemptPriority Preemptive priority value (starting from 0). |
Anna Bridge |
181:96ed750bd169 | 2447 | \param [out] pSubPriority Subpriority value (starting from 0). |
Anna Bridge |
181:96ed750bd169 | 2448 | */ |
Anna Bridge |
181:96ed750bd169 | 2449 | __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) |
Anna Bridge |
181:96ed750bd169 | 2450 | { |
Anna Bridge |
181:96ed750bd169 | 2451 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
Anna Bridge |
181:96ed750bd169 | 2452 | uint32_t PreemptPriorityBits; |
Anna Bridge |
181:96ed750bd169 | 2453 | uint32_t SubPriorityBits; |
Anna Bridge |
181:96ed750bd169 | 2454 | |
Anna Bridge |
181:96ed750bd169 | 2455 | PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); |
Anna Bridge |
181:96ed750bd169 | 2456 | SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); |
Anna Bridge |
181:96ed750bd169 | 2457 | |
Anna Bridge |
181:96ed750bd169 | 2458 | *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); |
Anna Bridge |
181:96ed750bd169 | 2459 | *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); |
Anna Bridge |
181:96ed750bd169 | 2460 | } |
Anna Bridge |
181:96ed750bd169 | 2461 | |
Anna Bridge |
181:96ed750bd169 | 2462 | |
Anna Bridge |
181:96ed750bd169 | 2463 | /** |
Anna Bridge |
181:96ed750bd169 | 2464 | \brief Set Interrupt Vector |
Anna Bridge |
181:96ed750bd169 | 2465 | \details Sets an interrupt vector in SRAM based interrupt vector table. |
Anna Bridge |
181:96ed750bd169 | 2466 | The interrupt number can be positive to specify a device specific interrupt, |
Anna Bridge |
181:96ed750bd169 | 2467 | or negative to specify a processor exception. |
Anna Bridge |
181:96ed750bd169 | 2468 | VTOR must been relocated to SRAM before. |
Anna Bridge |
181:96ed750bd169 | 2469 | \param [in] IRQn Interrupt number |
Anna Bridge |
181:96ed750bd169 | 2470 | \param [in] vector Address of interrupt handler function |
Anna Bridge |
181:96ed750bd169 | 2471 | */ |
Anna Bridge |
181:96ed750bd169 | 2472 | __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) |
Anna Bridge |
181:96ed750bd169 | 2473 | { |
Anna Bridge |
181:96ed750bd169 | 2474 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
Anna Bridge |
181:96ed750bd169 | 2475 | vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; |
Anna Bridge |
181:96ed750bd169 | 2476 | } |
Anna Bridge |
181:96ed750bd169 | 2477 | |
Anna Bridge |
181:96ed750bd169 | 2478 | |
Anna Bridge |
181:96ed750bd169 | 2479 | /** |
Anna Bridge |
181:96ed750bd169 | 2480 | \brief Get Interrupt Vector |
Anna Bridge |
181:96ed750bd169 | 2481 | \details Reads an interrupt vector from interrupt vector table. |
Anna Bridge |
181:96ed750bd169 | 2482 | The interrupt number can be positive to specify a device specific interrupt, |
Anna Bridge |
181:96ed750bd169 | 2483 | or negative to specify a processor exception. |
Anna Bridge |
181:96ed750bd169 | 2484 | \param [in] IRQn Interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2485 | \return Address of interrupt handler function |
Anna Bridge |
181:96ed750bd169 | 2486 | */ |
Anna Bridge |
181:96ed750bd169 | 2487 | __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2488 | { |
Anna Bridge |
181:96ed750bd169 | 2489 | uint32_t *vectors = (uint32_t *)SCB->VTOR; |
Anna Bridge |
181:96ed750bd169 | 2490 | return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; |
Anna Bridge |
181:96ed750bd169 | 2491 | } |
Anna Bridge |
181:96ed750bd169 | 2492 | |
Anna Bridge |
181:96ed750bd169 | 2493 | |
Anna Bridge |
181:96ed750bd169 | 2494 | /** |
Anna Bridge |
181:96ed750bd169 | 2495 | \brief System Reset |
Anna Bridge |
181:96ed750bd169 | 2496 | \details Initiates a system reset request to reset the MCU. |
Anna Bridge |
181:96ed750bd169 | 2497 | */ |
Anna Bridge |
181:96ed750bd169 | 2498 | __STATIC_INLINE void __NVIC_SystemReset(void) |
Anna Bridge |
181:96ed750bd169 | 2499 | { |
Anna Bridge |
181:96ed750bd169 | 2500 | __DSB(); /* Ensure all outstanding memory accesses included |
Anna Bridge |
181:96ed750bd169 | 2501 | buffered write are completed before reset */ |
Anna Bridge |
181:96ed750bd169 | 2502 | SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
Anna Bridge |
181:96ed750bd169 | 2503 | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | |
Anna Bridge |
181:96ed750bd169 | 2504 | SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ |
Anna Bridge |
181:96ed750bd169 | 2505 | __DSB(); /* Ensure completion of memory access */ |
Anna Bridge |
181:96ed750bd169 | 2506 | |
Anna Bridge |
181:96ed750bd169 | 2507 | for(;;) /* wait until reset */ |
Anna Bridge |
181:96ed750bd169 | 2508 | { |
Anna Bridge |
181:96ed750bd169 | 2509 | __NOP(); |
Anna Bridge |
181:96ed750bd169 | 2510 | } |
Anna Bridge |
181:96ed750bd169 | 2511 | } |
Anna Bridge |
181:96ed750bd169 | 2512 | |
Anna Bridge |
181:96ed750bd169 | 2513 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
Anna Bridge |
181:96ed750bd169 | 2514 | /** |
Anna Bridge |
181:96ed750bd169 | 2515 | \brief Set Priority Grouping (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2516 | \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. |
Anna Bridge |
181:96ed750bd169 | 2517 | The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. |
Anna Bridge |
181:96ed750bd169 | 2518 | Only values from 0..7 are used. |
Anna Bridge |
181:96ed750bd169 | 2519 | In case of a conflict between priority grouping and available |
Anna Bridge |
181:96ed750bd169 | 2520 | priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. |
Anna Bridge |
181:96ed750bd169 | 2521 | \param [in] PriorityGroup Priority grouping field. |
Anna Bridge |
181:96ed750bd169 | 2522 | */ |
Anna Bridge |
181:96ed750bd169 | 2523 | __STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) |
Anna Bridge |
181:96ed750bd169 | 2524 | { |
Anna Bridge |
181:96ed750bd169 | 2525 | uint32_t reg_value; |
Anna Bridge |
181:96ed750bd169 | 2526 | uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ |
Anna Bridge |
181:96ed750bd169 | 2527 | |
Anna Bridge |
181:96ed750bd169 | 2528 | reg_value = SCB_NS->AIRCR; /* read old register configuration */ |
Anna Bridge |
181:96ed750bd169 | 2529 | reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ |
Anna Bridge |
181:96ed750bd169 | 2530 | reg_value = (reg_value | |
Anna Bridge |
181:96ed750bd169 | 2531 | ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
Anna Bridge |
181:96ed750bd169 | 2532 | (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ |
Anna Bridge |
181:96ed750bd169 | 2533 | SCB_NS->AIRCR = reg_value; |
Anna Bridge |
181:96ed750bd169 | 2534 | } |
Anna Bridge |
181:96ed750bd169 | 2535 | |
Anna Bridge |
181:96ed750bd169 | 2536 | |
Anna Bridge |
181:96ed750bd169 | 2537 | /** |
Anna Bridge |
181:96ed750bd169 | 2538 | \brief Get Priority Grouping (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2539 | \details Reads the priority grouping field from the non-secure NVIC when in secure state. |
Anna Bridge |
181:96ed750bd169 | 2540 | \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). |
Anna Bridge |
181:96ed750bd169 | 2541 | */ |
Anna Bridge |
181:96ed750bd169 | 2542 | __STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) |
Anna Bridge |
181:96ed750bd169 | 2543 | { |
Anna Bridge |
181:96ed750bd169 | 2544 | return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); |
Anna Bridge |
181:96ed750bd169 | 2545 | } |
Anna Bridge |
181:96ed750bd169 | 2546 | |
Anna Bridge |
181:96ed750bd169 | 2547 | |
Anna Bridge |
181:96ed750bd169 | 2548 | /** |
Anna Bridge |
181:96ed750bd169 | 2549 | \brief Enable Interrupt (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2550 | \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. |
Anna Bridge |
181:96ed750bd169 | 2551 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2552 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2553 | */ |
Anna Bridge |
181:96ed750bd169 | 2554 | __STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2555 | { |
Anna Bridge |
181:96ed750bd169 | 2556 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2557 | { |
Anna Bridge |
181:96ed750bd169 | 2558 | NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
Anna Bridge |
181:96ed750bd169 | 2559 | } |
Anna Bridge |
181:96ed750bd169 | 2560 | } |
Anna Bridge |
181:96ed750bd169 | 2561 | |
Anna Bridge |
181:96ed750bd169 | 2562 | |
Anna Bridge |
181:96ed750bd169 | 2563 | /** |
Anna Bridge |
181:96ed750bd169 | 2564 | \brief Get Interrupt Enable status (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2565 | \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. |
Anna Bridge |
181:96ed750bd169 | 2566 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2567 | \return 0 Interrupt is not enabled. |
Anna Bridge |
181:96ed750bd169 | 2568 | \return 1 Interrupt is enabled. |
Anna Bridge |
181:96ed750bd169 | 2569 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2570 | */ |
Anna Bridge |
181:96ed750bd169 | 2571 | __STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2572 | { |
Anna Bridge |
181:96ed750bd169 | 2573 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2574 | { |
Anna Bridge |
181:96ed750bd169 | 2575 | return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
Anna Bridge |
181:96ed750bd169 | 2576 | } |
Anna Bridge |
181:96ed750bd169 | 2577 | else |
Anna Bridge |
181:96ed750bd169 | 2578 | { |
Anna Bridge |
181:96ed750bd169 | 2579 | return(0U); |
Anna Bridge |
181:96ed750bd169 | 2580 | } |
Anna Bridge |
181:96ed750bd169 | 2581 | } |
Anna Bridge |
181:96ed750bd169 | 2582 | |
Anna Bridge |
181:96ed750bd169 | 2583 | |
Anna Bridge |
181:96ed750bd169 | 2584 | /** |
Anna Bridge |
181:96ed750bd169 | 2585 | \brief Disable Interrupt (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2586 | \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. |
Anna Bridge |
181:96ed750bd169 | 2587 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2588 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2589 | */ |
Anna Bridge |
181:96ed750bd169 | 2590 | __STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2591 | { |
Anna Bridge |
181:96ed750bd169 | 2592 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2593 | { |
Anna Bridge |
181:96ed750bd169 | 2594 | NVIC_NS->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
Anna Bridge |
181:96ed750bd169 | 2595 | } |
Anna Bridge |
181:96ed750bd169 | 2596 | } |
Anna Bridge |
181:96ed750bd169 | 2597 | |
Anna Bridge |
181:96ed750bd169 | 2598 | |
Anna Bridge |
181:96ed750bd169 | 2599 | /** |
Anna Bridge |
181:96ed750bd169 | 2600 | \brief Get Pending Interrupt (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2601 | \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. |
Anna Bridge |
181:96ed750bd169 | 2602 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2603 | \return 0 Interrupt status is not pending. |
Anna Bridge |
181:96ed750bd169 | 2604 | \return 1 Interrupt status is pending. |
Anna Bridge |
181:96ed750bd169 | 2605 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2606 | */ |
Anna Bridge |
181:96ed750bd169 | 2607 | __STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2608 | { |
Anna Bridge |
181:96ed750bd169 | 2609 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2610 | { |
Anna Bridge |
181:96ed750bd169 | 2611 | return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
Anna Bridge |
181:96ed750bd169 | 2612 | } |
Anna Bridge |
181:96ed750bd169 | 2613 | else |
Anna Bridge |
181:96ed750bd169 | 2614 | { |
Anna Bridge |
181:96ed750bd169 | 2615 | return(0U); |
Anna Bridge |
181:96ed750bd169 | 2616 | } |
Anna Bridge |
181:96ed750bd169 | 2617 | } |
Anna Bridge |
181:96ed750bd169 | 2618 | |
Anna Bridge |
181:96ed750bd169 | 2619 | |
Anna Bridge |
181:96ed750bd169 | 2620 | /** |
Anna Bridge |
181:96ed750bd169 | 2621 | \brief Set Pending Interrupt (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2622 | \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. |
Anna Bridge |
181:96ed750bd169 | 2623 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2624 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2625 | */ |
Anna Bridge |
181:96ed750bd169 | 2626 | __STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2627 | { |
Anna Bridge |
181:96ed750bd169 | 2628 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2629 | { |
Anna Bridge |
181:96ed750bd169 | 2630 | NVIC_NS->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
Anna Bridge |
181:96ed750bd169 | 2631 | } |
Anna Bridge |
181:96ed750bd169 | 2632 | } |
Anna Bridge |
181:96ed750bd169 | 2633 | |
Anna Bridge |
181:96ed750bd169 | 2634 | |
Anna Bridge |
181:96ed750bd169 | 2635 | /** |
Anna Bridge |
181:96ed750bd169 | 2636 | \brief Clear Pending Interrupt (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2637 | \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. |
Anna Bridge |
181:96ed750bd169 | 2638 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2639 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2640 | */ |
Anna Bridge |
181:96ed750bd169 | 2641 | __STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2642 | { |
Anna Bridge |
181:96ed750bd169 | 2643 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2644 | { |
Anna Bridge |
181:96ed750bd169 | 2645 | NVIC_NS->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
Anna Bridge |
181:96ed750bd169 | 2646 | } |
Anna Bridge |
181:96ed750bd169 | 2647 | } |
Anna Bridge |
181:96ed750bd169 | 2648 | |
Anna Bridge |
181:96ed750bd169 | 2649 | |
Anna Bridge |
181:96ed750bd169 | 2650 | /** |
Anna Bridge |
181:96ed750bd169 | 2651 | \brief Get Active Interrupt (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2652 | \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. |
Anna Bridge |
181:96ed750bd169 | 2653 | \param [in] IRQn Device specific interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2654 | \return 0 Interrupt status is not active. |
Anna Bridge |
181:96ed750bd169 | 2655 | \return 1 Interrupt status is active. |
Anna Bridge |
181:96ed750bd169 | 2656 | \note IRQn must not be negative. |
Anna Bridge |
181:96ed750bd169 | 2657 | */ |
Anna Bridge |
181:96ed750bd169 | 2658 | __STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2659 | { |
Anna Bridge |
181:96ed750bd169 | 2660 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2661 | { |
Anna Bridge |
181:96ed750bd169 | 2662 | return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
Anna Bridge |
181:96ed750bd169 | 2663 | } |
Anna Bridge |
181:96ed750bd169 | 2664 | else |
Anna Bridge |
181:96ed750bd169 | 2665 | { |
Anna Bridge |
181:96ed750bd169 | 2666 | return(0U); |
Anna Bridge |
181:96ed750bd169 | 2667 | } |
Anna Bridge |
181:96ed750bd169 | 2668 | } |
Anna Bridge |
181:96ed750bd169 | 2669 | |
Anna Bridge |
181:96ed750bd169 | 2670 | |
Anna Bridge |
181:96ed750bd169 | 2671 | /** |
Anna Bridge |
181:96ed750bd169 | 2672 | \brief Set Interrupt Priority (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2673 | \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. |
Anna Bridge |
181:96ed750bd169 | 2674 | The interrupt number can be positive to specify a device specific interrupt, |
Anna Bridge |
181:96ed750bd169 | 2675 | or negative to specify a processor exception. |
Anna Bridge |
181:96ed750bd169 | 2676 | \param [in] IRQn Interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2677 | \param [in] priority Priority to set. |
Anna Bridge |
181:96ed750bd169 | 2678 | \note The priority cannot be set for every non-secure processor exception. |
Anna Bridge |
181:96ed750bd169 | 2679 | */ |
Anna Bridge |
181:96ed750bd169 | 2680 | __STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) |
Anna Bridge |
181:96ed750bd169 | 2681 | { |
Anna Bridge |
181:96ed750bd169 | 2682 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2683 | { |
Anna Bridge |
181:96ed750bd169 | 2684 | NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
Anna Bridge |
181:96ed750bd169 | 2685 | } |
Anna Bridge |
181:96ed750bd169 | 2686 | else |
Anna Bridge |
181:96ed750bd169 | 2687 | { |
Anna Bridge |
181:96ed750bd169 | 2688 | SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); |
Anna Bridge |
181:96ed750bd169 | 2689 | } |
Anna Bridge |
181:96ed750bd169 | 2690 | } |
Anna Bridge |
181:96ed750bd169 | 2691 | |
Anna Bridge |
181:96ed750bd169 | 2692 | |
Anna Bridge |
181:96ed750bd169 | 2693 | /** |
Anna Bridge |
181:96ed750bd169 | 2694 | \brief Get Interrupt Priority (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2695 | \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. |
Anna Bridge |
181:96ed750bd169 | 2696 | The interrupt number can be positive to specify a device specific interrupt, |
Anna Bridge |
181:96ed750bd169 | 2697 | or negative to specify a processor exception. |
Anna Bridge |
181:96ed750bd169 | 2698 | \param [in] IRQn Interrupt number. |
Anna Bridge |
181:96ed750bd169 | 2699 | \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. |
Anna Bridge |
181:96ed750bd169 | 2700 | */ |
Anna Bridge |
181:96ed750bd169 | 2701 | __STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) |
Anna Bridge |
181:96ed750bd169 | 2702 | { |
Anna Bridge |
181:96ed750bd169 | 2703 | |
Anna Bridge |
181:96ed750bd169 | 2704 | if ((int32_t)(IRQn) >= 0) |
Anna Bridge |
181:96ed750bd169 | 2705 | { |
Anna Bridge |
181:96ed750bd169 | 2706 | return(((uint32_t)NVIC_NS->IPR[((uint32_t)(int32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); |
Anna Bridge |
181:96ed750bd169 | 2707 | } |
Anna Bridge |
181:96ed750bd169 | 2708 | else |
Anna Bridge |
181:96ed750bd169 | 2709 | { |
Anna Bridge |
181:96ed750bd169 | 2710 | return(((uint32_t)SCB_NS->SHPR[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); |
Anna Bridge |
181:96ed750bd169 | 2711 | } |
Anna Bridge |
181:96ed750bd169 | 2712 | } |
Anna Bridge |
181:96ed750bd169 | 2713 | #endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ |
Anna Bridge |
181:96ed750bd169 | 2714 | |
Anna Bridge |
181:96ed750bd169 | 2715 | /*@} end of CMSIS_Core_NVICFunctions */ |
Anna Bridge |
181:96ed750bd169 | 2716 | |
Anna Bridge |
181:96ed750bd169 | 2717 | /* ########################## MPU functions #################################### */ |
Anna Bridge |
181:96ed750bd169 | 2718 | |
Anna Bridge |
181:96ed750bd169 | 2719 | #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) |
Anna Bridge |
181:96ed750bd169 | 2720 | |
Anna Bridge |
181:96ed750bd169 | 2721 | #include "mpu_armv8.h" |
Anna Bridge |
181:96ed750bd169 | 2722 | |
Anna Bridge |
181:96ed750bd169 | 2723 | #endif |
Anna Bridge |
181:96ed750bd169 | 2724 | |
Anna Bridge |
181:96ed750bd169 | 2725 | /* ########################## FPU functions #################################### */ |
Anna Bridge |
181:96ed750bd169 | 2726 | /** |
Anna Bridge |
181:96ed750bd169 | 2727 | \ingroup CMSIS_Core_FunctionInterface |
Anna Bridge |
181:96ed750bd169 | 2728 | \defgroup CMSIS_Core_FpuFunctions FPU Functions |
Anna Bridge |
181:96ed750bd169 | 2729 | \brief Function that provides FPU type. |
Anna Bridge |
181:96ed750bd169 | 2730 | @{ |
Anna Bridge |
181:96ed750bd169 | 2731 | */ |
Anna Bridge |
181:96ed750bd169 | 2732 | |
Anna Bridge |
181:96ed750bd169 | 2733 | /** |
Anna Bridge |
181:96ed750bd169 | 2734 | \brief get FPU type |
Anna Bridge |
181:96ed750bd169 | 2735 | \details returns the FPU type |
Anna Bridge |
181:96ed750bd169 | 2736 | \returns |
Anna Bridge |
181:96ed750bd169 | 2737 | - \b 0: No FPU |
Anna Bridge |
181:96ed750bd169 | 2738 | - \b 1: Single precision FPU |
Anna Bridge |
181:96ed750bd169 | 2739 | - \b 2: Double + Single precision FPU |
Anna Bridge |
181:96ed750bd169 | 2740 | */ |
Anna Bridge |
181:96ed750bd169 | 2741 | __STATIC_INLINE uint32_t SCB_GetFPUType(void) |
Anna Bridge |
181:96ed750bd169 | 2742 | { |
Anna Bridge |
181:96ed750bd169 | 2743 | uint32_t mvfr0; |
Anna Bridge |
181:96ed750bd169 | 2744 | |
Anna Bridge |
181:96ed750bd169 | 2745 | mvfr0 = FPU->MVFR0; |
Anna Bridge |
181:96ed750bd169 | 2746 | if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) |
Anna Bridge |
181:96ed750bd169 | 2747 | { |
Anna Bridge |
181:96ed750bd169 | 2748 | return 2U; /* Double + Single precision FPU */ |
Anna Bridge |
181:96ed750bd169 | 2749 | } |
Anna Bridge |
181:96ed750bd169 | 2750 | else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) |
Anna Bridge |
181:96ed750bd169 | 2751 | { |
Anna Bridge |
181:96ed750bd169 | 2752 | return 1U; /* Single precision FPU */ |
Anna Bridge |
181:96ed750bd169 | 2753 | } |
Anna Bridge |
181:96ed750bd169 | 2754 | else |
Anna Bridge |
181:96ed750bd169 | 2755 | { |
Anna Bridge |
181:96ed750bd169 | 2756 | return 0U; /* No FPU */ |
Anna Bridge |
181:96ed750bd169 | 2757 | } |
Anna Bridge |
181:96ed750bd169 | 2758 | } |
Anna Bridge |
181:96ed750bd169 | 2759 | |
Anna Bridge |
181:96ed750bd169 | 2760 | |
Anna Bridge |
181:96ed750bd169 | 2761 | /*@} end of CMSIS_Core_FpuFunctions */ |
Anna Bridge |
181:96ed750bd169 | 2762 | |
Anna Bridge |
181:96ed750bd169 | 2763 | |
Anna Bridge |
181:96ed750bd169 | 2764 | |
Anna Bridge |
181:96ed750bd169 | 2765 | /* ########################## SAU functions #################################### */ |
Anna Bridge |
181:96ed750bd169 | 2766 | /** |
Anna Bridge |
181:96ed750bd169 | 2767 | \ingroup CMSIS_Core_FunctionInterface |
Anna Bridge |
181:96ed750bd169 | 2768 | \defgroup CMSIS_Core_SAUFunctions SAU Functions |
Anna Bridge |
181:96ed750bd169 | 2769 | \brief Functions that configure the SAU. |
Anna Bridge |
181:96ed750bd169 | 2770 | @{ |
Anna Bridge |
181:96ed750bd169 | 2771 | */ |
Anna Bridge |
181:96ed750bd169 | 2772 | |
Anna Bridge |
181:96ed750bd169 | 2773 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
Anna Bridge |
181:96ed750bd169 | 2774 | |
Anna Bridge |
181:96ed750bd169 | 2775 | /** |
Anna Bridge |
181:96ed750bd169 | 2776 | \brief Enable SAU |
Anna Bridge |
181:96ed750bd169 | 2777 | \details Enables the Security Attribution Unit (SAU). |
Anna Bridge |
181:96ed750bd169 | 2778 | */ |
Anna Bridge |
181:96ed750bd169 | 2779 | __STATIC_INLINE void TZ_SAU_Enable(void) |
Anna Bridge |
181:96ed750bd169 | 2780 | { |
Anna Bridge |
181:96ed750bd169 | 2781 | SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); |
Anna Bridge |
181:96ed750bd169 | 2782 | } |
Anna Bridge |
181:96ed750bd169 | 2783 | |
Anna Bridge |
181:96ed750bd169 | 2784 | |
Anna Bridge |
181:96ed750bd169 | 2785 | |
Anna Bridge |
181:96ed750bd169 | 2786 | /** |
Anna Bridge |
181:96ed750bd169 | 2787 | \brief Disable SAU |
Anna Bridge |
181:96ed750bd169 | 2788 | \details Disables the Security Attribution Unit (SAU). |
Anna Bridge |
181:96ed750bd169 | 2789 | */ |
Anna Bridge |
181:96ed750bd169 | 2790 | __STATIC_INLINE void TZ_SAU_Disable(void) |
Anna Bridge |
181:96ed750bd169 | 2791 | { |
Anna Bridge |
181:96ed750bd169 | 2792 | SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); |
Anna Bridge |
181:96ed750bd169 | 2793 | } |
Anna Bridge |
181:96ed750bd169 | 2794 | |
Anna Bridge |
181:96ed750bd169 | 2795 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
Anna Bridge |
181:96ed750bd169 | 2796 | |
Anna Bridge |
181:96ed750bd169 | 2797 | /*@} end of CMSIS_Core_SAUFunctions */ |
Anna Bridge |
181:96ed750bd169 | 2798 | |
Anna Bridge |
181:96ed750bd169 | 2799 | |
Anna Bridge |
181:96ed750bd169 | 2800 | |
Anna Bridge |
181:96ed750bd169 | 2801 | |
Anna Bridge |
181:96ed750bd169 | 2802 | /* ################################## SysTick function ############################################ */ |
Anna Bridge |
181:96ed750bd169 | 2803 | /** |
Anna Bridge |
181:96ed750bd169 | 2804 | \ingroup CMSIS_Core_FunctionInterface |
Anna Bridge |
181:96ed750bd169 | 2805 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
Anna Bridge |
181:96ed750bd169 | 2806 | \brief Functions that configure the System. |
Anna Bridge |
181:96ed750bd169 | 2807 | @{ |
Anna Bridge |
181:96ed750bd169 | 2808 | */ |
Anna Bridge |
181:96ed750bd169 | 2809 | |
Anna Bridge |
181:96ed750bd169 | 2810 | #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) |
Anna Bridge |
181:96ed750bd169 | 2811 | |
Anna Bridge |
181:96ed750bd169 | 2812 | /** |
Anna Bridge |
181:96ed750bd169 | 2813 | \brief System Tick Configuration |
Anna Bridge |
181:96ed750bd169 | 2814 | \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. |
Anna Bridge |
181:96ed750bd169 | 2815 | Counter is in free running mode to generate periodic interrupts. |
Anna Bridge |
181:96ed750bd169 | 2816 | \param [in] ticks Number of ticks between two interrupts. |
Anna Bridge |
181:96ed750bd169 | 2817 | \return 0 Function succeeded. |
Anna Bridge |
181:96ed750bd169 | 2818 | \return 1 Function failed. |
Anna Bridge |
181:96ed750bd169 | 2819 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
Anna Bridge |
181:96ed750bd169 | 2820 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
Anna Bridge |
181:96ed750bd169 | 2821 | must contain a vendor-specific implementation of this function. |
Anna Bridge |
181:96ed750bd169 | 2822 | */ |
Anna Bridge |
181:96ed750bd169 | 2823 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
Anna Bridge |
181:96ed750bd169 | 2824 | { |
Anna Bridge |
181:96ed750bd169 | 2825 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
Anna Bridge |
181:96ed750bd169 | 2826 | { |
Anna Bridge |
181:96ed750bd169 | 2827 | return (1UL); /* Reload value impossible */ |
Anna Bridge |
181:96ed750bd169 | 2828 | } |
Anna Bridge |
181:96ed750bd169 | 2829 | |
Anna Bridge |
181:96ed750bd169 | 2830 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
Anna Bridge |
181:96ed750bd169 | 2831 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
Anna Bridge |
181:96ed750bd169 | 2832 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
Anna Bridge |
181:96ed750bd169 | 2833 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
Anna Bridge |
181:96ed750bd169 | 2834 | SysTick_CTRL_TICKINT_Msk | |
Anna Bridge |
181:96ed750bd169 | 2835 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
Anna Bridge |
181:96ed750bd169 | 2836 | return (0UL); /* Function successful */ |
Anna Bridge |
181:96ed750bd169 | 2837 | } |
Anna Bridge |
181:96ed750bd169 | 2838 | |
Anna Bridge |
181:96ed750bd169 | 2839 | #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) |
Anna Bridge |
181:96ed750bd169 | 2840 | /** |
Anna Bridge |
181:96ed750bd169 | 2841 | \brief System Tick Configuration (non-secure) |
Anna Bridge |
181:96ed750bd169 | 2842 | \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. |
Anna Bridge |
181:96ed750bd169 | 2843 | Counter is in free running mode to generate periodic interrupts. |
Anna Bridge |
181:96ed750bd169 | 2844 | \param [in] ticks Number of ticks between two interrupts. |
Anna Bridge |
181:96ed750bd169 | 2845 | \return 0 Function succeeded. |
Anna Bridge |
181:96ed750bd169 | 2846 | \return 1 Function failed. |
Anna Bridge |
181:96ed750bd169 | 2847 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
Anna Bridge |
181:96ed750bd169 | 2848 | function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b> |
Anna Bridge |
181:96ed750bd169 | 2849 | must contain a vendor-specific implementation of this function. |
Anna Bridge |
181:96ed750bd169 | 2850 | |
Anna Bridge |
181:96ed750bd169 | 2851 | */ |
Anna Bridge |
181:96ed750bd169 | 2852 | __STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) |
Anna Bridge |
181:96ed750bd169 | 2853 | { |
Anna Bridge |
181:96ed750bd169 | 2854 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) |
Anna Bridge |
181:96ed750bd169 | 2855 | { |
Anna Bridge |
181:96ed750bd169 | 2856 | return (1UL); /* Reload value impossible */ |
Anna Bridge |
181:96ed750bd169 | 2857 | } |
Anna Bridge |
181:96ed750bd169 | 2858 | |
Anna Bridge |
181:96ed750bd169 | 2859 | SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
Anna Bridge |
181:96ed750bd169 | 2860 | TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
Anna Bridge |
181:96ed750bd169 | 2861 | SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ |
Anna Bridge |
181:96ed750bd169 | 2862 | SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
Anna Bridge |
181:96ed750bd169 | 2863 | SysTick_CTRL_TICKINT_Msk | |
Anna Bridge |
181:96ed750bd169 | 2864 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
Anna Bridge |
181:96ed750bd169 | 2865 | return (0UL); /* Function successful */ |
Anna Bridge |
181:96ed750bd169 | 2866 | } |
Anna Bridge |
181:96ed750bd169 | 2867 | #endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ |
Anna Bridge |
181:96ed750bd169 | 2868 | |
Anna Bridge |
181:96ed750bd169 | 2869 | #endif |
Anna Bridge |
181:96ed750bd169 | 2870 | |
Anna Bridge |
181:96ed750bd169 | 2871 | /*@} end of CMSIS_Core_SysTickFunctions */ |
Anna Bridge |
181:96ed750bd169 | 2872 | |
Anna Bridge |
181:96ed750bd169 | 2873 | |
Anna Bridge |
181:96ed750bd169 | 2874 | |
Anna Bridge |
181:96ed750bd169 | 2875 | /* ##################################### Debug In/Output function ########################################### */ |
Anna Bridge |
181:96ed750bd169 | 2876 | /** |
Anna Bridge |
181:96ed750bd169 | 2877 | \ingroup CMSIS_Core_FunctionInterface |
Anna Bridge |
181:96ed750bd169 | 2878 | \defgroup CMSIS_core_DebugFunctions ITM Functions |
Anna Bridge |
181:96ed750bd169 | 2879 | \brief Functions that access the ITM debug interface. |
Anna Bridge |
181:96ed750bd169 | 2880 | @{ |
Anna Bridge |
181:96ed750bd169 | 2881 | */ |
Anna Bridge |
181:96ed750bd169 | 2882 | |
Anna Bridge |
181:96ed750bd169 | 2883 | extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ |
Anna Bridge |
181:96ed750bd169 | 2884 | #define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ |
Anna Bridge |
181:96ed750bd169 | 2885 | |
Anna Bridge |
181:96ed750bd169 | 2886 | |
Anna Bridge |
181:96ed750bd169 | 2887 | /** |
Anna Bridge |
181:96ed750bd169 | 2888 | \brief ITM Send Character |
Anna Bridge |
181:96ed750bd169 | 2889 | \details Transmits a character via the ITM channel 0, and |
Anna Bridge |
181:96ed750bd169 | 2890 | \li Just returns when no debugger is connected that has booked the output. |
Anna Bridge |
181:96ed750bd169 | 2891 | \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. |
Anna Bridge |
181:96ed750bd169 | 2892 | \param [in] ch Character to transmit. |
Anna Bridge |
181:96ed750bd169 | 2893 | \returns Character to transmit. |
Anna Bridge |
181:96ed750bd169 | 2894 | */ |
Anna Bridge |
181:96ed750bd169 | 2895 | __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) |
Anna Bridge |
181:96ed750bd169 | 2896 | { |
Anna Bridge |
181:96ed750bd169 | 2897 | if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ |
Anna Bridge |
181:96ed750bd169 | 2898 | ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ |
Anna Bridge |
181:96ed750bd169 | 2899 | { |
Anna Bridge |
181:96ed750bd169 | 2900 | while (ITM->PORT[0U].u32 == 0UL) |
Anna Bridge |
181:96ed750bd169 | 2901 | { |
Anna Bridge |
181:96ed750bd169 | 2902 | __NOP(); |
Anna Bridge |
181:96ed750bd169 | 2903 | } |
Anna Bridge |
181:96ed750bd169 | 2904 | ITM->PORT[0U].u8 = (uint8_t)ch; |
Anna Bridge |
181:96ed750bd169 | 2905 | } |
Anna Bridge |
181:96ed750bd169 | 2906 | return (ch); |
Anna Bridge |
181:96ed750bd169 | 2907 | } |
Anna Bridge |
181:96ed750bd169 | 2908 | |
Anna Bridge |
181:96ed750bd169 | 2909 | |
Anna Bridge |
181:96ed750bd169 | 2910 | /** |
Anna Bridge |
181:96ed750bd169 | 2911 | \brief ITM Receive Character |
Anna Bridge |
181:96ed750bd169 | 2912 | \details Inputs a character via the external variable \ref ITM_RxBuffer. |
Anna Bridge |
181:96ed750bd169 | 2913 | \return Received character. |
Anna Bridge |
181:96ed750bd169 | 2914 | \return -1 No character pending. |
Anna Bridge |
181:96ed750bd169 | 2915 | */ |
Anna Bridge |
181:96ed750bd169 | 2916 | __STATIC_INLINE int32_t ITM_ReceiveChar (void) |
Anna Bridge |
181:96ed750bd169 | 2917 | { |
Anna Bridge |
181:96ed750bd169 | 2918 | int32_t ch = -1; /* no character available */ |
Anna Bridge |
181:96ed750bd169 | 2919 | |
Anna Bridge |
181:96ed750bd169 | 2920 | if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) |
Anna Bridge |
181:96ed750bd169 | 2921 | { |
Anna Bridge |
181:96ed750bd169 | 2922 | ch = ITM_RxBuffer; |
Anna Bridge |
181:96ed750bd169 | 2923 | ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ |
Anna Bridge |
181:96ed750bd169 | 2924 | } |
Anna Bridge |
181:96ed750bd169 | 2925 | |
Anna Bridge |
181:96ed750bd169 | 2926 | return (ch); |
Anna Bridge |
181:96ed750bd169 | 2927 | } |
Anna Bridge |
181:96ed750bd169 | 2928 | |
Anna Bridge |
181:96ed750bd169 | 2929 | |
Anna Bridge |
181:96ed750bd169 | 2930 | /** |
Anna Bridge |
181:96ed750bd169 | 2931 | \brief ITM Check Character |
Anna Bridge |
181:96ed750bd169 | 2932 | \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. |
Anna Bridge |
181:96ed750bd169 | 2933 | \return 0 No character available. |
Anna Bridge |
181:96ed750bd169 | 2934 | \return 1 Character available. |
Anna Bridge |
181:96ed750bd169 | 2935 | */ |
Anna Bridge |
181:96ed750bd169 | 2936 | __STATIC_INLINE int32_t ITM_CheckChar (void) |
Anna Bridge |
181:96ed750bd169 | 2937 | { |
Anna Bridge |
181:96ed750bd169 | 2938 | |
Anna Bridge |
181:96ed750bd169 | 2939 | if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) |
Anna Bridge |
181:96ed750bd169 | 2940 | { |
Anna Bridge |
181:96ed750bd169 | 2941 | return (0); /* no character available */ |
Anna Bridge |
181:96ed750bd169 | 2942 | } |
Anna Bridge |
181:96ed750bd169 | 2943 | else |
Anna Bridge |
181:96ed750bd169 | 2944 | { |
Anna Bridge |
181:96ed750bd169 | 2945 | return (1); /* character available */ |
Anna Bridge |
181:96ed750bd169 | 2946 | } |
Anna Bridge |
181:96ed750bd169 | 2947 | } |
Anna Bridge |
181:96ed750bd169 | 2948 | |
Anna Bridge |
181:96ed750bd169 | 2949 | /*@} end of CMSIS_core_DebugFunctions */ |
Anna Bridge |
181:96ed750bd169 | 2950 | |
Anna Bridge |
181:96ed750bd169 | 2951 | |
Anna Bridge |
181:96ed750bd169 | 2952 | |
Anna Bridge |
181:96ed750bd169 | 2953 | |
Anna Bridge |
181:96ed750bd169 | 2954 | #ifdef __cplusplus |
Anna Bridge |
181:96ed750bd169 | 2955 | } |
Anna Bridge |
181:96ed750bd169 | 2956 | #endif |
Anna Bridge |
181:96ed750bd169 | 2957 | |
Anna Bridge |
181:96ed750bd169 | 2958 | #endif /* __CORE_CM33_H_DEPENDANT */ |
Anna Bridge |
181:96ed750bd169 | 2959 | |
Anna Bridge |
181:96ed750bd169 | 2960 | #endif /* __CMSIS_GENERIC */ |