Tux Leon / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_ll_crs.h@156:95d6b41a828b, 2017-01-16 (annotated)

Committer:
<>
Date:
Mon Jan 16 15:03:32 2017 +0000
Revision:
156:95d6b41a828b
Child:
181:96ed750bd169
This updates the lib to the mbed lib v134

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 156:95d6b41a828b 1 /**
<> 156:95d6b41a828b 2 ******************************************************************************
<> 156:95d6b41a828b 3 * @file stm32f0xx_ll_crs.h
<> 156:95d6b41a828b 4 * @author MCD Application Team
<> 156:95d6b41a828b 5 * @version V1.4.0
<> 156:95d6b41a828b 6 * @date 27-May-2016
<> 156:95d6b41a828b 7 * @brief Header file of CRS LL module.
<> 156:95d6b41a828b 8 ******************************************************************************
<> 156:95d6b41a828b 9 * @attention
<> 156:95d6b41a828b 10 *
<> 156:95d6b41a828b 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 156:95d6b41a828b 12 *
<> 156:95d6b41a828b 13 * Redistribution and use in source and binary forms, with or without modification,
<> 156:95d6b41a828b 14 * are permitted provided that the following conditions are met:
<> 156:95d6b41a828b 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 156:95d6b41a828b 16 * this list of conditions and the following disclaimer.
<> 156:95d6b41a828b 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 156:95d6b41a828b 18 * this list of conditions and the following disclaimer in the documentation
<> 156:95d6b41a828b 19 * and/or other materials provided with the distribution.
<> 156:95d6b41a828b 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 156:95d6b41a828b 21 * may be used to endorse or promote products derived from this software
<> 156:95d6b41a828b 22 * without specific prior written permission.
<> 156:95d6b41a828b 23 *
<> 156:95d6b41a828b 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 156:95d6b41a828b 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 156:95d6b41a828b 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 156:95d6b41a828b 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 156:95d6b41a828b 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 156:95d6b41a828b 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 156:95d6b41a828b 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 156:95d6b41a828b 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 156:95d6b41a828b 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 156:95d6b41a828b 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 156:95d6b41a828b 34 *
<> 156:95d6b41a828b 35 ******************************************************************************
<> 156:95d6b41a828b 36 */
<> 156:95d6b41a828b 37
<> 156:95d6b41a828b 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 156:95d6b41a828b 39 #ifndef __STM32F0xx_LL_CRS_H
<> 156:95d6b41a828b 40 #define __STM32F0xx_LL_CRS_H
<> 156:95d6b41a828b 41
<> 156:95d6b41a828b 42 #ifdef __cplusplus
<> 156:95d6b41a828b 43 extern "C" {
<> 156:95d6b41a828b 44 #endif
<> 156:95d6b41a828b 45
<> 156:95d6b41a828b 46 /* Includes ------------------------------------------------------------------*/
<> 156:95d6b41a828b 47 #include "stm32f0xx.h"
<> 156:95d6b41a828b 48
<> 156:95d6b41a828b 49 /** @addtogroup STM32F0xx_LL_Driver
<> 156:95d6b41a828b 50 * @{
<> 156:95d6b41a828b 51 */
<> 156:95d6b41a828b 52
<> 156:95d6b41a828b 53 #if defined(CRS)
<> 156:95d6b41a828b 54
<> 156:95d6b41a828b 55 /** @defgroup CRS_LL CRS
<> 156:95d6b41a828b 56 * @{
<> 156:95d6b41a828b 57 */
<> 156:95d6b41a828b 58
<> 156:95d6b41a828b 59 /* Private types -------------------------------------------------------------*/
<> 156:95d6b41a828b 60 /* Private variables ---------------------------------------------------------*/
<> 156:95d6b41a828b 61
<> 156:95d6b41a828b 62 /* Private constants ---------------------------------------------------------*/
<> 156:95d6b41a828b 63 /** @defgroup CRS_LL_Private_Constants CRS Private Constants
<> 156:95d6b41a828b 64 * @{
<> 156:95d6b41a828b 65 */
<> 156:95d6b41a828b 66
<> 156:95d6b41a828b 67 /* Defines used for the bit position in the register and perform offsets*/
<> 156:95d6b41a828b 68 #define CRS_POSITION_TRIM (uint32_t)8U /* bit position in CR reg */
<> 156:95d6b41a828b 69 #define CRS_POSITION_FECAP (uint32_t)16U /* bit position in ISR reg */
<> 156:95d6b41a828b 70 #define CRS_POSITION_RELOAD (uint32_t)0U /* bit position in CFGR reg */
<> 156:95d6b41a828b 71 #define CRS_POSITION_FELIM (uint32_t)16U /* bit position in CFGR reg */
<> 156:95d6b41a828b 72
<> 156:95d6b41a828b 73
<> 156:95d6b41a828b 74 /**
<> 156:95d6b41a828b 75 * @}
<> 156:95d6b41a828b 76 */
<> 156:95d6b41a828b 77
<> 156:95d6b41a828b 78 /* Private macros ------------------------------------------------------------*/
<> 156:95d6b41a828b 79
<> 156:95d6b41a828b 80 /* Exported types ------------------------------------------------------------*/
<> 156:95d6b41a828b 81 /* Exported constants --------------------------------------------------------*/
<> 156:95d6b41a828b 82 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
<> 156:95d6b41a828b 83 * @{
<> 156:95d6b41a828b 84 */
<> 156:95d6b41a828b 85
<> 156:95d6b41a828b 86 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
<> 156:95d6b41a828b 87 * @brief Flags defines which can be used with LL_CRS_ReadReg function
<> 156:95d6b41a828b 88 * @{
<> 156:95d6b41a828b 89 */
<> 156:95d6b41a828b 90 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
<> 156:95d6b41a828b 91 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
<> 156:95d6b41a828b 92 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF
<> 156:95d6b41a828b 93 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
<> 156:95d6b41a828b 94 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
<> 156:95d6b41a828b 95 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
<> 156:95d6b41a828b 96 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
<> 156:95d6b41a828b 97 /**
<> 156:95d6b41a828b 98 * @}
<> 156:95d6b41a828b 99 */
<> 156:95d6b41a828b 100
<> 156:95d6b41a828b 101 /** @defgroup CRS_LL_EC_IT IT Defines
<> 156:95d6b41a828b 102 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
<> 156:95d6b41a828b 103 * @{
<> 156:95d6b41a828b 104 */
<> 156:95d6b41a828b 105 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
<> 156:95d6b41a828b 106 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
<> 156:95d6b41a828b 107 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE
<> 156:95d6b41a828b 108 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
<> 156:95d6b41a828b 109 /**
<> 156:95d6b41a828b 110 * @}
<> 156:95d6b41a828b 111 */
<> 156:95d6b41a828b 112
<> 156:95d6b41a828b 113 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
<> 156:95d6b41a828b 114 * @{
<> 156:95d6b41a828b 115 */
<> 156:95d6b41a828b 116 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */
<> 156:95d6b41a828b 117 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
<> 156:95d6b41a828b 118 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
<> 156:95d6b41a828b 119 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
<> 156:95d6b41a828b 120 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
<> 156:95d6b41a828b 121 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
<> 156:95d6b41a828b 122 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
<> 156:95d6b41a828b 123 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
<> 156:95d6b41a828b 124 /**
<> 156:95d6b41a828b 125 * @}
<> 156:95d6b41a828b 126 */
<> 156:95d6b41a828b 127
<> 156:95d6b41a828b 128 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
<> 156:95d6b41a828b 129 * @{
<> 156:95d6b41a828b 130 */
<> 156:95d6b41a828b 131 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */
<> 156:95d6b41a828b 132 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
<> 156:95d6b41a828b 133 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
<> 156:95d6b41a828b 134 /**
<> 156:95d6b41a828b 135 * @}
<> 156:95d6b41a828b 136 */
<> 156:95d6b41a828b 137
<> 156:95d6b41a828b 138 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
<> 156:95d6b41a828b 139 * @{
<> 156:95d6b41a828b 140 */
<> 156:95d6b41a828b 141 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */
<> 156:95d6b41a828b 142 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
<> 156:95d6b41a828b 143 /**
<> 156:95d6b41a828b 144 * @}
<> 156:95d6b41a828b 145 */
<> 156:95d6b41a828b 146
<> 156:95d6b41a828b 147 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
<> 156:95d6b41a828b 148 * @{
<> 156:95d6b41a828b 149 */
<> 156:95d6b41a828b 150 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */
<> 156:95d6b41a828b 151 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
<> 156:95d6b41a828b 152 /**
<> 156:95d6b41a828b 153 * @}
<> 156:95d6b41a828b 154 */
<> 156:95d6b41a828b 155
<> 156:95d6b41a828b 156 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
<> 156:95d6b41a828b 157 * @{
<> 156:95d6b41a828b 158 */
<> 156:95d6b41a828b 159 /**
<> 156:95d6b41a828b 160 * @brief Reset value of the RELOAD field
<> 156:95d6b41a828b 161 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
<> 156:95d6b41a828b 162 * and a synchronization signal frequency of 1 kHz (SOF signal from USB)
<> 156:95d6b41a828b 163 */
<> 156:95d6b41a828b 164 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU)
<> 156:95d6b41a828b 165
<> 156:95d6b41a828b 166 /**
<> 156:95d6b41a828b 167 * @brief Reset value of Frequency error limit.
<> 156:95d6b41a828b 168 */
<> 156:95d6b41a828b 169 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U)
<> 156:95d6b41a828b 170
<> 156:95d6b41a828b 171 /**
<> 156:95d6b41a828b 172 * @brief Reset value of the HSI48 Calibration field
<> 156:95d6b41a828b 173 * @note The default value is 32, which corresponds to the middle of the trimming interval.
<> 156:95d6b41a828b 174 * The trimming step is around 67 kHz between two consecutive TRIM steps.
<> 156:95d6b41a828b 175 * A higher TRIM value corresponds to a higher output frequency
<> 156:95d6b41a828b 176 */
<> 156:95d6b41a828b 177 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U)
<> 156:95d6b41a828b 178 /**
<> 156:95d6b41a828b 179 * @}
<> 156:95d6b41a828b 180 */
<> 156:95d6b41a828b 181
<> 156:95d6b41a828b 182 /**
<> 156:95d6b41a828b 183 * @}
<> 156:95d6b41a828b 184 */
<> 156:95d6b41a828b 185
<> 156:95d6b41a828b 186 /* Exported macro ------------------------------------------------------------*/
<> 156:95d6b41a828b 187 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
<> 156:95d6b41a828b 188 * @{
<> 156:95d6b41a828b 189 */
<> 156:95d6b41a828b 190
<> 156:95d6b41a828b 191 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
<> 156:95d6b41a828b 192 * @{
<> 156:95d6b41a828b 193 */
<> 156:95d6b41a828b 194
<> 156:95d6b41a828b 195 /**
<> 156:95d6b41a828b 196 * @brief Write a value in CRS register
<> 156:95d6b41a828b 197 * @param __INSTANCE__ CRS Instance
<> 156:95d6b41a828b 198 * @param __REG__ Register to be written
<> 156:95d6b41a828b 199 * @param __VALUE__ Value to be written in the register
<> 156:95d6b41a828b 200 * @retval None
<> 156:95d6b41a828b 201 */
<> 156:95d6b41a828b 202 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
<> 156:95d6b41a828b 203
<> 156:95d6b41a828b 204 /**
<> 156:95d6b41a828b 205 * @brief Read a value in CRS register
<> 156:95d6b41a828b 206 * @param __INSTANCE__ CRS Instance
<> 156:95d6b41a828b 207 * @param __REG__ Register to be read
<> 156:95d6b41a828b 208 * @retval Register value
<> 156:95d6b41a828b 209 */
<> 156:95d6b41a828b 210 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
<> 156:95d6b41a828b 211 /**
<> 156:95d6b41a828b 212 * @}
<> 156:95d6b41a828b 213 */
<> 156:95d6b41a828b 214
<> 156:95d6b41a828b 215 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
<> 156:95d6b41a828b 216 * @{
<> 156:95d6b41a828b 217 */
<> 156:95d6b41a828b 218
<> 156:95d6b41a828b 219 /**
<> 156:95d6b41a828b 220 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
<> 156:95d6b41a828b 221 * @note The RELOAD value should be selected according to the ratio between
<> 156:95d6b41a828b 222 * the target frequency and the frequency of the synchronization source after
<> 156:95d6b41a828b 223 * prescaling. It is then decreased by one in order to reach the expected
<> 156:95d6b41a828b 224 * synchronization on the zero value. The formula is the following:
<> 156:95d6b41a828b 225 * RELOAD = (fTARGET / fSYNC) -1
<> 156:95d6b41a828b 226 * @param __FTARGET__ Target frequency (value in Hz)
<> 156:95d6b41a828b 227 * @param __FSYNC__ Synchronization signal frequency (value in Hz)
<> 156:95d6b41a828b 228 * @retval Reload value (in Hz)
<> 156:95d6b41a828b 229 */
<> 156:95d6b41a828b 230 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
<> 156:95d6b41a828b 231
<> 156:95d6b41a828b 232 /**
<> 156:95d6b41a828b 233 * @}
<> 156:95d6b41a828b 234 */
<> 156:95d6b41a828b 235
<> 156:95d6b41a828b 236 /**
<> 156:95d6b41a828b 237 * @}
<> 156:95d6b41a828b 238 */
<> 156:95d6b41a828b 239
<> 156:95d6b41a828b 240 /* Exported functions --------------------------------------------------------*/
<> 156:95d6b41a828b 241 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
<> 156:95d6b41a828b 242 * @{
<> 156:95d6b41a828b 243 */
<> 156:95d6b41a828b 244
<> 156:95d6b41a828b 245 /** @defgroup CRS_LL_EF_Configuration Configuration
<> 156:95d6b41a828b 246 * @{
<> 156:95d6b41a828b 247 */
<> 156:95d6b41a828b 248
<> 156:95d6b41a828b 249 /**
<> 156:95d6b41a828b 250 * @brief Enable Frequency error counter
<> 156:95d6b41a828b 251 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
<> 156:95d6b41a828b 252 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
<> 156:95d6b41a828b 253 * @retval None
<> 156:95d6b41a828b 254 */
<> 156:95d6b41a828b 255 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
<> 156:95d6b41a828b 256 {
<> 156:95d6b41a828b 257 SET_BIT(CRS->CR, CRS_CR_CEN);
<> 156:95d6b41a828b 258 }
<> 156:95d6b41a828b 259
<> 156:95d6b41a828b 260 /**
<> 156:95d6b41a828b 261 * @brief Disable Frequency error counter
<> 156:95d6b41a828b 262 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
<> 156:95d6b41a828b 263 * @retval None
<> 156:95d6b41a828b 264 */
<> 156:95d6b41a828b 265 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
<> 156:95d6b41a828b 266 {
<> 156:95d6b41a828b 267 CLEAR_BIT(CRS->CR, CRS_CR_CEN);
<> 156:95d6b41a828b 268 }
<> 156:95d6b41a828b 269
<> 156:95d6b41a828b 270 /**
<> 156:95d6b41a828b 271 * @brief Check if Frequency error counter is enabled or not
<> 156:95d6b41a828b 272 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
<> 156:95d6b41a828b 273 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 274 */
<> 156:95d6b41a828b 275 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
<> 156:95d6b41a828b 276 {
<> 156:95d6b41a828b 277 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN));
<> 156:95d6b41a828b 278 }
<> 156:95d6b41a828b 279
<> 156:95d6b41a828b 280 /**
<> 156:95d6b41a828b 281 * @brief Enable Automatic trimming counter
<> 156:95d6b41a828b 282 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
<> 156:95d6b41a828b 283 * @retval None
<> 156:95d6b41a828b 284 */
<> 156:95d6b41a828b 285 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
<> 156:95d6b41a828b 286 {
<> 156:95d6b41a828b 287 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
<> 156:95d6b41a828b 288 }
<> 156:95d6b41a828b 289
<> 156:95d6b41a828b 290 /**
<> 156:95d6b41a828b 291 * @brief Disable Automatic trimming counter
<> 156:95d6b41a828b 292 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
<> 156:95d6b41a828b 293 * @retval None
<> 156:95d6b41a828b 294 */
<> 156:95d6b41a828b 295 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
<> 156:95d6b41a828b 296 {
<> 156:95d6b41a828b 297 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
<> 156:95d6b41a828b 298 }
<> 156:95d6b41a828b 299
<> 156:95d6b41a828b 300 /**
<> 156:95d6b41a828b 301 * @brief Check if Automatic trimming is enabled or not
<> 156:95d6b41a828b 302 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
<> 156:95d6b41a828b 303 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 304 */
<> 156:95d6b41a828b 305 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
<> 156:95d6b41a828b 306 {
<> 156:95d6b41a828b 307 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN));
<> 156:95d6b41a828b 308 }
<> 156:95d6b41a828b 309
<> 156:95d6b41a828b 310 /**
<> 156:95d6b41a828b 311 * @brief Set HSI48 oscillator smooth trimming
<> 156:95d6b41a828b 312 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
<> 156:95d6b41a828b 313 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
<> 156:95d6b41a828b 314 * @param Value a number between Min_Data = 0 and Max_Data = 63
<> 156:95d6b41a828b 315 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
<> 156:95d6b41a828b 316 * @retval None
<> 156:95d6b41a828b 317 */
<> 156:95d6b41a828b 318 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
<> 156:95d6b41a828b 319 {
<> 156:95d6b41a828b 320 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
<> 156:95d6b41a828b 321 }
<> 156:95d6b41a828b 322
<> 156:95d6b41a828b 323 /**
<> 156:95d6b41a828b 324 * @brief Get HSI48 oscillator smooth trimming
<> 156:95d6b41a828b 325 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
<> 156:95d6b41a828b 326 * @retval a number between Min_Data = 0 and Max_Data = 63
<> 156:95d6b41a828b 327 */
<> 156:95d6b41a828b 328 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
<> 156:95d6b41a828b 329 {
<> 156:95d6b41a828b 330 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
<> 156:95d6b41a828b 331 }
<> 156:95d6b41a828b 332
<> 156:95d6b41a828b 333 /**
<> 156:95d6b41a828b 334 * @brief Set counter reload value
<> 156:95d6b41a828b 335 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
<> 156:95d6b41a828b 336 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
<> 156:95d6b41a828b 337 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
<> 156:95d6b41a828b 338 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
<> 156:95d6b41a828b 339 * @retval None
<> 156:95d6b41a828b 340 */
<> 156:95d6b41a828b 341 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
<> 156:95d6b41a828b 342 {
<> 156:95d6b41a828b 343 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
<> 156:95d6b41a828b 344 }
<> 156:95d6b41a828b 345
<> 156:95d6b41a828b 346 /**
<> 156:95d6b41a828b 347 * @brief Get counter reload value
<> 156:95d6b41a828b 348 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
<> 156:95d6b41a828b 349 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
<> 156:95d6b41a828b 350 */
<> 156:95d6b41a828b 351 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
<> 156:95d6b41a828b 352 {
<> 156:95d6b41a828b 353 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
<> 156:95d6b41a828b 354 }
<> 156:95d6b41a828b 355
<> 156:95d6b41a828b 356 /**
<> 156:95d6b41a828b 357 * @brief Set frequency error limit
<> 156:95d6b41a828b 358 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
<> 156:95d6b41a828b 359 * @param Value a number between Min_Data = 0 and Max_Data = 255
<> 156:95d6b41a828b 360 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
<> 156:95d6b41a828b 361 * @retval None
<> 156:95d6b41a828b 362 */
<> 156:95d6b41a828b 363 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
<> 156:95d6b41a828b 364 {
<> 156:95d6b41a828b 365 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
<> 156:95d6b41a828b 366 }
<> 156:95d6b41a828b 367
<> 156:95d6b41a828b 368 /**
<> 156:95d6b41a828b 369 * @brief Get frequency error limit
<> 156:95d6b41a828b 370 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
<> 156:95d6b41a828b 371 * @retval A number between Min_Data = 0 and Max_Data = 255
<> 156:95d6b41a828b 372 */
<> 156:95d6b41a828b 373 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
<> 156:95d6b41a828b 374 {
<> 156:95d6b41a828b 375 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
<> 156:95d6b41a828b 376 }
<> 156:95d6b41a828b 377
<> 156:95d6b41a828b 378 /**
<> 156:95d6b41a828b 379 * @brief Set division factor for SYNC signal
<> 156:95d6b41a828b 380 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
<> 156:95d6b41a828b 381 * @param Divider This parameter can be one of the following values:
<> 156:95d6b41a828b 382 * @arg @ref LL_CRS_SYNC_DIV_1
<> 156:95d6b41a828b 383 * @arg @ref LL_CRS_SYNC_DIV_2
<> 156:95d6b41a828b 384 * @arg @ref LL_CRS_SYNC_DIV_4
<> 156:95d6b41a828b 385 * @arg @ref LL_CRS_SYNC_DIV_8
<> 156:95d6b41a828b 386 * @arg @ref LL_CRS_SYNC_DIV_16
<> 156:95d6b41a828b 387 * @arg @ref LL_CRS_SYNC_DIV_32
<> 156:95d6b41a828b 388 * @arg @ref LL_CRS_SYNC_DIV_64
<> 156:95d6b41a828b 389 * @arg @ref LL_CRS_SYNC_DIV_128
<> 156:95d6b41a828b 390 * @retval None
<> 156:95d6b41a828b 391 */
<> 156:95d6b41a828b 392 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
<> 156:95d6b41a828b 393 {
<> 156:95d6b41a828b 394 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
<> 156:95d6b41a828b 395 }
<> 156:95d6b41a828b 396
<> 156:95d6b41a828b 397 /**
<> 156:95d6b41a828b 398 * @brief Get division factor for SYNC signal
<> 156:95d6b41a828b 399 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
<> 156:95d6b41a828b 400 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 401 * @arg @ref LL_CRS_SYNC_DIV_1
<> 156:95d6b41a828b 402 * @arg @ref LL_CRS_SYNC_DIV_2
<> 156:95d6b41a828b 403 * @arg @ref LL_CRS_SYNC_DIV_4
<> 156:95d6b41a828b 404 * @arg @ref LL_CRS_SYNC_DIV_8
<> 156:95d6b41a828b 405 * @arg @ref LL_CRS_SYNC_DIV_16
<> 156:95d6b41a828b 406 * @arg @ref LL_CRS_SYNC_DIV_32
<> 156:95d6b41a828b 407 * @arg @ref LL_CRS_SYNC_DIV_64
<> 156:95d6b41a828b 408 * @arg @ref LL_CRS_SYNC_DIV_128
<> 156:95d6b41a828b 409 */
<> 156:95d6b41a828b 410 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
<> 156:95d6b41a828b 411 {
<> 156:95d6b41a828b 412 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
<> 156:95d6b41a828b 413 }
<> 156:95d6b41a828b 414
<> 156:95d6b41a828b 415 /**
<> 156:95d6b41a828b 416 * @brief Set SYNC signal source
<> 156:95d6b41a828b 417 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
<> 156:95d6b41a828b 418 * @param Source This parameter can be one of the following values:
<> 156:95d6b41a828b 419 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
<> 156:95d6b41a828b 420 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
<> 156:95d6b41a828b 421 * @arg @ref LL_CRS_SYNC_SOURCE_USB
<> 156:95d6b41a828b 422 * @retval None
<> 156:95d6b41a828b 423 */
<> 156:95d6b41a828b 424 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
<> 156:95d6b41a828b 425 {
<> 156:95d6b41a828b 426 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
<> 156:95d6b41a828b 427 }
<> 156:95d6b41a828b 428
<> 156:95d6b41a828b 429 /**
<> 156:95d6b41a828b 430 * @brief Get SYNC signal source
<> 156:95d6b41a828b 431 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
<> 156:95d6b41a828b 432 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 433 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO
<> 156:95d6b41a828b 434 * @arg @ref LL_CRS_SYNC_SOURCE_LSE
<> 156:95d6b41a828b 435 * @arg @ref LL_CRS_SYNC_SOURCE_USB
<> 156:95d6b41a828b 436 */
<> 156:95d6b41a828b 437 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
<> 156:95d6b41a828b 438 {
<> 156:95d6b41a828b 439 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
<> 156:95d6b41a828b 440 }
<> 156:95d6b41a828b 441
<> 156:95d6b41a828b 442 /**
<> 156:95d6b41a828b 443 * @brief Set input polarity for the SYNC signal source
<> 156:95d6b41a828b 444 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
<> 156:95d6b41a828b 445 * @param Polarity This parameter can be one of the following values:
<> 156:95d6b41a828b 446 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
<> 156:95d6b41a828b 447 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
<> 156:95d6b41a828b 448 * @retval None
<> 156:95d6b41a828b 449 */
<> 156:95d6b41a828b 450 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
<> 156:95d6b41a828b 451 {
<> 156:95d6b41a828b 452 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
<> 156:95d6b41a828b 453 }
<> 156:95d6b41a828b 454
<> 156:95d6b41a828b 455 /**
<> 156:95d6b41a828b 456 * @brief Get input polarity for the SYNC signal source
<> 156:95d6b41a828b 457 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
<> 156:95d6b41a828b 458 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 459 * @arg @ref LL_CRS_SYNC_POLARITY_RISING
<> 156:95d6b41a828b 460 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING
<> 156:95d6b41a828b 461 */
<> 156:95d6b41a828b 462 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
<> 156:95d6b41a828b 463 {
<> 156:95d6b41a828b 464 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
<> 156:95d6b41a828b 465 }
<> 156:95d6b41a828b 466
<> 156:95d6b41a828b 467 /**
<> 156:95d6b41a828b 468 * @brief Configure CRS for the synchronization
<> 156:95d6b41a828b 469 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
<> 156:95d6b41a828b 470 * CFGR RELOAD LL_CRS_ConfigSynchronization\n
<> 156:95d6b41a828b 471 * CFGR FELIM LL_CRS_ConfigSynchronization\n
<> 156:95d6b41a828b 472 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
<> 156:95d6b41a828b 473 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
<> 156:95d6b41a828b 474 * CFGR SYNCPOL LL_CRS_ConfigSynchronization
<> 156:95d6b41a828b 475 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
<> 156:95d6b41a828b 476 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
<> 156:95d6b41a828b 477 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
<> 156:95d6b41a828b 478 * @param Settings This parameter can be a combination of the following values:
<> 156:95d6b41a828b 479 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
<> 156:95d6b41a828b 480 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128
<> 156:95d6b41a828b 481 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
<> 156:95d6b41a828b 482 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
<> 156:95d6b41a828b 483 * @retval None
<> 156:95d6b41a828b 484 */
<> 156:95d6b41a828b 485 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)
<> 156:95d6b41a828b 486 {
<> 156:95d6b41a828b 487 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
<> 156:95d6b41a828b 488 MODIFY_REG(CRS->CFGR,
<> 156:95d6b41a828b 489 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
<> 156:95d6b41a828b 490 ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
<> 156:95d6b41a828b 491 }
<> 156:95d6b41a828b 492
<> 156:95d6b41a828b 493 /**
<> 156:95d6b41a828b 494 * @}
<> 156:95d6b41a828b 495 */
<> 156:95d6b41a828b 496
<> 156:95d6b41a828b 497 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management
<> 156:95d6b41a828b 498 * @{
<> 156:95d6b41a828b 499 */
<> 156:95d6b41a828b 500
<> 156:95d6b41a828b 501 /**
<> 156:95d6b41a828b 502 * @brief Generate software SYNC event
<> 156:95d6b41a828b 503 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
<> 156:95d6b41a828b 504 * @retval None
<> 156:95d6b41a828b 505 */
<> 156:95d6b41a828b 506 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
<> 156:95d6b41a828b 507 {
<> 156:95d6b41a828b 508 SET_BIT(CRS->CR, CRS_CR_SWSYNC);
<> 156:95d6b41a828b 509 }
<> 156:95d6b41a828b 510
<> 156:95d6b41a828b 511 /**
<> 156:95d6b41a828b 512 * @brief Get the frequency error direction latched in the time of the last
<> 156:95d6b41a828b 513 * SYNC event
<> 156:95d6b41a828b 514 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
<> 156:95d6b41a828b 515 * @retval Returned value can be one of the following values:
<> 156:95d6b41a828b 516 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
<> 156:95d6b41a828b 517 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
<> 156:95d6b41a828b 518 */
<> 156:95d6b41a828b 519 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
<> 156:95d6b41a828b 520 {
<> 156:95d6b41a828b 521 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
<> 156:95d6b41a828b 522 }
<> 156:95d6b41a828b 523
<> 156:95d6b41a828b 524 /**
<> 156:95d6b41a828b 525 * @brief Get the frequency error counter value latched in the time of the last SYNC event
<> 156:95d6b41a828b 526 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
<> 156:95d6b41a828b 527 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
<> 156:95d6b41a828b 528 */
<> 156:95d6b41a828b 529 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
<> 156:95d6b41a828b 530 {
<> 156:95d6b41a828b 531 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
<> 156:95d6b41a828b 532 }
<> 156:95d6b41a828b 533
<> 156:95d6b41a828b 534 /**
<> 156:95d6b41a828b 535 * @}
<> 156:95d6b41a828b 536 */
<> 156:95d6b41a828b 537
<> 156:95d6b41a828b 538 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
<> 156:95d6b41a828b 539 * @{
<> 156:95d6b41a828b 540 */
<> 156:95d6b41a828b 541
<> 156:95d6b41a828b 542 /**
<> 156:95d6b41a828b 543 * @brief Check if SYNC event OK signal occurred or not
<> 156:95d6b41a828b 544 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
<> 156:95d6b41a828b 545 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 546 */
<> 156:95d6b41a828b 547 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
<> 156:95d6b41a828b 548 {
<> 156:95d6b41a828b 549 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF));
<> 156:95d6b41a828b 550 }
<> 156:95d6b41a828b 551
<> 156:95d6b41a828b 552 /**
<> 156:95d6b41a828b 553 * @brief Check if SYNC warning signal occurred or not
<> 156:95d6b41a828b 554 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
<> 156:95d6b41a828b 555 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 556 */
<> 156:95d6b41a828b 557 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
<> 156:95d6b41a828b 558 {
<> 156:95d6b41a828b 559 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF));
<> 156:95d6b41a828b 560 }
<> 156:95d6b41a828b 561
<> 156:95d6b41a828b 562 /**
<> 156:95d6b41a828b 563 * @brief Check if Synchronization or trimming error signal occurred or not
<> 156:95d6b41a828b 564 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
<> 156:95d6b41a828b 565 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 566 */
<> 156:95d6b41a828b 567 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
<> 156:95d6b41a828b 568 {
<> 156:95d6b41a828b 569 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF));
<> 156:95d6b41a828b 570 }
<> 156:95d6b41a828b 571
<> 156:95d6b41a828b 572 /**
<> 156:95d6b41a828b 573 * @brief Check if Expected SYNC signal occurred or not
<> 156:95d6b41a828b 574 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
<> 156:95d6b41a828b 575 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 576 */
<> 156:95d6b41a828b 577 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
<> 156:95d6b41a828b 578 {
<> 156:95d6b41a828b 579 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF));
<> 156:95d6b41a828b 580 }
<> 156:95d6b41a828b 581
<> 156:95d6b41a828b 582 /**
<> 156:95d6b41a828b 583 * @brief Check if SYNC error signal occurred or not
<> 156:95d6b41a828b 584 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
<> 156:95d6b41a828b 585 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 586 */
<> 156:95d6b41a828b 587 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
<> 156:95d6b41a828b 588 {
<> 156:95d6b41a828b 589 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR));
<> 156:95d6b41a828b 590 }
<> 156:95d6b41a828b 591
<> 156:95d6b41a828b 592 /**
<> 156:95d6b41a828b 593 * @brief Check if SYNC missed error signal occurred or not
<> 156:95d6b41a828b 594 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
<> 156:95d6b41a828b 595 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 596 */
<> 156:95d6b41a828b 597 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
<> 156:95d6b41a828b 598 {
<> 156:95d6b41a828b 599 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS));
<> 156:95d6b41a828b 600 }
<> 156:95d6b41a828b 601
<> 156:95d6b41a828b 602 /**
<> 156:95d6b41a828b 603 * @brief Check if Trimming overflow or underflow occurred or not
<> 156:95d6b41a828b 604 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
<> 156:95d6b41a828b 605 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 606 */
<> 156:95d6b41a828b 607 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
<> 156:95d6b41a828b 608 {
<> 156:95d6b41a828b 609 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF));
<> 156:95d6b41a828b 610 }
<> 156:95d6b41a828b 611
<> 156:95d6b41a828b 612 /**
<> 156:95d6b41a828b 613 * @brief Clear the SYNC event OK flag
<> 156:95d6b41a828b 614 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
<> 156:95d6b41a828b 615 * @retval None
<> 156:95d6b41a828b 616 */
<> 156:95d6b41a828b 617 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
<> 156:95d6b41a828b 618 {
<> 156:95d6b41a828b 619 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
<> 156:95d6b41a828b 620 }
<> 156:95d6b41a828b 621
<> 156:95d6b41a828b 622 /**
<> 156:95d6b41a828b 623 * @brief Clear the SYNC warning flag
<> 156:95d6b41a828b 624 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
<> 156:95d6b41a828b 625 * @retval None
<> 156:95d6b41a828b 626 */
<> 156:95d6b41a828b 627 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
<> 156:95d6b41a828b 628 {
<> 156:95d6b41a828b 629 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
<> 156:95d6b41a828b 630 }
<> 156:95d6b41a828b 631
<> 156:95d6b41a828b 632 /**
<> 156:95d6b41a828b 633 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
<> 156:95d6b41a828b 634 * the ERR flag
<> 156:95d6b41a828b 635 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
<> 156:95d6b41a828b 636 * @retval None
<> 156:95d6b41a828b 637 */
<> 156:95d6b41a828b 638 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
<> 156:95d6b41a828b 639 {
<> 156:95d6b41a828b 640 WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
<> 156:95d6b41a828b 641 }
<> 156:95d6b41a828b 642
<> 156:95d6b41a828b 643 /**
<> 156:95d6b41a828b 644 * @brief Clear Expected SYNC flag
<> 156:95d6b41a828b 645 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
<> 156:95d6b41a828b 646 * @retval None
<> 156:95d6b41a828b 647 */
<> 156:95d6b41a828b 648 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
<> 156:95d6b41a828b 649 {
<> 156:95d6b41a828b 650 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
<> 156:95d6b41a828b 651 }
<> 156:95d6b41a828b 652
<> 156:95d6b41a828b 653 /**
<> 156:95d6b41a828b 654 * @}
<> 156:95d6b41a828b 655 */
<> 156:95d6b41a828b 656
<> 156:95d6b41a828b 657 /** @defgroup CRS_LL_EF_IT_Management IT_Management
<> 156:95d6b41a828b 658 * @{
<> 156:95d6b41a828b 659 */
<> 156:95d6b41a828b 660
<> 156:95d6b41a828b 661 /**
<> 156:95d6b41a828b 662 * @brief Enable SYNC event OK interrupt
<> 156:95d6b41a828b 663 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
<> 156:95d6b41a828b 664 * @retval None
<> 156:95d6b41a828b 665 */
<> 156:95d6b41a828b 666 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
<> 156:95d6b41a828b 667 {
<> 156:95d6b41a828b 668 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
<> 156:95d6b41a828b 669 }
<> 156:95d6b41a828b 670
<> 156:95d6b41a828b 671 /**
<> 156:95d6b41a828b 672 * @brief Disable SYNC event OK interrupt
<> 156:95d6b41a828b 673 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
<> 156:95d6b41a828b 674 * @retval None
<> 156:95d6b41a828b 675 */
<> 156:95d6b41a828b 676 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
<> 156:95d6b41a828b 677 {
<> 156:95d6b41a828b 678 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
<> 156:95d6b41a828b 679 }
<> 156:95d6b41a828b 680
<> 156:95d6b41a828b 681 /**
<> 156:95d6b41a828b 682 * @brief Check if SYNC event OK interrupt is enabled or not
<> 156:95d6b41a828b 683 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
<> 156:95d6b41a828b 684 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 685 */
<> 156:95d6b41a828b 686 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
<> 156:95d6b41a828b 687 {
<> 156:95d6b41a828b 688 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE));
<> 156:95d6b41a828b 689 }
<> 156:95d6b41a828b 690
<> 156:95d6b41a828b 691 /**
<> 156:95d6b41a828b 692 * @brief Enable SYNC warning interrupt
<> 156:95d6b41a828b 693 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
<> 156:95d6b41a828b 694 * @retval None
<> 156:95d6b41a828b 695 */
<> 156:95d6b41a828b 696 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
<> 156:95d6b41a828b 697 {
<> 156:95d6b41a828b 698 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
<> 156:95d6b41a828b 699 }
<> 156:95d6b41a828b 700
<> 156:95d6b41a828b 701 /**
<> 156:95d6b41a828b 702 * @brief Disable SYNC warning interrupt
<> 156:95d6b41a828b 703 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
<> 156:95d6b41a828b 704 * @retval None
<> 156:95d6b41a828b 705 */
<> 156:95d6b41a828b 706 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
<> 156:95d6b41a828b 707 {
<> 156:95d6b41a828b 708 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
<> 156:95d6b41a828b 709 }
<> 156:95d6b41a828b 710
<> 156:95d6b41a828b 711 /**
<> 156:95d6b41a828b 712 * @brief Check if SYNC warning interrupt is enabled or not
<> 156:95d6b41a828b 713 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
<> 156:95d6b41a828b 714 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 715 */
<> 156:95d6b41a828b 716 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
<> 156:95d6b41a828b 717 {
<> 156:95d6b41a828b 718 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE));
<> 156:95d6b41a828b 719 }
<> 156:95d6b41a828b 720
<> 156:95d6b41a828b 721 /**
<> 156:95d6b41a828b 722 * @brief Enable Synchronization or trimming error interrupt
<> 156:95d6b41a828b 723 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
<> 156:95d6b41a828b 724 * @retval None
<> 156:95d6b41a828b 725 */
<> 156:95d6b41a828b 726 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
<> 156:95d6b41a828b 727 {
<> 156:95d6b41a828b 728 SET_BIT(CRS->CR, CRS_CR_ERRIE);
<> 156:95d6b41a828b 729 }
<> 156:95d6b41a828b 730
<> 156:95d6b41a828b 731 /**
<> 156:95d6b41a828b 732 * @brief Disable Synchronization or trimming error interrupt
<> 156:95d6b41a828b 733 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
<> 156:95d6b41a828b 734 * @retval None
<> 156:95d6b41a828b 735 */
<> 156:95d6b41a828b 736 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
<> 156:95d6b41a828b 737 {
<> 156:95d6b41a828b 738 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
<> 156:95d6b41a828b 739 }
<> 156:95d6b41a828b 740
<> 156:95d6b41a828b 741 /**
<> 156:95d6b41a828b 742 * @brief Check if Synchronization or trimming error interrupt is enabled or not
<> 156:95d6b41a828b 743 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
<> 156:95d6b41a828b 744 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 745 */
<> 156:95d6b41a828b 746 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
<> 156:95d6b41a828b 747 {
<> 156:95d6b41a828b 748 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE));
<> 156:95d6b41a828b 749 }
<> 156:95d6b41a828b 750
<> 156:95d6b41a828b 751 /**
<> 156:95d6b41a828b 752 * @brief Enable Expected SYNC interrupt
<> 156:95d6b41a828b 753 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
<> 156:95d6b41a828b 754 * @retval None
<> 156:95d6b41a828b 755 */
<> 156:95d6b41a828b 756 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
<> 156:95d6b41a828b 757 {
<> 156:95d6b41a828b 758 SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
<> 156:95d6b41a828b 759 }
<> 156:95d6b41a828b 760
<> 156:95d6b41a828b 761 /**
<> 156:95d6b41a828b 762 * @brief Disable Expected SYNC interrupt
<> 156:95d6b41a828b 763 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
<> 156:95d6b41a828b 764 * @retval None
<> 156:95d6b41a828b 765 */
<> 156:95d6b41a828b 766 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
<> 156:95d6b41a828b 767 {
<> 156:95d6b41a828b 768 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
<> 156:95d6b41a828b 769 }
<> 156:95d6b41a828b 770
<> 156:95d6b41a828b 771 /**
<> 156:95d6b41a828b 772 * @brief Check if Expected SYNC interrupt is enabled or not
<> 156:95d6b41a828b 773 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
<> 156:95d6b41a828b 774 * @retval State of bit (1 or 0).
<> 156:95d6b41a828b 775 */
<> 156:95d6b41a828b 776 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
<> 156:95d6b41a828b 777 {
<> 156:95d6b41a828b 778 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE));
<> 156:95d6b41a828b 779 }
<> 156:95d6b41a828b 780
<> 156:95d6b41a828b 781 /**
<> 156:95d6b41a828b 782 * @}
<> 156:95d6b41a828b 783 */
<> 156:95d6b41a828b 784
<> 156:95d6b41a828b 785 #if defined(USE_FULL_LL_DRIVER)
<> 156:95d6b41a828b 786 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
<> 156:95d6b41a828b 787 * @{
<> 156:95d6b41a828b 788 */
<> 156:95d6b41a828b 789
<> 156:95d6b41a828b 790 ErrorStatus LL_CRS_DeInit(void);
<> 156:95d6b41a828b 791
<> 156:95d6b41a828b 792 /**
<> 156:95d6b41a828b 793 * @}
<> 156:95d6b41a828b 794 */
<> 156:95d6b41a828b 795 #endif /* USE_FULL_LL_DRIVER */
<> 156:95d6b41a828b 796
<> 156:95d6b41a828b 797 /**
<> 156:95d6b41a828b 798 * @}
<> 156:95d6b41a828b 799 */
<> 156:95d6b41a828b 800
<> 156:95d6b41a828b 801 /**
<> 156:95d6b41a828b 802 * @}
<> 156:95d6b41a828b 803 */
<> 156:95d6b41a828b 804
<> 156:95d6b41a828b 805 #endif /* defined(CRS) */
<> 156:95d6b41a828b 806
<> 156:95d6b41a828b 807 /**
<> 156:95d6b41a828b 808 * @}
<> 156:95d6b41a828b 809 */
<> 156:95d6b41a828b 810
<> 156:95d6b41a828b 811 #ifdef __cplusplus
<> 156:95d6b41a828b 812 }
<> 156:95d6b41a828b 813 #endif
<> 156:95d6b41a828b 814
<> 156:95d6b41a828b 815 #endif /* __STM32F0xx_LL_CRS_H */
<> 156:95d6b41a828b 816
<> 156:95d6b41a828b 817 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/