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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h@149:156823d33999, 2016-10-28 (annotated)

Committer:: <>
Date:: Fri Oct 28 11:17:30 2016 +0100
Revision:: 149:156823d33999
Parent:: targets/cmsis/TARGET_STM/TARGET_STM32L4/stm32l4xx_hal_uart.h@144:ef7eb2e8f9f7
Child:: 167:e84263d55307

This updates the lib to the mbed lib v128

NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

User	Revision	Line number	New contents of line
<>	144:ef7eb2e8f9f7	1	/**
<>	144:ef7eb2e8f9f7	2	******************************************************************************
<>	144:ef7eb2e8f9f7	3	* @file stm32l4xx_hal_uart.h
<>	144:ef7eb2e8f9f7	4	* @author MCD Application Team
<>	144:ef7eb2e8f9f7	5	* @version V1.5.1
<>	144:ef7eb2e8f9f7	6	* @date 31-May-2016
<>	144:ef7eb2e8f9f7	7	* @brief Header file of UART HAL module.
<>	144:ef7eb2e8f9f7	8	******************************************************************************
<>	144:ef7eb2e8f9f7	9	* @attention
<>	144:ef7eb2e8f9f7	10	*
<>	144:ef7eb2e8f9f7	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<>	144:ef7eb2e8f9f7	12	*
<>	144:ef7eb2e8f9f7	13	* Redistribution and use in source and binary forms, with or without modification,
<>	144:ef7eb2e8f9f7	14	* are permitted provided that the following conditions are met:
<>	144:ef7eb2e8f9f7	15	* 1. Redistributions of source code must retain the above copyright notice,
<>	144:ef7eb2e8f9f7	16	* this list of conditions and the following disclaimer.
<>	144:ef7eb2e8f9f7	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
<>	144:ef7eb2e8f9f7	18	* this list of conditions and the following disclaimer in the documentation
<>	144:ef7eb2e8f9f7	19	* and/or other materials provided with the distribution.
<>	144:ef7eb2e8f9f7	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
<>	144:ef7eb2e8f9f7	21	* may be used to endorse or promote products derived from this software
<>	144:ef7eb2e8f9f7	22	* without specific prior written permission.
<>	144:ef7eb2e8f9f7	23	*
<>	144:ef7eb2e8f9f7	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<>	144:ef7eb2e8f9f7	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<>	144:ef7eb2e8f9f7	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<>	144:ef7eb2e8f9f7	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<>	144:ef7eb2e8f9f7	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<>	144:ef7eb2e8f9f7	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<>	144:ef7eb2e8f9f7	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<>	144:ef7eb2e8f9f7	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<>	144:ef7eb2e8f9f7	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<>	144:ef7eb2e8f9f7	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<>	144:ef7eb2e8f9f7	34	*
<>	144:ef7eb2e8f9f7	35	******************************************************************************
<>	144:ef7eb2e8f9f7	36	*/
<>	144:ef7eb2e8f9f7	37
<>	144:ef7eb2e8f9f7	38	/* Define to prevent recursive inclusion -------------------------------------*/
<>	144:ef7eb2e8f9f7	39	#ifndef __STM32L4xx_HAL_UART_H
<>	144:ef7eb2e8f9f7	40	#define __STM32L4xx_HAL_UART_H
<>	144:ef7eb2e8f9f7	41
<>	144:ef7eb2e8f9f7	42	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	43	extern "C" {
<>	144:ef7eb2e8f9f7	44	#endif
<>	144:ef7eb2e8f9f7	45
<>	144:ef7eb2e8f9f7	46	/* Includes ------------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	47	#include "stm32l4xx_hal_def.h"
<>	144:ef7eb2e8f9f7	48
<>	144:ef7eb2e8f9f7	49	/** @addtogroup STM32L4xx_HAL_Driver
<>	144:ef7eb2e8f9f7	50	* @{
<>	144:ef7eb2e8f9f7	51	*/
<>	144:ef7eb2e8f9f7	52
<>	144:ef7eb2e8f9f7	53	/** @addtogroup UART
<>	144:ef7eb2e8f9f7	54	* @{
<>	144:ef7eb2e8f9f7	55	*/
<>	144:ef7eb2e8f9f7	56
<>	144:ef7eb2e8f9f7	57	/* Exported types ------------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	58	/** @defgroup UART_Exported_Types UART Exported Types
<>	144:ef7eb2e8f9f7	59	* @{
<>	144:ef7eb2e8f9f7	60	*/
<>	144:ef7eb2e8f9f7	61
<>	144:ef7eb2e8f9f7	62	/**
<>	144:ef7eb2e8f9f7	63	* @brief UART Init Structure definition
<>	144:ef7eb2e8f9f7	64	*/
<>	144:ef7eb2e8f9f7	65	typedef struct
<>	144:ef7eb2e8f9f7	66	{
<>	144:ef7eb2e8f9f7	67	uint32_t BaudRate; /*!< This member configures the UART communication baud rate.
<>	144:ef7eb2e8f9f7	68	The baud rate register is computed using the following formula:
<>	144:ef7eb2e8f9f7	69	- If oversampling is 16 or in LIN mode,
<>	144:ef7eb2e8f9f7	70	Baud Rate Register = ((PCLKx) / ((huart->Init.BaudRate)))
<>	144:ef7eb2e8f9f7	71	- If oversampling is 8,
<>	144:ef7eb2e8f9f7	72	Baud Rate Register[15:4] = ((2 * PCLKx) / ((huart->Init.BaudRate)))[15:4]
<>	144:ef7eb2e8f9f7	73	Baud Rate Register[3] = 0
<>	144:ef7eb2e8f9f7	74	Baud Rate Register[2:0] = (((2 * PCLKx) / ((huart->Init.BaudRate)))[3:0]) >> 1 */
<>	144:ef7eb2e8f9f7	75
<>	144:ef7eb2e8f9f7	76	uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
<>	144:ef7eb2e8f9f7	77	This parameter can be a value of @ref UARTEx_Word_Length. */
<>	144:ef7eb2e8f9f7	78
<>	144:ef7eb2e8f9f7	79	uint32_t StopBits; /*!< Specifies the number of stop bits transmitted.
<>	144:ef7eb2e8f9f7	80	This parameter can be a value of @ref UART_Stop_Bits. */
<>	144:ef7eb2e8f9f7	81
<>	144:ef7eb2e8f9f7	82	uint32_t Parity; /*!< Specifies the parity mode.
<>	144:ef7eb2e8f9f7	83	This parameter can be a value of @ref UART_Parity
<>	144:ef7eb2e8f9f7	84	@note When parity is enabled, the computed parity is inserted
<>	144:ef7eb2e8f9f7	85	at the MSB position of the transmitted data (9th bit when
<>	144:ef7eb2e8f9f7	86	the word length is set to 9 data bits; 8th bit when the
<>	144:ef7eb2e8f9f7	87	word length is set to 8 data bits). */
<>	144:ef7eb2e8f9f7	88
<>	144:ef7eb2e8f9f7	89	uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
<>	144:ef7eb2e8f9f7	90	This parameter can be a value of @ref UART_Mode. */
<>	144:ef7eb2e8f9f7	91
<>	144:ef7eb2e8f9f7	92	uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled
<>	144:ef7eb2e8f9f7	93	or disabled.
<>	144:ef7eb2e8f9f7	94	This parameter can be a value of @ref UART_Hardware_Flow_Control. */
<>	144:ef7eb2e8f9f7	95
<>	144:ef7eb2e8f9f7	96	uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).
<>	144:ef7eb2e8f9f7	97	This parameter can be a value of @ref UART_Over_Sampling. */
<>	144:ef7eb2e8f9f7	98
<>	144:ef7eb2e8f9f7	99	uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected.
<>	144:ef7eb2e8f9f7	100	Selecting the single sample method increases the receiver tolerance to clock
<>	144:ef7eb2e8f9f7	101	deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
<>	144:ef7eb2e8f9f7	102	}UART_InitTypeDef;
<>	144:ef7eb2e8f9f7	103
<>	144:ef7eb2e8f9f7	104	/**
<>	144:ef7eb2e8f9f7	105	* @brief UART Advanced Features initalization structure definition
<>	144:ef7eb2e8f9f7	106	*/
<>	144:ef7eb2e8f9f7	107	typedef struct
<>	144:ef7eb2e8f9f7	108	{
<>	144:ef7eb2e8f9f7	109	uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several
<>	144:ef7eb2e8f9f7	110	Advanced Features may be initialized at the same time .
<>	144:ef7eb2e8f9f7	111	This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */
<>	144:ef7eb2e8f9f7	112
<>	144:ef7eb2e8f9f7	113	uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted.
<>	144:ef7eb2e8f9f7	114	This parameter can be a value of @ref UART_Tx_Inv. */
<>	144:ef7eb2e8f9f7	115
<>	144:ef7eb2e8f9f7	116	uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted.
<>	144:ef7eb2e8f9f7	117	This parameter can be a value of @ref UART_Rx_Inv. */
<>	144:ef7eb2e8f9f7	118
<>	144:ef7eb2e8f9f7	119	uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic
<>	144:ef7eb2e8f9f7	120	vs negative/inverted logic).
<>	144:ef7eb2e8f9f7	121	This parameter can be a value of @ref UART_Data_Inv. */
<>	144:ef7eb2e8f9f7	122
<>	144:ef7eb2e8f9f7	123	uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped.
<>	144:ef7eb2e8f9f7	124	This parameter can be a value of @ref UART_Rx_Tx_Swap. */
<>	144:ef7eb2e8f9f7	125
<>	144:ef7eb2e8f9f7	126	uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled.
<>	144:ef7eb2e8f9f7	127	This parameter can be a value of @ref UART_Overrun_Disable. */
<>	144:ef7eb2e8f9f7	128
<>	144:ef7eb2e8f9f7	129	uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error.
<>	144:ef7eb2e8f9f7	130	This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
<>	144:ef7eb2e8f9f7	131
<>	144:ef7eb2e8f9f7	132	uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled.
<>	144:ef7eb2e8f9f7	133	This parameter can be a value of @ref UART_AutoBaudRate_Enable */
<>	144:ef7eb2e8f9f7	134
<>	144:ef7eb2e8f9f7	135	uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate
<>	144:ef7eb2e8f9f7	136	detection is carried out.
<>	144:ef7eb2e8f9f7	137	This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
<>	144:ef7eb2e8f9f7	138
<>	144:ef7eb2e8f9f7	139	uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line.
<>	144:ef7eb2e8f9f7	140	This parameter can be a value of @ref UART_MSB_First. */
<>	144:ef7eb2e8f9f7	141	} UART_AdvFeatureInitTypeDef;
<>	144:ef7eb2e8f9f7	142
<>	144:ef7eb2e8f9f7	143
<>	144:ef7eb2e8f9f7	144
<>	144:ef7eb2e8f9f7	145	/**
<>	144:ef7eb2e8f9f7	146	* @brief HAL UART State structures definition
<>	144:ef7eb2e8f9f7	147	* @note HAL UART State value is a combination of 2 different substates: gState and RxState.
<>	144:ef7eb2e8f9f7	148	* - gState contains UART state information related to global Handle management
<>	144:ef7eb2e8f9f7	149	* and also information related to Tx operations.
<>	144:ef7eb2e8f9f7	150	* gState value coding follow below described bitmap :
<>	144:ef7eb2e8f9f7	151	* b7-b6 Error information
<>	144:ef7eb2e8f9f7	152	* 00 : No Error
<>	144:ef7eb2e8f9f7	153	* 01 : (Not Used)
<>	144:ef7eb2e8f9f7	154	* 10 : Timeout
<>	144:ef7eb2e8f9f7	155	* 11 : Error
<>	144:ef7eb2e8f9f7	156	* b5 IP initilisation status
<>	144:ef7eb2e8f9f7	157	* 0 : Reset (IP not initialized)
<>	144:ef7eb2e8f9f7	158	* 1 : Init done (IP not initialized. HAL UART Init function already called)
<>	144:ef7eb2e8f9f7	159	* b4-b3 (not used)
<>	144:ef7eb2e8f9f7	160	* xx : Should be set to 00
<>	144:ef7eb2e8f9f7	161	* b2 Intrinsic process state
<>	144:ef7eb2e8f9f7	162	* 0 : Ready
<>	144:ef7eb2e8f9f7	163	* 1 : Busy (IP busy with some configuration or internal operations)
<>	144:ef7eb2e8f9f7	164	* b1 (not used)
<>	144:ef7eb2e8f9f7	165	* x : Should be set to 0
<>	144:ef7eb2e8f9f7	166	* b0 Tx state
<>	144:ef7eb2e8f9f7	167	* 0 : Ready (no Tx operation ongoing)
<>	144:ef7eb2e8f9f7	168	* 1 : Busy (Tx operation ongoing)
<>	144:ef7eb2e8f9f7	169	* - RxState contains information related to Rx operations.
<>	144:ef7eb2e8f9f7	170	* RxState value coding follow below described bitmap :
<>	144:ef7eb2e8f9f7	171	* b7-b6 (not used)
<>	144:ef7eb2e8f9f7	172	* xx : Should be set to 00
<>	144:ef7eb2e8f9f7	173	* b5 IP initilisation status
<>	144:ef7eb2e8f9f7	174	* 0 : Reset (IP not initialized)
<>	144:ef7eb2e8f9f7	175	* 1 : Init done (IP not initialized)
<>	144:ef7eb2e8f9f7	176	* b4-b2 (not used)
<>	144:ef7eb2e8f9f7	177	* xxx : Should be set to 000
<>	144:ef7eb2e8f9f7	178	* b1 Rx state
<>	144:ef7eb2e8f9f7	179	* 0 : Ready (no Rx operation ongoing)
<>	144:ef7eb2e8f9f7	180	* 1 : Busy (Rx operation ongoing)
<>	144:ef7eb2e8f9f7	181	* b0 (not used)
<>	144:ef7eb2e8f9f7	182	* x : Should be set to 0.
<>	144:ef7eb2e8f9f7	183	*/
<>	144:ef7eb2e8f9f7	184	typedef enum
<>	144:ef7eb2e8f9f7	185	{
<>	144:ef7eb2e8f9f7	186	HAL_UART_STATE_RESET = 0x00U, /*!< Peripheral is not initialized
<>	144:ef7eb2e8f9f7	187	Value is allowed for gState and RxState */
<>	144:ef7eb2e8f9f7	188	HAL_UART_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
<>	144:ef7eb2e8f9f7	189	Value is allowed for gState and RxState */
<>	144:ef7eb2e8f9f7	190	HAL_UART_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
<>	144:ef7eb2e8f9f7	191	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	192	HAL_UART_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
<>	144:ef7eb2e8f9f7	193	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	194	HAL_UART_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
<>	144:ef7eb2e8f9f7	195	Value is allowed for RxState only */
<>	144:ef7eb2e8f9f7	196	HAL_UART_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
<>	144:ef7eb2e8f9f7	197	Not to be used for neither gState nor RxState.
<>	144:ef7eb2e8f9f7	198	Value is result of combination (Or) between gState and RxState values */
<>	144:ef7eb2e8f9f7	199	HAL_UART_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
<>	144:ef7eb2e8f9f7	200	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	201	HAL_UART_STATE_ERROR = 0xE0U /*!< Error
<>	144:ef7eb2e8f9f7	202	Value is allowed for gState only */
<>	144:ef7eb2e8f9f7	203	}HAL_UART_StateTypeDef;
<>	144:ef7eb2e8f9f7	204
<>	144:ef7eb2e8f9f7	205	/**
<>	144:ef7eb2e8f9f7	206	* @brief HAL UART Error Code structure definition
<>	144:ef7eb2e8f9f7	207	*/
<>	144:ef7eb2e8f9f7	208	typedef enum
<>	144:ef7eb2e8f9f7	209	{
<>	144:ef7eb2e8f9f7	210	HAL_UART_ERROR_NONE = 0x00, /!< No error /
<>	144:ef7eb2e8f9f7	211	HAL_UART_ERROR_PE = 0x01, /!< Parity error /
<>	144:ef7eb2e8f9f7	212	HAL_UART_ERROR_NE = 0x02, /!< Noise error /
<>	144:ef7eb2e8f9f7	213	HAL_UART_ERROR_FE = 0x04, /!< frame error /
<>	144:ef7eb2e8f9f7	214	HAL_UART_ERROR_ORE = 0x08, /!< Overrun error /
<>	144:ef7eb2e8f9f7	215	HAL_UART_ERROR_DMA = 0x10 /!< DMA transfer error /
<>	144:ef7eb2e8f9f7	216	}HAL_UART_ErrorTypeDef;
<>	144:ef7eb2e8f9f7	217
<>	144:ef7eb2e8f9f7	218	/**
<>	144:ef7eb2e8f9f7	219	* @brief UART clock sources definition
<>	144:ef7eb2e8f9f7	220	*/
<>	144:ef7eb2e8f9f7	221	typedef enum
<>	144:ef7eb2e8f9f7	222	{
<>	144:ef7eb2e8f9f7	223	UART_CLOCKSOURCE_PCLK1 = 0x00, /!< PCLK1 clock source /
<>	144:ef7eb2e8f9f7	224	UART_CLOCKSOURCE_PCLK2 = 0x01, /!< PCLK2 clock source /
<>	144:ef7eb2e8f9f7	225	UART_CLOCKSOURCE_HSI = 0x02, /!< HSI clock source /
<>	144:ef7eb2e8f9f7	226	UART_CLOCKSOURCE_SYSCLK = 0x04, /!< SYSCLK clock source /
<>	144:ef7eb2e8f9f7	227	UART_CLOCKSOURCE_LSE = 0x08, /!< LSE clock source /
<>	144:ef7eb2e8f9f7	228	UART_CLOCKSOURCE_UNDEFINED = 0x10 /!< Undefined clock source /
<>	144:ef7eb2e8f9f7	229	}UART_ClockSourceTypeDef;
<>	144:ef7eb2e8f9f7	230
<>	144:ef7eb2e8f9f7	231	/**
<>	144:ef7eb2e8f9f7	232	* @brief UART handle Structure definition
<>	144:ef7eb2e8f9f7	233	*/
<>	144:ef7eb2e8f9f7	234	typedef struct
<>	144:ef7eb2e8f9f7	235	{
<>	144:ef7eb2e8f9f7	236	USART_TypeDef Instance; /!< UART registers base address */
<>	144:ef7eb2e8f9f7	237
<>	144:ef7eb2e8f9f7	238	UART_InitTypeDef Init; /!< UART communication parameters /
<>	144:ef7eb2e8f9f7	239
<>	144:ef7eb2e8f9f7	240	UART_AdvFeatureInitTypeDef AdvancedInit; /!< UART Advanced Features initialization parameters /
<>	144:ef7eb2e8f9f7	241
<>	144:ef7eb2e8f9f7	242	uint8_t pTxBuffPtr; /!< Pointer to UART Tx transfer Buffer */
<>	144:ef7eb2e8f9f7	243
<>	144:ef7eb2e8f9f7	244	uint16_t TxXferSize; /!< UART Tx Transfer size /
<>	144:ef7eb2e8f9f7	245
<>	144:ef7eb2e8f9f7	246	uint16_t TxXferCount; /!< UART Tx Transfer Counter /
<>	144:ef7eb2e8f9f7	247
<>	144:ef7eb2e8f9f7	248	uint8_t pRxBuffPtr; /!< Pointer to UART Rx transfer Buffer */
<>	144:ef7eb2e8f9f7	249
<>	144:ef7eb2e8f9f7	250	uint16_t RxXferSize; /!< UART Rx Transfer size /
<>	144:ef7eb2e8f9f7	251
<>	144:ef7eb2e8f9f7	252	uint16_t RxXferCount; /!< UART Rx Transfer Counter /
<>	144:ef7eb2e8f9f7	253
<>	144:ef7eb2e8f9f7	254	uint16_t Mask; /!< UART Rx RDR register mask /
<>	144:ef7eb2e8f9f7	255
<>	144:ef7eb2e8f9f7	256	DMA_HandleTypeDef hdmatx; /!< UART Tx DMA Handle parameters */
<>	144:ef7eb2e8f9f7	257
<>	144:ef7eb2e8f9f7	258	DMA_HandleTypeDef hdmarx; /!< UART Rx DMA Handle parameters */
<>	144:ef7eb2e8f9f7	259
<>	144:ef7eb2e8f9f7	260	HAL_LockTypeDef Lock; /!< Locking object /
<>	144:ef7eb2e8f9f7	261
<>	144:ef7eb2e8f9f7	262	__IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management
<>	144:ef7eb2e8f9f7	263	and also related to Tx operations.
<>	144:ef7eb2e8f9f7	264	This parameter can be a value of @ref HAL_UART_StateTypeDef */
<>	144:ef7eb2e8f9f7	265
<>	144:ef7eb2e8f9f7	266	__IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations.
<>	144:ef7eb2e8f9f7	267	This parameter can be a value of @ref HAL_UART_StateTypeDef */
<>	144:ef7eb2e8f9f7	268
<>	144:ef7eb2e8f9f7	269	__IO uint32_t ErrorCode; /!< UART Error code /
<>	144:ef7eb2e8f9f7	270
<>	144:ef7eb2e8f9f7	271	}UART_HandleTypeDef;
<>	144:ef7eb2e8f9f7	272
<>	144:ef7eb2e8f9f7	273	/**
<>	144:ef7eb2e8f9f7	274	* @}
<>	144:ef7eb2e8f9f7	275	*/
<>	144:ef7eb2e8f9f7	276
<>	144:ef7eb2e8f9f7	277	/* Exported constants --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	278	/** @defgroup UART_Exported_Constants UART Exported Constants
<>	144:ef7eb2e8f9f7	279	* @{
<>	144:ef7eb2e8f9f7	280	*/
<>	144:ef7eb2e8f9f7	281
<>	144:ef7eb2e8f9f7	282	/** @defgroup UART_Stop_Bits UART Number of Stop Bits
<>	144:ef7eb2e8f9f7	283	* @{
<>	144:ef7eb2e8f9f7	284	*/
<>	144:ef7eb2e8f9f7	285	#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /!< UART frame with 0.5 stop bit /
<>	144:ef7eb2e8f9f7	286	#define UART_STOPBITS_1 ((uint32_t)0x00000000) /!< UART frame with 1 stop bit /
<>	144:ef7eb2e8f9f7	287	#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 \| USART_CR2_STOP_1) /!< UART frame with 1.5 stop bits /
<>	144:ef7eb2e8f9f7	288	#define UART_STOPBITS_2 USART_CR2_STOP_1 /!< UART frame with 2 stop bits /
<>	144:ef7eb2e8f9f7	289	/**
<>	144:ef7eb2e8f9f7	290	* @}
<>	144:ef7eb2e8f9f7	291	*/
<>	144:ef7eb2e8f9f7	292
<>	144:ef7eb2e8f9f7	293	/** @defgroup UART_Parity UART Parity
<>	144:ef7eb2e8f9f7	294	* @{
<>	144:ef7eb2e8f9f7	295	*/
<>	144:ef7eb2e8f9f7	296	#define UART_PARITY_NONE ((uint32_t)0x00000000) /!< No parity /
<>	144:ef7eb2e8f9f7	297	#define UART_PARITY_EVEN ((uint32_t)USART_CR1_PCE) /!< Even parity /
<>	144:ef7eb2e8f9f7	298	#define UART_PARITY_ODD ((uint32_t)(USART_CR1_PCE \| USART_CR1_PS)) /!< Odd parity /
<>	144:ef7eb2e8f9f7	299	/**
<>	144:ef7eb2e8f9f7	300	* @}
<>	144:ef7eb2e8f9f7	301	*/
<>	144:ef7eb2e8f9f7	302
<>	144:ef7eb2e8f9f7	303	/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
<>	144:ef7eb2e8f9f7	304	* @{
<>	144:ef7eb2e8f9f7	305	*/
<>	144:ef7eb2e8f9f7	306	#define UART_HWCONTROL_NONE ((uint32_t)0x00000000) /!< No hardware control /
<>	144:ef7eb2e8f9f7	307	#define UART_HWCONTROL_RTS ((uint32_t)USART_CR3_RTSE) /!< Request To Send /
<>	144:ef7eb2e8f9f7	308	#define UART_HWCONTROL_CTS ((uint32_t)USART_CR3_CTSE) /!< Clear To Send /
<>	144:ef7eb2e8f9f7	309	#define UART_HWCONTROL_RTS_CTS ((uint32_t)(USART_CR3_RTSE \| USART_CR3_CTSE)) /!< Request and Clear To Send /
<>	144:ef7eb2e8f9f7	310	/**
<>	144:ef7eb2e8f9f7	311	* @}
<>	144:ef7eb2e8f9f7	312	*/
<>	144:ef7eb2e8f9f7	313
<>	144:ef7eb2e8f9f7	314	/** @defgroup UART_Mode UART Transfer Mode
<>	144:ef7eb2e8f9f7	315	* @{
<>	144:ef7eb2e8f9f7	316	*/
<>	144:ef7eb2e8f9f7	317	#define UART_MODE_RX ((uint32_t)USART_CR1_RE) /!< RX mode /
<>	144:ef7eb2e8f9f7	318	#define UART_MODE_TX ((uint32_t)USART_CR1_TE) /!< TX mode /
<>	144:ef7eb2e8f9f7	319	#define UART_MODE_TX_RX ((uint32_t)(USART_CR1_TE \|USART_CR1_RE)) /!< RX and TX mode /
<>	144:ef7eb2e8f9f7	320	/**
<>	144:ef7eb2e8f9f7	321	* @}
<>	144:ef7eb2e8f9f7	322	*/
<>	144:ef7eb2e8f9f7	323
<>	144:ef7eb2e8f9f7	324	/** @defgroup UART_State UART State
<>	144:ef7eb2e8f9f7	325	* @{
<>	144:ef7eb2e8f9f7	326	*/
<>	144:ef7eb2e8f9f7	327	#define UART_STATE_DISABLE ((uint32_t)0x00000000) /!< UART disabled /
<>	144:ef7eb2e8f9f7	328	#define UART_STATE_ENABLE ((uint32_t)USART_CR1_UE) /!< UART enabled /
<>	144:ef7eb2e8f9f7	329	/**
<>	144:ef7eb2e8f9f7	330	* @}
<>	144:ef7eb2e8f9f7	331	*/
<>	144:ef7eb2e8f9f7	332
<>	144:ef7eb2e8f9f7	333	/** @defgroup UART_Over_Sampling UART Over Sampling
<>	144:ef7eb2e8f9f7	334	* @{
<>	144:ef7eb2e8f9f7	335	*/
<>	144:ef7eb2e8f9f7	336	#define UART_OVERSAMPLING_16 ((uint32_t)0x00000000) /!< Oversampling by 16 /
<>	144:ef7eb2e8f9f7	337	#define UART_OVERSAMPLING_8 ((uint32_t)USART_CR1_OVER8) /!< Oversampling by 8 /
<>	144:ef7eb2e8f9f7	338	/**
<>	144:ef7eb2e8f9f7	339	* @}
<>	144:ef7eb2e8f9f7	340	*/
<>	144:ef7eb2e8f9f7	341
<>	144:ef7eb2e8f9f7	342	/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
<>	144:ef7eb2e8f9f7	343	* @{
<>	144:ef7eb2e8f9f7	344	*/
<>	144:ef7eb2e8f9f7	345	#define UART_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000) /!< One-bit sampling disable /
<>	144:ef7eb2e8f9f7	346	#define UART_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT) /!< One-bit sampling enable /
<>	144:ef7eb2e8f9f7	347	/**
<>	144:ef7eb2e8f9f7	348	* @}
<>	144:ef7eb2e8f9f7	349	*/
<>	144:ef7eb2e8f9f7	350
<>	144:ef7eb2e8f9f7	351	/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode
<>	144:ef7eb2e8f9f7	352	* @{
<>	144:ef7eb2e8f9f7	353	*/
<>	144:ef7eb2e8f9f7	354	#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT ((uint32_t)0x00000000) /!< Auto Baud rate detection on start bit /
<>	144:ef7eb2e8f9f7	355	#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE ((uint32_t)USART_CR2_ABRMODE_0) /!< Auto Baud rate detection on falling edge /
<>	144:ef7eb2e8f9f7	356	#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME ((uint32_t)USART_CR2_ABRMODE_1) /!< Auto Baud rate detection on 0x7F frame detection /
<>	144:ef7eb2e8f9f7	357	#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME ((uint32_t)USART_CR2_ABRMODE) /!< Auto Baud rate detection on 0x55 frame detection /
<>	144:ef7eb2e8f9f7	358	/**
<>	144:ef7eb2e8f9f7	359	* @}
<>	144:ef7eb2e8f9f7	360	*/
<>	144:ef7eb2e8f9f7	361
<>	144:ef7eb2e8f9f7	362	/** @defgroup UART_Receiver_TimeOut UART Receiver TimeOut
<>	144:ef7eb2e8f9f7	363	* @{
<>	144:ef7eb2e8f9f7	364	*/
<>	144:ef7eb2e8f9f7	365	#define UART_RECEIVER_TIMEOUT_DISABLE ((uint32_t)0x00000000) /!< UART receiver timeout disable /
<>	144:ef7eb2e8f9f7	366	#define UART_RECEIVER_TIMEOUT_ENABLE ((uint32_t)USART_CR2_RTOEN) /!< UART receiver timeout enable /
<>	144:ef7eb2e8f9f7	367	/**
<>	144:ef7eb2e8f9f7	368	* @}
<>	144:ef7eb2e8f9f7	369	*/
<>	144:ef7eb2e8f9f7	370
<>	144:ef7eb2e8f9f7	371	/** @defgroup UART_LIN UART Local Interconnection Network mode
<>	144:ef7eb2e8f9f7	372	* @{
<>	144:ef7eb2e8f9f7	373	*/
<>	144:ef7eb2e8f9f7	374	#define UART_LIN_DISABLE ((uint32_t)0x00000000) /!< Local Interconnect Network disable /
<>	144:ef7eb2e8f9f7	375	#define UART_LIN_ENABLE ((uint32_t)USART_CR2_LINEN) /!< Local Interconnect Network enable /
<>	144:ef7eb2e8f9f7	376	/**
<>	144:ef7eb2e8f9f7	377	* @}
<>	144:ef7eb2e8f9f7	378	*/
<>	144:ef7eb2e8f9f7	379
<>	144:ef7eb2e8f9f7	380	/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection
<>	144:ef7eb2e8f9f7	381	* @{
<>	144:ef7eb2e8f9f7	382	*/
<>	144:ef7eb2e8f9f7	383	#define UART_LINBREAKDETECTLENGTH_10B ((uint32_t)0x00000000) /!< LIN 10-bit break detection length /
<>	144:ef7eb2e8f9f7	384	#define UART_LINBREAKDETECTLENGTH_11B ((uint32_t)USART_CR2_LBDL) /!< LIN 11-bit break detection length /
<>	144:ef7eb2e8f9f7	385	/**
<>	144:ef7eb2e8f9f7	386	* @}
<>	144:ef7eb2e8f9f7	387	*/
<>	144:ef7eb2e8f9f7	388
<>	144:ef7eb2e8f9f7	389	/** @defgroup UART_DMA_Tx UART DMA Tx
<>	144:ef7eb2e8f9f7	390	* @{
<>	144:ef7eb2e8f9f7	391	*/
<>	144:ef7eb2e8f9f7	392	#define UART_DMA_TX_DISABLE ((uint32_t)0x00000000) /!< UART DMA TX disabled /
<>	144:ef7eb2e8f9f7	393	#define UART_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT) /!< UART DMA TX enabled /
<>	144:ef7eb2e8f9f7	394	/**
<>	144:ef7eb2e8f9f7	395	* @}
<>	144:ef7eb2e8f9f7	396	*/
<>	144:ef7eb2e8f9f7	397
<>	144:ef7eb2e8f9f7	398	/** @defgroup UART_DMA_Rx UART DMA Rx
<>	144:ef7eb2e8f9f7	399	* @{
<>	144:ef7eb2e8f9f7	400	*/
<>	144:ef7eb2e8f9f7	401	#define UART_DMA_RX_DISABLE ((uint32_t)0x00000000) /!< UART DMA RX disabled /
<>	144:ef7eb2e8f9f7	402	#define UART_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR) /!< UART DMA RX enabled /
<>	144:ef7eb2e8f9f7	403	/**
<>	144:ef7eb2e8f9f7	404	* @}
<>	144:ef7eb2e8f9f7	405	*/
<>	144:ef7eb2e8f9f7	406
<>	144:ef7eb2e8f9f7	407	/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection
<>	144:ef7eb2e8f9f7	408	* @{
<>	144:ef7eb2e8f9f7	409	*/
<>	144:ef7eb2e8f9f7	410	#define UART_HALF_DUPLEX_DISABLE ((uint32_t)0x00000000) /!< UART half-duplex disabled /
<>	144:ef7eb2e8f9f7	411	#define UART_HALF_DUPLEX_ENABLE ((uint32_t)USART_CR3_HDSEL) /!< UART half-duplex enabled /
<>	144:ef7eb2e8f9f7	412	/**
<>	144:ef7eb2e8f9f7	413	* @}
<>	144:ef7eb2e8f9f7	414	*/
<>	144:ef7eb2e8f9f7	415
<>	144:ef7eb2e8f9f7	416	/** @defgroup UART_WakeUp_Methods UART WakeUp Methods
<>	144:ef7eb2e8f9f7	417	* @{
<>	144:ef7eb2e8f9f7	418	*/
<>	144:ef7eb2e8f9f7	419	#define UART_WAKEUPMETHOD_IDLELINE ((uint32_t)0x00000000) /!< UART wake-up on idle line /
<>	144:ef7eb2e8f9f7	420	#define UART_WAKEUPMETHOD_ADDRESSMARK ((uint32_t)USART_CR1_WAKE) /!< UART wake-up on address mark /
<>	144:ef7eb2e8f9f7	421	/**
<>	144:ef7eb2e8f9f7	422	* @}
<>	144:ef7eb2e8f9f7	423	*/
<>	144:ef7eb2e8f9f7	424
<>	144:ef7eb2e8f9f7	425	/** @defgroup UART_Request_Parameters UART Request Parameters
<>	144:ef7eb2e8f9f7	426	* @{
<>	144:ef7eb2e8f9f7	427	*/
<>	144:ef7eb2e8f9f7	428	#define UART_AUTOBAUD_REQUEST ((uint32_t)USART_RQR_ABRRQ) /!< Auto-Baud Rate Request /
<>	144:ef7eb2e8f9f7	429	#define UART_SENDBREAK_REQUEST ((uint32_t)USART_RQR_SBKRQ) /!< Send Break Request /
<>	144:ef7eb2e8f9f7	430	#define UART_MUTE_MODE_REQUEST ((uint32_t)USART_RQR_MMRQ) /!< Mute Mode Request /
<>	144:ef7eb2e8f9f7	431	#define UART_RXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_RXFRQ) /!< Receive Data flush Request /
<>	144:ef7eb2e8f9f7	432	#define UART_TXDATA_FLUSH_REQUEST ((uint32_t)USART_RQR_TXFRQ) /!< Transmit data flush Request /
<>	144:ef7eb2e8f9f7	433	/**
<>	144:ef7eb2e8f9f7	434	* @}
<>	144:ef7eb2e8f9f7	435	*/
<>	144:ef7eb2e8f9f7	436
<>	144:ef7eb2e8f9f7	437	/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type
<>	144:ef7eb2e8f9f7	438	* @{
<>	144:ef7eb2e8f9f7	439	*/
<>	144:ef7eb2e8f9f7	440	#define UART_ADVFEATURE_NO_INIT ((uint32_t)0x00000000) /!< No advanced feature initialization /
<>	144:ef7eb2e8f9f7	441	#define UART_ADVFEATURE_TXINVERT_INIT ((uint32_t)0x00000001) /!< TX pin active level inversion /
<>	144:ef7eb2e8f9f7	442	#define UART_ADVFEATURE_RXINVERT_INIT ((uint32_t)0x00000002) /!< RX pin active level inversion /
<>	144:ef7eb2e8f9f7	443	#define UART_ADVFEATURE_DATAINVERT_INIT ((uint32_t)0x00000004) /!< Binary data inversion /
<>	144:ef7eb2e8f9f7	444	#define UART_ADVFEATURE_SWAP_INIT ((uint32_t)0x00000008) /!< TX/RX pins swap /
<>	144:ef7eb2e8f9f7	445	#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT ((uint32_t)0x00000010) /!< RX overrun disable /
<>	144:ef7eb2e8f9f7	446	#define UART_ADVFEATURE_DMADISABLEONERROR_INIT ((uint32_t)0x00000020) /!< DMA disable on Reception Error /
<>	144:ef7eb2e8f9f7	447	#define UART_ADVFEATURE_AUTOBAUDRATE_INIT ((uint32_t)0x00000040) /!< Auto Baud rate detection initialization /
<>	144:ef7eb2e8f9f7	448	#define UART_ADVFEATURE_MSBFIRST_INIT ((uint32_t)0x00000080) /!< Most significant bit sent/received first /
<>	144:ef7eb2e8f9f7	449	/**
<>	144:ef7eb2e8f9f7	450	* @}
<>	144:ef7eb2e8f9f7	451	*/
<>	144:ef7eb2e8f9f7	452
<>	144:ef7eb2e8f9f7	453	/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
<>	144:ef7eb2e8f9f7	454	* @{
<>	144:ef7eb2e8f9f7	455	*/
<>	144:ef7eb2e8f9f7	456	#define UART_ADVFEATURE_TXINV_DISABLE ((uint32_t)0x00000000) /!< TX pin active level inversion disable /
<>	144:ef7eb2e8f9f7	457	#define UART_ADVFEATURE_TXINV_ENABLE ((uint32_t)USART_CR2_TXINV) /!< TX pin active level inversion enable /
<>	144:ef7eb2e8f9f7	458	/**
<>	144:ef7eb2e8f9f7	459	* @}
<>	144:ef7eb2e8f9f7	460	*/
<>	144:ef7eb2e8f9f7	461
<>	144:ef7eb2e8f9f7	462	/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
<>	144:ef7eb2e8f9f7	463	* @{
<>	144:ef7eb2e8f9f7	464	*/
<>	144:ef7eb2e8f9f7	465	#define UART_ADVFEATURE_RXINV_DISABLE ((uint32_t)0x00000000) /!< RX pin active level inversion disable /
<>	144:ef7eb2e8f9f7	466	#define UART_ADVFEATURE_RXINV_ENABLE ((uint32_t)USART_CR2_RXINV) /!< RX pin active level inversion enable /
<>	144:ef7eb2e8f9f7	467	/**
<>	144:ef7eb2e8f9f7	468	* @}
<>	144:ef7eb2e8f9f7	469	*/
<>	144:ef7eb2e8f9f7	470
<>	144:ef7eb2e8f9f7	471	/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion
<>	144:ef7eb2e8f9f7	472	* @{
<>	144:ef7eb2e8f9f7	473	*/
<>	144:ef7eb2e8f9f7	474	#define UART_ADVFEATURE_DATAINV_DISABLE ((uint32_t)0x00000000) /!< Binary data inversion disable /
<>	144:ef7eb2e8f9f7	475	#define UART_ADVFEATURE_DATAINV_ENABLE ((uint32_t)USART_CR2_DATAINV) /!< Binary data inversion enable /
<>	144:ef7eb2e8f9f7	476	/**
<>	144:ef7eb2e8f9f7	477	* @}
<>	144:ef7eb2e8f9f7	478	*/
<>	144:ef7eb2e8f9f7	479
<>	144:ef7eb2e8f9f7	480	/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
<>	144:ef7eb2e8f9f7	481	* @{
<>	144:ef7eb2e8f9f7	482	*/
<>	144:ef7eb2e8f9f7	483	#define UART_ADVFEATURE_SWAP_DISABLE ((uint32_t)0x00000000) /!< TX/RX pins swap disable /
<>	144:ef7eb2e8f9f7	484	#define UART_ADVFEATURE_SWAP_ENABLE ((uint32_t)USART_CR2_SWAP) /!< TX/RX pins swap enable /
<>	144:ef7eb2e8f9f7	485	/**
<>	144:ef7eb2e8f9f7	486	* @}
<>	144:ef7eb2e8f9f7	487	*/
<>	144:ef7eb2e8f9f7	488
<>	144:ef7eb2e8f9f7	489	/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable
<>	144:ef7eb2e8f9f7	490	* @{
<>	144:ef7eb2e8f9f7	491	*/
<>	144:ef7eb2e8f9f7	492	#define UART_ADVFEATURE_OVERRUN_ENABLE ((uint32_t)0x00000000) /!< RX overrun enable /
<>	144:ef7eb2e8f9f7	493	#define UART_ADVFEATURE_OVERRUN_DISABLE ((uint32_t)USART_CR3_OVRDIS) /!< RX overrun disable /
<>	144:ef7eb2e8f9f7	494	/**
<>	144:ef7eb2e8f9f7	495	* @}
<>	144:ef7eb2e8f9f7	496	*/
<>	144:ef7eb2e8f9f7	497
<>	144:ef7eb2e8f9f7	498	/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable
<>	144:ef7eb2e8f9f7	499	* @{
<>	144:ef7eb2e8f9f7	500	*/
<>	144:ef7eb2e8f9f7	501	#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE ((uint32_t)0x00000000) /!< RX Auto Baud rate detection enable /
<>	144:ef7eb2e8f9f7	502	#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE ((uint32_t)USART_CR2_ABREN) /!< RX Auto Baud rate detection disable /
<>	144:ef7eb2e8f9f7	503	/**
<>	144:ef7eb2e8f9f7	504	* @}
<>	144:ef7eb2e8f9f7	505	*/
<>	144:ef7eb2e8f9f7	506
<>	144:ef7eb2e8f9f7	507	/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error
<>	144:ef7eb2e8f9f7	508	* @{
<>	144:ef7eb2e8f9f7	509	*/
<>	144:ef7eb2e8f9f7	510	#define UART_ADVFEATURE_DMA_ENABLEONRXERROR ((uint32_t)0x00000000) /!< DMA enable on Reception Error /
<>	144:ef7eb2e8f9f7	511	#define UART_ADVFEATURE_DMA_DISABLEONRXERROR ((uint32_t)USART_CR3_DDRE) /!< DMA disable on Reception Error /
<>	144:ef7eb2e8f9f7	512	/**
<>	144:ef7eb2e8f9f7	513	* @}
<>	144:ef7eb2e8f9f7	514	*/
<>	144:ef7eb2e8f9f7	515
<>	144:ef7eb2e8f9f7	516	/** @defgroup UART_MSB_First UART Advanced Feature MSB First
<>	144:ef7eb2e8f9f7	517	* @{
<>	144:ef7eb2e8f9f7	518	*/
<>	144:ef7eb2e8f9f7	519	#define UART_ADVFEATURE_MSBFIRST_DISABLE ((uint32_t)0x00000000) /!< Most significant bit sent/received first disable /
<>	144:ef7eb2e8f9f7	520	#define UART_ADVFEATURE_MSBFIRST_ENABLE ((uint32_t)USART_CR2_MSBFIRST) /!< Most significant bit sent/received first enable /
<>	144:ef7eb2e8f9f7	521	/**
<>	144:ef7eb2e8f9f7	522	* @}
<>	144:ef7eb2e8f9f7	523	*/
<>	144:ef7eb2e8f9f7	524
<>	144:ef7eb2e8f9f7	525	/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable
<>	144:ef7eb2e8f9f7	526	* @{
<>	144:ef7eb2e8f9f7	527	*/
<>	144:ef7eb2e8f9f7	528	#define UART_ADVFEATURE_STOPMODE_DISABLE ((uint32_t)0x00000000) /!< UART stop mode disable /
<>	144:ef7eb2e8f9f7	529	#define UART_ADVFEATURE_STOPMODE_ENABLE ((uint32_t)USART_CR1_UESM) /!< UART stop mode enable /
<>	144:ef7eb2e8f9f7	530	/**
<>	144:ef7eb2e8f9f7	531	* @}
<>	144:ef7eb2e8f9f7	532	*/
<>	144:ef7eb2e8f9f7	533
<>	144:ef7eb2e8f9f7	534	/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable
<>	144:ef7eb2e8f9f7	535	* @{
<>	144:ef7eb2e8f9f7	536	*/
<>	144:ef7eb2e8f9f7	537	#define UART_ADVFEATURE_MUTEMODE_DISABLE ((uint32_t)0x00000000) /!< UART mute mode disable /
<>	144:ef7eb2e8f9f7	538	#define UART_ADVFEATURE_MUTEMODE_ENABLE ((uint32_t)USART_CR1_MME) /!< UART mute mode enable /
<>	144:ef7eb2e8f9f7	539	/**
<>	144:ef7eb2e8f9f7	540	* @}
<>	144:ef7eb2e8f9f7	541	*/
<>	144:ef7eb2e8f9f7	542
<>	144:ef7eb2e8f9f7	543	/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register
<>	144:ef7eb2e8f9f7	544	* @{
<>	144:ef7eb2e8f9f7	545	*/
<>	144:ef7eb2e8f9f7	546	#define UART_CR2_ADDRESS_LSB_POS ((uint32_t) 24) /!< UART address-matching LSB position in CR2 register /
<>	144:ef7eb2e8f9f7	547	/**
<>	144:ef7eb2e8f9f7	548	* @}
<>	144:ef7eb2e8f9f7	549	*/
<>	144:ef7eb2e8f9f7	550
<>	144:ef7eb2e8f9f7	551	/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection
<>	144:ef7eb2e8f9f7	552	* @{
<>	144:ef7eb2e8f9f7	553	*/
<>	144:ef7eb2e8f9f7	554	#define UART_WAKEUP_ON_ADDRESS ((uint32_t)0x00000000) /!< UART wake-up on address /
<>	144:ef7eb2e8f9f7	555	#define UART_WAKEUP_ON_STARTBIT ((uint32_t)USART_CR3_WUS_1) /!< UART wake-up on start bit /
<>	144:ef7eb2e8f9f7	556	#define UART_WAKEUP_ON_READDATA_NONEMPTY ((uint32_t)USART_CR3_WUS) /!< UART wake-up on receive data register not empty /
<>	144:ef7eb2e8f9f7	557	/**
<>	144:ef7eb2e8f9f7	558	* @}
<>	144:ef7eb2e8f9f7	559	*/
<>	144:ef7eb2e8f9f7	560
<>	144:ef7eb2e8f9f7	561	/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity
<>	144:ef7eb2e8f9f7	562	* @{
<>	144:ef7eb2e8f9f7	563	*/
<>	144:ef7eb2e8f9f7	564	#define UART_DE_POLARITY_HIGH ((uint32_t)0x00000000) /!< Driver enable signal is active high /
<>	144:ef7eb2e8f9f7	565	#define UART_DE_POLARITY_LOW ((uint32_t)USART_CR3_DEP) /!< Driver enable signal is active low /
<>	144:ef7eb2e8f9f7	566	/**
<>	144:ef7eb2e8f9f7	567	* @}
<>	144:ef7eb2e8f9f7	568	*/
<>	144:ef7eb2e8f9f7	569
<>	144:ef7eb2e8f9f7	570	/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register
<>	144:ef7eb2e8f9f7	571	* @{
<>	144:ef7eb2e8f9f7	572	*/
<>	144:ef7eb2e8f9f7	573	#define UART_CR1_DEAT_ADDRESS_LSB_POS ((uint32_t) 21) /!< UART Driver Enable assertion time LSB position in CR1 register /
<>	144:ef7eb2e8f9f7	574	/**
<>	144:ef7eb2e8f9f7	575	* @}
<>	144:ef7eb2e8f9f7	576	*/
<>	144:ef7eb2e8f9f7	577
<>	144:ef7eb2e8f9f7	578	/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register
<>	144:ef7eb2e8f9f7	579	* @{
<>	144:ef7eb2e8f9f7	580	*/
<>	144:ef7eb2e8f9f7	581	#define UART_CR1_DEDT_ADDRESS_LSB_POS ((uint32_t) 16) /!< UART Driver Enable de-assertion time LSB position in CR1 register /
<>	144:ef7eb2e8f9f7	582	/**
<>	144:ef7eb2e8f9f7	583	* @}
<>	144:ef7eb2e8f9f7	584	*/
<>	144:ef7eb2e8f9f7	585
<>	144:ef7eb2e8f9f7	586	/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask
<>	144:ef7eb2e8f9f7	587	* @{
<>	144:ef7eb2e8f9f7	588	*/
<>	144:ef7eb2e8f9f7	589	#define UART_IT_MASK ((uint32_t)0x001F) /!< UART interruptions flags mask /
<>	144:ef7eb2e8f9f7	590	/**
<>	144:ef7eb2e8f9f7	591	* @}
<>	144:ef7eb2e8f9f7	592	*/
<>	144:ef7eb2e8f9f7	593
<>	144:ef7eb2e8f9f7	594	/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value
<>	144:ef7eb2e8f9f7	595	* @{
<>	144:ef7eb2e8f9f7	596	*/
<>	144:ef7eb2e8f9f7	597	#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFF /!< UART polling-based communications time-out value /
<>	144:ef7eb2e8f9f7	598	/**
<>	144:ef7eb2e8f9f7	599	* @}
<>	144:ef7eb2e8f9f7	600	*/
<>	144:ef7eb2e8f9f7	601
<>	144:ef7eb2e8f9f7	602	/** @defgroup UART_Flags UART Status Flags
<>	144:ef7eb2e8f9f7	603	* Elements values convention: 0xXXXX
<>	144:ef7eb2e8f9f7	604	* - 0xXXXX : Flag mask in the ISR register
<>	144:ef7eb2e8f9f7	605	* @{
<>	144:ef7eb2e8f9f7	606	*/
<>	144:ef7eb2e8f9f7	607	#define UART_FLAG_REACK ((uint32_t)0x00400000) /!< UART receive enable acknowledge flag /
<>	144:ef7eb2e8f9f7	608	#define UART_FLAG_TEACK ((uint32_t)0x00200000) /!< UART transmit enable acknowledge flag /
<>	144:ef7eb2e8f9f7	609	#define UART_FLAG_WUF ((uint32_t)0x00100000) /!< UART wake-up from stop mode flag /
<>	144:ef7eb2e8f9f7	610	#define UART_FLAG_RWU ((uint32_t)0x00080000) /!< UART receiver wake-up from mute mode flag /
<>	144:ef7eb2e8f9f7	611	#define UART_FLAG_SBKF ((uint32_t)0x00040000) /!< UART send break flag /
<>	144:ef7eb2e8f9f7	612	#define UART_FLAG_CMF ((uint32_t)0x00020000) /!< UART character match flag /
<>	144:ef7eb2e8f9f7	613	#define UART_FLAG_BUSY ((uint32_t)0x00010000) /!< UART busy flag /
<>	144:ef7eb2e8f9f7	614	#define UART_FLAG_ABRF ((uint32_t)0x00008000) /!< UART auto Baud rate flag /
<>	144:ef7eb2e8f9f7	615	#define UART_FLAG_ABRE ((uint32_t)0x00004000) /!< UART uto Baud rate error /
<>	144:ef7eb2e8f9f7	616	#define UART_FLAG_EOBF ((uint32_t)0x00001000) /!< UART end of block flag /
<>	144:ef7eb2e8f9f7	617	#define UART_FLAG_RTOF ((uint32_t)0x00000800) /!< UART receiver timeout flag /
<>	144:ef7eb2e8f9f7	618	#define UART_FLAG_CTS ((uint32_t)0x00000400) /!< UART clear to send flag /
<>	144:ef7eb2e8f9f7	619	#define UART_FLAG_CTSIF ((uint32_t)0x00000200) /!< UART clear to send interrupt flag /
<>	144:ef7eb2e8f9f7	620	#define UART_FLAG_LBDF ((uint32_t)0x00000100) /!< UART LIN break detection flag /
<>	144:ef7eb2e8f9f7	621	#define UART_FLAG_TXE ((uint32_t)0x00000080) /!< UART transmit data register empty /
<>	144:ef7eb2e8f9f7	622	#define UART_FLAG_TC ((uint32_t)0x00000040) /!< UART transmission complete /
<>	144:ef7eb2e8f9f7	623	#define UART_FLAG_RXNE ((uint32_t)0x00000020) /!< UART read data register not empty /
<>	144:ef7eb2e8f9f7	624	#define UART_FLAG_IDLE ((uint32_t)0x00000010) /!< UART idle flag /
<>	144:ef7eb2e8f9f7	625	#define UART_FLAG_ORE ((uint32_t)0x00000008) /!< UART overrun error /
<>	144:ef7eb2e8f9f7	626	#define UART_FLAG_NE ((uint32_t)0x00000004) /!< UART noise error /
<>	144:ef7eb2e8f9f7	627	#define UART_FLAG_FE ((uint32_t)0x00000002) /!< UART frame error /
<>	144:ef7eb2e8f9f7	628	#define UART_FLAG_PE ((uint32_t)0x00000001) /!< UART parity error /
<>	144:ef7eb2e8f9f7	629	/**
<>	144:ef7eb2e8f9f7	630	* @}
<>	144:ef7eb2e8f9f7	631	*/
<>	144:ef7eb2e8f9f7	632
<>	144:ef7eb2e8f9f7	633	/** @defgroup UART_Interrupt_definition UART Interrupts Definition
<>	144:ef7eb2e8f9f7	634	* Elements values convention: 000ZZZZZ0XXYYYYYb
<>	144:ef7eb2e8f9f7	635	* - YYYYY : Interrupt source position in the XX register (5bits)
<>	144:ef7eb2e8f9f7	636	* - XX : Interrupt source register (2bits)
<>	144:ef7eb2e8f9f7	637	* - 01: CR1 register
<>	144:ef7eb2e8f9f7	638	* - 10: CR2 register
<>	144:ef7eb2e8f9f7	639	* - 11: CR3 register
<>	144:ef7eb2e8f9f7	640	* - ZZZZZ : Flag position in the ISR register(5bits)
<>	144:ef7eb2e8f9f7	641	* @{
<>	144:ef7eb2e8f9f7	642	*/
<>	144:ef7eb2e8f9f7	643	#define UART_IT_PE ((uint32_t)0x0028) /!< UART parity error interruption /
<>	144:ef7eb2e8f9f7	644	#define UART_IT_TXE ((uint32_t)0x0727) /!< UART transmit data register empty interruption /
<>	144:ef7eb2e8f9f7	645	#define UART_IT_TC ((uint32_t)0x0626) /!< UART transmission complete interruption /
<>	144:ef7eb2e8f9f7	646	#define UART_IT_RXNE ((uint32_t)0x0525) /!< UART read data register not empty interruption /
<>	144:ef7eb2e8f9f7	647	#define UART_IT_IDLE ((uint32_t)0x0424) /!< UART idle interruption /
<>	144:ef7eb2e8f9f7	648	#define UART_IT_LBD ((uint32_t)0x0846) /!< UART LIN break detection interruption /
<>	144:ef7eb2e8f9f7	649	#define UART_IT_CTS ((uint32_t)0x096A) /!< UART CTS interruption /
<>	144:ef7eb2e8f9f7	650	#define UART_IT_CM ((uint32_t)0x112E) /!< UART character match interruption /
<>	144:ef7eb2e8f9f7	651	#define UART_IT_WUF ((uint32_t)0x1476) /!< UART wake-up from stop mode interruption /
<>	144:ef7eb2e8f9f7	652
<>	144:ef7eb2e8f9f7	653	/* Elements values convention: 000000000XXYYYYYb
<>	144:ef7eb2e8f9f7	654	- YYYYY : Interrupt source position in the XX register (5bits)
<>	144:ef7eb2e8f9f7	655	- XX : Interrupt source register (2bits)
<>	144:ef7eb2e8f9f7	656	- 01: CR1 register
<>	144:ef7eb2e8f9f7	657	- 10: CR2 register
<>	144:ef7eb2e8f9f7	658	- 11: CR3 register */
<>	144:ef7eb2e8f9f7	659	#define UART_IT_ERR ((uint32_t)0x0060) /!< UART error interruption /
<>	144:ef7eb2e8f9f7	660
<>	144:ef7eb2e8f9f7	661	/* Elements values convention: 0000ZZZZ00000000b
<>	144:ef7eb2e8f9f7	662	- ZZZZ : Flag position in the ISR register(4bits) */
<>	144:ef7eb2e8f9f7	663	#define UART_IT_ORE ((uint32_t)0x0300) /!< UART overrun error interruption /
<>	144:ef7eb2e8f9f7	664	#define UART_IT_NE ((uint32_t)0x0200) /!< UART noise error interruption /
<>	144:ef7eb2e8f9f7	665	#define UART_IT_FE ((uint32_t)0x0100) /!< UART frame error interruption /
<>	144:ef7eb2e8f9f7	666	/**
<>	144:ef7eb2e8f9f7	667	* @}
<>	144:ef7eb2e8f9f7	668	*/
<>	144:ef7eb2e8f9f7	669
<>	144:ef7eb2e8f9f7	670	/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags
<>	144:ef7eb2e8f9f7	671	* @{
<>	144:ef7eb2e8f9f7	672	*/
<>	144:ef7eb2e8f9f7	673	#define UART_CLEAR_PEF USART_ICR_PECF /!< Parity Error Clear Flag /
<>	144:ef7eb2e8f9f7	674	#define UART_CLEAR_FEF USART_ICR_FECF /!< Framing Error Clear Flag /
<>	144:ef7eb2e8f9f7	675	#define UART_CLEAR_NEF USART_ICR_NCF /!< Noise detected Clear Flag /
<>	144:ef7eb2e8f9f7	676	#define UART_CLEAR_OREF USART_ICR_ORECF /!< Overrun Error Clear Flag /
<>	144:ef7eb2e8f9f7	677	#define UART_CLEAR_IDLEF USART_ICR_IDLECF /!< IDLE line detected Clear Flag /
<>	144:ef7eb2e8f9f7	678	#define UART_CLEAR_TCF USART_ICR_TCCF /!< Transmission Complete Clear Flag /
<>	144:ef7eb2e8f9f7	679	#define UART_CLEAR_LBDF USART_ICR_LBDCF /!< LIN Break Detection Clear Flag /
<>	144:ef7eb2e8f9f7	680	#define UART_CLEAR_CTSF USART_ICR_CTSCF /!< CTS Interrupt Clear Flag /
<>	144:ef7eb2e8f9f7	681	#define UART_CLEAR_RTOF USART_ICR_RTOCF /!< Receiver Time Out Clear Flag /
<>	144:ef7eb2e8f9f7	682	#define UART_CLEAR_EOBF USART_ICR_EOBCF /!< End Of Block Clear Flag /
<>	144:ef7eb2e8f9f7	683	#define UART_CLEAR_CMF USART_ICR_CMCF /!< Character Match Clear Flag /
<>	144:ef7eb2e8f9f7	684	#define UART_CLEAR_WUF USART_ICR_WUCF /!< Wake Up from stop mode Clear Flag /
<>	144:ef7eb2e8f9f7	685	/**
<>	144:ef7eb2e8f9f7	686	* @}
<>	144:ef7eb2e8f9f7	687	*/
<>	144:ef7eb2e8f9f7	688
<>	144:ef7eb2e8f9f7	689
<>	144:ef7eb2e8f9f7	690	/**
<>	144:ef7eb2e8f9f7	691	* @}
<>	144:ef7eb2e8f9f7	692	*/
<>	144:ef7eb2e8f9f7	693
<>	144:ef7eb2e8f9f7	694	/* Exported macros -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	695	/** @defgroup UART_Exported_Macros UART Exported Macros
<>	144:ef7eb2e8f9f7	696	* @{
<>	144:ef7eb2e8f9f7	697	*/
<>	144:ef7eb2e8f9f7	698
<>	144:ef7eb2e8f9f7	699	/** @brief Reset UART handle states.
<>	144:ef7eb2e8f9f7	700	* @param __HANDLE__: UART handle.
<>	144:ef7eb2e8f9f7	701	* @retval None
<>	144:ef7eb2e8f9f7	702	*/
<>	144:ef7eb2e8f9f7	703	#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
<>	144:ef7eb2e8f9f7	704	(__HANDLE__)->gState = HAL_UART_STATE_RESET; \
<>	144:ef7eb2e8f9f7	705	(__HANDLE__)->RxState = HAL_UART_STATE_RESET; \
<>	144:ef7eb2e8f9f7	706	} while(0)
<>	144:ef7eb2e8f9f7	707	/** @brief Flush the UART Data registers.
<>	144:ef7eb2e8f9f7	708	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	709	* @retval None
<>	144:ef7eb2e8f9f7	710	*/
<>	144:ef7eb2e8f9f7	711	#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
<>	144:ef7eb2e8f9f7	712	do{ \
<>	144:ef7eb2e8f9f7	713	SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
<>	144:ef7eb2e8f9f7	714	SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
<>	144:ef7eb2e8f9f7	715	} while(0)
<>	144:ef7eb2e8f9f7	716
<>	144:ef7eb2e8f9f7	717	/** @brief Clear the specified UART pending flag.
<>	144:ef7eb2e8f9f7	718	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	719	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	720	* This parameter can be any combination of the following values:
<>	144:ef7eb2e8f9f7	721	* @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
<>	144:ef7eb2e8f9f7	722	* @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
<>	144:ef7eb2e8f9f7	723	* @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
<>	144:ef7eb2e8f9f7	724	* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
<>	144:ef7eb2e8f9f7	725	* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
<>	144:ef7eb2e8f9f7	726	* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
<>	144:ef7eb2e8f9f7	727	* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
<>	144:ef7eb2e8f9f7	728	* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
<>	144:ef7eb2e8f9f7	729	* @arg @ref UART_CLEAR_RTOF Receiver Time Out Clear Flag
<>	144:ef7eb2e8f9f7	730	* @arg @ref UART_CLEAR_EOBF End Of Block Clear Flag
<>	144:ef7eb2e8f9f7	731	* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
<>	144:ef7eb2e8f9f7	732	* @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
<>	144:ef7eb2e8f9f7	733	* @retval None
<>	144:ef7eb2e8f9f7	734	*/
<>	144:ef7eb2e8f9f7	735	#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
<>	144:ef7eb2e8f9f7	736
<>	144:ef7eb2e8f9f7	737	/** @brief Clear the UART PE pending flag.
<>	144:ef7eb2e8f9f7	738	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	739	* @retval None
<>	144:ef7eb2e8f9f7	740	*/
<>	144:ef7eb2e8f9f7	741	#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
<>	144:ef7eb2e8f9f7	742
<>	144:ef7eb2e8f9f7	743	/** @brief Clear the UART FE pending flag.
<>	144:ef7eb2e8f9f7	744	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	745	* @retval None
<>	144:ef7eb2e8f9f7	746	*/
<>	144:ef7eb2e8f9f7	747	#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
<>	144:ef7eb2e8f9f7	748
<>	144:ef7eb2e8f9f7	749	/** @brief Clear the UART NE pending flag.
<>	144:ef7eb2e8f9f7	750	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	751	* @retval None
<>	144:ef7eb2e8f9f7	752	*/
<>	144:ef7eb2e8f9f7	753	#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
<>	144:ef7eb2e8f9f7	754
<>	144:ef7eb2e8f9f7	755	/** @brief Clear the UART ORE pending flag.
<>	144:ef7eb2e8f9f7	756	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	757	* @retval None
<>	144:ef7eb2e8f9f7	758	*/
<>	144:ef7eb2e8f9f7	759	#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
<>	144:ef7eb2e8f9f7	760
<>	144:ef7eb2e8f9f7	761	/** @brief Clear the UART IDLE pending flag.
<>	144:ef7eb2e8f9f7	762	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	763	* @retval None
<>	144:ef7eb2e8f9f7	764	*/
<>	144:ef7eb2e8f9f7	765	#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
<>	144:ef7eb2e8f9f7	766
<>	144:ef7eb2e8f9f7	767	/** @brief Check whether the specified UART flag is set or not.
<>	144:ef7eb2e8f9f7	768	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	769	* @param __FLAG__: specifies the flag to check.
<>	144:ef7eb2e8f9f7	770	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	771	* @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
<>	144:ef7eb2e8f9f7	772	* @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
<>	144:ef7eb2e8f9f7	773	* @arg @ref UART_FLAG_WUF Wake up from stop mode flag
<>	144:ef7eb2e8f9f7	774	* @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode)
<>	144:ef7eb2e8f9f7	775	* @arg @ref UART_FLAG_SBKF Send Break flag
<>	144:ef7eb2e8f9f7	776	* @arg @ref UART_FLAG_CMF Character match flag
<>	144:ef7eb2e8f9f7	777	* @arg @ref UART_FLAG_BUSY Busy flag
<>	144:ef7eb2e8f9f7	778	* @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag
<>	144:ef7eb2e8f9f7	779	* @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag
<>	144:ef7eb2e8f9f7	780	* @arg @ref UART_FLAG_EOBF End of block flag
<>	144:ef7eb2e8f9f7	781	* @arg @ref UART_FLAG_RTOF Receiver timeout flag
<>	144:ef7eb2e8f9f7	782	* @arg @ref UART_FLAG_CTS CTS Change flag
<>	144:ef7eb2e8f9f7	783	* @arg @ref UART_FLAG_LBDF LIN Break detection flag
<>	144:ef7eb2e8f9f7	784	* @arg @ref UART_FLAG_TXE Transmit data register empty flag
<>	144:ef7eb2e8f9f7	785	* @arg @ref UART_FLAG_TC Transmission Complete flag
<>	144:ef7eb2e8f9f7	786	* @arg @ref UART_FLAG_RXNE Receive data register not empty flag
<>	144:ef7eb2e8f9f7	787	* @arg @ref UART_FLAG_IDLE Idle Line detection flag
<>	144:ef7eb2e8f9f7	788	* @arg @ref UART_FLAG_ORE Overrun Error flag
<>	144:ef7eb2e8f9f7	789	* @arg @ref UART_FLAG_NE Noise Error flag
<>	144:ef7eb2e8f9f7	790	* @arg @ref UART_FLAG_FE Framing Error flag
<>	144:ef7eb2e8f9f7	791	* @arg @ref UART_FLAG_PE Parity Error flag
<>	144:ef7eb2e8f9f7	792	* @retval The new state of __FLAG__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	793	*/
<>	144:ef7eb2e8f9f7	794	#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
<>	144:ef7eb2e8f9f7	795
<>	144:ef7eb2e8f9f7	796	/** @brief Enable the specified UART interrupt.
<>	144:ef7eb2e8f9f7	797	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	798	* @param __INTERRUPT__: specifies the UART interrupt source to enable.
<>	144:ef7eb2e8f9f7	799	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	800	* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
<>	144:ef7eb2e8f9f7	801	* @arg @ref UART_IT_CM Character match interrupt
<>	144:ef7eb2e8f9f7	802	* @arg @ref UART_IT_CTS CTS change interrupt
<>	144:ef7eb2e8f9f7	803	* @arg @ref UART_IT_LBD LIN Break detection interrupt
<>	144:ef7eb2e8f9f7	804	* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<>	144:ef7eb2e8f9f7	805	* @arg @ref UART_IT_TC Transmission complete interrupt
<>	144:ef7eb2e8f9f7	806	* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<>	144:ef7eb2e8f9f7	807	* @arg @ref UART_IT_IDLE Idle line detection interrupt
<>	144:ef7eb2e8f9f7	808	* @arg @ref UART_IT_PE Parity Error interrupt
<>	144:ef7eb2e8f9f7	809	* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
<>	144:ef7eb2e8f9f7	810	* @retval None
<>	144:ef7eb2e8f9f7	811	*/
<>	144:ef7eb2e8f9f7	812	#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	813	((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	814	((__HANDLE__)->Instance->CR3 \|= (1U << ((__INTERRUPT__) & UART_IT_MASK))))
<>	144:ef7eb2e8f9f7	815
<>	144:ef7eb2e8f9f7	816
<>	144:ef7eb2e8f9f7	817	/** @brief Disable the specified UART interrupt.
<>	144:ef7eb2e8f9f7	818	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	819	* @param __INTERRUPT__: specifies the UART interrupt source to disable.
<>	144:ef7eb2e8f9f7	820	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	821	* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
<>	144:ef7eb2e8f9f7	822	* @arg @ref UART_IT_CM Character match interrupt
<>	144:ef7eb2e8f9f7	823	* @arg @ref UART_IT_CTS CTS change interrupt
<>	144:ef7eb2e8f9f7	824	* @arg @ref UART_IT_LBD LIN Break detection interrupt
<>	144:ef7eb2e8f9f7	825	* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<>	144:ef7eb2e8f9f7	826	* @arg @ref UART_IT_TC Transmission complete interrupt
<>	144:ef7eb2e8f9f7	827	* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<>	144:ef7eb2e8f9f7	828	* @arg @ref UART_IT_IDLE Idle line detection interrupt
<>	144:ef7eb2e8f9f7	829	* @arg @ref UART_IT_PE Parity Error interrupt
<>	144:ef7eb2e8f9f7	830	* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
<>	144:ef7eb2e8f9f7	831	* @retval None
<>	144:ef7eb2e8f9f7	832	*/
<>	144:ef7eb2e8f9f7	833	#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	834	((((uint8_t)(__INTERRUPT__)) >> 5U) == 2)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \
<>	144:ef7eb2e8f9f7	835	((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
<>	144:ef7eb2e8f9f7	836
<>	144:ef7eb2e8f9f7	837	/** @brief Check whether the specified UART interrupt has occurred or not.
<>	144:ef7eb2e8f9f7	838	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	839	* @param __IT__: specifies the UART interrupt to check.
<>	144:ef7eb2e8f9f7	840	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	841	* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
<>	144:ef7eb2e8f9f7	842	* @arg @ref UART_IT_CM Character match interrupt
<>	144:ef7eb2e8f9f7	843	* @arg @ref UART_IT_CTS CTS change interrupt
<>	144:ef7eb2e8f9f7	844	* @arg @ref UART_IT_LBD LIN Break detection interrupt
<>	144:ef7eb2e8f9f7	845	* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<>	144:ef7eb2e8f9f7	846	* @arg @ref UART_IT_TC Transmission complete interrupt
<>	144:ef7eb2e8f9f7	847	* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<>	144:ef7eb2e8f9f7	848	* @arg @ref UART_IT_IDLE Idle line detection interrupt
<>	144:ef7eb2e8f9f7	849	* @arg @ref UART_IT_ORE Overrun Error interrupt
<>	144:ef7eb2e8f9f7	850	* @arg @ref UART_IT_NE Noise Error interrupt
<>	144:ef7eb2e8f9f7	851	* @arg @ref UART_IT_FE Framing Error interrupt
<>	144:ef7eb2e8f9f7	852	* @arg @ref UART_IT_PE Parity Error interrupt
<>	144:ef7eb2e8f9f7	853	* @retval The new state of __IT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	854	*/
<>	144:ef7eb2e8f9f7	855	#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
<>	144:ef7eb2e8f9f7	856
<>	144:ef7eb2e8f9f7	857	/** @brief Check whether the specified UART interrupt source is enabled or not.
<>	144:ef7eb2e8f9f7	858	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	859	* @param __IT__: specifies the UART interrupt source to check.
<>	144:ef7eb2e8f9f7	860	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	861	* @arg @ref UART_IT_WUF Wakeup from stop mode interrupt
<>	144:ef7eb2e8f9f7	862	* @arg @ref UART_IT_CM Character match interrupt
<>	144:ef7eb2e8f9f7	863	* @arg @ref UART_IT_CTS CTS change interrupt
<>	144:ef7eb2e8f9f7	864	* @arg @ref UART_IT_LBD LIN Break detection interrupt
<>	144:ef7eb2e8f9f7	865	* @arg @ref UART_IT_TXE Transmit Data Register empty interrupt
<>	144:ef7eb2e8f9f7	866	* @arg @ref UART_IT_TC Transmission complete interrupt
<>	144:ef7eb2e8f9f7	867	* @arg @ref UART_IT_RXNE Receive Data register not empty interrupt
<>	144:ef7eb2e8f9f7	868	* @arg @ref UART_IT_IDLE Idle line detection interrupt
<>	144:ef7eb2e8f9f7	869	* @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error)
<>	144:ef7eb2e8f9f7	870	* @arg @ref UART_IT_PE Parity Error interrupt
<>	144:ef7eb2e8f9f7	871	* @retval The new state of __IT__ (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	872	*/
<>	144:ef7eb2e8f9f7	873	#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) ((((((uint8_t)(__IT__)) >> 5U) == 1)? (__HANDLE__)->Instance->CR1:(((((uint8_t)(__IT__)) >> 5U) == 2)? \
<>	144:ef7eb2e8f9f7	874	(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
<>	144:ef7eb2e8f9f7	875
<>	144:ef7eb2e8f9f7	876	/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag.
<>	144:ef7eb2e8f9f7	877	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	878	* @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
<>	144:ef7eb2e8f9f7	879	* to clear the corresponding interrupt
<>	144:ef7eb2e8f9f7	880	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	881	* @arg @ref UART_CLEAR_PEF Parity Error Clear Flag
<>	144:ef7eb2e8f9f7	882	* @arg @ref UART_CLEAR_FEF Framing Error Clear Flag
<>	144:ef7eb2e8f9f7	883	* @arg @ref UART_CLEAR_NEF Noise detected Clear Flag
<>	144:ef7eb2e8f9f7	884	* @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag
<>	144:ef7eb2e8f9f7	885	* @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag
<>	144:ef7eb2e8f9f7	886	* @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag
<>	144:ef7eb2e8f9f7	887	* @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag
<>	144:ef7eb2e8f9f7	888	* @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag
<>	144:ef7eb2e8f9f7	889	* @arg @ref UART_CLEAR_CMF Character Match Clear Flag
<>	144:ef7eb2e8f9f7	890	* @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag
<>	144:ef7eb2e8f9f7	891	* @retval None
<>	144:ef7eb2e8f9f7	892	*/
<>	144:ef7eb2e8f9f7	893	#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
<>	144:ef7eb2e8f9f7	894
<>	144:ef7eb2e8f9f7	895	/** @brief Set a specific UART request flag.
<>	144:ef7eb2e8f9f7	896	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	897	* @param __REQ__: specifies the request flag to set
<>	144:ef7eb2e8f9f7	898	* This parameter can be one of the following values:
<>	144:ef7eb2e8f9f7	899	* @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
<>	144:ef7eb2e8f9f7	900	* @arg @ref UART_SENDBREAK_REQUEST Send Break Request
<>	144:ef7eb2e8f9f7	901	* @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
<>	144:ef7eb2e8f9f7	902	* @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
<>	144:ef7eb2e8f9f7	903	* @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
<>	144:ef7eb2e8f9f7	904	* @retval None
<>	144:ef7eb2e8f9f7	905	*/
<>	144:ef7eb2e8f9f7	906	#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR \|= (uint32_t)(__REQ__))
<>	144:ef7eb2e8f9f7	907
<>	144:ef7eb2e8f9f7	908	/** @brief Enable the UART one bit sample method.
<>	144:ef7eb2e8f9f7	909	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	910	* @retval None
<>	144:ef7eb2e8f9f7	911	*/
<>	144:ef7eb2e8f9f7	912	#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\|= USART_CR3_ONEBIT)
<>	144:ef7eb2e8f9f7	913
<>	144:ef7eb2e8f9f7	914	/** @brief Disable the UART one bit sample method.
<>	144:ef7eb2e8f9f7	915	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	916	* @retval None
<>	144:ef7eb2e8f9f7	917	*/
<>	144:ef7eb2e8f9f7	918	#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
<>	144:ef7eb2e8f9f7	919
<>	144:ef7eb2e8f9f7	920	/** @brief Enable UART.
<>	144:ef7eb2e8f9f7	921	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	922	* @retval None
<>	144:ef7eb2e8f9f7	923	*/
<>	144:ef7eb2e8f9f7	924	#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 \|= USART_CR1_UE)
<>	144:ef7eb2e8f9f7	925
<>	144:ef7eb2e8f9f7	926	/** @brief Disable UART.
<>	144:ef7eb2e8f9f7	927	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	928	* @retval None
<>	144:ef7eb2e8f9f7	929	*/
<>	144:ef7eb2e8f9f7	930	#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
<>	144:ef7eb2e8f9f7	931
<>	144:ef7eb2e8f9f7	932	/** @brief Enable CTS flow control.
<>	144:ef7eb2e8f9f7	933	* @note This macro allows to enable CTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	934	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	935	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	936	* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	937	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	938	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	939	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	940	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	941	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	942	* @retval None
<>	144:ef7eb2e8f9f7	943	*/
<>	144:ef7eb2e8f9f7	944	#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	945	do{ \
<>	144:ef7eb2e8f9f7	946	SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<>	144:ef7eb2e8f9f7	947	(__HANDLE__)->Init.HwFlowCtl \|= USART_CR3_CTSE; \
<>	144:ef7eb2e8f9f7	948	} while(0)
<>	144:ef7eb2e8f9f7	949
<>	144:ef7eb2e8f9f7	950	/** @brief Disable CTS flow control.
<>	144:ef7eb2e8f9f7	951	* @note This macro allows to disable CTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	952	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	953	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	954	* @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	955	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	956	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	957	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	958	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	959	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	960	* @retval None
<>	144:ef7eb2e8f9f7	961	*/
<>	144:ef7eb2e8f9f7	962	#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	963	do{ \
<>	144:ef7eb2e8f9f7	964	CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
<>	144:ef7eb2e8f9f7	965	(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \
<>	144:ef7eb2e8f9f7	966	} while(0)
<>	144:ef7eb2e8f9f7	967
<>	144:ef7eb2e8f9f7	968	/** @brief Enable RTS flow control.
<>	144:ef7eb2e8f9f7	969	* @note This macro allows to enable RTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	970	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	971	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	972	* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	973	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	974	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	975	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	976	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	977	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	978	* @retval None
<>	144:ef7eb2e8f9f7	979	*/
<>	144:ef7eb2e8f9f7	980	#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	981	do{ \
<>	144:ef7eb2e8f9f7	982	SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
<>	144:ef7eb2e8f9f7	983	(__HANDLE__)->Init.HwFlowCtl \|= USART_CR3_RTSE; \
<>	144:ef7eb2e8f9f7	984	} while(0)
<>	144:ef7eb2e8f9f7	985
<>	144:ef7eb2e8f9f7	986	/** @brief Disable RTS flow control.
<>	144:ef7eb2e8f9f7	987	* @note This macro allows to disable RTS hardware flow control for a given UART instance,
<>	144:ef7eb2e8f9f7	988	* without need to call HAL_UART_Init() function.
<>	144:ef7eb2e8f9f7	989	* As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
<>	144:ef7eb2e8f9f7	990	* @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
<>	144:ef7eb2e8f9f7	991	* for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
<>	144:ef7eb2e8f9f7	992	* - UART instance should have already been initialised (through call of HAL_UART_Init() )
<>	144:ef7eb2e8f9f7	993	* - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))
<>	144:ef7eb2e8f9f7	994	* and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
<>	144:ef7eb2e8f9f7	995	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	996	* @retval None
<>	144:ef7eb2e8f9f7	997	*/
<>	144:ef7eb2e8f9f7	998	#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \
<>	144:ef7eb2e8f9f7	999	do{ \
<>	144:ef7eb2e8f9f7	1000	CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
<>	144:ef7eb2e8f9f7	1001	(__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \
<>	144:ef7eb2e8f9f7	1002	} while(0)
<>	144:ef7eb2e8f9f7	1003
<>	144:ef7eb2e8f9f7	1004	/**
<>	144:ef7eb2e8f9f7	1005	* @}
<>	144:ef7eb2e8f9f7	1006	*/
<>	144:ef7eb2e8f9f7	1007
<>	144:ef7eb2e8f9f7	1008	/* Private macros --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1009	/** @defgroup UART_Private_Macros UART Private Macros
<>	144:ef7eb2e8f9f7	1010	* @{
<>	144:ef7eb2e8f9f7	1011	*/
<>	144:ef7eb2e8f9f7	1012	/** @brief BRR division operation to set BRR register with LPUART.
<>	144:ef7eb2e8f9f7	1013	* @param __PCLK__: LPUART clock.
<>	144:ef7eb2e8f9f7	1014	* @param __BAUD__: Baud rate set by the user.
<>	144:ef7eb2e8f9f7	1015	* @retval Division result
<>	144:ef7eb2e8f9f7	1016	*/
<>	144:ef7eb2e8f9f7	1017	#define UART_DIV_LPUART(__PCLK__, __BAUD__) ((((uint64_t)(__PCLK__)*256) + ((__BAUD__)/2)) / (__BAUD__))
<>	144:ef7eb2e8f9f7	1018
<>	144:ef7eb2e8f9f7	1019	/** @brief BRR division operation to set BRR register in 8-bit oversampling mode.
<>	144:ef7eb2e8f9f7	1020	* @param __PCLK__: UART clock.
<>	144:ef7eb2e8f9f7	1021	* @param __BAUD__: Baud rate set by the user.
<>	144:ef7eb2e8f9f7	1022	* @retval Division result
<>	144:ef7eb2e8f9f7	1023	*/
<>	144:ef7eb2e8f9f7	1024	#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__) ((((__PCLK__)*2) + ((__BAUD__)/2)) / (__BAUD__))
<>	144:ef7eb2e8f9f7	1025
<>	144:ef7eb2e8f9f7	1026	/** @brief BRR division operation to set BRR register in 16-bit oversampling mode.
<>	144:ef7eb2e8f9f7	1027	* @param __PCLK__: UART clock.
<>	144:ef7eb2e8f9f7	1028	* @param __BAUD__: Baud rate set by the user.
<>	144:ef7eb2e8f9f7	1029	* @retval Division result
<>	144:ef7eb2e8f9f7	1030	*/
<>	144:ef7eb2e8f9f7	1031	#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__) (((__PCLK__) + ((__BAUD__)/2)) / (__BAUD__))
<>	144:ef7eb2e8f9f7	1032
<>	144:ef7eb2e8f9f7	1033	/** @brief Check whether or not UART instance is Low Power UART.
<>	144:ef7eb2e8f9f7	1034	* @param __HANDLE__: specifies the UART Handle.
<>	144:ef7eb2e8f9f7	1035	* @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
<>	144:ef7eb2e8f9f7	1036	*/
<>	144:ef7eb2e8f9f7	1037	#define UART_INSTANCE_LOWPOWER(__HANDLE__) (((__HANDLE__)->Instance == LPUART1) ? SET : RESET )
<>	144:ef7eb2e8f9f7	1038
<>	144:ef7eb2e8f9f7	1039	/** @brief Check UART Baud rate.
<>	144:ef7eb2e8f9f7	1040	* @param __BAUDRATE__: Baudrate specified by the user.
<>	144:ef7eb2e8f9f7	1041	* The maximum Baud Rate is derived from the maximum clock on L4 (i.e. 80 MHz)
<>	144:ef7eb2e8f9f7	1042	* divided by the smallest oversampling used on the USART (i.e. 8)
<>	144:ef7eb2e8f9f7	1043	* @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
<>	144:ef7eb2e8f9f7	1044	*/
<>	144:ef7eb2e8f9f7	1045	#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 10000001)
<>	144:ef7eb2e8f9f7	1046
<>	144:ef7eb2e8f9f7	1047	/** @brief Check UART assertion time.
<>	144:ef7eb2e8f9f7	1048	* @param __TIME__: 5-bit value assertion time.
<>	144:ef7eb2e8f9f7	1049	* @retval Test result (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1050	*/
<>	144:ef7eb2e8f9f7	1051	#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
<>	144:ef7eb2e8f9f7	1052
<>	144:ef7eb2e8f9f7	1053	/** @brief Check UART deassertion time.
<>	144:ef7eb2e8f9f7	1054	* @param __TIME__: 5-bit value deassertion time.
<>	144:ef7eb2e8f9f7	1055	* @retval Test result (TRUE or FALSE).
<>	144:ef7eb2e8f9f7	1056	*/
<>	144:ef7eb2e8f9f7	1057	#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1F)
<>	144:ef7eb2e8f9f7	1058
<>	144:ef7eb2e8f9f7	1059	/**
<>	144:ef7eb2e8f9f7	1060	* @brief Ensure that UART frame number of stop bits is valid.
<>	144:ef7eb2e8f9f7	1061	* @param __STOPBITS__: UART frame number of stop bits.
<>	144:ef7eb2e8f9f7	1062	* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) UART_STOPBITS_1_5
<>	144:ef7eb2e8f9f7	1063	*/
<>	144:ef7eb2e8f9f7	1064	#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) \|\| \
<>	144:ef7eb2e8f9f7	1065	((__STOPBITS__) == UART_STOPBITS_1) \|\| \
<>	144:ef7eb2e8f9f7	1066	((__STOPBITS__) == UART_STOPBITS_1_5) \|\| \
<>	144:ef7eb2e8f9f7	1067	((__STOPBITS__) == UART_STOPBITS_2))
<>	144:ef7eb2e8f9f7	1068
<>	144:ef7eb2e8f9f7	1069	/**
<>	144:ef7eb2e8f9f7	1070	* @brief Ensure that LPUART frame number of stop bits is valid.
<>	144:ef7eb2e8f9f7	1071	* @param __STOPBITS__: LPUART frame number of stop bits.
<>	144:ef7eb2e8f9f7	1072	* @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
<>	144:ef7eb2e8f9f7	1073	*/
<>	144:ef7eb2e8f9f7	1074	#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) \|\| \
<>	144:ef7eb2e8f9f7	1075	((__STOPBITS__) == UART_STOPBITS_2))
<>	144:ef7eb2e8f9f7	1076
<>	144:ef7eb2e8f9f7	1077	/**
<>	144:ef7eb2e8f9f7	1078	* @brief Ensure that UART frame parity is valid.
<>	144:ef7eb2e8f9f7	1079	* @param __PARITY__: UART frame parity.
<>	144:ef7eb2e8f9f7	1080	* @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
<>	144:ef7eb2e8f9f7	1081	*/
<>	144:ef7eb2e8f9f7	1082	#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1083	((__PARITY__) == UART_PARITY_EVEN) \|\| \
<>	144:ef7eb2e8f9f7	1084	((__PARITY__) == UART_PARITY_ODD))
<>	144:ef7eb2e8f9f7	1085
<>	144:ef7eb2e8f9f7	1086	/**
<>	144:ef7eb2e8f9f7	1087	* @brief Ensure that UART hardware flow control is valid.
<>	144:ef7eb2e8f9f7	1088	* @param __CONTROL__: UART hardware flow control.
<>	144:ef7eb2e8f9f7	1089	* @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
<>	144:ef7eb2e8f9f7	1090	*/
<>	144:ef7eb2e8f9f7	1091	#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
<>	144:ef7eb2e8f9f7	1092	(((__CONTROL__) == UART_HWCONTROL_NONE) \|\| \
<>	144:ef7eb2e8f9f7	1093	((__CONTROL__) == UART_HWCONTROL_RTS) \|\| \
<>	144:ef7eb2e8f9f7	1094	((__CONTROL__) == UART_HWCONTROL_CTS) \|\| \
<>	144:ef7eb2e8f9f7	1095	((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
<>	144:ef7eb2e8f9f7	1096
<>	144:ef7eb2e8f9f7	1097	/**
<>	144:ef7eb2e8f9f7	1098	* @brief Ensure that UART communication mode is valid.
<>	144:ef7eb2e8f9f7	1099	* @param __MODE__: UART communication mode.
<>	144:ef7eb2e8f9f7	1100	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<>	144:ef7eb2e8f9f7	1101	*/
<>	144:ef7eb2e8f9f7	1102	#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
<>	144:ef7eb2e8f9f7	1103
<>	144:ef7eb2e8f9f7	1104	/**
<>	144:ef7eb2e8f9f7	1105	* @brief Ensure that UART state is valid.
<>	144:ef7eb2e8f9f7	1106	* @param __STATE__: UART state.
<>	144:ef7eb2e8f9f7	1107	* @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
<>	144:ef7eb2e8f9f7	1108	*/
<>	144:ef7eb2e8f9f7	1109	#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1110	((__STATE__) == UART_STATE_ENABLE))
<>	144:ef7eb2e8f9f7	1111
<>	144:ef7eb2e8f9f7	1112	/**
<>	144:ef7eb2e8f9f7	1113	* @brief Ensure that UART oversampling is valid.
<>	144:ef7eb2e8f9f7	1114	* @param __SAMPLING__: UART oversampling.
<>	144:ef7eb2e8f9f7	1115	* @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
<>	144:ef7eb2e8f9f7	1116	*/
<>	144:ef7eb2e8f9f7	1117	#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) \|\| \
<>	144:ef7eb2e8f9f7	1118	((__SAMPLING__) == UART_OVERSAMPLING_8))
<>	144:ef7eb2e8f9f7	1119
<>	144:ef7eb2e8f9f7	1120	/**
<>	144:ef7eb2e8f9f7	1121	* @brief Ensure that UART frame sampling is valid.
<>	144:ef7eb2e8f9f7	1122	* @param __ONEBIT__: UART frame sampling.
<>	144:ef7eb2e8f9f7	1123	* @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
<>	144:ef7eb2e8f9f7	1124	*/
<>	144:ef7eb2e8f9f7	1125	#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1126	((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
<>	144:ef7eb2e8f9f7	1127
<>	144:ef7eb2e8f9f7	1128	/**
<>	144:ef7eb2e8f9f7	1129	* @brief Ensure that UART auto Baud rate detection mode is valid.
<>	144:ef7eb2e8f9f7	1130	* @param __MODE__: UART auto Baud rate detection mode.
<>	144:ef7eb2e8f9f7	1131	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
<>	144:ef7eb2e8f9f7	1132	*/
<>	144:ef7eb2e8f9f7	1133	#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) \|\| \
<>	144:ef7eb2e8f9f7	1134	((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) \|\| \
<>	144:ef7eb2e8f9f7	1135	((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) \|\| \
<>	144:ef7eb2e8f9f7	1136	((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
<>	144:ef7eb2e8f9f7	1137
<>	144:ef7eb2e8f9f7	1138	/**
<>	144:ef7eb2e8f9f7	1139	* @brief Ensure that UART receiver timeout setting is valid.
<>	144:ef7eb2e8f9f7	1140	* @param __TIMEOUT__: UART receiver timeout setting.
<>	144:ef7eb2e8f9f7	1141	* @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
<>	144:ef7eb2e8f9f7	1142	*/
<>	144:ef7eb2e8f9f7	1143	#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1144	((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
<>	144:ef7eb2e8f9f7	1145
<>	144:ef7eb2e8f9f7	1146	/**
<>	144:ef7eb2e8f9f7	1147	* @brief Ensure that UART LIN state is valid.
<>	144:ef7eb2e8f9f7	1148	* @param __LIN__: UART LIN state.
<>	144:ef7eb2e8f9f7	1149	* @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
<>	144:ef7eb2e8f9f7	1150	*/
<>	144:ef7eb2e8f9f7	1151	#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1152	((__LIN__) == UART_LIN_ENABLE))
<>	144:ef7eb2e8f9f7	1153
<>	144:ef7eb2e8f9f7	1154	/**
<>	144:ef7eb2e8f9f7	1155	* @brief Ensure that UART LIN break detection length is valid.
<>	144:ef7eb2e8f9f7	1156	* @param __LENGTH__: UART LIN break detection length.
<>	144:ef7eb2e8f9f7	1157	* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
<>	144:ef7eb2e8f9f7	1158	*/
<>	144:ef7eb2e8f9f7	1159	#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) \|\| \
<>	144:ef7eb2e8f9f7	1160	((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
<>	144:ef7eb2e8f9f7	1161
<>	144:ef7eb2e8f9f7	1162	/**
<>	144:ef7eb2e8f9f7	1163	* @brief Ensure that UART DMA TX state is valid.
<>	144:ef7eb2e8f9f7	1164	* @param __DMATX__: UART DMA TX state.
<>	144:ef7eb2e8f9f7	1165	* @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
<>	144:ef7eb2e8f9f7	1166	*/
<>	144:ef7eb2e8f9f7	1167	#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1168	((__DMATX__) == UART_DMA_TX_ENABLE))
<>	144:ef7eb2e8f9f7	1169
<>	144:ef7eb2e8f9f7	1170	/**
<>	144:ef7eb2e8f9f7	1171	* @brief Ensure that UART DMA RX state is valid.
<>	144:ef7eb2e8f9f7	1172	* @param __DMARX__: UART DMA RX state.
<>	144:ef7eb2e8f9f7	1173	* @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
<>	144:ef7eb2e8f9f7	1174	*/
<>	144:ef7eb2e8f9f7	1175	#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1176	((__DMARX__) == UART_DMA_RX_ENABLE))
<>	144:ef7eb2e8f9f7	1177
<>	144:ef7eb2e8f9f7	1178	/**
<>	144:ef7eb2e8f9f7	1179	* @brief Ensure that UART half-duplex state is valid.
<>	144:ef7eb2e8f9f7	1180	* @param __HDSEL__: UART half-duplex state.
<>	144:ef7eb2e8f9f7	1181	* @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
<>	144:ef7eb2e8f9f7	1182	*/
<>	144:ef7eb2e8f9f7	1183	#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1184	((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
<>	144:ef7eb2e8f9f7	1185
<>	144:ef7eb2e8f9f7	1186	/**
<>	144:ef7eb2e8f9f7	1187	* @brief Ensure that UART wake-up method is valid.
<>	144:ef7eb2e8f9f7	1188	* @param __WAKEUP__: UART wake-up method .
<>	144:ef7eb2e8f9f7	1189	* @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
<>	144:ef7eb2e8f9f7	1190	*/
<>	144:ef7eb2e8f9f7	1191	#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) \|\| \
<>	144:ef7eb2e8f9f7	1192	((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
<>	144:ef7eb2e8f9f7	1193
<>	144:ef7eb2e8f9f7	1194	/**
<>	144:ef7eb2e8f9f7	1195	* @brief Ensure that UART request parameter is valid.
<>	144:ef7eb2e8f9f7	1196	* @param __PARAM__: UART request parameter.
<>	144:ef7eb2e8f9f7	1197	* @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
<>	144:ef7eb2e8f9f7	1198	*/
<>	144:ef7eb2e8f9f7	1199	#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1200	((__PARAM__) == UART_SENDBREAK_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1201	((__PARAM__) == UART_MUTE_MODE_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1202	((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) \|\| \
<>	144:ef7eb2e8f9f7	1203	((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
<>	144:ef7eb2e8f9f7	1204
<>	144:ef7eb2e8f9f7	1205	/**
<>	144:ef7eb2e8f9f7	1206	* @brief Ensure that UART advanced features initialization is valid.
<>	144:ef7eb2e8f9f7	1207	* @param __INIT__: UART advanced features initialization.
<>	144:ef7eb2e8f9f7	1208	* @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
<>	144:ef7eb2e8f9f7	1209	*/
<>	144:ef7eb2e8f9f7	1210	#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT \| \
<>	144:ef7eb2e8f9f7	1211	UART_ADVFEATURE_TXINVERT_INIT \| \
<>	144:ef7eb2e8f9f7	1212	UART_ADVFEATURE_RXINVERT_INIT \| \
<>	144:ef7eb2e8f9f7	1213	UART_ADVFEATURE_DATAINVERT_INIT \| \
<>	144:ef7eb2e8f9f7	1214	UART_ADVFEATURE_SWAP_INIT \| \
<>	144:ef7eb2e8f9f7	1215	UART_ADVFEATURE_RXOVERRUNDISABLE_INIT \| \
<>	144:ef7eb2e8f9f7	1216	UART_ADVFEATURE_DMADISABLEONERROR_INIT \| \
<>	144:ef7eb2e8f9f7	1217	UART_ADVFEATURE_AUTOBAUDRATE_INIT \| \
<>	144:ef7eb2e8f9f7	1218	UART_ADVFEATURE_MSBFIRST_INIT))
<>	144:ef7eb2e8f9f7	1219
<>	144:ef7eb2e8f9f7	1220	/**
<>	144:ef7eb2e8f9f7	1221	* @brief Ensure that UART frame TX inversion setting is valid.
<>	144:ef7eb2e8f9f7	1222	* @param __TXINV__: UART frame TX inversion setting.
<>	144:ef7eb2e8f9f7	1223	* @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
<>	144:ef7eb2e8f9f7	1224	*/
<>	144:ef7eb2e8f9f7	1225	#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1226	((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
<>	144:ef7eb2e8f9f7	1227
<>	144:ef7eb2e8f9f7	1228	/**
<>	144:ef7eb2e8f9f7	1229	* @brief Ensure that UART frame RX inversion setting is valid.
<>	144:ef7eb2e8f9f7	1230	* @param __RXINV__: UART frame RX inversion setting.
<>	144:ef7eb2e8f9f7	1231	* @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
<>	144:ef7eb2e8f9f7	1232	*/
<>	144:ef7eb2e8f9f7	1233	#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1234	((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
<>	144:ef7eb2e8f9f7	1235
<>	144:ef7eb2e8f9f7	1236	/**
<>	144:ef7eb2e8f9f7	1237	* @brief Ensure that UART frame data inversion setting is valid.
<>	144:ef7eb2e8f9f7	1238	* @param __DATAINV__: UART frame data inversion setting.
<>	144:ef7eb2e8f9f7	1239	* @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
<>	144:ef7eb2e8f9f7	1240	*/
<>	144:ef7eb2e8f9f7	1241	#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1242	((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
<>	144:ef7eb2e8f9f7	1243
<>	144:ef7eb2e8f9f7	1244	/**
<>	144:ef7eb2e8f9f7	1245	* @brief Ensure that UART frame RX/TX pins swap setting is valid.
<>	144:ef7eb2e8f9f7	1246	* @param __SWAP__: UART frame RX/TX pins swap setting.
<>	144:ef7eb2e8f9f7	1247	* @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
<>	144:ef7eb2e8f9f7	1248	*/
<>	144:ef7eb2e8f9f7	1249	#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1250	((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
<>	144:ef7eb2e8f9f7	1251
<>	144:ef7eb2e8f9f7	1252	/**
<>	144:ef7eb2e8f9f7	1253	* @brief Ensure that UART frame overrun setting is valid.
<>	144:ef7eb2e8f9f7	1254	* @param __OVERRUN__: UART frame overrun setting.
<>	144:ef7eb2e8f9f7	1255	* @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
<>	144:ef7eb2e8f9f7	1256	*/
<>	144:ef7eb2e8f9f7	1257	#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) \|\| \
<>	144:ef7eb2e8f9f7	1258	((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
<>	144:ef7eb2e8f9f7	1259
<>	144:ef7eb2e8f9f7	1260	/**
<>	144:ef7eb2e8f9f7	1261	* @brief Ensure that UART auto Baud rate state is valid.
<>	144:ef7eb2e8f9f7	1262	* @param __AUTOBAUDRATE__: UART auto Baud rate state.
<>	144:ef7eb2e8f9f7	1263	* @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
<>	144:ef7eb2e8f9f7	1264	*/
<>	144:ef7eb2e8f9f7	1265	#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1266	((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
<>	144:ef7eb2e8f9f7	1267
<>	144:ef7eb2e8f9f7	1268	/**
<>	144:ef7eb2e8f9f7	1269	* @brief Ensure that UART DMA enabling or disabling on error setting is valid.
<>	144:ef7eb2e8f9f7	1270	* @param __DMA__: UART DMA enabling or disabling on error setting.
<>	144:ef7eb2e8f9f7	1271	* @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
<>	144:ef7eb2e8f9f7	1272	*/
<>	144:ef7eb2e8f9f7	1273	#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) \|\| \
<>	144:ef7eb2e8f9f7	1274	((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
<>	144:ef7eb2e8f9f7	1275
<>	144:ef7eb2e8f9f7	1276	/**
<>	144:ef7eb2e8f9f7	1277	* @brief Ensure that UART frame MSB first setting is valid.
<>	144:ef7eb2e8f9f7	1278	* @param __MSBFIRST__: UART frame MSB first setting.
<>	144:ef7eb2e8f9f7	1279	* @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
<>	144:ef7eb2e8f9f7	1280	*/
<>	144:ef7eb2e8f9f7	1281	#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1282	((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
<>	144:ef7eb2e8f9f7	1283
<>	144:ef7eb2e8f9f7	1284	/**
<>	144:ef7eb2e8f9f7	1285	* @brief Ensure that UART stop mode state is valid.
<>	144:ef7eb2e8f9f7	1286	* @param __STOPMODE__: UART stop mode state.
<>	144:ef7eb2e8f9f7	1287	* @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
<>	144:ef7eb2e8f9f7	1288	*/
<>	144:ef7eb2e8f9f7	1289	#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1290	((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
<>	144:ef7eb2e8f9f7	1291
<>	144:ef7eb2e8f9f7	1292	/**
<>	144:ef7eb2e8f9f7	1293	* @brief Ensure that UART mute mode state is valid.
<>	144:ef7eb2e8f9f7	1294	* @param __MUTE__: UART mute mode state.
<>	144:ef7eb2e8f9f7	1295	* @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
<>	144:ef7eb2e8f9f7	1296	*/
<>	144:ef7eb2e8f9f7	1297	#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) \|\| \
<>	144:ef7eb2e8f9f7	1298	((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
<>	144:ef7eb2e8f9f7	1299
<>	144:ef7eb2e8f9f7	1300	/**
<>	144:ef7eb2e8f9f7	1301	* @brief Ensure that UART wake-up selection is valid.
<>	144:ef7eb2e8f9f7	1302	* @param __WAKE__: UART wake-up selection.
<>	144:ef7eb2e8f9f7	1303	* @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
<>	144:ef7eb2e8f9f7	1304	*/
<>	144:ef7eb2e8f9f7	1305	#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) \|\| \
<>	144:ef7eb2e8f9f7	1306	((__WAKE__) == UART_WAKEUP_ON_STARTBIT) \|\| \
<>	144:ef7eb2e8f9f7	1307	((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
<>	144:ef7eb2e8f9f7	1308
<>	144:ef7eb2e8f9f7	1309	/**
<>	144:ef7eb2e8f9f7	1310	* @brief Ensure that UART driver enable polarity is valid.
<>	144:ef7eb2e8f9f7	1311	* @param __POLARITY__: UART driver enable polarity.
<>	144:ef7eb2e8f9f7	1312	* @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
<>	144:ef7eb2e8f9f7	1313	*/
<>	144:ef7eb2e8f9f7	1314	#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) \|\| \
<>	144:ef7eb2e8f9f7	1315	((__POLARITY__) == UART_DE_POLARITY_LOW))
<>	144:ef7eb2e8f9f7	1316
<>	144:ef7eb2e8f9f7	1317	/**
<>	144:ef7eb2e8f9f7	1318	* @}
<>	144:ef7eb2e8f9f7	1319	*/
<>	144:ef7eb2e8f9f7	1320
<>	144:ef7eb2e8f9f7	1321	/* Include UART HAL Extended module */
<>	144:ef7eb2e8f9f7	1322	#include "stm32l4xx_hal_uart_ex.h"
<>	144:ef7eb2e8f9f7	1323
<>	144:ef7eb2e8f9f7	1324	/* Exported functions --------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1325	/** @addtogroup UART_Exported_Functions UART Exported Functions
<>	144:ef7eb2e8f9f7	1326	* @{
<>	144:ef7eb2e8f9f7	1327	*/
<>	144:ef7eb2e8f9f7	1328
<>	144:ef7eb2e8f9f7	1329	/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
<>	144:ef7eb2e8f9f7	1330	* @{
<>	144:ef7eb2e8f9f7	1331	*/
<>	144:ef7eb2e8f9f7	1332
<>	144:ef7eb2e8f9f7	1333	/* Initialization and de-initialization functions ****************************/
<>	144:ef7eb2e8f9f7	1334	HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1335	HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1336	HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
<>	144:ef7eb2e8f9f7	1337	HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
<>	144:ef7eb2e8f9f7	1338	HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1339	void HAL_UART_MspInit(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1340	void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1341
<>	144:ef7eb2e8f9f7	1342	/**
<>	144:ef7eb2e8f9f7	1343	* @}
<>	144:ef7eb2e8f9f7	1344	*/
<>	144:ef7eb2e8f9f7	1345
<>	144:ef7eb2e8f9f7	1346	/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
<>	144:ef7eb2e8f9f7	1347	* @{
<>	144:ef7eb2e8f9f7	1348	*/
<>	144:ef7eb2e8f9f7	1349
<>	144:ef7eb2e8f9f7	1350	/* IO operation functions *****************************************************/
<>	144:ef7eb2e8f9f7	1351	HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1352	HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1353	HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1354	HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1355	HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1356	HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef huart, uint8_t pData, uint16_t Size);
<>	144:ef7eb2e8f9f7	1357	HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1358	HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1359	HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1360	void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1361	void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1362	void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1363	void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1364	void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1365	void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1366
<>	144:ef7eb2e8f9f7	1367	/**
<>	144:ef7eb2e8f9f7	1368	* @}
<>	144:ef7eb2e8f9f7	1369	*/
<>	144:ef7eb2e8f9f7	1370
<>	144:ef7eb2e8f9f7	1371	/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
<>	144:ef7eb2e8f9f7	1372	* @{
<>	144:ef7eb2e8f9f7	1373	*/
<>	144:ef7eb2e8f9f7	1374
<>	144:ef7eb2e8f9f7	1375	/* Peripheral Control functions ************************************************/
<>	144:ef7eb2e8f9f7	1376	HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1377	HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1378	HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1379	void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1380	HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1381	HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1382
<>	144:ef7eb2e8f9f7	1383	/**
<>	144:ef7eb2e8f9f7	1384	* @}
<>	144:ef7eb2e8f9f7	1385	*/
<>	144:ef7eb2e8f9f7	1386
<>	144:ef7eb2e8f9f7	1387	/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
<>	144:ef7eb2e8f9f7	1388	* @{
<>	144:ef7eb2e8f9f7	1389	*/
<>	144:ef7eb2e8f9f7	1390
<>	144:ef7eb2e8f9f7	1391	/* Peripheral State and Errors functions **************************************************/
<>	144:ef7eb2e8f9f7	1392	HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1393	uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1394
<>	144:ef7eb2e8f9f7	1395	/**
<>	144:ef7eb2e8f9f7	1396	* @}
<>	144:ef7eb2e8f9f7	1397	*/
<>	144:ef7eb2e8f9f7	1398
<>	144:ef7eb2e8f9f7	1399	/**
<>	144:ef7eb2e8f9f7	1400	* @}
<>	144:ef7eb2e8f9f7	1401	*/
<>	144:ef7eb2e8f9f7	1402
<>	144:ef7eb2e8f9f7	1403	/* Private functions -----------------------------------------------------------*/
<>	144:ef7eb2e8f9f7	1404	/** @addtogroup UART_Private_Functions UART Private Functions
<>	144:ef7eb2e8f9f7	1405	* @{
<>	144:ef7eb2e8f9f7	1406	*/
<>	144:ef7eb2e8f9f7	1407
<>	144:ef7eb2e8f9f7	1408	HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1409	HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1410	HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout);
<>	144:ef7eb2e8f9f7	1411	void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
<>	144:ef7eb2e8f9f7	1412
<>	144:ef7eb2e8f9f7	1413	/**
<>	144:ef7eb2e8f9f7	1414	* @}
<>	144:ef7eb2e8f9f7	1415	*/
<>	144:ef7eb2e8f9f7	1416
<>	144:ef7eb2e8f9f7	1417	/**
<>	144:ef7eb2e8f9f7	1418	* @}
<>	144:ef7eb2e8f9f7	1419	*/
<>	144:ef7eb2e8f9f7	1420
<>	144:ef7eb2e8f9f7	1421	/**
<>	144:ef7eb2e8f9f7	1422	* @}
<>	144:ef7eb2e8f9f7	1423	*/
<>	144:ef7eb2e8f9f7	1424
<>	144:ef7eb2e8f9f7	1425	#ifdef __cplusplus
<>	144:ef7eb2e8f9f7	1426	}
<>	144:ef7eb2e8f9f7	1427	#endif
<>	144:ef7eb2e8f9f7	1428
<>	144:ef7eb2e8f9f7	1429	#endif /* __STM32L4xx_HAL_UART_H */
<>	144:ef7eb2e8f9f7	1430
<>	144:ef7eb2e8f9f7	1431	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	11 Feb 2018
Imports:	0
Forks:	0
Commits:	182
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targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_uart.h@149:156823d33999, 2016-10-28 (annotated)

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