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mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by mbed official

targets/TARGET_RENESAS/TARGET_RZ_A1H/device/inc/iodefines/scux_iodefine.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/inc/iodefines/scux_iodefine.h@119:3921aeca8633
Child:
181:96ed750bd169
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 119:3921aeca8633 1 /*******************************************************************************
mbed_official 119:3921aeca8633 2 * DISCLAIMER
mbed_official 119:3921aeca8633 3 * This software is supplied by Renesas Electronics Corporation and is only
mbed_official 119:3921aeca8633 4 * intended for use with Renesas products. No other uses are authorized. This
mbed_official 119:3921aeca8633 5 * software is owned by Renesas Electronics Corporation and is protected under
mbed_official 119:3921aeca8633 6 * all applicable laws, including copyright laws.
mbed_official 119:3921aeca8633 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
mbed_official 119:3921aeca8633 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
mbed_official 119:3921aeca8633 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
mbed_official 119:3921aeca8633 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
mbed_official 119:3921aeca8633 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
mbed_official 119:3921aeca8633 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
mbed_official 119:3921aeca8633 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
mbed_official 119:3921aeca8633 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
mbed_official 119:3921aeca8633 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
mbed_official 119:3921aeca8633 16 * Renesas reserves the right, without notice, to make changes to this software
mbed_official 119:3921aeca8633 17 * and to discontinue the availability of this software. By using this software,
mbed_official 119:3921aeca8633 18 * you agree to the additional terms and conditions found by accessing the
mbed_official 119:3921aeca8633 19 * following link:
mbed_official 119:3921aeca8633 20 * http://www.renesas.com/disclaimer*
mbed_official 119:3921aeca8633 21 * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved.
mbed_official 119:3921aeca8633 22 *******************************************************************************/
mbed_official 119:3921aeca8633 23 /*******************************************************************************
mbed_official 119:3921aeca8633 24 * File Name : scux_iodefine.h
mbed_official 119:3921aeca8633 25 * $Rev: $
mbed_official 119:3921aeca8633 26 * $Date:: $
mbed_official 119:3921aeca8633 27 * Description : Definition of I/O Register (V1.00a)
mbed_official 119:3921aeca8633 28 ******************************************************************************/
mbed_official 119:3921aeca8633 29 #ifndef SCUX_IODEFINE_H
mbed_official 119:3921aeca8633 30 #define SCUX_IODEFINE_H
mbed_official 119:3921aeca8633 31 /* ->QAC 0639 : Over 127 members (C90) */
mbed_official 119:3921aeca8633 32 /* ->SEC M1.10.1 : Not magic number */
mbed_official 119:3921aeca8633 33
mbed_official 119:3921aeca8633 34 struct st_scux
mbed_official 119:3921aeca8633 35 { /* SCUX */
mbed_official 119:3921aeca8633 36 /* start of struct st_scux_from_ipcir_ipc0_n */
mbed_official 119:3921aeca8633 37 volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
mbed_official 119:3921aeca8633 38 volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
mbed_official 119:3921aeca8633 39 volatile uint8_t dummy259[248]; /* */
mbed_official 119:3921aeca8633 40 /* end of struct st_scux_from_ipcir_ipc0_n */
mbed_official 119:3921aeca8633 41 /* start of struct st_scux_from_ipcir_ipc0_n */
mbed_official 119:3921aeca8633 42 volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */
mbed_official 119:3921aeca8633 43 volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */
mbed_official 119:3921aeca8633 44 volatile uint8_t dummy260[248]; /* */
mbed_official 119:3921aeca8633 45 /* end of struct st_scux_from_ipcir_ipc0_n */
mbed_official 119:3921aeca8633 46 /* start of struct st_scux_from_ipcir_ipc0_n */
mbed_official 119:3921aeca8633 47 volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */
mbed_official 119:3921aeca8633 48 volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */
mbed_official 119:3921aeca8633 49 volatile uint8_t dummy261[248]; /* */
mbed_official 119:3921aeca8633 50 /* end of struct st_scux_from_ipcir_ipc0_n */
mbed_official 119:3921aeca8633 51 /* start of struct st_scux_from_ipcir_ipc0_n */
mbed_official 119:3921aeca8633 52 volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */
mbed_official 119:3921aeca8633 53 volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */
mbed_official 119:3921aeca8633 54 volatile uint8_t dummy262[248]; /* */
mbed_official 119:3921aeca8633 55 /* end of struct st_scux_from_ipcir_ipc0_n */
mbed_official 119:3921aeca8633 56 /* start of struct st_scux_from_opcir_opc0_n */
mbed_official 119:3921aeca8633 57 volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
mbed_official 119:3921aeca8633 58 volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
mbed_official 119:3921aeca8633 59 volatile uint8_t dummy263[248]; /* */
mbed_official 119:3921aeca8633 60 /* end of struct st_scux_from_opcir_opc0_n */
mbed_official 119:3921aeca8633 61 /* start of struct st_scux_from_opcir_opc0_n */
mbed_official 119:3921aeca8633 62 volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */
mbed_official 119:3921aeca8633 63 volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */
mbed_official 119:3921aeca8633 64 volatile uint8_t dummy264[248]; /* */
mbed_official 119:3921aeca8633 65 /* end of struct st_scux_from_opcir_opc0_n */
mbed_official 119:3921aeca8633 66 /* start of struct st_scux_from_opcir_opc0_n */
mbed_official 119:3921aeca8633 67 volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */
mbed_official 119:3921aeca8633 68 volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */
mbed_official 119:3921aeca8633 69 volatile uint8_t dummy265[248]; /* */
mbed_official 119:3921aeca8633 70 /* end of struct st_scux_from_opcir_opc0_n */
mbed_official 119:3921aeca8633 71 /* start of struct st_scux_from_opcir_opc0_n */
mbed_official 119:3921aeca8633 72 volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */
mbed_official 119:3921aeca8633 73 volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */
mbed_official 119:3921aeca8633 74 volatile uint8_t dummy266[248]; /* */
mbed_official 119:3921aeca8633 75 /* end of struct st_scux_from_opcir_opc0_n */
mbed_official 119:3921aeca8633 76 /* start of struct st_scux_from_ffdir_ffd0_n */
mbed_official 119:3921aeca8633 77 volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
mbed_official 119:3921aeca8633 78 volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
mbed_official 119:3921aeca8633 79 volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
mbed_official 119:3921aeca8633 80 volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
mbed_official 119:3921aeca8633 81 volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
mbed_official 119:3921aeca8633 82 volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
mbed_official 119:3921aeca8633 83 volatile uint8_t dummy267[4]; /* */
mbed_official 119:3921aeca8633 84 volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
mbed_official 119:3921aeca8633 85 /* end of struct st_scux_from_ffdir_ffd0_n */
mbed_official 119:3921aeca8633 86 volatile uint8_t dummy268[224]; /* */
mbed_official 119:3921aeca8633 87 /* start of struct st_scux_from_ffdir_ffd0_n */
mbed_official 119:3921aeca8633 88 volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */
mbed_official 119:3921aeca8633 89 volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */
mbed_official 119:3921aeca8633 90 volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */
mbed_official 119:3921aeca8633 91 volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */
mbed_official 119:3921aeca8633 92 volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */
mbed_official 119:3921aeca8633 93 volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */
mbed_official 119:3921aeca8633 94 volatile uint8_t dummy269[4]; /* */
mbed_official 119:3921aeca8633 95 volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */
mbed_official 119:3921aeca8633 96 /* end of struct st_scux_from_ffdir_ffd0_n */
mbed_official 119:3921aeca8633 97 volatile uint8_t dummy270[224]; /* */
mbed_official 119:3921aeca8633 98 /* start of struct st_scux_from_ffdir_ffd0_n */
mbed_official 119:3921aeca8633 99 volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */
mbed_official 119:3921aeca8633 100 volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */
mbed_official 119:3921aeca8633 101 volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */
mbed_official 119:3921aeca8633 102 volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */
mbed_official 119:3921aeca8633 103 volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */
mbed_official 119:3921aeca8633 104 volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */
mbed_official 119:3921aeca8633 105 volatile uint8_t dummy271[4]; /* */
mbed_official 119:3921aeca8633 106 volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */
mbed_official 119:3921aeca8633 107 /* end of struct st_scux_from_ffdir_ffd0_n */
mbed_official 119:3921aeca8633 108 volatile uint8_t dummy272[224]; /* */
mbed_official 119:3921aeca8633 109 /* start of struct st_scux_from_ffdir_ffd0_n */
mbed_official 119:3921aeca8633 110 volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */
mbed_official 119:3921aeca8633 111 volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */
mbed_official 119:3921aeca8633 112 volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */
mbed_official 119:3921aeca8633 113 volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */
mbed_official 119:3921aeca8633 114 volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */
mbed_official 119:3921aeca8633 115 volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */
mbed_official 119:3921aeca8633 116 volatile uint8_t dummy273[4]; /* */
mbed_official 119:3921aeca8633 117 volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */
mbed_official 119:3921aeca8633 118 /* end of struct st_scux_from_ffdir_ffd0_n */
mbed_official 119:3921aeca8633 119 volatile uint8_t dummy274[224]; /* */
mbed_official 119:3921aeca8633 120 /* start of struct st_scux_from_ffuir_ffu0_n */
mbed_official 119:3921aeca8633 121 volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
mbed_official 119:3921aeca8633 122 volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
mbed_official 119:3921aeca8633 123 volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
mbed_official 119:3921aeca8633 124 volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
mbed_official 119:3921aeca8633 125 volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
mbed_official 119:3921aeca8633 126 volatile uint8_t dummy275[4]; /* */
mbed_official 119:3921aeca8633 127 volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
mbed_official 119:3921aeca8633 128 /* end of struct st_scux_from_ffuir_ffu0_n */
mbed_official 119:3921aeca8633 129 volatile uint8_t dummy276[228]; /* */
mbed_official 119:3921aeca8633 130 /* start of struct st_scux_from_ffuir_ffu0_n */
mbed_official 119:3921aeca8633 131 volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */
mbed_official 119:3921aeca8633 132 volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */
mbed_official 119:3921aeca8633 133 volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */
mbed_official 119:3921aeca8633 134 volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */
mbed_official 119:3921aeca8633 135 volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */
mbed_official 119:3921aeca8633 136 volatile uint8_t dummy277[4]; /* */
mbed_official 119:3921aeca8633 137 volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */
mbed_official 119:3921aeca8633 138 /* end of struct st_scux_from_ffuir_ffu0_n */
mbed_official 119:3921aeca8633 139 volatile uint8_t dummy278[228]; /* */
mbed_official 119:3921aeca8633 140 /* start of struct st_scux_from_ffuir_ffu0_n */
mbed_official 119:3921aeca8633 141 volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */
mbed_official 119:3921aeca8633 142 volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */
mbed_official 119:3921aeca8633 143 volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */
mbed_official 119:3921aeca8633 144 volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */
mbed_official 119:3921aeca8633 145 volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */
mbed_official 119:3921aeca8633 146 volatile uint8_t dummy279[4]; /* */
mbed_official 119:3921aeca8633 147 volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */
mbed_official 119:3921aeca8633 148 /* end of struct st_scux_from_ffuir_ffu0_n */
mbed_official 119:3921aeca8633 149 volatile uint8_t dummy280[228]; /* */
mbed_official 119:3921aeca8633 150 /* start of struct st_scux_from_ffuir_ffu0_n */
mbed_official 119:3921aeca8633 151 volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */
mbed_official 119:3921aeca8633 152 volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */
mbed_official 119:3921aeca8633 153 volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */
mbed_official 119:3921aeca8633 154 volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */
mbed_official 119:3921aeca8633 155 volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */
mbed_official 119:3921aeca8633 156 volatile uint8_t dummy281[4]; /* */
mbed_official 119:3921aeca8633 157 volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */
mbed_official 119:3921aeca8633 158 /* end of struct st_scux_from_ffuir_ffu0_n */
mbed_official 119:3921aeca8633 159 volatile uint8_t dummy282[228]; /* */
mbed_official 119:3921aeca8633 160 /* start of struct st_scux_from_srcir0_2src0_n */
mbed_official 119:3921aeca8633 161 volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
mbed_official 119:3921aeca8633 162 volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
mbed_official 119:3921aeca8633 163 volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
mbed_official 119:3921aeca8633 164 volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
mbed_official 119:3921aeca8633 165 volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
mbed_official 119:3921aeca8633 166 volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
mbed_official 119:3921aeca8633 167 volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
mbed_official 119:3921aeca8633 168 volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
mbed_official 119:3921aeca8633 169 volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
mbed_official 119:3921aeca8633 170 volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
mbed_official 119:3921aeca8633 171 volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
mbed_official 119:3921aeca8633 172 volatile uint8_t dummy283[4]; /* */
mbed_official 119:3921aeca8633 173 volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
mbed_official 119:3921aeca8633 174 volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
mbed_official 119:3921aeca8633 175 volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
mbed_official 119:3921aeca8633 176 volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
mbed_official 119:3921aeca8633 177 volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
mbed_official 119:3921aeca8633 178 volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
mbed_official 119:3921aeca8633 179 volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
mbed_official 119:3921aeca8633 180 volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
mbed_official 119:3921aeca8633 181 volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
mbed_official 119:3921aeca8633 182 volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
mbed_official 119:3921aeca8633 183 volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
mbed_official 119:3921aeca8633 184 volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
mbed_official 119:3921aeca8633 185 volatile uint8_t dummy284[4]; /* */
mbed_official 119:3921aeca8633 186 volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
mbed_official 119:3921aeca8633 187 volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
mbed_official 119:3921aeca8633 188 /* end of struct st_scux_from_srcir0_2src0_n */
mbed_official 119:3921aeca8633 189 volatile uint8_t dummy285[148]; /* */
mbed_official 119:3921aeca8633 190 /* start of struct st_scux_from_srcir0_2src0_n */
mbed_official 119:3921aeca8633 191 volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */
mbed_official 119:3921aeca8633 192 volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */
mbed_official 119:3921aeca8633 193 volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */
mbed_official 119:3921aeca8633 194 volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */
mbed_official 119:3921aeca8633 195 volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */
mbed_official 119:3921aeca8633 196 volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */
mbed_official 119:3921aeca8633 197 volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */
mbed_official 119:3921aeca8633 198 volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */
mbed_official 119:3921aeca8633 199 volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */
mbed_official 119:3921aeca8633 200 volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */
mbed_official 119:3921aeca8633 201 volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */
mbed_official 119:3921aeca8633 202 volatile uint8_t dummy286[4]; /* */
mbed_official 119:3921aeca8633 203 volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */
mbed_official 119:3921aeca8633 204 volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */
mbed_official 119:3921aeca8633 205 volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */
mbed_official 119:3921aeca8633 206 volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */
mbed_official 119:3921aeca8633 207 volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */
mbed_official 119:3921aeca8633 208 volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */
mbed_official 119:3921aeca8633 209 volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */
mbed_official 119:3921aeca8633 210 volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */
mbed_official 119:3921aeca8633 211 volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */
mbed_official 119:3921aeca8633 212 volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */
mbed_official 119:3921aeca8633 213 volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */
mbed_official 119:3921aeca8633 214 volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */
mbed_official 119:3921aeca8633 215 volatile uint8_t dummy287[4]; /* */
mbed_official 119:3921aeca8633 216 volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */
mbed_official 119:3921aeca8633 217 volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */
mbed_official 119:3921aeca8633 218 /* end of struct st_scux_from_srcir0_2src0_n */
mbed_official 119:3921aeca8633 219 volatile uint8_t dummy288[148]; /* */
mbed_official 119:3921aeca8633 220 /* start of struct st_scux_from_dvuir_dvu0_n */
mbed_official 119:3921aeca8633 221 volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
mbed_official 119:3921aeca8633 222 volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
mbed_official 119:3921aeca8633 223 volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
mbed_official 119:3921aeca8633 224 volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
mbed_official 119:3921aeca8633 225 volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
mbed_official 119:3921aeca8633 226 volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
mbed_official 119:3921aeca8633 227 volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
mbed_official 119:3921aeca8633 228 volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
mbed_official 119:3921aeca8633 229 volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
mbed_official 119:3921aeca8633 230 volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
mbed_official 119:3921aeca8633 231 volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
mbed_official 119:3921aeca8633 232 volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
mbed_official 119:3921aeca8633 233 volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
mbed_official 119:3921aeca8633 234 volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
mbed_official 119:3921aeca8633 235 volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
mbed_official 119:3921aeca8633 236 volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
mbed_official 119:3921aeca8633 237 volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
mbed_official 119:3921aeca8633 238 volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
mbed_official 119:3921aeca8633 239 volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
mbed_official 119:3921aeca8633 240 volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
mbed_official 119:3921aeca8633 241 volatile uint8_t dummy289[4]; /* */
mbed_official 119:3921aeca8633 242 volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
mbed_official 119:3921aeca8633 243 /* end of struct st_scux_from_dvuir_dvu0_n */
mbed_official 119:3921aeca8633 244 volatile uint8_t dummy290[168]; /* */
mbed_official 119:3921aeca8633 245 /* start of struct st_scux_from_dvuir_dvu0_n */
mbed_official 119:3921aeca8633 246 volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */
mbed_official 119:3921aeca8633 247 volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */
mbed_official 119:3921aeca8633 248 volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */
mbed_official 119:3921aeca8633 249 volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */
mbed_official 119:3921aeca8633 250 volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */
mbed_official 119:3921aeca8633 251 volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */
mbed_official 119:3921aeca8633 252 volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */
mbed_official 119:3921aeca8633 253 volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */
mbed_official 119:3921aeca8633 254 volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */
mbed_official 119:3921aeca8633 255 volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */
mbed_official 119:3921aeca8633 256 volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */
mbed_official 119:3921aeca8633 257 volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */
mbed_official 119:3921aeca8633 258 volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */
mbed_official 119:3921aeca8633 259 volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */
mbed_official 119:3921aeca8633 260 volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */
mbed_official 119:3921aeca8633 261 volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */
mbed_official 119:3921aeca8633 262 volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */
mbed_official 119:3921aeca8633 263 volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */
mbed_official 119:3921aeca8633 264 volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */
mbed_official 119:3921aeca8633 265 volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */
mbed_official 119:3921aeca8633 266 volatile uint8_t dummy291[4]; /* */
mbed_official 119:3921aeca8633 267 volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */
mbed_official 119:3921aeca8633 268 /* end of struct st_scux_from_dvuir_dvu0_n */
mbed_official 119:3921aeca8633 269 volatile uint8_t dummy292[168]; /* */
mbed_official 119:3921aeca8633 270 /* start of struct st_scux_from_dvuir_dvu0_n */
mbed_official 119:3921aeca8633 271 volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */
mbed_official 119:3921aeca8633 272 volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */
mbed_official 119:3921aeca8633 273 volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */
mbed_official 119:3921aeca8633 274 volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */
mbed_official 119:3921aeca8633 275 volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */
mbed_official 119:3921aeca8633 276 volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */
mbed_official 119:3921aeca8633 277 volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */
mbed_official 119:3921aeca8633 278 volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */
mbed_official 119:3921aeca8633 279 volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */
mbed_official 119:3921aeca8633 280 volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */
mbed_official 119:3921aeca8633 281 volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */
mbed_official 119:3921aeca8633 282 volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */
mbed_official 119:3921aeca8633 283 volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */
mbed_official 119:3921aeca8633 284 volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */
mbed_official 119:3921aeca8633 285 volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */
mbed_official 119:3921aeca8633 286 volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */
mbed_official 119:3921aeca8633 287 volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */
mbed_official 119:3921aeca8633 288 volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */
mbed_official 119:3921aeca8633 289 volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */
mbed_official 119:3921aeca8633 290 volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */
mbed_official 119:3921aeca8633 291 volatile uint8_t dummy293[4]; /* */
mbed_official 119:3921aeca8633 292 volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */
mbed_official 119:3921aeca8633 293 /* end of struct st_scux_from_dvuir_dvu0_n */
mbed_official 119:3921aeca8633 294 volatile uint8_t dummy294[168]; /* */
mbed_official 119:3921aeca8633 295 /* start of struct st_scux_from_dvuir_dvu0_n */
mbed_official 119:3921aeca8633 296 volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */
mbed_official 119:3921aeca8633 297 volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */
mbed_official 119:3921aeca8633 298 volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */
mbed_official 119:3921aeca8633 299 volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */
mbed_official 119:3921aeca8633 300 volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */
mbed_official 119:3921aeca8633 301 volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */
mbed_official 119:3921aeca8633 302 volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */
mbed_official 119:3921aeca8633 303 volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */
mbed_official 119:3921aeca8633 304 volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */
mbed_official 119:3921aeca8633 305 volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */
mbed_official 119:3921aeca8633 306 volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */
mbed_official 119:3921aeca8633 307 volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */
mbed_official 119:3921aeca8633 308 volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */
mbed_official 119:3921aeca8633 309 volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */
mbed_official 119:3921aeca8633 310 volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */
mbed_official 119:3921aeca8633 311 volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */
mbed_official 119:3921aeca8633 312 volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */
mbed_official 119:3921aeca8633 313 volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */
mbed_official 119:3921aeca8633 314 volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */
mbed_official 119:3921aeca8633 315 volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */
mbed_official 119:3921aeca8633 316 volatile uint8_t dummy295[4]; /* */
mbed_official 119:3921aeca8633 317 volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */
mbed_official 119:3921aeca8633 318 /* end of struct st_scux_from_dvuir_dvu0_n */
mbed_official 119:3921aeca8633 319 volatile uint8_t dummy296[168]; /* */
mbed_official 119:3921aeca8633 320 volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */
mbed_official 119:3921aeca8633 321 volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */
mbed_official 119:3921aeca8633 322 volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */
mbed_official 119:3921aeca8633 323 volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */
mbed_official 119:3921aeca8633 324 volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */
mbed_official 119:3921aeca8633 325 volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */
mbed_official 119:3921aeca8633 326 volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */
mbed_official 119:3921aeca8633 327 volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */
mbed_official 119:3921aeca8633 328 volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */
mbed_official 119:3921aeca8633 329 volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */
mbed_official 119:3921aeca8633 330 volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */
mbed_official 119:3921aeca8633 331 volatile uint8_t dummy297[212]; /* */
mbed_official 119:3921aeca8633 332 volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */
mbed_official 119:3921aeca8633 333 volatile uint32_t DMACR_CIM; /* DMACR_CIM */
mbed_official 119:3921aeca8633 334 #define SCUX_DMATDn_CIM_COUNT 4
mbed_official 119:3921aeca8633 335 union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */
mbed_official 119:3921aeca8633 336 union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */
mbed_official 119:3921aeca8633 337 union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */
mbed_official 119:3921aeca8633 338 union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */
mbed_official 119:3921aeca8633 339 #define SCUX_DMATUn_CIM_COUNT 4
mbed_official 119:3921aeca8633 340 union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */
mbed_official 119:3921aeca8633 341 union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */
mbed_official 119:3921aeca8633 342 union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */
mbed_official 119:3921aeca8633 343 union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */
mbed_official 119:3921aeca8633 344
mbed_official 119:3921aeca8633 345 volatile uint8_t dummy298[16]; /* */
mbed_official 119:3921aeca8633 346 volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */
mbed_official 119:3921aeca8633 347 #define SCUX_FDTSELn_CIM_COUNT 4
mbed_official 119:3921aeca8633 348 volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */
mbed_official 119:3921aeca8633 349 volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */
mbed_official 119:3921aeca8633 350 volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */
mbed_official 119:3921aeca8633 351 volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */
mbed_official 119:3921aeca8633 352 #define SCUX_FUTSELn_CIM_COUNT 4
mbed_official 119:3921aeca8633 353 volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */
mbed_official 119:3921aeca8633 354 volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */
mbed_official 119:3921aeca8633 355 volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */
mbed_official 119:3921aeca8633 356 volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */
mbed_official 119:3921aeca8633 357 volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */
mbed_official 119:3921aeca8633 358 volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */
mbed_official 119:3921aeca8633 359 #define SCUX_SRCRSELn_CIM_COUNT 4
mbed_official 119:3921aeca8633 360 volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */
mbed_official 119:3921aeca8633 361 volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */
mbed_official 119:3921aeca8633 362 volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */
mbed_official 119:3921aeca8633 363 volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */
mbed_official 119:3921aeca8633 364 volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */
mbed_official 119:3921aeca8633 365 };
mbed_official 119:3921aeca8633 366
mbed_official 119:3921aeca8633 367
mbed_official 119:3921aeca8633 368 struct st_scux_from_ipcir_ipc0_n
mbed_official 119:3921aeca8633 369 {
mbed_official 119:3921aeca8633 370 volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
mbed_official 119:3921aeca8633 371 volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
mbed_official 119:3921aeca8633 372 volatile uint8_t dummy1[248]; /* */
mbed_official 119:3921aeca8633 373 };
mbed_official 119:3921aeca8633 374
mbed_official 119:3921aeca8633 375
mbed_official 119:3921aeca8633 376 struct st_scux_from_opcir_opc0_n
mbed_official 119:3921aeca8633 377 {
mbed_official 119:3921aeca8633 378 volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
mbed_official 119:3921aeca8633 379 volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
mbed_official 119:3921aeca8633 380 volatile uint8_t dummy1[248]; /* */
mbed_official 119:3921aeca8633 381 };
mbed_official 119:3921aeca8633 382
mbed_official 119:3921aeca8633 383
mbed_official 119:3921aeca8633 384 struct st_scux_from_ffdir_ffd0_n
mbed_official 119:3921aeca8633 385 {
mbed_official 119:3921aeca8633 386 volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
mbed_official 119:3921aeca8633 387 volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
mbed_official 119:3921aeca8633 388 volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
mbed_official 119:3921aeca8633 389 volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
mbed_official 119:3921aeca8633 390 volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
mbed_official 119:3921aeca8633 391 volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
mbed_official 119:3921aeca8633 392 volatile uint8_t dummy1[4]; /* */
mbed_official 119:3921aeca8633 393 volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
mbed_official 119:3921aeca8633 394 };
mbed_official 119:3921aeca8633 395
mbed_official 119:3921aeca8633 396
mbed_official 119:3921aeca8633 397 struct st_scux_from_ffuir_ffu0_n
mbed_official 119:3921aeca8633 398 {
mbed_official 119:3921aeca8633 399 volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
mbed_official 119:3921aeca8633 400 volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
mbed_official 119:3921aeca8633 401 volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
mbed_official 119:3921aeca8633 402 volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
mbed_official 119:3921aeca8633 403 volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
mbed_official 119:3921aeca8633 404 volatile uint8_t dummy1[4]; /* */
mbed_official 119:3921aeca8633 405 volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
mbed_official 119:3921aeca8633 406 };
mbed_official 119:3921aeca8633 407
mbed_official 119:3921aeca8633 408
mbed_official 119:3921aeca8633 409 struct st_scux_from_srcir0_2src0_n
mbed_official 119:3921aeca8633 410 {
mbed_official 119:3921aeca8633 411 volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
mbed_official 119:3921aeca8633 412 volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
mbed_official 119:3921aeca8633 413 volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
mbed_official 119:3921aeca8633 414 volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
mbed_official 119:3921aeca8633 415 volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
mbed_official 119:3921aeca8633 416 volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
mbed_official 119:3921aeca8633 417 volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
mbed_official 119:3921aeca8633 418 volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
mbed_official 119:3921aeca8633 419 volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
mbed_official 119:3921aeca8633 420 volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
mbed_official 119:3921aeca8633 421 volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
mbed_official 119:3921aeca8633 422 volatile uint8_t dummy1[4]; /* */
mbed_official 119:3921aeca8633 423 volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
mbed_official 119:3921aeca8633 424 volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
mbed_official 119:3921aeca8633 425 volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
mbed_official 119:3921aeca8633 426 volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
mbed_official 119:3921aeca8633 427 volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
mbed_official 119:3921aeca8633 428 volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
mbed_official 119:3921aeca8633 429 volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
mbed_official 119:3921aeca8633 430 volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
mbed_official 119:3921aeca8633 431 volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
mbed_official 119:3921aeca8633 432 volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
mbed_official 119:3921aeca8633 433 volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
mbed_official 119:3921aeca8633 434 volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
mbed_official 119:3921aeca8633 435 volatile uint8_t dummy2[4]; /* */
mbed_official 119:3921aeca8633 436 volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
mbed_official 119:3921aeca8633 437 volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
mbed_official 119:3921aeca8633 438 };
mbed_official 119:3921aeca8633 439
mbed_official 119:3921aeca8633 440
mbed_official 119:3921aeca8633 441 struct st_scux_from_dvuir_dvu0_n
mbed_official 119:3921aeca8633 442 {
mbed_official 119:3921aeca8633 443 volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
mbed_official 119:3921aeca8633 444 volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
mbed_official 119:3921aeca8633 445 volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
mbed_official 119:3921aeca8633 446 volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
mbed_official 119:3921aeca8633 447 volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
mbed_official 119:3921aeca8633 448 volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
mbed_official 119:3921aeca8633 449 volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
mbed_official 119:3921aeca8633 450 volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
mbed_official 119:3921aeca8633 451 volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
mbed_official 119:3921aeca8633 452 volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
mbed_official 119:3921aeca8633 453 volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
mbed_official 119:3921aeca8633 454 volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
mbed_official 119:3921aeca8633 455 volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
mbed_official 119:3921aeca8633 456 volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
mbed_official 119:3921aeca8633 457 volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
mbed_official 119:3921aeca8633 458 volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
mbed_official 119:3921aeca8633 459 volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
mbed_official 119:3921aeca8633 460 volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
mbed_official 119:3921aeca8633 461 volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
mbed_official 119:3921aeca8633 462 volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
mbed_official 119:3921aeca8633 463 volatile uint8_t dummy1[4]; /* */
mbed_official 119:3921aeca8633 464 volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
mbed_official 119:3921aeca8633 465 };
mbed_official 119:3921aeca8633 466
mbed_official 119:3921aeca8633 467
mbed_official 119:3921aeca8633 468 #define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */
mbed_official 119:3921aeca8633 469
mbed_official 119:3921aeca8633 470
mbed_official 119:3921aeca8633 471 /* Start of channnel array defines of SCUX */
mbed_official 119:3921aeca8633 472
mbed_official 119:3921aeca8633 473 /* Channnel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
mbed_official 119:3921aeca8633 474 /*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
mbed_official 119:3921aeca8633 475 #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT 4
mbed_official 119:3921aeca8633 476 #define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
mbed_official 119:3921aeca8633 477 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 119:3921aeca8633 478 &SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
mbed_official 119:3921aeca8633 479 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 119:3921aeca8633 480 #define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
mbed_official 119:3921aeca8633 481 #define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
mbed_official 119:3921aeca8633 482 #define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
mbed_official 119:3921aeca8633 483 #define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
mbed_official 119:3921aeca8633 484
mbed_official 119:3921aeca8633 485
mbed_official 119:3921aeca8633 486 /* Channnel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
mbed_official 119:3921aeca8633 487 /*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
mbed_official 119:3921aeca8633 488 #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT 2
mbed_official 119:3921aeca8633 489 #define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
mbed_official 119:3921aeca8633 490 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 119:3921aeca8633 491 &SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
mbed_official 119:3921aeca8633 492 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 119:3921aeca8633 493 #define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
mbed_official 119:3921aeca8633 494 #define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
mbed_official 119:3921aeca8633 495
mbed_official 119:3921aeca8633 496
mbed_official 119:3921aeca8633 497 /* Channnel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
mbed_official 119:3921aeca8633 498 /*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
mbed_official 119:3921aeca8633 499 #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT 4
mbed_official 119:3921aeca8633 500 #define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
mbed_official 119:3921aeca8633 501 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 119:3921aeca8633 502 &SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
mbed_official 119:3921aeca8633 503 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 119:3921aeca8633 504 #define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
mbed_official 119:3921aeca8633 505 #define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
mbed_official 119:3921aeca8633 506 #define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
mbed_official 119:3921aeca8633 507 #define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
mbed_official 119:3921aeca8633 508
mbed_official 119:3921aeca8633 509
mbed_official 119:3921aeca8633 510 /* Channnel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
mbed_official 119:3921aeca8633 511 /*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
mbed_official 119:3921aeca8633 512 #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT 4
mbed_official 119:3921aeca8633 513 #define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
mbed_official 119:3921aeca8633 514 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 119:3921aeca8633 515 &SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
mbed_official 119:3921aeca8633 516 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 119:3921aeca8633 517 #define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
mbed_official 119:3921aeca8633 518 #define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
mbed_official 119:3921aeca8633 519 #define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
mbed_official 119:3921aeca8633 520 #define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
mbed_official 119:3921aeca8633 521
mbed_official 119:3921aeca8633 522
mbed_official 119:3921aeca8633 523 /* Channnel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
mbed_official 119:3921aeca8633 524 /*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
mbed_official 119:3921aeca8633 525 #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT 4
mbed_official 119:3921aeca8633 526 #define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
mbed_official 119:3921aeca8633 527 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 119:3921aeca8633 528 &SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
mbed_official 119:3921aeca8633 529 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 119:3921aeca8633 530 #define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
mbed_official 119:3921aeca8633 531 #define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
mbed_official 119:3921aeca8633 532 #define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
mbed_official 119:3921aeca8633 533 #define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
mbed_official 119:3921aeca8633 534
mbed_official 119:3921aeca8633 535
mbed_official 119:3921aeca8633 536 /* Channnel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
mbed_official 119:3921aeca8633 537 /*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
mbed_official 119:3921aeca8633 538 #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT 4
mbed_official 119:3921aeca8633 539 #define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
mbed_official 119:3921aeca8633 540 { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
mbed_official 119:3921aeca8633 541 &SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
mbed_official 119:3921aeca8633 542 } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
mbed_official 119:3921aeca8633 543 #define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
mbed_official 119:3921aeca8633 544 #define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
mbed_official 119:3921aeca8633 545 #define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
mbed_official 119:3921aeca8633 546 #define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
mbed_official 119:3921aeca8633 547
mbed_official 119:3921aeca8633 548 /* End of channnel array defines of SCUX */
mbed_official 119:3921aeca8633 549
mbed_official 119:3921aeca8633 550
mbed_official 119:3921aeca8633 551 #define SCUXIPCIR_IPC0_0 SCUX.IPCIR_IPC0_0
mbed_official 119:3921aeca8633 552 #define SCUXIPSLR_IPC0_0 SCUX.IPSLR_IPC0_0
mbed_official 119:3921aeca8633 553 #define SCUXIPCIR_IPC0_1 SCUX.IPCIR_IPC0_1
mbed_official 119:3921aeca8633 554 #define SCUXIPSLR_IPC0_1 SCUX.IPSLR_IPC0_1
mbed_official 119:3921aeca8633 555 #define SCUXIPCIR_IPC0_2 SCUX.IPCIR_IPC0_2
mbed_official 119:3921aeca8633 556 #define SCUXIPSLR_IPC0_2 SCUX.IPSLR_IPC0_2
mbed_official 119:3921aeca8633 557 #define SCUXIPCIR_IPC0_3 SCUX.IPCIR_IPC0_3
mbed_official 119:3921aeca8633 558 #define SCUXIPSLR_IPC0_3 SCUX.IPSLR_IPC0_3
mbed_official 119:3921aeca8633 559 #define SCUXOPCIR_OPC0_0 SCUX.OPCIR_OPC0_0
mbed_official 119:3921aeca8633 560 #define SCUXOPSLR_OPC0_0 SCUX.OPSLR_OPC0_0
mbed_official 119:3921aeca8633 561 #define SCUXOPCIR_OPC0_1 SCUX.OPCIR_OPC0_1
mbed_official 119:3921aeca8633 562 #define SCUXOPSLR_OPC0_1 SCUX.OPSLR_OPC0_1
mbed_official 119:3921aeca8633 563 #define SCUXOPCIR_OPC0_2 SCUX.OPCIR_OPC0_2
mbed_official 119:3921aeca8633 564 #define SCUXOPSLR_OPC0_2 SCUX.OPSLR_OPC0_2
mbed_official 119:3921aeca8633 565 #define SCUXOPCIR_OPC0_3 SCUX.OPCIR_OPC0_3
mbed_official 119:3921aeca8633 566 #define SCUXOPSLR_OPC0_3 SCUX.OPSLR_OPC0_3
mbed_official 119:3921aeca8633 567 #define SCUXFFDIR_FFD0_0 SCUX.FFDIR_FFD0_0
mbed_official 119:3921aeca8633 568 #define SCUXFDAIR_FFD0_0 SCUX.FDAIR_FFD0_0
mbed_official 119:3921aeca8633 569 #define SCUXDRQSR_FFD0_0 SCUX.DRQSR_FFD0_0
mbed_official 119:3921aeca8633 570 #define SCUXFFDPR_FFD0_0 SCUX.FFDPR_FFD0_0
mbed_official 119:3921aeca8633 571 #define SCUXFFDBR_FFD0_0 SCUX.FFDBR_FFD0_0
mbed_official 119:3921aeca8633 572 #define SCUXDEVMR_FFD0_0 SCUX.DEVMR_FFD0_0
mbed_official 119:3921aeca8633 573 #define SCUXDEVCR_FFD0_0 SCUX.DEVCR_FFD0_0
mbed_official 119:3921aeca8633 574 #define SCUXFFDIR_FFD0_1 SCUX.FFDIR_FFD0_1
mbed_official 119:3921aeca8633 575 #define SCUXFDAIR_FFD0_1 SCUX.FDAIR_FFD0_1
mbed_official 119:3921aeca8633 576 #define SCUXDRQSR_FFD0_1 SCUX.DRQSR_FFD0_1
mbed_official 119:3921aeca8633 577 #define SCUXFFDPR_FFD0_1 SCUX.FFDPR_FFD0_1
mbed_official 119:3921aeca8633 578 #define SCUXFFDBR_FFD0_1 SCUX.FFDBR_FFD0_1
mbed_official 119:3921aeca8633 579 #define SCUXDEVMR_FFD0_1 SCUX.DEVMR_FFD0_1
mbed_official 119:3921aeca8633 580 #define SCUXDEVCR_FFD0_1 SCUX.DEVCR_FFD0_1
mbed_official 119:3921aeca8633 581 #define SCUXFFDIR_FFD0_2 SCUX.FFDIR_FFD0_2
mbed_official 119:3921aeca8633 582 #define SCUXFDAIR_FFD0_2 SCUX.FDAIR_FFD0_2
mbed_official 119:3921aeca8633 583 #define SCUXDRQSR_FFD0_2 SCUX.DRQSR_FFD0_2
mbed_official 119:3921aeca8633 584 #define SCUXFFDPR_FFD0_2 SCUX.FFDPR_FFD0_2
mbed_official 119:3921aeca8633 585 #define SCUXFFDBR_FFD0_2 SCUX.FFDBR_FFD0_2
mbed_official 119:3921aeca8633 586 #define SCUXDEVMR_FFD0_2 SCUX.DEVMR_FFD0_2
mbed_official 119:3921aeca8633 587 #define SCUXDEVCR_FFD0_2 SCUX.DEVCR_FFD0_2
mbed_official 119:3921aeca8633 588 #define SCUXFFDIR_FFD0_3 SCUX.FFDIR_FFD0_3
mbed_official 119:3921aeca8633 589 #define SCUXFDAIR_FFD0_3 SCUX.FDAIR_FFD0_3
mbed_official 119:3921aeca8633 590 #define SCUXDRQSR_FFD0_3 SCUX.DRQSR_FFD0_3
mbed_official 119:3921aeca8633 591 #define SCUXFFDPR_FFD0_3 SCUX.FFDPR_FFD0_3
mbed_official 119:3921aeca8633 592 #define SCUXFFDBR_FFD0_3 SCUX.FFDBR_FFD0_3
mbed_official 119:3921aeca8633 593 #define SCUXDEVMR_FFD0_3 SCUX.DEVMR_FFD0_3
mbed_official 119:3921aeca8633 594 #define SCUXDEVCR_FFD0_3 SCUX.DEVCR_FFD0_3
mbed_official 119:3921aeca8633 595 #define SCUXFFUIR_FFU0_0 SCUX.FFUIR_FFU0_0
mbed_official 119:3921aeca8633 596 #define SCUXFUAIR_FFU0_0 SCUX.FUAIR_FFU0_0
mbed_official 119:3921aeca8633 597 #define SCUXURQSR_FFU0_0 SCUX.URQSR_FFU0_0
mbed_official 119:3921aeca8633 598 #define SCUXFFUPR_FFU0_0 SCUX.FFUPR_FFU0_0
mbed_official 119:3921aeca8633 599 #define SCUXUEVMR_FFU0_0 SCUX.UEVMR_FFU0_0
mbed_official 119:3921aeca8633 600 #define SCUXUEVCR_FFU0_0 SCUX.UEVCR_FFU0_0
mbed_official 119:3921aeca8633 601 #define SCUXFFUIR_FFU0_1 SCUX.FFUIR_FFU0_1
mbed_official 119:3921aeca8633 602 #define SCUXFUAIR_FFU0_1 SCUX.FUAIR_FFU0_1
mbed_official 119:3921aeca8633 603 #define SCUXURQSR_FFU0_1 SCUX.URQSR_FFU0_1
mbed_official 119:3921aeca8633 604 #define SCUXFFUPR_FFU0_1 SCUX.FFUPR_FFU0_1
mbed_official 119:3921aeca8633 605 #define SCUXUEVMR_FFU0_1 SCUX.UEVMR_FFU0_1
mbed_official 119:3921aeca8633 606 #define SCUXUEVCR_FFU0_1 SCUX.UEVCR_FFU0_1
mbed_official 119:3921aeca8633 607 #define SCUXFFUIR_FFU0_2 SCUX.FFUIR_FFU0_2
mbed_official 119:3921aeca8633 608 #define SCUXFUAIR_FFU0_2 SCUX.FUAIR_FFU0_2
mbed_official 119:3921aeca8633 609 #define SCUXURQSR_FFU0_2 SCUX.URQSR_FFU0_2
mbed_official 119:3921aeca8633 610 #define SCUXFFUPR_FFU0_2 SCUX.FFUPR_FFU0_2
mbed_official 119:3921aeca8633 611 #define SCUXUEVMR_FFU0_2 SCUX.UEVMR_FFU0_2
mbed_official 119:3921aeca8633 612 #define SCUXUEVCR_FFU0_2 SCUX.UEVCR_FFU0_2
mbed_official 119:3921aeca8633 613 #define SCUXFFUIR_FFU0_3 SCUX.FFUIR_FFU0_3
mbed_official 119:3921aeca8633 614 #define SCUXFUAIR_FFU0_3 SCUX.FUAIR_FFU0_3
mbed_official 119:3921aeca8633 615 #define SCUXURQSR_FFU0_3 SCUX.URQSR_FFU0_3
mbed_official 119:3921aeca8633 616 #define SCUXFFUPR_FFU0_3 SCUX.FFUPR_FFU0_3
mbed_official 119:3921aeca8633 617 #define SCUXUEVMR_FFU0_3 SCUX.UEVMR_FFU0_3
mbed_official 119:3921aeca8633 618 #define SCUXUEVCR_FFU0_3 SCUX.UEVCR_FFU0_3
mbed_official 119:3921aeca8633 619 #define SCUXSRCIR0_2SRC0_0 SCUX.SRCIR0_2SRC0_0
mbed_official 119:3921aeca8633 620 #define SCUXSADIR0_2SRC0_0 SCUX.SADIR0_2SRC0_0
mbed_official 119:3921aeca8633 621 #define SCUXSRCBR0_2SRC0_0 SCUX.SRCBR0_2SRC0_0
mbed_official 119:3921aeca8633 622 #define SCUXIFSCR0_2SRC0_0 SCUX.IFSCR0_2SRC0_0
mbed_official 119:3921aeca8633 623 #define SCUXIFSVR0_2SRC0_0 SCUX.IFSVR0_2SRC0_0
mbed_official 119:3921aeca8633 624 #define SCUXSRCCR0_2SRC0_0 SCUX.SRCCR0_2SRC0_0
mbed_official 119:3921aeca8633 625 #define SCUXMNFSR0_2SRC0_0 SCUX.MNFSR0_2SRC0_0
mbed_official 119:3921aeca8633 626 #define SCUXBFSSR0_2SRC0_0 SCUX.BFSSR0_2SRC0_0
mbed_official 119:3921aeca8633 627 #define SCUXSC2SR0_2SRC0_0 SCUX.SC2SR0_2SRC0_0
mbed_official 119:3921aeca8633 628 #define SCUXWATSR0_2SRC0_0 SCUX.WATSR0_2SRC0_0
mbed_official 119:3921aeca8633 629 #define SCUXSEVMR0_2SRC0_0 SCUX.SEVMR0_2SRC0_0
mbed_official 119:3921aeca8633 630 #define SCUXSEVCR0_2SRC0_0 SCUX.SEVCR0_2SRC0_0
mbed_official 119:3921aeca8633 631 #define SCUXSRCIR1_2SRC0_0 SCUX.SRCIR1_2SRC0_0
mbed_official 119:3921aeca8633 632 #define SCUXSADIR1_2SRC0_0 SCUX.SADIR1_2SRC0_0
mbed_official 119:3921aeca8633 633 #define SCUXSRCBR1_2SRC0_0 SCUX.SRCBR1_2SRC0_0
mbed_official 119:3921aeca8633 634 #define SCUXIFSCR1_2SRC0_0 SCUX.IFSCR1_2SRC0_0
mbed_official 119:3921aeca8633 635 #define SCUXIFSVR1_2SRC0_0 SCUX.IFSVR1_2SRC0_0
mbed_official 119:3921aeca8633 636 #define SCUXSRCCR1_2SRC0_0 SCUX.SRCCR1_2SRC0_0
mbed_official 119:3921aeca8633 637 #define SCUXMNFSR1_2SRC0_0 SCUX.MNFSR1_2SRC0_0
mbed_official 119:3921aeca8633 638 #define SCUXBFSSR1_2SRC0_0 SCUX.BFSSR1_2SRC0_0
mbed_official 119:3921aeca8633 639 #define SCUXSC2SR1_2SRC0_0 SCUX.SC2SR1_2SRC0_0
mbed_official 119:3921aeca8633 640 #define SCUXWATSR1_2SRC0_0 SCUX.WATSR1_2SRC0_0
mbed_official 119:3921aeca8633 641 #define SCUXSEVMR1_2SRC0_0 SCUX.SEVMR1_2SRC0_0
mbed_official 119:3921aeca8633 642 #define SCUXSEVCR1_2SRC0_0 SCUX.SEVCR1_2SRC0_0
mbed_official 119:3921aeca8633 643 #define SCUXSRCIRR_2SRC0_0 SCUX.SRCIRR_2SRC0_0
mbed_official 119:3921aeca8633 644 #define SCUXSRCIR0_2SRC0_1 SCUX.SRCIR0_2SRC0_1
mbed_official 119:3921aeca8633 645 #define SCUXSADIR0_2SRC0_1 SCUX.SADIR0_2SRC0_1
mbed_official 119:3921aeca8633 646 #define SCUXSRCBR0_2SRC0_1 SCUX.SRCBR0_2SRC0_1
mbed_official 119:3921aeca8633 647 #define SCUXIFSCR0_2SRC0_1 SCUX.IFSCR0_2SRC0_1
mbed_official 119:3921aeca8633 648 #define SCUXIFSVR0_2SRC0_1 SCUX.IFSVR0_2SRC0_1
mbed_official 119:3921aeca8633 649 #define SCUXSRCCR0_2SRC0_1 SCUX.SRCCR0_2SRC0_1
mbed_official 119:3921aeca8633 650 #define SCUXMNFSR0_2SRC0_1 SCUX.MNFSR0_2SRC0_1
mbed_official 119:3921aeca8633 651 #define SCUXBFSSR0_2SRC0_1 SCUX.BFSSR0_2SRC0_1
mbed_official 119:3921aeca8633 652 #define SCUXSC2SR0_2SRC0_1 SCUX.SC2SR0_2SRC0_1
mbed_official 119:3921aeca8633 653 #define SCUXWATSR0_2SRC0_1 SCUX.WATSR0_2SRC0_1
mbed_official 119:3921aeca8633 654 #define SCUXSEVMR0_2SRC0_1 SCUX.SEVMR0_2SRC0_1
mbed_official 119:3921aeca8633 655 #define SCUXSEVCR0_2SRC0_1 SCUX.SEVCR0_2SRC0_1
mbed_official 119:3921aeca8633 656 #define SCUXSRCIR1_2SRC0_1 SCUX.SRCIR1_2SRC0_1
mbed_official 119:3921aeca8633 657 #define SCUXSADIR1_2SRC0_1 SCUX.SADIR1_2SRC0_1
mbed_official 119:3921aeca8633 658 #define SCUXSRCBR1_2SRC0_1 SCUX.SRCBR1_2SRC0_1
mbed_official 119:3921aeca8633 659 #define SCUXIFSCR1_2SRC0_1 SCUX.IFSCR1_2SRC0_1
mbed_official 119:3921aeca8633 660 #define SCUXIFSVR1_2SRC0_1 SCUX.IFSVR1_2SRC0_1
mbed_official 119:3921aeca8633 661 #define SCUXSRCCR1_2SRC0_1 SCUX.SRCCR1_2SRC0_1
mbed_official 119:3921aeca8633 662 #define SCUXMNFSR1_2SRC0_1 SCUX.MNFSR1_2SRC0_1
mbed_official 119:3921aeca8633 663 #define SCUXBFSSR1_2SRC0_1 SCUX.BFSSR1_2SRC0_1
mbed_official 119:3921aeca8633 664 #define SCUXSC2SR1_2SRC0_1 SCUX.SC2SR1_2SRC0_1
mbed_official 119:3921aeca8633 665 #define SCUXWATSR1_2SRC0_1 SCUX.WATSR1_2SRC0_1
mbed_official 119:3921aeca8633 666 #define SCUXSEVMR1_2SRC0_1 SCUX.SEVMR1_2SRC0_1
mbed_official 119:3921aeca8633 667 #define SCUXSEVCR1_2SRC0_1 SCUX.SEVCR1_2SRC0_1
mbed_official 119:3921aeca8633 668 #define SCUXSRCIRR_2SRC0_1 SCUX.SRCIRR_2SRC0_1
mbed_official 119:3921aeca8633 669 #define SCUXDVUIR_DVU0_0 SCUX.DVUIR_DVU0_0
mbed_official 119:3921aeca8633 670 #define SCUXVADIR_DVU0_0 SCUX.VADIR_DVU0_0
mbed_official 119:3921aeca8633 671 #define SCUXDVUBR_DVU0_0 SCUX.DVUBR_DVU0_0
mbed_official 119:3921aeca8633 672 #define SCUXDVUCR_DVU0_0 SCUX.DVUCR_DVU0_0
mbed_official 119:3921aeca8633 673 #define SCUXZCMCR_DVU0_0 SCUX.ZCMCR_DVU0_0
mbed_official 119:3921aeca8633 674 #define SCUXVRCTR_DVU0_0 SCUX.VRCTR_DVU0_0
mbed_official 119:3921aeca8633 675 #define SCUXVRPDR_DVU0_0 SCUX.VRPDR_DVU0_0
mbed_official 119:3921aeca8633 676 #define SCUXVRDBR_DVU0_0 SCUX.VRDBR_DVU0_0
mbed_official 119:3921aeca8633 677 #define SCUXVRWTR_DVU0_0 SCUX.VRWTR_DVU0_0
mbed_official 119:3921aeca8633 678 #define SCUXVOL0R_DVU0_0 SCUX.VOL0R_DVU0_0
mbed_official 119:3921aeca8633 679 #define SCUXVOL1R_DVU0_0 SCUX.VOL1R_DVU0_0
mbed_official 119:3921aeca8633 680 #define SCUXVOL2R_DVU0_0 SCUX.VOL2R_DVU0_0
mbed_official 119:3921aeca8633 681 #define SCUXVOL3R_DVU0_0 SCUX.VOL3R_DVU0_0
mbed_official 119:3921aeca8633 682 #define SCUXVOL4R_DVU0_0 SCUX.VOL4R_DVU0_0
mbed_official 119:3921aeca8633 683 #define SCUXVOL5R_DVU0_0 SCUX.VOL5R_DVU0_0
mbed_official 119:3921aeca8633 684 #define SCUXVOL6R_DVU0_0 SCUX.VOL6R_DVU0_0
mbed_official 119:3921aeca8633 685 #define SCUXVOL7R_DVU0_0 SCUX.VOL7R_DVU0_0
mbed_official 119:3921aeca8633 686 #define SCUXDVUER_DVU0_0 SCUX.DVUER_DVU0_0
mbed_official 119:3921aeca8633 687 #define SCUXDVUSR_DVU0_0 SCUX.DVUSR_DVU0_0
mbed_official 119:3921aeca8633 688 #define SCUXVEVMR_DVU0_0 SCUX.VEVMR_DVU0_0
mbed_official 119:3921aeca8633 689 #define SCUXVEVCR_DVU0_0 SCUX.VEVCR_DVU0_0
mbed_official 119:3921aeca8633 690 #define SCUXDVUIR_DVU0_1 SCUX.DVUIR_DVU0_1
mbed_official 119:3921aeca8633 691 #define SCUXVADIR_DVU0_1 SCUX.VADIR_DVU0_1
mbed_official 119:3921aeca8633 692 #define SCUXDVUBR_DVU0_1 SCUX.DVUBR_DVU0_1
mbed_official 119:3921aeca8633 693 #define SCUXDVUCR_DVU0_1 SCUX.DVUCR_DVU0_1
mbed_official 119:3921aeca8633 694 #define SCUXZCMCR_DVU0_1 SCUX.ZCMCR_DVU0_1
mbed_official 119:3921aeca8633 695 #define SCUXVRCTR_DVU0_1 SCUX.VRCTR_DVU0_1
mbed_official 119:3921aeca8633 696 #define SCUXVRPDR_DVU0_1 SCUX.VRPDR_DVU0_1
mbed_official 119:3921aeca8633 697 #define SCUXVRDBR_DVU0_1 SCUX.VRDBR_DVU0_1
mbed_official 119:3921aeca8633 698 #define SCUXVRWTR_DVU0_1 SCUX.VRWTR_DVU0_1
mbed_official 119:3921aeca8633 699 #define SCUXVOL0R_DVU0_1 SCUX.VOL0R_DVU0_1
mbed_official 119:3921aeca8633 700 #define SCUXVOL1R_DVU0_1 SCUX.VOL1R_DVU0_1
mbed_official 119:3921aeca8633 701 #define SCUXVOL2R_DVU0_1 SCUX.VOL2R_DVU0_1
mbed_official 119:3921aeca8633 702 #define SCUXVOL3R_DVU0_1 SCUX.VOL3R_DVU0_1
mbed_official 119:3921aeca8633 703 #define SCUXVOL4R_DVU0_1 SCUX.VOL4R_DVU0_1
mbed_official 119:3921aeca8633 704 #define SCUXVOL5R_DVU0_1 SCUX.VOL5R_DVU0_1
mbed_official 119:3921aeca8633 705 #define SCUXVOL6R_DVU0_1 SCUX.VOL6R_DVU0_1
mbed_official 119:3921aeca8633 706 #define SCUXVOL7R_DVU0_1 SCUX.VOL7R_DVU0_1
mbed_official 119:3921aeca8633 707 #define SCUXDVUER_DVU0_1 SCUX.DVUER_DVU0_1
mbed_official 119:3921aeca8633 708 #define SCUXDVUSR_DVU0_1 SCUX.DVUSR_DVU0_1
mbed_official 119:3921aeca8633 709 #define SCUXVEVMR_DVU0_1 SCUX.VEVMR_DVU0_1
mbed_official 119:3921aeca8633 710 #define SCUXVEVCR_DVU0_1 SCUX.VEVCR_DVU0_1
mbed_official 119:3921aeca8633 711 #define SCUXDVUIR_DVU0_2 SCUX.DVUIR_DVU0_2
mbed_official 119:3921aeca8633 712 #define SCUXVADIR_DVU0_2 SCUX.VADIR_DVU0_2
mbed_official 119:3921aeca8633 713 #define SCUXDVUBR_DVU0_2 SCUX.DVUBR_DVU0_2
mbed_official 119:3921aeca8633 714 #define SCUXDVUCR_DVU0_2 SCUX.DVUCR_DVU0_2
mbed_official 119:3921aeca8633 715 #define SCUXZCMCR_DVU0_2 SCUX.ZCMCR_DVU0_2
mbed_official 119:3921aeca8633 716 #define SCUXVRCTR_DVU0_2 SCUX.VRCTR_DVU0_2
mbed_official 119:3921aeca8633 717 #define SCUXVRPDR_DVU0_2 SCUX.VRPDR_DVU0_2
mbed_official 119:3921aeca8633 718 #define SCUXVRDBR_DVU0_2 SCUX.VRDBR_DVU0_2
mbed_official 119:3921aeca8633 719 #define SCUXVRWTR_DVU0_2 SCUX.VRWTR_DVU0_2
mbed_official 119:3921aeca8633 720 #define SCUXVOL0R_DVU0_2 SCUX.VOL0R_DVU0_2
mbed_official 119:3921aeca8633 721 #define SCUXVOL1R_DVU0_2 SCUX.VOL1R_DVU0_2
mbed_official 119:3921aeca8633 722 #define SCUXVOL2R_DVU0_2 SCUX.VOL2R_DVU0_2
mbed_official 119:3921aeca8633 723 #define SCUXVOL3R_DVU0_2 SCUX.VOL3R_DVU0_2
mbed_official 119:3921aeca8633 724 #define SCUXVOL4R_DVU0_2 SCUX.VOL4R_DVU0_2
mbed_official 119:3921aeca8633 725 #define SCUXVOL5R_DVU0_2 SCUX.VOL5R_DVU0_2
mbed_official 119:3921aeca8633 726 #define SCUXVOL6R_DVU0_2 SCUX.VOL6R_DVU0_2
mbed_official 119:3921aeca8633 727 #define SCUXVOL7R_DVU0_2 SCUX.VOL7R_DVU0_2
mbed_official 119:3921aeca8633 728 #define SCUXDVUER_DVU0_2 SCUX.DVUER_DVU0_2
mbed_official 119:3921aeca8633 729 #define SCUXDVUSR_DVU0_2 SCUX.DVUSR_DVU0_2
mbed_official 119:3921aeca8633 730 #define SCUXVEVMR_DVU0_2 SCUX.VEVMR_DVU0_2
mbed_official 119:3921aeca8633 731 #define SCUXVEVCR_DVU0_2 SCUX.VEVCR_DVU0_2
mbed_official 119:3921aeca8633 732 #define SCUXDVUIR_DVU0_3 SCUX.DVUIR_DVU0_3
mbed_official 119:3921aeca8633 733 #define SCUXVADIR_DVU0_3 SCUX.VADIR_DVU0_3
mbed_official 119:3921aeca8633 734 #define SCUXDVUBR_DVU0_3 SCUX.DVUBR_DVU0_3
mbed_official 119:3921aeca8633 735 #define SCUXDVUCR_DVU0_3 SCUX.DVUCR_DVU0_3
mbed_official 119:3921aeca8633 736 #define SCUXZCMCR_DVU0_3 SCUX.ZCMCR_DVU0_3
mbed_official 119:3921aeca8633 737 #define SCUXVRCTR_DVU0_3 SCUX.VRCTR_DVU0_3
mbed_official 119:3921aeca8633 738 #define SCUXVRPDR_DVU0_3 SCUX.VRPDR_DVU0_3
mbed_official 119:3921aeca8633 739 #define SCUXVRDBR_DVU0_3 SCUX.VRDBR_DVU0_3
mbed_official 119:3921aeca8633 740 #define SCUXVRWTR_DVU0_3 SCUX.VRWTR_DVU0_3
mbed_official 119:3921aeca8633 741 #define SCUXVOL0R_DVU0_3 SCUX.VOL0R_DVU0_3
mbed_official 119:3921aeca8633 742 #define SCUXVOL1R_DVU0_3 SCUX.VOL1R_DVU0_3
mbed_official 119:3921aeca8633 743 #define SCUXVOL2R_DVU0_3 SCUX.VOL2R_DVU0_3
mbed_official 119:3921aeca8633 744 #define SCUXVOL3R_DVU0_3 SCUX.VOL3R_DVU0_3
mbed_official 119:3921aeca8633 745 #define SCUXVOL4R_DVU0_3 SCUX.VOL4R_DVU0_3
mbed_official 119:3921aeca8633 746 #define SCUXVOL5R_DVU0_3 SCUX.VOL5R_DVU0_3
mbed_official 119:3921aeca8633 747 #define SCUXVOL6R_DVU0_3 SCUX.VOL6R_DVU0_3
mbed_official 119:3921aeca8633 748 #define SCUXVOL7R_DVU0_3 SCUX.VOL7R_DVU0_3
mbed_official 119:3921aeca8633 749 #define SCUXDVUER_DVU0_3 SCUX.DVUER_DVU0_3
mbed_official 119:3921aeca8633 750 #define SCUXDVUSR_DVU0_3 SCUX.DVUSR_DVU0_3
mbed_official 119:3921aeca8633 751 #define SCUXVEVMR_DVU0_3 SCUX.VEVMR_DVU0_3
mbed_official 119:3921aeca8633 752 #define SCUXVEVCR_DVU0_3 SCUX.VEVCR_DVU0_3
mbed_official 119:3921aeca8633 753 #define SCUXMIXIR_MIX0_0 SCUX.MIXIR_MIX0_0
mbed_official 119:3921aeca8633 754 #define SCUXMADIR_MIX0_0 SCUX.MADIR_MIX0_0
mbed_official 119:3921aeca8633 755 #define SCUXMIXBR_MIX0_0 SCUX.MIXBR_MIX0_0
mbed_official 119:3921aeca8633 756 #define SCUXMIXMR_MIX0_0 SCUX.MIXMR_MIX0_0
mbed_official 119:3921aeca8633 757 #define SCUXMVPDR_MIX0_0 SCUX.MVPDR_MIX0_0
mbed_official 119:3921aeca8633 758 #define SCUXMDBAR_MIX0_0 SCUX.MDBAR_MIX0_0
mbed_official 119:3921aeca8633 759 #define SCUXMDBBR_MIX0_0 SCUX.MDBBR_MIX0_0
mbed_official 119:3921aeca8633 760 #define SCUXMDBCR_MIX0_0 SCUX.MDBCR_MIX0_0
mbed_official 119:3921aeca8633 761 #define SCUXMDBDR_MIX0_0 SCUX.MDBDR_MIX0_0
mbed_official 119:3921aeca8633 762 #define SCUXMDBER_MIX0_0 SCUX.MDBER_MIX0_0
mbed_official 119:3921aeca8633 763 #define SCUXMIXSR_MIX0_0 SCUX.MIXSR_MIX0_0
mbed_official 119:3921aeca8633 764 #define SCUXSWRSR_CIM SCUX.SWRSR_CIM
mbed_official 119:3921aeca8633 765 #define SCUXDMACR_CIM SCUX.DMACR_CIM
mbed_official 119:3921aeca8633 766 #define SCUXDMATD0_CIM SCUX.DMATD0_CIM.UINT32
mbed_official 119:3921aeca8633 767 #define SCUXDMATD0_CIML SCUX.DMATD0_CIM.UINT16[L]
mbed_official 119:3921aeca8633 768 #define SCUXDMATD0_CIMH SCUX.DMATD0_CIM.UINT16[H]
mbed_official 119:3921aeca8633 769 #define SCUXDMATD1_CIM SCUX.DMATD1_CIM.UINT32
mbed_official 119:3921aeca8633 770 #define SCUXDMATD1_CIML SCUX.DMATD1_CIM.UINT16[L]
mbed_official 119:3921aeca8633 771 #define SCUXDMATD1_CIMH SCUX.DMATD1_CIM.UINT16[H]
mbed_official 119:3921aeca8633 772 #define SCUXDMATD2_CIM SCUX.DMATD2_CIM.UINT32
mbed_official 119:3921aeca8633 773 #define SCUXDMATD2_CIML SCUX.DMATD2_CIM.UINT16[L]
mbed_official 119:3921aeca8633 774 #define SCUXDMATD2_CIMH SCUX.DMATD2_CIM.UINT16[H]
mbed_official 119:3921aeca8633 775 #define SCUXDMATD3_CIM SCUX.DMATD3_CIM.UINT32
mbed_official 119:3921aeca8633 776 #define SCUXDMATD3_CIML SCUX.DMATD3_CIM.UINT16[L]
mbed_official 119:3921aeca8633 777 #define SCUXDMATD3_CIMH SCUX.DMATD3_CIM.UINT16[H]
mbed_official 119:3921aeca8633 778 #define SCUXDMATU0_CIM SCUX.DMATU0_CIM.UINT32
mbed_official 119:3921aeca8633 779 #define SCUXDMATU0_CIML SCUX.DMATU0_CIM.UINT16[L]
mbed_official 119:3921aeca8633 780 #define SCUXDMATU0_CIMH SCUX.DMATU0_CIM.UINT16[H]
mbed_official 119:3921aeca8633 781 #define SCUXDMATU1_CIM SCUX.DMATU1_CIM.UINT32
mbed_official 119:3921aeca8633 782 #define SCUXDMATU1_CIML SCUX.DMATU1_CIM.UINT16[L]
mbed_official 119:3921aeca8633 783 #define SCUXDMATU1_CIMH SCUX.DMATU1_CIM.UINT16[H]
mbed_official 119:3921aeca8633 784 #define SCUXDMATU2_CIM SCUX.DMATU2_CIM.UINT32
mbed_official 119:3921aeca8633 785 #define SCUXDMATU2_CIML SCUX.DMATU2_CIM.UINT16[L]
mbed_official 119:3921aeca8633 786 #define SCUXDMATU2_CIMH SCUX.DMATU2_CIM.UINT16[H]
mbed_official 119:3921aeca8633 787 #define SCUXDMATU3_CIM SCUX.DMATU3_CIM.UINT32
mbed_official 119:3921aeca8633 788 #define SCUXDMATU3_CIML SCUX.DMATU3_CIM.UINT16[L]
mbed_official 119:3921aeca8633 789 #define SCUXDMATU3_CIMH SCUX.DMATU3_CIM.UINT16[H]
mbed_official 119:3921aeca8633 790 #define SCUXSSIRSEL_CIM SCUX.SSIRSEL_CIM
mbed_official 119:3921aeca8633 791 #define SCUXFDTSEL0_CIM SCUX.FDTSEL0_CIM
mbed_official 119:3921aeca8633 792 #define SCUXFDTSEL1_CIM SCUX.FDTSEL1_CIM
mbed_official 119:3921aeca8633 793 #define SCUXFDTSEL2_CIM SCUX.FDTSEL2_CIM
mbed_official 119:3921aeca8633 794 #define SCUXFDTSEL3_CIM SCUX.FDTSEL3_CIM
mbed_official 119:3921aeca8633 795 #define SCUXFUTSEL0_CIM SCUX.FUTSEL0_CIM
mbed_official 119:3921aeca8633 796 #define SCUXFUTSEL1_CIM SCUX.FUTSEL1_CIM
mbed_official 119:3921aeca8633 797 #define SCUXFUTSEL2_CIM SCUX.FUTSEL2_CIM
mbed_official 119:3921aeca8633 798 #define SCUXFUTSEL3_CIM SCUX.FUTSEL3_CIM
mbed_official 119:3921aeca8633 799 #define SCUXSSIPMD_CIM SCUX.SSIPMD_CIM
mbed_official 119:3921aeca8633 800 #define SCUXSSICTRL_CIM SCUX.SSICTRL_CIM
mbed_official 119:3921aeca8633 801 #define SCUXSRCRSEL0_CIM SCUX.SRCRSEL0_CIM
mbed_official 119:3921aeca8633 802 #define SCUXSRCRSEL1_CIM SCUX.SRCRSEL1_CIM
mbed_official 119:3921aeca8633 803 #define SCUXSRCRSEL2_CIM SCUX.SRCRSEL2_CIM
mbed_official 119:3921aeca8633 804 #define SCUXSRCRSEL3_CIM SCUX.SRCRSEL3_CIM
mbed_official 119:3921aeca8633 805 #define SCUXMIXRSEL_CIM SCUX.MIXRSEL_CIM
mbed_official 119:3921aeca8633 806 /* <-SEC M1.10.1 */
mbed_official 119:3921aeca8633 807 /* <-QAC 0639 */
mbed_official 119:3921aeca8633 808 #endif