Tick Tock / Mbed 2 deprecated CANcan

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Dependencies:   SDHCFileSystem mbed

PowerControl/EthernetPowerControl.cpp@11:d97071bf877b, 2012-12-09 (annotated)

Committer:
TickTock
Date:
Sun Dec 09 22:40:03 2012 +0000
Revision:
11:d97071bf877b
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
TickTock 11:d97071bf877b 1 #include "EthernetPowerControl.h"
TickTock 11:d97071bf877b 2
TickTock 11:d97071bf877b 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
TickTock 11:d97071bf877b 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
TickTock 11:d97071bf877b 5 unsigned int tout;
TickTock 11:d97071bf877b 6 /* Hardware MII Management for LPC176x devices. */
TickTock 11:d97071bf877b 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
TickTock 11:d97071bf877b 8 LPC_EMAC->MWTD = Value;
TickTock 11:d97071bf877b 9
TickTock 11:d97071bf877b 10 /* Wait utill operation completed */
TickTock 11:d97071bf877b 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
TickTock 11:d97071bf877b 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
TickTock 11:d97071bf877b 13 break;
TickTock 11:d97071bf877b 14 }
TickTock 11:d97071bf877b 15 }
TickTock 11:d97071bf877b 16 }
TickTock 11:d97071bf877b 17
TickTock 11:d97071bf877b 18 static unsigned short read_PHY (unsigned int PhyReg) {
TickTock 11:d97071bf877b 19 /* Read a PHY register 'PhyReg'. */
TickTock 11:d97071bf877b 20 unsigned int tout, val;
TickTock 11:d97071bf877b 21
TickTock 11:d97071bf877b 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
TickTock 11:d97071bf877b 23 LPC_EMAC->MCMD = MCMD_READ;
TickTock 11:d97071bf877b 24
TickTock 11:d97071bf877b 25 /* Wait until operation completed */
TickTock 11:d97071bf877b 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
TickTock 11:d97071bf877b 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
TickTock 11:d97071bf877b 28 break;
TickTock 11:d97071bf877b 29 }
TickTock 11:d97071bf877b 30 }
TickTock 11:d97071bf877b 31 LPC_EMAC->MCMD = 0;
TickTock 11:d97071bf877b 32 val = LPC_EMAC->MRDD;
TickTock 11:d97071bf877b 33
TickTock 11:d97071bf877b 34 return (val);
TickTock 11:d97071bf877b 35 }
TickTock 11:d97071bf877b 36
TickTock 11:d97071bf877b 37 void EMAC_Init()
TickTock 11:d97071bf877b 38 {
TickTock 11:d97071bf877b 39 unsigned int tout,regv;
TickTock 11:d97071bf877b 40 /* Power Up the EMAC controller. */
TickTock 11:d97071bf877b 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
TickTock 11:d97071bf877b 42
TickTock 11:d97071bf877b 43 LPC_PINCON->PINSEL2 = 0x50150105;
TickTock 11:d97071bf877b 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
TickTock 11:d97071bf877b 45 LPC_PINCON->PINSEL3 |= 0x00000005;
TickTock 11:d97071bf877b 46
TickTock 11:d97071bf877b 47 /* Reset all EMAC internal modules. */
TickTock 11:d97071bf877b 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
TickTock 11:d97071bf877b 49 MAC1_SIM_RES | MAC1_SOFT_RES;
TickTock 11:d97071bf877b 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
TickTock 11:d97071bf877b 51
TickTock 11:d97071bf877b 52 /* A short delay after reset. */
TickTock 11:d97071bf877b 53 for (tout = 100; tout; tout--);
TickTock 11:d97071bf877b 54
TickTock 11:d97071bf877b 55 /* Initialize MAC control registers. */
TickTock 11:d97071bf877b 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
TickTock 11:d97071bf877b 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
TickTock 11:d97071bf877b 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
TickTock 11:d97071bf877b 59 LPC_EMAC->CLRT = CLRT_DEF;
TickTock 11:d97071bf877b 60 LPC_EMAC->IPGR = IPGR_DEF;
TickTock 11:d97071bf877b 61
TickTock 11:d97071bf877b 62 /* Enable Reduced MII interface. */
TickTock 11:d97071bf877b 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
TickTock 11:d97071bf877b 64
TickTock 11:d97071bf877b 65 /* Reset Reduced MII Logic. */
TickTock 11:d97071bf877b 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
TickTock 11:d97071bf877b 67 for (tout = 100; tout; tout--);
TickTock 11:d97071bf877b 68 LPC_EMAC->SUPP = 0;
TickTock 11:d97071bf877b 69
TickTock 11:d97071bf877b 70 /* Put the DP83848C in reset mode */
TickTock 11:d97071bf877b 71 write_PHY (PHY_REG_BMCR, 0x8000);
TickTock 11:d97071bf877b 72
TickTock 11:d97071bf877b 73 /* Wait for hardware reset to end. */
TickTock 11:d97071bf877b 74 for (tout = 0; tout < 0x100000; tout++) {
TickTock 11:d97071bf877b 75 regv = read_PHY (PHY_REG_BMCR);
TickTock 11:d97071bf877b 76 if (!(regv & 0x8000)) {
TickTock 11:d97071bf877b 77 /* Reset complete */
TickTock 11:d97071bf877b 78 break;
TickTock 11:d97071bf877b 79 }
TickTock 11:d97071bf877b 80 }
TickTock 11:d97071bf877b 81 }
TickTock 11:d97071bf877b 82
TickTock 11:d97071bf877b 83
TickTock 11:d97071bf877b 84 void PHY_PowerDown()
TickTock 11:d97071bf877b 85 {
TickTock 11:d97071bf877b 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
TickTock 11:d97071bf877b 87 EMAC_Init(); //init EMAC if it is not already init'd
TickTock 11:d97071bf877b 88
TickTock 11:d97071bf877b 89 unsigned int regv;
TickTock 11:d97071bf877b 90 regv = read_PHY(PHY_REG_BMCR);
TickTock 11:d97071bf877b 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
TickTock 11:d97071bf877b 92 regv = read_PHY(PHY_REG_BMCR);
TickTock 11:d97071bf877b 93
TickTock 11:d97071bf877b 94 //shouldn't need the EMAC now.
TickTock 11:d97071bf877b 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
TickTock 11:d97071bf877b 96
TickTock 11:d97071bf877b 97 //and turn off the PHY OSC
TickTock 11:d97071bf877b 98 LPC_GPIO1->FIODIR |= 0x8000000;
TickTock 11:d97071bf877b 99 LPC_GPIO1->FIOCLR = 0x8000000;
TickTock 11:d97071bf877b 100 }
TickTock 11:d97071bf877b 101
TickTock 11:d97071bf877b 102 void PHY_PowerUp()
TickTock 11:d97071bf877b 103 {
TickTock 11:d97071bf877b 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
TickTock 11:d97071bf877b 105 EMAC_Init(); //init EMAC if it is not already init'd
TickTock 11:d97071bf877b 106
TickTock 11:d97071bf877b 107 LPC_GPIO1->FIODIR |= 0x8000000;
TickTock 11:d97071bf877b 108 LPC_GPIO1->FIOSET = 0x8000000;
TickTock 11:d97071bf877b 109
TickTock 11:d97071bf877b 110 //wait for osc to be stable
TickTock 11:d97071bf877b 111 wait_ms(200);
TickTock 11:d97071bf877b 112
TickTock 11:d97071bf877b 113 unsigned int regv;
TickTock 11:d97071bf877b 114 regv = read_PHY(PHY_REG_BMCR);
TickTock 11:d97071bf877b 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
TickTock 11:d97071bf877b 116 regv = read_PHY(PHY_REG_BMCR);
TickTock 11:d97071bf877b 117 }
TickTock 11:d97071bf877b 118
TickTock 11:d97071bf877b 119 void PHY_EnergyDetect_Enable()
TickTock 11:d97071bf877b 120 {
TickTock 11:d97071bf877b 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
TickTock 11:d97071bf877b 122 EMAC_Init(); //init EMAC if it is not already init'd
TickTock 11:d97071bf877b 123
TickTock 11:d97071bf877b 124 unsigned int regv;
TickTock 11:d97071bf877b 125 regv = read_PHY(PHY_REG_EDCR);
TickTock 11:d97071bf877b 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
TickTock 11:d97071bf877b 127 regv = read_PHY(PHY_REG_EDCR);
TickTock 11:d97071bf877b 128 }
TickTock 11:d97071bf877b 129
TickTock 11:d97071bf877b 130 void PHY_EnergyDetect_Disable()
TickTock 11:d97071bf877b 131 {
TickTock 11:d97071bf877b 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
TickTock 11:d97071bf877b 133 EMAC_Init(); //init EMAC if it is not already init'd
TickTock 11:d97071bf877b 134 unsigned int regv;
TickTock 11:d97071bf877b 135 regv = read_PHY(PHY_REG_EDCR);
TickTock 11:d97071bf877b 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
TickTock 11:d97071bf877b 137 regv = read_PHY(PHY_REG_EDCR);
TickTock 11:d97071bf877b 138 }