Tom N / LidarSpi

This is a class which contains function to interface with the MLX75320

Dependents:   MLX75320_API

LidarSpi.h@0:dfe498e03679, 2016-02-25 (annotated)

Committer:
TNU
Date:
Thu Feb 25 08:02:11 2016 +0000
Revision:
0:dfe498e03679
Child:
3:9ed1d493c235
MLX75320 class

Who changed what in which revision?

UserRevisionLine numberNew contents of line
TNU 0:dfe498e03679 1 #ifndef LIDARSPI_H
TNU 0:dfe498e03679 2 #define LIDARSPI_H
TNU 0:dfe498e03679 3
TNU 0:dfe498e03679 4 #include "mbed.h"
TNU 0:dfe498e03679 5 #include "typeDef.h"
TNU 0:dfe498e03679 6 #include "FunctionPointer.h"
TNU 0:dfe498e03679 7
TNU 0:dfe498e03679 8
TNU 0:dfe498e03679 9 class LidarSpi
TNU 0:dfe498e03679 10 {
TNU 0:dfe498e03679 11 public:
TNU 0:dfe498e03679 12
TNU 0:dfe498e03679 13 // Type used to read/write register values. Here, it is 16 bits
TNU 0:dfe498e03679 14 typedef uint16_t REGTYPE;
TNU 0:dfe498e03679 15 typedef unsigned char uchar;
TNU 0:dfe498e03679 16
TNU 0:dfe498e03679 17 static const uint16_t CRC_SZ = 2; // Bytes in SPI CRC field
TNU 0:dfe498e03679 18 static const uint16_t SHORT_SZ = 8; // Bytes in short SPI packet
TNU 0:dfe498e03679 19 static const uint16_t LONG_SZ = 300; // Bytes in long SPI packet
TNU 0:dfe498e03679 20 static const uint16_t HDR_SZ = 2; // Bytes in SPI header field
TNU 0:dfe498e03679 21
TNU 0:dfe498e03679 22 static const uint16_t MAXCH = 16; // Number of channels
TNU 0:dfe498e03679 23 static const uint16_t MAXSET = 2; // Number of acquisition sets
TNU 0:dfe498e03679 24 static const uint16_t MAXPTCNT = 64; // Max number of base points
TNU 0:dfe498e03679 25 static const uint16_t MAXECH = 64 ; // Max echo count
TNU 0:dfe498e03679 26 static const uint16_t MAXACCLOG = 10; // Max accumulation log2
TNU 0:dfe498e03679 27 static const uint16_t MAXOVRLOG = 3; // Max oversampling log2
TNU 0:dfe498e03679 28 static const uint16_t MAXLED = 16; // Max LED power
TNU 0:dfe498e03679 29 static const uint16_t MAXACC = 1<<MAXACCLOG;
TNU 0:dfe498e03679 30 static const uint16_t MAXOVR = 1<<MAXOVRLOG;
TNU 0:dfe498e03679 31 static const uint16_t MAXTRCLEN = 74*8*MAXCH*2; // Max length of a trace in bytes (samples * MAXOVR * MAXCH * 2bytes)
TNU 0:dfe498e03679 32 static const uint16_t BYTES_PER_ECH = 24; // Nb of bytes per echo
TNU 0:dfe498e03679 33 static const uint16_t START_DELAY =10;
TNU 0:dfe498e03679 34
TNU 0:dfe498e03679 35 // Used on header ADDR field to request all channels and as idx argument of GetTrace function
TNU 0:dfe498e03679 36 static const uint16_t ADDR_ALLCH= 0x1F;
TNU 0:dfe498e03679 37
TNU 0:dfe498e03679 38 struct Echo
TNU 0:dfe498e03679 39 {
TNU 0:dfe498e03679 40 uint32_t mDistance;
TNU 0:dfe498e03679 41 uint32_t mAmplitude;
TNU 0:dfe498e03679 42 uint32_t mBase;
TNU 0:dfe498e03679 43 uint16_t mMaxIndex;
TNU 0:dfe498e03679 44 uint8_t mChannelIndex;
TNU 0:dfe498e03679 45 uint8_t mValid;
TNU 0:dfe498e03679 46 uint32_t mAmplitudeLowScale;
TNU 0:dfe498e03679 47 uint32_t mSaturationWidth;
TNU 0:dfe498e03679 48 };
TNU 0:dfe498e03679 49
TNU 0:dfe498e03679 50 /// \enum eASICREG
TNU 0:dfe498e03679 51 /// \brief Lists all registers. Enum value is directly the register address.
TNU 0:dfe498e03679 52 /// Naming convention: REG_ + <name> + <L/H> + <#>
TNU 0:dfe498e03679 53 /// <name> = name of register
TNU 0:dfe498e03679 54 /// <L/H> = optional low or high register part
TNU 0:dfe498e03679 55 /// <#> = optional number, either for acquisition source 0/1 or index
TNU 0:dfe498e03679 56 typedef enum
TNU 0:dfe498e03679 57 {
TNU 0:dfe498e03679 58 REG_MEACL = 0x00,
TNU 0:dfe498e03679 59 REG_MEACH,
TNU 0:dfe498e03679 60 REG_CONTROL,
TNU 0:dfe498e03679 61 REG_ACQCTL0,
TNU 0:dfe498e03679 62 REG_ACQCTL1,
TNU 0:dfe498e03679 63 REG_PTCNT,
TNU 0:dfe498e03679 64 REG_SCANCTL,
TNU 0:dfe498e03679 65 REG_TRIGCTL,
TNU 0:dfe498e03679 66 REG_DELAY,
TNU 0:dfe498e03679 67 REG_TMPSET,
TNU 0:dfe498e03679 68 REG_TMPSHUT,
TNU 0:dfe498e03679 69 REG_TMPIC,
TNU 0:dfe498e03679 70 REG_TMPSRC,
TNU 0:dfe498e03679 71 REG_GAIN0,
TNU 0:dfe498e03679 72 REG_GAIN1,
TNU 0:dfe498e03679 73 REG_GAIN2,
TNU 0:dfe498e03679 74 REG_GAIN3,
TNU 0:dfe498e03679 75 REG_CHANNEL,
TNU 0:dfe498e03679 76 REG_PWMPERIOD0,
TNU 0:dfe498e03679 77 REG_PWMPERIOD1,
TNU 0:dfe498e03679 78 REG_PWMCOUNT,
TNU 0:dfe498e03679 79 REG_PWMWIDTH0,
TNU 0:dfe498e03679 80 REG_PWMWIDTH1 = REG_PWMWIDTH0 + 8,
TNU 0:dfe498e03679 81 REG_FILTER0 = REG_PWMWIDTH1 + 8,
TNU 0:dfe498e03679 82 REG_FILTER1 = REG_FILTER0 + 16,
TNU 0:dfe498e03679 83 REG_THRNEARL0 = REG_FILTER1 + 16,
TNU 0:dfe498e03679 84 REG_THRNEARH0,
TNU 0:dfe498e03679 85 REG_THRMEDL0,
TNU 0:dfe498e03679 86 REG_THRMEDH0,
TNU 0:dfe498e03679 87 REG_THRFARL0,
TNU 0:dfe498e03679 88 REG_THRFARH0,
TNU 0:dfe498e03679 89 REG_THRNEARL1,
TNU 0:dfe498e03679 90 REG_THRNEARH1,
TNU 0:dfe498e03679 91 REG_THRMEDL1,
TNU 0:dfe498e03679 92 REG_THRMEDH1,
TNU 0:dfe498e03679 93 REG_THRFARL1,
TNU 0:dfe498e03679 94 REG_THRFARH1,
TNU 0:dfe498e03679 95 REG_NOISE0,
TNU 0:dfe498e03679 96 REG_NOISE1,
TNU 0:dfe498e03679 97 REG_OFFSETL0,
TNU 0:dfe498e03679 98 REG_OFFSETH0 = REG_OFFSETL0 + 16,
TNU 0:dfe498e03679 99 REG_OFFSETL1 = REG_OFFSETH0 + 16,
TNU 0:dfe498e03679 100 REG_OFFSETH1 = REG_OFFSETL1 + 16,
TNU 0:dfe498e03679 101 REG_SCALEL0 = REG_OFFSETH1 + 16,
TNU 0:dfe498e03679 102 REG_SCALEH0,
TNU 0:dfe498e03679 103 REG_SCALEL1,
TNU 0:dfe498e03679 104 REG_SCALEH1,
TNU 0:dfe498e03679 105 REG_FACTORY,
TNU 0:dfe498e03679 106 REG_ASIL,
TNU 0:dfe498e03679 107 REG_OTP0,
TNU 0:dfe498e03679 108 REG_OTP1,
TNU 0:dfe498e03679 109 REG_OTP2,
TNU 0:dfe498e03679 110 REG_OTP3,
TNU 0:dfe498e03679 111 REG_OTP4,
TNU 0:dfe498e03679 112 REG_OTP5,
TNU 0:dfe498e03679 113 REG_OTP6,
TNU 0:dfe498e03679 114 REG_OTP7,
TNU 0:dfe498e03679 115 REG_SOFTVER,
TNU 0:dfe498e03679 116 REG_ASICVER,
TNU 0:dfe498e03679 117 REG_WATCHDOGL,
TNU 0:dfe498e03679 118 REG_WATCHDOGH,
TNU 0:dfe498e03679 119 // Wai: Changed from REG_MAX
TNU 0:dfe498e03679 120 REG_MAX = 0xFFFF // Number of registers
TNU 0:dfe498e03679 121 } eASICREG;
TNU 0:dfe498e03679 122
TNU 0:dfe498e03679 123 enum PackType
TNU 0:dfe498e03679 124 {
TNU 0:dfe498e03679 125 PACK_RREG = 0, ///< Read register request
TNU 0:dfe498e03679 126 PACK_WREG, ///< Write register request
TNU 0:dfe498e03679 127 PACK_RFIRM, ///< Read firmware request
TNU 0:dfe498e03679 128 PACK_WFIRM, ///< Write firmware request
TNU 0:dfe498e03679 129 PACK_STATUS_S, ///< Status short
TNU 0:dfe498e03679 130 PACK_STATUS_L, ///< Status long
TNU 0:dfe498e03679 131 PACK_RDATA_RESP_S, ///< Read data response short
TNU 0:dfe498e03679 132 PACK_RDATA_RESP_L, ///< Read data response long
TNU 0:dfe498e03679 133 PACK_WDATA_L, ///< Write data long
TNU 0:dfe498e03679 134 };
TNU 0:dfe498e03679 135
TNU 0:dfe498e03679 136 enum StatusType
TNU 0:dfe498e03679 137 {
TNU 0:dfe498e03679 138 STAT_OK = 0,
TNU 0:dfe498e03679 139 STAT_BUSY,
TNU 0:dfe498e03679 140 STAT_CRC,
TNU 0:dfe498e03679 141 STAT_INVALID_REQ,
TNU 0:dfe498e03679 142 STAT_SEQ_NB,
TNU 0:dfe498e03679 143 STAT_TIMEOUT,
TNU 0:dfe498e03679 144 };
TNU 0:dfe498e03679 145
TNU 0:dfe498e03679 146 enum FirmType
TNU 0:dfe498e03679 147 {
TNU 0:dfe498e03679 148 FW_OTP = 0,
TNU 0:dfe498e03679 149 FW_PROCESSED,
TNU 0:dfe498e03679 150 FW_RAW,
TNU 0:dfe498e03679 151 FW_PATCH,
TNU 0:dfe498e03679 152 FW_PRELOAD,
TNU 0:dfe498e03679 153 FW_TEST,
TNU 0:dfe498e03679 154 };
TNU 0:dfe498e03679 155
TNU 0:dfe498e03679 156
TNU 0:dfe498e03679 157 LidarSpi(PinName mosi, PinName miso, PinName clk, PinName chipSelect, PinName dr, PinName rs, PinName tr);
TNU 0:dfe498e03679 158 int SpiSetting(long freq, int mode, Serial* pc);
TNU 0:dfe498e03679 159 int TxPacket(uint8_t* rData, uint16_t *rSz, uint8_t *tData, uint16_t tSz);
TNU 0:dfe498e03679 160 int TxPacketWord(uint8_t* rData, uint16_t *rSz, uint8_t *tData, uint16_t tSz);
TNU 0:dfe498e03679 161 int TxPacket(uint8_t* rData, uint16_t *rSz, uint8_t *tData, uint16_t tSz, Serial* pc);
TNU 0:dfe498e03679 162 int TxPacketSlow(uint8_t* rData, uint16_t *rSz, uint8_t *tData, uint16_t tSz, uint16_t usDelay);
TNU 0:dfe498e03679 163 int BasicRead();
TNU 0:dfe498e03679 164 int BasicTransfer(uint8_t* rData, uint16_t rSz, uint8_t *wData, uint16_t wSz, const event_callback_t callback);
TNU 0:dfe498e03679 165 int ReadReg ( uint32_t reg, uint32_t *val);
TNU 0:dfe498e03679 166 int ReadReg(uint32_t reg, uint32_t *val, Serial* pc);
TNU 0:dfe498e03679 167 int WriteReg ( uint32_t reg, uint32_t val);
TNU 0:dfe498e03679 168 int WriteRegSpeed ( uint32_t reg, uint32_t val, uint16_t usDelay);
TNU 0:dfe498e03679 169 int WriteReg ( uint32_t reg, uint32_t val, Serial* pc);
TNU 0:dfe498e03679 170 int WriteRegSpeed ( uint32_t reg, uint32_t val, uint16_t usDelay, Serial* pc);
TNU 0:dfe498e03679 171 //int GetRegNfo ( uint16_t reg, const RegInfo **nfo);
TNU 0:dfe498e03679 172 int GetEchoes ( Echo *ech, uint16_t maxN, uint16_t mode);
TNU 0:dfe498e03679 173 int GetEchoes ( Echo *ech, uint16_t maxN, uint16_t mode, Serial* pc);
TNU 0:dfe498e03679 174 int GetTrace ( uint16_t *buf, uint16_t maxN, uint16_t nSam, uint16_t idx, Serial* pc);
TNU 0:dfe498e03679 175 int GetTraceOne ( uint16_t *buf, uint16_t maxN, uint16_t nSam, uint16_t idx,int index , Serial* pc);
TNU 0:dfe498e03679 176 int LoadPatch ( uint16_t address, uint8_t *buf, uint16_t nBytes);
TNU 0:dfe498e03679 177 int PrintAllReg (uint16_t * regs, uint32_t * val, uint16_t size);
TNU 0:dfe498e03679 178
TNU 0:dfe498e03679 179 void Trigger(int level);
TNU 0:dfe498e03679 180 //int SetConfig ( int configNum);
TNU 0:dfe498e03679 181 //int SetAcqCfg ( uint16_t set, uint16_t led, uint16_t accLog, uint16_t ovrLog);
TNU 0:dfe498e03679 182 //int Acquire ( uchar ab, uchar evGain, uchar evCh, uchar odGain, uchar odCh);
TNU 0:dfe498e03679 183 //int GetFrame ( uint16_t *buf, uint16_t maxN, uint16_t nSam, uint16_t nFrm);
TNU 0:dfe498e03679 184
TNU 0:dfe498e03679 185
TNU 0:dfe498e03679 186
TNU 0:dfe498e03679 187
TNU 0:dfe498e03679 188 private:
TNU 0:dfe498e03679 189 SPI device;
TNU 0:dfe498e03679 190 DigitalOut chipS;
TNU 0:dfe498e03679 191 DigitalIn dataReady;
TNU 0:dfe498e03679 192 DigitalIn resetPin;
TNU 0:dfe498e03679 193 DigitalOut trigger;
TNU 0:dfe498e03679 194
TNU 0:dfe498e03679 195
TNU 0:dfe498e03679 196
TNU 0:dfe498e03679 197
TNU 0:dfe498e03679 198 };
TNU 0:dfe498e03679 199
TNU 0:dfe498e03679 200
TNU 0:dfe498e03679 201
TNU 0:dfe498e03679 202
TNU 0:dfe498e03679 203 #endif