test
Dependents: Telemetria_RX_SD_GPS_copy Telemetria_RX_SD_GPS Telemetria_TX Telemetria_TX ... more
sx1276/sx1276-hal.cpp@28:6d83af9f8563, 2017-04-25 (annotated)
- Committer:
- Helmut Tschemernjak
- Date:
- Tue Apr 25 21:02:48 2017 +0200
- Revision:
- 28:6d83af9f8563
- Parent:
- 26:87796ee62589
- Child:
- 30:d7e36d83ec9d
Fixed MURATA spelling
Added proper support of the RFM95 module detection
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
GregCr | 0:e6ceb13d2d05 | 1 | /* |
GregCr | 0:e6ceb13d2d05 | 2 | / _____) _ | | |
GregCr | 0:e6ceb13d2d05 | 3 | ( (____ _____ ____ _| |_ _____ ____| |__ |
GregCr | 0:e6ceb13d2d05 | 4 | \____ \| ___ | (_ _) ___ |/ ___) _ \ |
GregCr | 0:e6ceb13d2d05 | 5 | _____) ) ____| | | || |_| ____( (___| | | | |
GregCr | 0:e6ceb13d2d05 | 6 | (______/|_____)_|_|_| \__)_____)\____)_| |_| |
mluis | 22:7f3aab69cca9 | 7 | (C) 2014 Semtech |
GregCr | 0:e6ceb13d2d05 | 8 | |
GregCr | 0:e6ceb13d2d05 | 9 | Description: - |
GregCr | 0:e6ceb13d2d05 | 10 | |
GregCr | 0:e6ceb13d2d05 | 11 | License: Revised BSD License, see LICENSE.TXT file include in the project |
GregCr | 0:e6ceb13d2d05 | 12 | |
GregCr | 0:e6ceb13d2d05 | 13 | Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin |
GregCr | 0:e6ceb13d2d05 | 14 | */ |
GregCr | 0:e6ceb13d2d05 | 15 | #include "sx1276-hal.h" |
GregCr | 0:e6ceb13d2d05 | 16 | |
mluis | 22:7f3aab69cca9 | 17 | const RadioRegisters_t SX1276MB1xAS::RadioRegsInit[] = RADIO_INIT_REGISTERS_VALUE; |
GregCr | 0:e6ceb13d2d05 | 18 | |
mluis | 21:2e496deb7858 | 19 | SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events, |
GregCr | 0:e6ceb13d2d05 | 20 | PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset, |
GregCr | 0:e6ceb13d2d05 | 21 | PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5, |
Helmut Tschemernjak | 28:6d83af9f8563 | 22 | #ifdef MURATA_ANT_SWITCH |
Helmut64 | 26:87796ee62589 | 23 | PinName antSwitch, PinName antSwitchTX, PinName antSwitchTXBoost ) |
Helmut64 | 26:87796ee62589 | 24 | #else |
GregCr | 0:e6ceb13d2d05 | 25 | PinName antSwitch ) |
Helmut64 | 26:87796ee62589 | 26 | #endif |
mluis | 21:2e496deb7858 | 27 | : SX1276( events, mosi, miso, sclk, nss, reset, dio0, dio1, dio2, dio3, dio4, dio5 ), |
Helmut Tschemernjak | 28:6d83af9f8563 | 28 | #ifdef MURATA_ANT_SWITCH |
Helmut64 | 26:87796ee62589 | 29 | antSwitch(antSwitch), antSwitchTX(antSwitchTX), antSwitchTXBoost(antSwitchTXBoost), |
Helmut64 | 26:87796ee62589 | 30 | #else |
GregCr | 0:e6ceb13d2d05 | 31 | antSwitch( antSwitch ), |
Helmut64 | 26:87796ee62589 | 32 | #endif |
Helmut64 | 26:87796ee62589 | 33 | #if( defined ( TARGET_NUCLEO_L152RE ) ) |
mluis | 25:3778e6204cc1 | 34 | fake( D8 ) |
Helmut64 | 26:87796ee62589 | 35 | #else |
GregCr | 0:e6ceb13d2d05 | 36 | fake( A3 ) |
Helmut64 | 26:87796ee62589 | 37 | #endif |
GregCr | 0:e6ceb13d2d05 | 38 | { |
mluis | 21:2e496deb7858 | 39 | this->RadioEvents = events; |
mluis | 21:2e496deb7858 | 40 | |
GregCr | 0:e6ceb13d2d05 | 41 | Reset( ); |
mluis | 25:3778e6204cc1 | 42 | |
GregCr | 0:e6ceb13d2d05 | 43 | RxChainCalibration( ); |
mluis | 25:3778e6204cc1 | 44 | |
GregCr | 0:e6ceb13d2d05 | 45 | IoInit( ); |
mluis | 25:3778e6204cc1 | 46 | |
GregCr | 0:e6ceb13d2d05 | 47 | SetOpMode( RF_OPMODE_SLEEP ); |
mluis | 25:3778e6204cc1 | 48 | |
GregCr | 0:e6ceb13d2d05 | 49 | IoIrqInit( dioIrq ); |
mluis | 25:3778e6204cc1 | 50 | |
GregCr | 0:e6ceb13d2d05 | 51 | RadioRegistersInit( ); |
GregCr | 0:e6ceb13d2d05 | 52 | |
GregCr | 0:e6ceb13d2d05 | 53 | SetModem( MODEM_FSK ); |
GregCr | 0:e6ceb13d2d05 | 54 | |
mluis | 21:2e496deb7858 | 55 | this->settings.State = RF_IDLE ; |
GregCr | 0:e6ceb13d2d05 | 56 | } |
GregCr | 0:e6ceb13d2d05 | 57 | |
mluis | 25:3778e6204cc1 | 58 | SX1276MB1xAS::SX1276MB1xAS( RadioEvents_t *events ) |
GregCr | 12:aa5b3bf7fdf4 | 59 | #if defined ( TARGET_NUCLEO_L152RE ) |
mluis | 21:2e496deb7858 | 60 | : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, A3, D9 ), // For NUCLEO L152RE dio4 is on port A3 |
GregCr | 0:e6ceb13d2d05 | 61 | antSwitch( A4 ), |
GregCr | 0:e6ceb13d2d05 | 62 | fake( D8 ) |
mluis | 20:e05596ba4166 | 63 | #elif defined( TARGET_LPC11U6X ) |
mluis | 21:2e496deb7858 | 64 | : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ), |
mluis | 20:e05596ba4166 | 65 | antSwitch( P0_23 ), |
mluis | 20:e05596ba4166 | 66 | fake( A3 ) |
GregCr | 0:e6ceb13d2d05 | 67 | #else |
mluis | 21:2e496deb7858 | 68 | : SX1276( events, D11, D12, D13, D10, A0, D2, D3, D4, D5, D8, D9 ), |
Helmut Tschemernjak | 28:6d83af9f8563 | 69 | #ifdef MURATA_ANT_SWITCH |
Helmut64 | 26:87796ee62589 | 70 | antSwitch(A4), antSwitchTX(NC), antSwitchTXBoost(NC), |
Helmut64 | 26:87796ee62589 | 71 | #else |
GregCr | 12:aa5b3bf7fdf4 | 72 | antSwitch( A4 ), |
Helmut64 | 26:87796ee62589 | 73 | #endif |
GregCr | 12:aa5b3bf7fdf4 | 74 | fake( A3 ) |
GregCr | 0:e6ceb13d2d05 | 75 | #endif |
GregCr | 0:e6ceb13d2d05 | 76 | { |
mluis | 21:2e496deb7858 | 77 | this->RadioEvents = events; |
mluis | 21:2e496deb7858 | 78 | |
GregCr | 0:e6ceb13d2d05 | 79 | Reset( ); |
mluis | 25:3778e6204cc1 | 80 | |
GregCr | 5:11ec8a6ba4f0 | 81 | boardConnected = UNKNOWN; |
mluis | 25:3778e6204cc1 | 82 | |
GregCr | 1:f979673946c0 | 83 | DetectBoardType( ); |
mluis | 25:3778e6204cc1 | 84 | |
GregCr | 0:e6ceb13d2d05 | 85 | RxChainCalibration( ); |
mluis | 25:3778e6204cc1 | 86 | |
GregCr | 0:e6ceb13d2d05 | 87 | IoInit( ); |
mluis | 25:3778e6204cc1 | 88 | |
GregCr | 0:e6ceb13d2d05 | 89 | SetOpMode( RF_OPMODE_SLEEP ); |
GregCr | 0:e6ceb13d2d05 | 90 | IoIrqInit( dioIrq ); |
mluis | 25:3778e6204cc1 | 91 | |
GregCr | 0:e6ceb13d2d05 | 92 | RadioRegistersInit( ); |
GregCr | 0:e6ceb13d2d05 | 93 | |
GregCr | 0:e6ceb13d2d05 | 94 | SetModem( MODEM_FSK ); |
GregCr | 0:e6ceb13d2d05 | 95 | |
mluis | 21:2e496deb7858 | 96 | this->settings.State = RF_IDLE ; |
GregCr | 0:e6ceb13d2d05 | 97 | } |
GregCr | 0:e6ceb13d2d05 | 98 | |
GregCr | 0:e6ceb13d2d05 | 99 | //------------------------------------------------------------------------- |
GregCr | 0:e6ceb13d2d05 | 100 | // Board relative functions |
GregCr | 0:e6ceb13d2d05 | 101 | //------------------------------------------------------------------------- |
GregCr | 2:5eb3066446dd | 102 | uint8_t SX1276MB1xAS::DetectBoardType( void ) |
GregCr | 1:f979673946c0 | 103 | { |
GregCr | 5:11ec8a6ba4f0 | 104 | if( boardConnected == UNKNOWN ) |
GregCr | 1:f979673946c0 | 105 | { |
GregCr | 5:11ec8a6ba4f0 | 106 | antSwitch.input( ); |
GregCr | 5:11ec8a6ba4f0 | 107 | wait_ms( 1 ); |
GregCr | 5:11ec8a6ba4f0 | 108 | if( antSwitch == 1 ) |
GregCr | 5:11ec8a6ba4f0 | 109 | { |
GregCr | 5:11ec8a6ba4f0 | 110 | boardConnected = SX1276MB1LAS; |
GregCr | 5:11ec8a6ba4f0 | 111 | } |
GregCr | 5:11ec8a6ba4f0 | 112 | else |
GregCr | 5:11ec8a6ba4f0 | 113 | { |
GregCr | 5:11ec8a6ba4f0 | 114 | boardConnected = SX1276MB1MAS; |
GregCr | 5:11ec8a6ba4f0 | 115 | } |
GregCr | 5:11ec8a6ba4f0 | 116 | antSwitch.output( ); |
GregCr | 5:11ec8a6ba4f0 | 117 | wait_ms( 1 ); |
GregCr | 1:f979673946c0 | 118 | } |
Helmut Tschemernjak | 28:6d83af9f8563 | 119 | #ifdef RFM95_MODULE |
Helmut Tschemernjak | 28:6d83af9f8563 | 120 | boardConnected = SX1276MB1LAS; |
Helmut Tschemernjak | 28:6d83af9f8563 | 121 | #endif |
GregCr | 2:5eb3066446dd | 122 | return ( boardConnected ); |
GregCr | 1:f979673946c0 | 123 | } |
GregCr | 0:e6ceb13d2d05 | 124 | |
GregCr | 0:e6ceb13d2d05 | 125 | void SX1276MB1xAS::IoInit( void ) |
GregCr | 0:e6ceb13d2d05 | 126 | { |
GregCr | 0:e6ceb13d2d05 | 127 | AntSwInit( ); |
GregCr | 0:e6ceb13d2d05 | 128 | SpiInit( ); |
GregCr | 0:e6ceb13d2d05 | 129 | } |
GregCr | 0:e6ceb13d2d05 | 130 | |
mluis | 22:7f3aab69cca9 | 131 | void SX1276MB1xAS::RadioRegistersInit( ) |
mluis | 22:7f3aab69cca9 | 132 | { |
GregCr | 0:e6ceb13d2d05 | 133 | uint8_t i = 0; |
GregCr | 0:e6ceb13d2d05 | 134 | for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters_t ); i++ ) |
GregCr | 0:e6ceb13d2d05 | 135 | { |
GregCr | 0:e6ceb13d2d05 | 136 | SetModem( RadioRegsInit[i].Modem ); |
GregCr | 0:e6ceb13d2d05 | 137 | Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value ); |
GregCr | 0:e6ceb13d2d05 | 138 | } |
GregCr | 0:e6ceb13d2d05 | 139 | } |
GregCr | 0:e6ceb13d2d05 | 140 | |
GregCr | 0:e6ceb13d2d05 | 141 | void SX1276MB1xAS::SpiInit( void ) |
GregCr | 0:e6ceb13d2d05 | 142 | { |
GregCr | 0:e6ceb13d2d05 | 143 | nss = 1; |
GregCr | 0:e6ceb13d2d05 | 144 | spi.format( 8,0 ); |
GregCr | 0:e6ceb13d2d05 | 145 | uint32_t frequencyToSet = 8000000; |
Helmut64 | 26:87796ee62589 | 146 | #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) || defined(TARGET_STM) ) |
GregCr | 0:e6ceb13d2d05 | 147 | spi.frequency( frequencyToSet ); |
GregCr | 0:e6ceb13d2d05 | 148 | #elif( defined ( TARGET_KL25Z ) ) //busclock frequency is halved -> double the spi frequency to compensate |
GregCr | 0:e6ceb13d2d05 | 149 | spi.frequency( frequencyToSet * 2 ); |
GregCr | 0:e6ceb13d2d05 | 150 | #else |
GregCr | 0:e6ceb13d2d05 | 151 | #warning "Check the board's SPI frequency" |
GregCr | 0:e6ceb13d2d05 | 152 | #endif |
GregCr | 0:e6ceb13d2d05 | 153 | wait(0.1); |
GregCr | 0:e6ceb13d2d05 | 154 | } |
GregCr | 0:e6ceb13d2d05 | 155 | |
GregCr | 0:e6ceb13d2d05 | 156 | void SX1276MB1xAS::IoIrqInit( DioIrqHandler *irqHandlers ) |
GregCr | 0:e6ceb13d2d05 | 157 | { |
mluis | 25:3778e6204cc1 | 158 | #if( defined ( TARGET_NUCLEO_L152RE ) || defined ( TARGET_LPC11U6X ) ) |
mluis | 25:3778e6204cc1 | 159 | dio0.mode( PullDown ); |
mluis | 25:3778e6204cc1 | 160 | dio1.mode( PullDown ); |
mluis | 25:3778e6204cc1 | 161 | dio2.mode( PullDown ); |
mluis | 25:3778e6204cc1 | 162 | dio3.mode( PullDown ); |
mluis | 25:3778e6204cc1 | 163 | dio4.mode( PullDown ); |
mluis | 22:7f3aab69cca9 | 164 | #endif |
GregCr | 0:e6ceb13d2d05 | 165 | dio0.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[0] ) ); |
GregCr | 0:e6ceb13d2d05 | 166 | dio1.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[1] ) ); |
GregCr | 0:e6ceb13d2d05 | 167 | dio2.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[2] ) ); |
GregCr | 0:e6ceb13d2d05 | 168 | dio3.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[3] ) ); |
GregCr | 0:e6ceb13d2d05 | 169 | dio4.rise( this, static_cast< TriggerMB1xAS > ( irqHandlers[4] ) ); |
GregCr | 0:e6ceb13d2d05 | 170 | } |
GregCr | 0:e6ceb13d2d05 | 171 | |
GregCr | 0:e6ceb13d2d05 | 172 | void SX1276MB1xAS::IoDeInit( void ) |
GregCr | 0:e6ceb13d2d05 | 173 | { |
GregCr | 0:e6ceb13d2d05 | 174 | //nothing |
GregCr | 0:e6ceb13d2d05 | 175 | } |
GregCr | 0:e6ceb13d2d05 | 176 | |
GregCr | 0:e6ceb13d2d05 | 177 | uint8_t SX1276MB1xAS::GetPaSelect( uint32_t channel ) |
GregCr | 0:e6ceb13d2d05 | 178 | { |
GregCr | 0:e6ceb13d2d05 | 179 | if( channel > RF_MID_BAND_THRESH ) |
GregCr | 0:e6ceb13d2d05 | 180 | { |
GregCr | 3:ca84be1f3fac | 181 | if( boardConnected == SX1276MB1LAS ) |
GregCr | 1:f979673946c0 | 182 | { |
GregCr | 1:f979673946c0 | 183 | return RF_PACONFIG_PASELECT_PABOOST; |
GregCr | 1:f979673946c0 | 184 | } |
GregCr | 1:f979673946c0 | 185 | else |
GregCr | 1:f979673946c0 | 186 | { |
GregCr | 1:f979673946c0 | 187 | return RF_PACONFIG_PASELECT_RFO; |
GregCr | 1:f979673946c0 | 188 | } |
GregCr | 0:e6ceb13d2d05 | 189 | } |
GregCr | 0:e6ceb13d2d05 | 190 | else |
GregCr | 0:e6ceb13d2d05 | 191 | { |
GregCr | 0:e6ceb13d2d05 | 192 | return RF_PACONFIG_PASELECT_RFO; |
GregCr | 0:e6ceb13d2d05 | 193 | } |
GregCr | 0:e6ceb13d2d05 | 194 | } |
GregCr | 0:e6ceb13d2d05 | 195 | |
GregCr | 0:e6ceb13d2d05 | 196 | void SX1276MB1xAS::SetAntSwLowPower( bool status ) |
GregCr | 0:e6ceb13d2d05 | 197 | { |
GregCr | 0:e6ceb13d2d05 | 198 | if( isRadioActive != status ) |
GregCr | 0:e6ceb13d2d05 | 199 | { |
GregCr | 0:e6ceb13d2d05 | 200 | isRadioActive = status; |
GregCr | 0:e6ceb13d2d05 | 201 | |
GregCr | 0:e6ceb13d2d05 | 202 | if( status == false ) |
GregCr | 0:e6ceb13d2d05 | 203 | { |
GregCr | 0:e6ceb13d2d05 | 204 | AntSwInit( ); |
GregCr | 0:e6ceb13d2d05 | 205 | } |
GregCr | 0:e6ceb13d2d05 | 206 | else |
GregCr | 0:e6ceb13d2d05 | 207 | { |
GregCr | 0:e6ceb13d2d05 | 208 | AntSwDeInit( ); |
GregCr | 0:e6ceb13d2d05 | 209 | } |
GregCr | 0:e6ceb13d2d05 | 210 | } |
GregCr | 0:e6ceb13d2d05 | 211 | } |
GregCr | 0:e6ceb13d2d05 | 212 | |
GregCr | 0:e6ceb13d2d05 | 213 | void SX1276MB1xAS::AntSwInit( void ) |
GregCr | 0:e6ceb13d2d05 | 214 | { |
GregCr | 0:e6ceb13d2d05 | 215 | antSwitch = 0; |
Helmut Tschemernjak | 28:6d83af9f8563 | 216 | #ifdef MURATA_ANT_SWITCH |
Helmut64 | 26:87796ee62589 | 217 | antSwitchTX = 0; |
Helmut64 | 26:87796ee62589 | 218 | antSwitchTXBoost = 0; |
Helmut64 | 26:87796ee62589 | 219 | #endif |
GregCr | 0:e6ceb13d2d05 | 220 | } |
GregCr | 0:e6ceb13d2d05 | 221 | |
GregCr | 0:e6ceb13d2d05 | 222 | void SX1276MB1xAS::AntSwDeInit( void ) |
GregCr | 0:e6ceb13d2d05 | 223 | { |
GregCr | 0:e6ceb13d2d05 | 224 | antSwitch = 0; |
Helmut Tschemernjak | 28:6d83af9f8563 | 225 | #ifdef MURATA_ANT_SWITCH |
Helmut64 | 26:87796ee62589 | 226 | antSwitchTX = 0; |
Helmut64 | 26:87796ee62589 | 227 | antSwitchTXBoost = 0; |
Helmut64 | 26:87796ee62589 | 228 | #endif |
GregCr | 0:e6ceb13d2d05 | 229 | } |
GregCr | 0:e6ceb13d2d05 | 230 | |
GregCr | 0:e6ceb13d2d05 | 231 | void SX1276MB1xAS::SetAntSw( uint8_t rxTx ) |
GregCr | 0:e6ceb13d2d05 | 232 | { |
GregCr | 0:e6ceb13d2d05 | 233 | |
GregCr | 0:e6ceb13d2d05 | 234 | this->rxTx = rxTx; |
GregCr | 0:e6ceb13d2d05 | 235 | |
mluis | 25:3778e6204cc1 | 236 | // 1: Tx, 0: Rx |
GregCr | 0:e6ceb13d2d05 | 237 | if( rxTx != 0 ) |
GregCr | 0:e6ceb13d2d05 | 238 | { |
Helmut Tschemernjak | 28:6d83af9f8563 | 239 | #ifdef MURATA_ANT_SWITCH |
Helmut64 | 26:87796ee62589 | 240 | antSwitch = 0; // RX |
Helmut64 | 26:87796ee62589 | 241 | antSwitchTX = 1; // alternate: antSwitchTXBoost = 1 |
Helmut64 | 26:87796ee62589 | 242 | #else |
GregCr | 0:e6ceb13d2d05 | 243 | antSwitch = 1; |
Helmut64 | 26:87796ee62589 | 244 | #endif |
Helmut64 | 26:87796ee62589 | 245 | } else { |
Helmut Tschemernjak | 28:6d83af9f8563 | 246 | #ifdef MURATA_ANT_SWITCH |
Helmut64 | 26:87796ee62589 | 247 | antSwitch = 1; // RX |
Helmut64 | 26:87796ee62589 | 248 | antSwitchTX = 0; |
Helmut64 | 26:87796ee62589 | 249 | antSwitchTXBoost = 0; |
Helmut64 | 26:87796ee62589 | 250 | #else |
GregCr | 0:e6ceb13d2d05 | 251 | antSwitch = 0; |
Helmut64 | 26:87796ee62589 | 252 | #endif |
GregCr | 0:e6ceb13d2d05 | 253 | } |
GregCr | 0:e6ceb13d2d05 | 254 | } |
GregCr | 0:e6ceb13d2d05 | 255 | |
GregCr | 0:e6ceb13d2d05 | 256 | bool SX1276MB1xAS::CheckRfFrequency( uint32_t frequency ) |
GregCr | 0:e6ceb13d2d05 | 257 | { |
GregCr | 0:e6ceb13d2d05 | 258 | //TODO: Implement check, currently all frequencies are supported |
GregCr | 0:e6ceb13d2d05 | 259 | return true; |
GregCr | 0:e6ceb13d2d05 | 260 | } |
GregCr | 0:e6ceb13d2d05 | 261 | |
GregCr | 0:e6ceb13d2d05 | 262 | |
GregCr | 0:e6ceb13d2d05 | 263 | void SX1276MB1xAS::Reset( void ) |
GregCr | 0:e6ceb13d2d05 | 264 | { |
GregCr | 4:f0ce52e94d3f | 265 | reset.output(); |
GregCr | 0:e6ceb13d2d05 | 266 | reset = 0; |
GregCr | 0:e6ceb13d2d05 | 267 | wait_ms( 1 ); |
GregCr | 4:f0ce52e94d3f | 268 | reset.input(); |
GregCr | 0:e6ceb13d2d05 | 269 | wait_ms( 6 ); |
GregCr | 0:e6ceb13d2d05 | 270 | } |
GregCr | 0:e6ceb13d2d05 | 271 | |
GregCr | 0:e6ceb13d2d05 | 272 | void SX1276MB1xAS::Write( uint8_t addr, uint8_t data ) |
GregCr | 0:e6ceb13d2d05 | 273 | { |
GregCr | 0:e6ceb13d2d05 | 274 | Write( addr, &data, 1 ); |
GregCr | 0:e6ceb13d2d05 | 275 | } |
GregCr | 0:e6ceb13d2d05 | 276 | |
GregCr | 0:e6ceb13d2d05 | 277 | uint8_t SX1276MB1xAS::Read( uint8_t addr ) |
GregCr | 0:e6ceb13d2d05 | 278 | { |
GregCr | 0:e6ceb13d2d05 | 279 | uint8_t data; |
GregCr | 0:e6ceb13d2d05 | 280 | Read( addr, &data, 1 ); |
GregCr | 0:e6ceb13d2d05 | 281 | return data; |
GregCr | 0:e6ceb13d2d05 | 282 | } |
GregCr | 0:e6ceb13d2d05 | 283 | |
GregCr | 0:e6ceb13d2d05 | 284 | void SX1276MB1xAS::Write( uint8_t addr, uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 285 | { |
GregCr | 0:e6ceb13d2d05 | 286 | uint8_t i; |
GregCr | 0:e6ceb13d2d05 | 287 | |
GregCr | 0:e6ceb13d2d05 | 288 | nss = 0; |
GregCr | 0:e6ceb13d2d05 | 289 | spi.write( addr | 0x80 ); |
GregCr | 0:e6ceb13d2d05 | 290 | for( i = 0; i < size; i++ ) |
GregCr | 0:e6ceb13d2d05 | 291 | { |
GregCr | 0:e6ceb13d2d05 | 292 | spi.write( buffer[i] ); |
GregCr | 0:e6ceb13d2d05 | 293 | } |
GregCr | 0:e6ceb13d2d05 | 294 | nss = 1; |
GregCr | 0:e6ceb13d2d05 | 295 | } |
GregCr | 0:e6ceb13d2d05 | 296 | |
GregCr | 0:e6ceb13d2d05 | 297 | void SX1276MB1xAS::Read( uint8_t addr, uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 298 | { |
GregCr | 0:e6ceb13d2d05 | 299 | uint8_t i; |
GregCr | 0:e6ceb13d2d05 | 300 | |
GregCr | 0:e6ceb13d2d05 | 301 | nss = 0; |
GregCr | 0:e6ceb13d2d05 | 302 | spi.write( addr & 0x7F ); |
GregCr | 0:e6ceb13d2d05 | 303 | for( i = 0; i < size; i++ ) |
GregCr | 0:e6ceb13d2d05 | 304 | { |
GregCr | 0:e6ceb13d2d05 | 305 | buffer[i] = spi.write( 0 ); |
GregCr | 0:e6ceb13d2d05 | 306 | } |
GregCr | 0:e6ceb13d2d05 | 307 | nss = 1; |
GregCr | 0:e6ceb13d2d05 | 308 | } |
GregCr | 0:e6ceb13d2d05 | 309 | |
GregCr | 0:e6ceb13d2d05 | 310 | void SX1276MB1xAS::WriteFifo( uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 311 | { |
GregCr | 0:e6ceb13d2d05 | 312 | Write( 0, buffer, size ); |
GregCr | 0:e6ceb13d2d05 | 313 | } |
GregCr | 0:e6ceb13d2d05 | 314 | |
GregCr | 0:e6ceb13d2d05 | 315 | void SX1276MB1xAS::ReadFifo( uint8_t *buffer, uint8_t size ) |
GregCr | 0:e6ceb13d2d05 | 316 | { |
GregCr | 0:e6ceb13d2d05 | 317 | Read( 0, buffer, size ); |
GregCr | 0:e6ceb13d2d05 | 318 | } |