tetsuya noguchi / Mbed 2 deprecated ov7670_CQ

CQ出版 Interface記事用サンプル。 トラ技カメラ+FIFOからデータを得て、 エリア判定後、デバイスに保存

Dependencies:   SDFileSystem mbed

ov7670reg.h@4:ed062dc75c52, 2014-02-04 (annotated)

Committer:
TETSUYA
Date:
Tue Feb 04 05:42:17 2014 +0000
Revision:
4:ed062dc75c52
Parent:
0:1648bb4e70e5 
???????

Who changed what in which revision?

UserRevisionLine numberNew contents of line
TETSUYA 0:1648bb4e70e5 1 // size register
TETSUYA 0:1648bb4e70e5 2 #define REG_COM7 0x12 /* Control 7 */
TETSUYA 0:1648bb4e70e5 3 #define REG_HSTART 0x17 /* Horiz start high bits */
TETSUYA 0:1648bb4e70e5 4 #define REG_HSTOP 0x18 /* Horiz stop high bits */
TETSUYA 0:1648bb4e70e5 5 #define REG_HREF 0x32 /* HREF pieces */
TETSUYA 0:1648bb4e70e5 6 #define REG_VSTART 0x19 /* Vert start high bits */
TETSUYA 0:1648bb4e70e5 7 #define REG_VSTOP 0x1a /* Vert stop high bits */
TETSUYA 0:1648bb4e70e5 8 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
TETSUYA 0:1648bb4e70e5 9 #define REG_COM3 0x0c /* Control 3 */
TETSUYA 0:1648bb4e70e5 10 #define REG_COM14 0x3e /* Control 14 */
TETSUYA 0:1648bb4e70e5 11 #define REG_SCALING_XSC 0x70
TETSUYA 0:1648bb4e70e5 12 #define REG_SCALING_YSC 0x71
TETSUYA 0:1648bb4e70e5 13 #define REG_SCALING_DCWCTR 0x72
TETSUYA 0:1648bb4e70e5 14 #define REG_SCALING_PCLK_DIV 0x73
TETSUYA 0:1648bb4e70e5 15 #define REG_SCALING_PCLK_DELAY 0xa2
TETSUYA 0:1648bb4e70e5 16
TETSUYA 0:1648bb4e70e5 17 // VGA setting
TETSUYA 0:1648bb4e70e5 18 #define COM7_VGA 0x00
TETSUYA 0:1648bb4e70e5 19 #define HSTART_VGA 0x13
TETSUYA 0:1648bb4e70e5 20 #define HSTOP_VGA 0x01
TETSUYA 0:1648bb4e70e5 21 #define HREF_VGA 0x36 //0xb6 0x36
TETSUYA 0:1648bb4e70e5 22 #define VSTART_VGA 0x02
TETSUYA 0:1648bb4e70e5 23 #define VSTOP_VGA 0x7a
TETSUYA 0:1648bb4e70e5 24 #define VREF_VGA 0x0a
TETSUYA 0:1648bb4e70e5 25 #define COM3_VGA 0x00
TETSUYA 0:1648bb4e70e5 26 #define COM14_VGA 0x00
TETSUYA 0:1648bb4e70e5 27 #define SCALING_XSC_VGA 0x3a
TETSUYA 0:1648bb4e70e5 28 #define SCALING_YSC_VGA 0x35
TETSUYA 0:1648bb4e70e5 29 #define SCALING_DCWCTR_VGA 0x11
TETSUYA 0:1648bb4e70e5 30 #define SCALING_PCLK_DIV_VGA 0xf0
TETSUYA 0:1648bb4e70e5 31 #define SCALING_PCLK_DELAY_VGA 0x02
TETSUYA 0:1648bb4e70e5 32
TETSUYA 0:1648bb4e70e5 33 // QVGA setting
TETSUYA 0:1648bb4e70e5 34 #define COM7_QVGA 0x00
TETSUYA 0:1648bb4e70e5 35 #define HSTART_QVGA 0x16
TETSUYA 0:1648bb4e70e5 36 #define HSTOP_QVGA 0x04
TETSUYA 0:1648bb4e70e5 37 #define HREF_QVGA 0x00
TETSUYA 0:1648bb4e70e5 38 #define VSTART_QVGA 0x02
TETSUYA 0:1648bb4e70e5 39 #define VSTOP_QVGA 0x7a
TETSUYA 0:1648bb4e70e5 40 #define VREF_QVGA 0x0a
TETSUYA 0:1648bb4e70e5 41 #define COM3_QVGA 0x04
TETSUYA 0:1648bb4e70e5 42 #define COM14_QVGA 0x19
TETSUYA 0:1648bb4e70e5 43 #define SCALING_XSC_QVGA 0x3a
TETSUYA 0:1648bb4e70e5 44 #define SCALING_YSC_QVGA 0x35
TETSUYA 0:1648bb4e70e5 45 #define SCALING_DCWCTR_QVGA 0x11
TETSUYA 0:1648bb4e70e5 46 #define SCALING_PCLK_DIV_QVGA 0xf1
TETSUYA 0:1648bb4e70e5 47 #define SCALING_PCLK_DELAY_QVGA 0x02
TETSUYA 0:1648bb4e70e5 48
TETSUYA 0:1648bb4e70e5 49 // QQVGA setting
TETSUYA 0:1648bb4e70e5 50 #define COM7_QQVGA 0x00
TETSUYA 0:1648bb4e70e5 51 #define HSTART_QQVGA 0x16
TETSUYA 0:1648bb4e70e5 52 #define HSTOP_QQVGA 0x04
TETSUYA 0:1648bb4e70e5 53 #define HREF_QQVGA 0xa4 //0x24? 0xa4?
TETSUYA 0:1648bb4e70e5 54 #define VSTART_QQVGA 0x02
TETSUYA 0:1648bb4e70e5 55 #define VSTOP_QQVGA 0x7a
TETSUYA 0:1648bb4e70e5 56 #define VREF_QQVGA 0x0a
TETSUYA 0:1648bb4e70e5 57 #define COM3_QQVGA 0x04
TETSUYA 0:1648bb4e70e5 58 #define COM14_QQVGA 0x1a
TETSUYA 0:1648bb4e70e5 59 #define SCALING_XSC_QQVGA 0x3a
TETSUYA 0:1648bb4e70e5 60 #define SCALING_YSC_QQVGA 0x35
TETSUYA 0:1648bb4e70e5 61 #define SCALING_DCWCTR_QQVGA 0x22
TETSUYA 0:1648bb4e70e5 62 #define SCALING_PCLK_DIV_QQVGA 0xf2
TETSUYA 0:1648bb4e70e5 63 #define SCALING_PCLK_DELAY_QQVGA 0x02
TETSUYA 0:1648bb4e70e5 64
TETSUYA 0:1648bb4e70e5 65 // CIF setting no tested linux src 2.6.29-rc5 ov7670_soc.c
TETSUYA 0:1648bb4e70e5 66 #define COM7_CIF 0x00
TETSUYA 0:1648bb4e70e5 67 #define HSTART_CIF 0x15
TETSUYA 0:1648bb4e70e5 68 #define HSTOP_CIF 0x0b
TETSUYA 0:1648bb4e70e5 69 #define HREF_CIF 0xb6
TETSUYA 0:1648bb4e70e5 70 #define VSTART_CIF 0x03
TETSUYA 0:1648bb4e70e5 71 #define VSTOP_CIF 0x7b
TETSUYA 0:1648bb4e70e5 72 #define VREF_CIF 0x02
TETSUYA 0:1648bb4e70e5 73 #define COM3_CIF 0x08
TETSUYA 0:1648bb4e70e5 74 #define COM14_CIF 0x11
TETSUYA 0:1648bb4e70e5 75 #define SCALING_XSC_CIF 0x3a
TETSUYA 0:1648bb4e70e5 76 #define SCALING_YSC_CIF 0x35
TETSUYA 0:1648bb4e70e5 77 #define SCALING_DCWCTR_CIF 0x11
TETSUYA 0:1648bb4e70e5 78 #define SCALING_PCLK_DIV_CIF 0xf1
TETSUYA 0:1648bb4e70e5 79 #define SCALING_PCLK_DELAY_CIF 0x02
TETSUYA 0:1648bb4e70e5 80
TETSUYA 0:1648bb4e70e5 81 // QCIF setting no tested no tested linux src 2.6.29-rc5 ov7670_soc.c
TETSUYA 0:1648bb4e70e5 82 #define COM7_QCIF 0x00
TETSUYA 0:1648bb4e70e5 83 #define HSTART_QCIF 0x39
TETSUYA 0:1648bb4e70e5 84 #define HSTOP_QCIF 0x03
TETSUYA 0:1648bb4e70e5 85 #define HREF_QCIF 0x80
TETSUYA 0:1648bb4e70e5 86 #define VSTART_QCIF 0x03
TETSUYA 0:1648bb4e70e5 87 #define VSTOP_QCIF 0x7b
TETSUYA 0:1648bb4e70e5 88 #define VREF_QCIF 0x02
TETSUYA 0:1648bb4e70e5 89 #define COM3_QCIF 0x0c
TETSUYA 0:1648bb4e70e5 90 #define COM14_QCIF 0x11
TETSUYA 0:1648bb4e70e5 91 #define SCALING_XSC_QCIF 0x3a
TETSUYA 0:1648bb4e70e5 92 #define SCALING_YSC_QCIF 0x35
TETSUYA 0:1648bb4e70e5 93 #define SCALING_DCWCTR_QCIF 0x11
TETSUYA 0:1648bb4e70e5 94 #define SCALING_PCLK_DIV_QCIF 0xf1
TETSUYA 0:1648bb4e70e5 95 #define SCALING_PCLK_DELAY_QCIF 0x52
TETSUYA 0:1648bb4e70e5 96
TETSUYA 0:1648bb4e70e5 97 // YUV
TETSUYA 0:1648bb4e70e5 98 #define REG_COM13 0x3d /* Control 13 */
TETSUYA 0:1648bb4e70e5 99 #define REG_TSLB 0x3a /* lots of stuff */
TETSUYA 0:1648bb4e70e5 100
TETSUYA 0:1648bb4e70e5 101 #define COM7_YUV 0x00 /* YUV */
TETSUYA 0:1648bb4e70e5 102 #define COM13_UV 0x00 /* U before V - w/TSLB */
TETSUYA 0:1648bb4e70e5 103 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
TETSUYA 0:1648bb4e70e5 104 #define TSLB_VLAST 0x00 /* YUYV - see com13 */
TETSUYA 0:1648bb4e70e5 105 #define TSLB_ULAST 0x00 /* YVYU - see com13 */
TETSUYA 0:1648bb4e70e5 106 #define TSLB_YLAST 0x08 /* UYVY or VYUY - see com13 */
TETSUYA 0:1648bb4e70e5 107
TETSUYA 0:1648bb4e70e5 108 // RGB
TETSUYA 0:1648bb4e70e5 109 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
TETSUYA 0:1648bb4e70e5 110
TETSUYA 0:1648bb4e70e5 111 // RGB444
TETSUYA 0:1648bb4e70e5 112 #define REG_RGB444 0x8c /* RGB 444 control */
TETSUYA 0:1648bb4e70e5 113 #define REG_COM15 0x40 /* Control 15 */
TETSUYA 0:1648bb4e70e5 114
TETSUYA 0:1648bb4e70e5 115 #define RGB444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
TETSUYA 0:1648bb4e70e5 116 #define RGB444_XBGR 0x00
TETSUYA 0:1648bb4e70e5 117 #define RGB444_BGRX 0x01 /* Empty nibble at end */
TETSUYA 0:1648bb4e70e5 118 #define COM15_RGB444 0x10 /* RGB444 output */
TETSUYA 0:1648bb4e70e5 119
TETSUYA 0:1648bb4e70e5 120 // RGB555
TETSUYA 0:1648bb4e70e5 121 #define RGB444_DISABLE 0x00 /* Turn off RGB444, overrides 5x5 */
TETSUYA 0:1648bb4e70e5 122 #define COM15_RGB555 0x30 /* RGB555 output */
TETSUYA 0:1648bb4e70e5 123
TETSUYA 0:1648bb4e70e5 124 // RGB565
TETSUYA 0:1648bb4e70e5 125 #define COM15_RGB565 0x10 /* RGB565 output */
TETSUYA 0:1648bb4e70e5 126
TETSUYA 0:1648bb4e70e5 127 // Bayer RGB
TETSUYA 0:1648bb4e70e5 128 #define COM7_BAYER 0x01 /* Bayer format */
TETSUYA 0:1648bb4e70e5 129 #define COM7_PBAYER 0x05 /* "Processed bayer" */
TETSUYA 0:1648bb4e70e5 130
TETSUYA 0:1648bb4e70e5 131
TETSUYA 0:1648bb4e70e5 132 // data format
TETSUYA 0:1648bb4e70e5 133 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
TETSUYA 0:1648bb4e70e5 134 #define COM15_R01FE 0x80 /* 01 to FE */
TETSUYA 0:1648bb4e70e5 135 #define COM15_R00FF 0xc0 /* 00 to FF */
TETSUYA 0:1648bb4e70e5 136
TETSUYA 0:1648bb4e70e5 137 // Night mode, flicker, banding /
TETSUYA 0:1648bb4e70e5 138 #define REG_COM11 0x3b /* Control 11 */
TETSUYA 0:1648bb4e70e5 139 #define COM11_NIGHT 0x80 /* NIght mode enable */
TETSUYA 0:1648bb4e70e5 140 #define COM11_NIGHT_MIN_RATE_1_1 0x00 /* Normal mode same */
TETSUYA 0:1648bb4e70e5 141 #define COM11_NIGHT_MIN_RATE_1_2 0x20 /* Normal mode 1/2 */
TETSUYA 0:1648bb4e70e5 142 #define COM11_NIGHT_MIN_RATE_1_4 0x40 /* Normal mode 1/4 */
TETSUYA 0:1648bb4e70e5 143 #define COM11_NIGHT_MIN_RATE_1_8 0x60 /* Normal mode 1/5 */
TETSUYA 0:1648bb4e70e5 144 #define COM11_HZAUTO_ON 0x10 /* Auto detect 50/60 Hz on */
TETSUYA 0:1648bb4e70e5 145 #define COM11_HZAUTO_OFF 0x00 /* Auto detect 50/60 Hz off */
TETSUYA 0:1648bb4e70e5 146 #define COM11_60HZ 0x00 /* Manual 60Hz select */
TETSUYA 0:1648bb4e70e5 147 #define COM11_50HZ 0x08 /* Manual 50Hz select */
TETSUYA 0:1648bb4e70e5 148 #define COM11_EXP 0x02
TETSUYA 0:1648bb4e70e5 149
TETSUYA 0:1648bb4e70e5 150 #define REG_MTX1 0x4f
TETSUYA 0:1648bb4e70e5 151 #define REG_MTX2 0x50
TETSUYA 0:1648bb4e70e5 152 #define REG_MTX3 0x51
TETSUYA 0:1648bb4e70e5 153 #define REG_MTX4 0x52
TETSUYA 0:1648bb4e70e5 154 #define REG_MTX5 0x53
TETSUYA 0:1648bb4e70e5 155 #define REG_MTX6 0x54
TETSUYA 0:1648bb4e70e5 156 #define REG_BRIGHT 0x55 /* Brightness */
TETSUYA 0:1648bb4e70e5 157 #define REG_CONTRAS 0x56 /* Contrast control */
TETSUYA 0:1648bb4e70e5 158 #define REG_CONTRAS_CENTER 0x57
TETSUYA 0:1648bb4e70e5 159 #define REG_MTXS 0x58
TETSUYA 0:1648bb4e70e5 160 #define REG_MANU 0x67
TETSUYA 0:1648bb4e70e5 161 #define REG_MANV 0x68
TETSUYA 0:1648bb4e70e5 162 #define REG_GFIX 0x69 /* Fix gain control */
TETSUYA 0:1648bb4e70e5 163 #define REG_GGAIN 0x6a
TETSUYA 0:1648bb4e70e5 164 #define REG_DBLV 0x6b
TETSUYA 0:1648bb4e70e5 165
TETSUYA 0:1648bb4e70e5 166 #define REG_COM9 0x14 // Control 9 - gain ceiling
TETSUYA 0:1648bb4e70e5 167 #define COM9_AGC_2X 0x00
TETSUYA 0:1648bb4e70e5 168 #define COM9_AGC_4X 0x10
TETSUYA 0:1648bb4e70e5 169 #define COM9_AGC_8X 0x20
TETSUYA 0:1648bb4e70e5 170 #define COM9_AGC_16X 0x30
TETSUYA 0:1648bb4e70e5 171 #define COM9_AGC_32X 0x40
TETSUYA 0:1648bb4e70e5 172 #define COM9_AGC_64X 0x50
TETSUYA 0:1648bb4e70e5 173 #define COM9_AGC_128X 0x60
TETSUYA 0:1648bb4e70e5 174 #define COM9_AGC_MASK 0x70
TETSUYA 0:1648bb4e70e5 175 #define COM9_FREEZE 0x01
TETSUYA 0:1648bb4e70e5 176 #define COM13_GAMMA 0x80 /* Gamma enable */
TETSUYA 0:1648bb4e70e5 177 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
TETSUYA 0:1648bb4e70e5 178 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
TETSUYA 0:1648bb4e70e5 179 #define REG_BLUE 0x01 /* blue gain */
TETSUYA 0:1648bb4e70e5 180 #define REG_RED 0x02 /* red gain */
TETSUYA 0:1648bb4e70e5 181 #define REG_COM1 0x04 /* Control 1 */
TETSUYA 0:1648bb4e70e5 182 #define COM1_CCIR656 0x40 /* CCIR656 enable */
TETSUYA 0:1648bb4e70e5 183 #define REG_BAVE 0x05 /* U/B Average level */
TETSUYA 0:1648bb4e70e5 184 #define REG_GbAVE 0x06 /* Y/Gb Average level */
TETSUYA 0:1648bb4e70e5 185 #define REG_AECHH 0x07 /* AEC MS 5 bits */
TETSUYA 0:1648bb4e70e5 186 #define REG_RAVE 0x08 /* V/R Average level */
TETSUYA 0:1648bb4e70e5 187 #define REG_COM2 0x09 /* Control 2 */
TETSUYA 0:1648bb4e70e5 188 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
TETSUYA 0:1648bb4e70e5 189 #define REG_PID 0x0a /* Product ID MSB */
TETSUYA 0:1648bb4e70e5 190 #define REG_VER 0x0b /* Product ID LSB */
TETSUYA 0:1648bb4e70e5 191 #define COM3_SWAP 0x40 /* Byte swap */
TETSUYA 0:1648bb4e70e5 192 #define COM3_SCALEEN 0x08 /* Enable scaling */
TETSUYA 0:1648bb4e70e5 193 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
TETSUYA 0:1648bb4e70e5 194 #define REG_COM4 0x0d /* Control 4 */
TETSUYA 0:1648bb4e70e5 195 #define REG_COM5 0x0e /* All "reserved" */
TETSUYA 0:1648bb4e70e5 196 #define REG_COM6 0x0f /* Control 6 */
TETSUYA 0:1648bb4e70e5 197 #define REG_AECH 0x10 /* More bits of AEC value */
TETSUYA 0:1648bb4e70e5 198 #define REG_CLKRC 0x11 /* Clocl control */
TETSUYA 0:1648bb4e70e5 199 #define CLK_EXT 0x40 /* Use external clock directly */
TETSUYA 0:1648bb4e70e5 200 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
TETSUYA 0:1648bb4e70e5 201 #define COM7_RESET 0x80 /* Register reset */
TETSUYA 0:1648bb4e70e5 202 #define COM7_FMT_MASK 0x38
TETSUYA 0:1648bb4e70e5 203 #define COM7_FMT_VGA 0x00
TETSUYA 0:1648bb4e70e5 204 #define COM7_FMT_CIF 0x20 /* CIF format */
TETSUYA 0:1648bb4e70e5 205 #define COM7_FMT_QVGA 0x10 /* QVGA format */
TETSUYA 0:1648bb4e70e5 206 #define COM7_FMT_QCIF 0x08 /* QCIF format */
TETSUYA 0:1648bb4e70e5 207 #define REG_COM8 0x13 /* Control 8 */
TETSUYA 0:1648bb4e70e5 208 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
TETSUYA 0:1648bb4e70e5 209 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
TETSUYA 0:1648bb4e70e5 210 #define COM8_BFILT 0x20 /* Band filter enable */
TETSUYA 0:1648bb4e70e5 211 #define COM8_AGC 0x04 /* Auto gain enable */
TETSUYA 0:1648bb4e70e5 212 #define COM8_AWB 0x02 /* White balance enable */
TETSUYA 0:1648bb4e70e5 213 #define COM8_AEC 0x01 /* Auto exposure enable */
TETSUYA 0:1648bb4e70e5 214 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
TETSUYA 0:1648bb4e70e5 215 #define REG_COM10 0x15 /* Control 10 */
TETSUYA 0:1648bb4e70e5 216 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
TETSUYA 0:1648bb4e70e5 217 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
TETSUYA 0:1648bb4e70e5 218 #define COM10_HREF_REV 0x08 /* Reverse HREF */
TETSUYA 0:1648bb4e70e5 219 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
TETSUYA 0:1648bb4e70e5 220 #define COM10_VS_NEG 0x02 /* VSYNC negative */
TETSUYA 0:1648bb4e70e5 221 #define COM10_HS_NEG 0x01 /* HSYNC negative */
TETSUYA 0:1648bb4e70e5 222 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
TETSUYA 0:1648bb4e70e5 223 #define REG_MIDH 0x1c /* Manuf. ID high */
TETSUYA 0:1648bb4e70e5 224 #define REG_MIDL 0x1d /* Manuf. ID low */
TETSUYA 0:1648bb4e70e5 225 #define REG_MVFP 0x1e /* Mirror / vflip */
TETSUYA 0:1648bb4e70e5 226 #define MVFP_MIRROR 0x20 /* Mirror image */
TETSUYA 0:1648bb4e70e5 227 #define MVFP_FLIP 0x10 /* Vertical flip */
TETSUYA 0:1648bb4e70e5 228 #define REG_AEW 0x24 /* AGC upper limit */
TETSUYA 0:1648bb4e70e5 229 #define REG_AEB 0x25 /* AGC lower limit */
TETSUYA 0:1648bb4e70e5 230 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
TETSUYA 0:1648bb4e70e5 231 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
TETSUYA 0:1648bb4e70e5 232 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
TETSUYA 0:1648bb4e70e5 233 #define REG_COM12 0x3c /* Control 12 */
TETSUYA 0:1648bb4e70e5 234 #define COM12_HREF 0x80 /* HREF always */
TETSUYA 0:1648bb4e70e5 235 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
TETSUYA 0:1648bb4e70e5 236 #define REG_EDGE 0x3f /* Edge enhancement factor */
TETSUYA 0:1648bb4e70e5 237 #define REG_COM16 0x41 /* Control 16 */
TETSUYA 0:1648bb4e70e5 238 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
TETSUYA 0:1648bb4e70e5 239 #define REG_COM17 0x42 /* Control 17 */
TETSUYA 0:1648bb4e70e5 240 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
TETSUYA 0:1648bb4e70e5 241 #define COM17_CBAR 0x08 /* DSP Color bar */
TETSUYA 0:1648bb4e70e5 242 #define REG_CMATRIX_BASE 0x4f
TETSUYA 0:1648bb4e70e5 243 #define CMATRIX_LEN 6
TETSUYA 0:1648bb4e70e5 244 #define REG_REG76 0x76 /* OV's name */
TETSUYA 0:1648bb4e70e5 245 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
TETSUYA 0:1648bb4e70e5 246 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
TETSUYA 0:1648bb4e70e5 247 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
TETSUYA 0:1648bb4e70e5 248 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
TETSUYA 0:1648bb4e70e5 249 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
TETSUYA 0:1648bb4e70e5 250 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
TETSUYA 0:1648bb4e70e5 251 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
TETSUYA 0:1648bb4e70e5 252 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
TETSUYA 0:1648bb4e70e5 253 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
TETSUYA 0:1648bb4e70e5 254 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
TETSUYA 0:1648bb4e70e5 255 #define REG_BD60MAX 0xab /* 60hz banding step limit */