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targets/cmsis/TARGET_STM/TARGET_STM32F3/stm32f3xx_hal_rcc.c@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
0:9b334a45a8ff 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f3xx_hal_rcc.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.3.0
<> 144:ef7eb2e8f9f7 6 * @date 01-July-2016
<> 144:ef7eb2e8f9f7 7 * @brief RCC HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Reset and Clock Control (RCC) peripheral:
<> 144:ef7eb2e8f9f7 10 * + Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 11 * + Peripheral Control functions
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 @verbatim
<> 144:ef7eb2e8f9f7 14 ==============================================================================
<> 144:ef7eb2e8f9f7 15 ##### RCC specific features #####
<> 144:ef7eb2e8f9f7 16 ==============================================================================
<> 144:ef7eb2e8f9f7 17 [..]
<> 144:ef7eb2e8f9f7 18 After reset the device is running from Internal High Speed oscillator
<> 144:ef7eb2e8f9f7 19 (HSI 8MHz) with Flash 0 wait state, Flash prefetch buffer is enabled,
<> 144:ef7eb2e8f9f7 20 and all peripherals are off except internal SRAM, Flash and JTAG.
<> 144:ef7eb2e8f9f7 21 (+) There is no prescaler on High speed (AHB) and Low speed (APB) buses;
<> 144:ef7eb2e8f9f7 22 all peripherals mapped on these buses are running at HSI speed.
<> 144:ef7eb2e8f9f7 23 (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
<> 144:ef7eb2e8f9f7 24 (+) All GPIOs are in input floating state, except the JTAG pins which
<> 144:ef7eb2e8f9f7 25 are assigned to be used for debug purpose.
<> 144:ef7eb2e8f9f7 26 [..] Once the device started from reset, the user application has to:
<> 144:ef7eb2e8f9f7 27 (+) Configure the clock source to be used to drive the System clock
<> 144:ef7eb2e8f9f7 28 (if the application needs higher frequency/performance)
<> 144:ef7eb2e8f9f7 29 (+) Configure the System clock frequency and Flash settings
<> 144:ef7eb2e8f9f7 30 (+) Configure the AHB and APB buses prescalers
<> 144:ef7eb2e8f9f7 31 (+) Enable the clock for the peripheral(s) to be used
<> 144:ef7eb2e8f9f7 32 (+) Configure the clock source(s) for peripherals whose clocks are not
<> 144:ef7eb2e8f9f7 33 derived from the System clock (RTC, ADC, I2C, I2S, TIM, USB FS)
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 ##### RCC Limitations #####
<> 144:ef7eb2e8f9f7 36 ==============================================================================
<> 144:ef7eb2e8f9f7 37 [..]
<> 144:ef7eb2e8f9f7 38 A delay between an RCC peripheral clock enable and the effective peripheral
<> 144:ef7eb2e8f9f7 39 enabling should be taken into account in order to manage the peripheral read/write
<> 144:ef7eb2e8f9f7 40 from/to registers.
<> 144:ef7eb2e8f9f7 41 (+) This delay depends on the peripheral mapping.
<> 144:ef7eb2e8f9f7 42 (++) AHB & APB peripherals, 1 dummy read is necessary
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 [..]
<> 144:ef7eb2e8f9f7 45 Workarounds:
<> 144:ef7eb2e8f9f7 46 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
<> 144:ef7eb2e8f9f7 47 inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 @endverbatim
<> 144:ef7eb2e8f9f7 50 ******************************************************************************
<> 144:ef7eb2e8f9f7 51 * @attention
<> 144:ef7eb2e8f9f7 52 *
<> 144:ef7eb2e8f9f7 53 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 54 *
<> 144:ef7eb2e8f9f7 55 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 56 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 57 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 58 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 59 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 60 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 61 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 62 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 63 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 64 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 65 *
<> 144:ef7eb2e8f9f7 66 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 67 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 68 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 69 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 70 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 71 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 72 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 73 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 74 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 75 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 ******************************************************************************
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 81 #include "stm32f3xx_hal.h"
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** @addtogroup STM32F3xx_HAL_Driver
<> 144:ef7eb2e8f9f7 84 * @{
<> 144:ef7eb2e8f9f7 85 */
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 /** @defgroup RCC RCC
<> 144:ef7eb2e8f9f7 88 * @brief RCC HAL module driver
<> 144:ef7eb2e8f9f7 89 * @{
<> 144:ef7eb2e8f9f7 90 */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 #ifdef HAL_RCC_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 95 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 96 /** @defgroup RCC_Private_Constants RCC Private Constants
<> 144:ef7eb2e8f9f7 97 * @{
<> 144:ef7eb2e8f9f7 98 */
<> 144:ef7eb2e8f9f7 99 /* Bits position in in the CFGR register */
<> 144:ef7eb2e8f9f7 100 #define RCC_CFGR_HPRE_BITNUMBER POSITION_VAL(RCC_CFGR_HPRE)
<> 144:ef7eb2e8f9f7 101 #define RCC_CFGR_PPRE1_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE1)
<> 144:ef7eb2e8f9f7 102 #define RCC_CFGR_PPRE2_BITNUMBER POSITION_VAL(RCC_CFGR_PPRE2)
<> 144:ef7eb2e8f9f7 103 /**
<> 144:ef7eb2e8f9f7 104 * @}
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 107 /** @defgroup RCC_Private_Macros RCC Private Macros
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
<> 144:ef7eb2e8f9f7 112 #define MCO1_GPIO_PORT GPIOA
<> 144:ef7eb2e8f9f7 113 #define MCO1_PIN GPIO_PIN_8
<> 144:ef7eb2e8f9f7 114
<> 144:ef7eb2e8f9f7 115 /**
<> 144:ef7eb2e8f9f7 116 * @}
<> 144:ef7eb2e8f9f7 117 */
<> 144:ef7eb2e8f9f7 118
<> 144:ef7eb2e8f9f7 119 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 120 /** @defgroup RCC_Private_Variables RCC Private Variables
<> 144:ef7eb2e8f9f7 121 * @{
<> 144:ef7eb2e8f9f7 122 */
<> 144:ef7eb2e8f9f7 123 const uint8_t aPLLMULFactorTable[16] = { 2, 3, 4, 5, 6, 7, 8, 9,
<> 144:ef7eb2e8f9f7 124 10, 11, 12, 13, 14, 15, 16, 16};
<> 144:ef7eb2e8f9f7 125 const uint8_t aPredivFactorTable[16] = { 1, 2, 3, 4, 5, 6, 7, 8,
<> 144:ef7eb2e8f9f7 126 9,10, 11, 12, 13, 14, 15, 16};
<> 144:ef7eb2e8f9f7 127 /**
<> 144:ef7eb2e8f9f7 128 * @}
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 132 /* Exported functions ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 /** @defgroup RCC_Exported_Functions RCC Exported Functions
<> 144:ef7eb2e8f9f7 135 * @{
<> 144:ef7eb2e8f9f7 136 */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
<> 144:ef7eb2e8f9f7 139 * @brief Initialization and Configuration functions
<> 144:ef7eb2e8f9f7 140 *
<> 144:ef7eb2e8f9f7 141 @verbatim
<> 144:ef7eb2e8f9f7 142 ===============================================================================
<> 144:ef7eb2e8f9f7 143 ##### Initialization and de-initialization functions #####
<> 144:ef7eb2e8f9f7 144 ===============================================================================
<> 144:ef7eb2e8f9f7 145 [..]
<> 144:ef7eb2e8f9f7 146 This section provides functions allowing to configure the internal/external oscillators
<> 144:ef7eb2e8f9f7 147 (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
<> 144:ef7eb2e8f9f7 148 and APB2).
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150 [..] Internal/external clock and PLL configuration
<> 144:ef7eb2e8f9f7 151 (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly or through
<> 144:ef7eb2e8f9f7 152 the PLL as System clock source.
<> 144:ef7eb2e8f9f7 153 The HSI clock can be used also to clock the USART and I2C peripherals.
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155 (#) LSI (low-speed internal), ~40 KHz low consumption RC used as IWDG and/or RTC
<> 144:ef7eb2e8f9f7 156 clock source.
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
<> 144:ef7eb2e8f9f7 159 through the PLL as System clock source. Can be used also as RTC clock source.
<> 144:ef7eb2e8f9f7 160
<> 144:ef7eb2e8f9f7 161 (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 (#) PLL (clocked by HSI or HSE), featuring different output clocks:
<> 144:ef7eb2e8f9f7 164 (++) The first output is used to generate the high speed system clock (up to 72 MHz)
<> 144:ef7eb2e8f9f7 165 (++) The second output is used to generate the clock for the USB FS (48 MHz)
<> 144:ef7eb2e8f9f7 166 (++) The third output may be used to generate the clock for the ADC peripherals (up to 72 MHz)
<> 144:ef7eb2e8f9f7 167 (++) The fourth output may be used to generate the clock for the TIM peripherals (144 MHz)
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
<> 144:ef7eb2e8f9f7 170 and if a HSE clock failure occurs(HSE used directly or through PLL as System
<> 144:ef7eb2e8f9f7 171 clock source), the System clocks automatically switched to HSI and an interrupt
<> 144:ef7eb2e8f9f7 172 is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
<> 144:ef7eb2e8f9f7 173 (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSE, LSI, LSE or PLL
<> 144:ef7eb2e8f9f7 176 clock (divided by 2) output on pin (such as PA8 pin).
<> 144:ef7eb2e8f9f7 177
<> 144:ef7eb2e8f9f7 178 [..] System, AHB and APB buses clocks configuration
<> 144:ef7eb2e8f9f7 179 (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
<> 144:ef7eb2e8f9f7 180 HSE and PLL.
<> 144:ef7eb2e8f9f7 181 The AHB clock (HCLK) is derived from System clock through configurable
<> 144:ef7eb2e8f9f7 182 prescaler and used to clock the CPU, memory and peripherals mapped
<> 144:ef7eb2e8f9f7 183 on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
<> 144:ef7eb2e8f9f7 184 from AHB clock through configurable prescalers and used to clock
<> 144:ef7eb2e8f9f7 185 the peripherals mapped on these buses. You can use
<> 144:ef7eb2e8f9f7 186 "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 (#) All the peripheral clocks are derived from the System clock (SYSCLK) except:
<> 144:ef7eb2e8f9f7 189 (++) The FLASH program/erase clock which is always HSI 8MHz clock.
<> 144:ef7eb2e8f9f7 190 (++) The USB 48 MHz clock which is derived from the PLL VCO clock.
<> 144:ef7eb2e8f9f7 191 (++) The USART clock which can be derived as well from HSI 8MHz, LSI or LSE.
<> 144:ef7eb2e8f9f7 192 (++) The I2C clock which can be derived as well from HSI 8MHz clock.
<> 144:ef7eb2e8f9f7 193 (++) The ADC clock which is derived from PLL output.
<> 144:ef7eb2e8f9f7 194 (++) The RTC clock which is derived from the LSE, LSI or 1 MHz HSE_RTC
<> 144:ef7eb2e8f9f7 195 (HSE divided by a programmable prescaler). The System clock (SYSCLK)
<> 144:ef7eb2e8f9f7 196 frequency must be higher or equal to the RTC clock frequency.
<> 144:ef7eb2e8f9f7 197 (++) IWDG clock which is always the LSI clock.
<> 144:ef7eb2e8f9f7 198
<> 144:ef7eb2e8f9f7 199 (#) For the STM32F3xx devices, the maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 72 MHz,
<> 144:ef7eb2e8f9f7 200 Depending on the SYSCLK frequency, the flash latency should be adapted accordingly.
<> 144:ef7eb2e8f9f7 201
<> 144:ef7eb2e8f9f7 202 (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
<> 144:ef7eb2e8f9f7 203 prefetch is disabled.
<> 144:ef7eb2e8f9f7 204 @endverbatim
<> 144:ef7eb2e8f9f7 205 * @{
<> 144:ef7eb2e8f9f7 206 */
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 /*
<> 144:ef7eb2e8f9f7 209 Additional consideration on the SYSCLK based on Latency settings:
<> 144:ef7eb2e8f9f7 210 +-----------------------------------------------+
<> 144:ef7eb2e8f9f7 211 | Latency | SYSCLK clock frequency (MHz) |
<> 144:ef7eb2e8f9f7 212 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 213 |0WS(1CPU cycle)| 0 < SYSCLK <= 24 |
<> 144:ef7eb2e8f9f7 214 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 215 |1WS(2CPU cycle)| 24 < SYSCLK <= 48 |
<> 144:ef7eb2e8f9f7 216 |---------------|-------------------------------|
<> 144:ef7eb2e8f9f7 217 |2WS(3CPU cycle)| 48 < SYSCLK <= 72 |
<> 144:ef7eb2e8f9f7 218 +-----------------------------------------------+
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 /**
<> 144:ef7eb2e8f9f7 222 * @brief Resets the RCC clock configuration to the default reset state.
<> 144:ef7eb2e8f9f7 223 * @note The default reset state of the clock configuration is given below:
<> 144:ef7eb2e8f9f7 224 * - HSI ON and used as system clock source
<> 144:ef7eb2e8f9f7 225 * - HSE and PLL OFF
<> 144:ef7eb2e8f9f7 226 * - AHB, APB1 and APB2 prescaler set to 1.
<> 144:ef7eb2e8f9f7 227 * - CSS and MCO1 OFF
<> 144:ef7eb2e8f9f7 228 * - All interrupts disabled
<> 144:ef7eb2e8f9f7 229 * @note This function does not modify the configuration of the
<> 144:ef7eb2e8f9f7 230 * - Peripheral clocks
<> 144:ef7eb2e8f9f7 231 * - LSI, LSE and RTC clocks
<> 144:ef7eb2e8f9f7 232 * @retval None
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234 void HAL_RCC_DeInit(void)
<> 144:ef7eb2e8f9f7 235 {
<> 144:ef7eb2e8f9f7 236 /* Set HSION bit, HSITRIM[4:0] bits to the reset value*/
<> 144:ef7eb2e8f9f7 237 SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0] and MCOSEL[2:0] bits */
<> 144:ef7eb2e8f9f7 240 CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 | RCC_CFGR_MCO);
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* Reset HSEON, CSSON, PLLON bits */
<> 144:ef7eb2e8f9f7 243 CLEAR_BIT(RCC->CR, RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_HSEON);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Reset HSEBYP bit */
<> 144:ef7eb2e8f9f7 246 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Reset CFGR register */
<> 144:ef7eb2e8f9f7 249 CLEAR_REG(RCC->CFGR);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* Reset CFGR2 register */
<> 144:ef7eb2e8f9f7 252 CLEAR_REG(RCC->CFGR2);
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* Reset CFGR3 register */
<> 144:ef7eb2e8f9f7 255 CLEAR_REG(RCC->CFGR3);
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* Disable all interrupts */
<> 144:ef7eb2e8f9f7 258 CLEAR_REG(RCC->CIR);
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 261 SystemCoreClock = HSI_VALUE;
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /**
<> 144:ef7eb2e8f9f7 265 * @brief Initializes the RCC Oscillators according to the specified parameters in the
<> 144:ef7eb2e8f9f7 266 * RCC_OscInitTypeDef.
<> 144:ef7eb2e8f9f7 267 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 268 * contains the configuration information for the RCC Oscillators.
<> 144:ef7eb2e8f9f7 269 * @note The PLL is not disabled when used as system clock.
<> 144:ef7eb2e8f9f7 270 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
<> 144:ef7eb2e8f9f7 271 * supported by this macro. User should request a transition to LSE Off
<> 144:ef7eb2e8f9f7 272 * first and then LSE On or LSE Bypass.
<> 144:ef7eb2e8f9f7 273 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
<> 144:ef7eb2e8f9f7 274 * supported by this macro. User should request a transition to HSE Off
<> 144:ef7eb2e8f9f7 275 * first and then HSE On or HSE Bypass.
<> 144:ef7eb2e8f9f7 276 * @retval HAL status
<> 144:ef7eb2e8f9f7 277 */
<> 144:ef7eb2e8f9f7 278 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 279 {
<> 144:ef7eb2e8f9f7 280 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 281
<> 144:ef7eb2e8f9f7 282 /* Check the parameters */
<> 144:ef7eb2e8f9f7 283 assert_param(RCC_OscInitStruct != NULL);
<> 144:ef7eb2e8f9f7 284 assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 /*------------------------------- HSE Configuration ------------------------*/
<> 144:ef7eb2e8f9f7 287 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
<> 144:ef7eb2e8f9f7 288 {
<> 144:ef7eb2e8f9f7 289 /* Check the parameters */
<> 144:ef7eb2e8f9f7 290 assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
<> 144:ef7eb2e8f9f7 291
<> 144:ef7eb2e8f9f7 292 /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
<> 144:ef7eb2e8f9f7 293 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 294 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
<> 144:ef7eb2e8f9f7 295 {
<> 144:ef7eb2e8f9f7 296 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
<> 144:ef7eb2e8f9f7 297 {
<> 144:ef7eb2e8f9f7 298 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 299 }
<> 144:ef7eb2e8f9f7 300 }
<> 144:ef7eb2e8f9f7 301 else
<> 144:ef7eb2e8f9f7 302 {
<> 144:ef7eb2e8f9f7 303 /* Set the new HSE configuration ---------------------------------------*/
<> 144:ef7eb2e8f9f7 304 __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
<> 144:ef7eb2e8f9f7 307 /* Configure the HSE predivision factor --------------------------------*/
<> 144:ef7eb2e8f9f7 308 __HAL_RCC_HSE_PREDIV_CONFIG(RCC_OscInitStruct->HSEPredivValue);
<> 144:ef7eb2e8f9f7 309 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 /* Check the HSE State */
<> 144:ef7eb2e8f9f7 312 if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 315 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Wait till HSE is ready */
<> 144:ef7eb2e8f9f7 318 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 319 {
<> 144:ef7eb2e8f9f7 320 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 321 {
<> 144:ef7eb2e8f9f7 322 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 323 }
<> 144:ef7eb2e8f9f7 324 }
<> 144:ef7eb2e8f9f7 325 }
<> 144:ef7eb2e8f9f7 326 else
<> 144:ef7eb2e8f9f7 327 {
<> 144:ef7eb2e8f9f7 328 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 329 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 330
<> 144:ef7eb2e8f9f7 331 /* Wait till HSE is disabled */
<> 144:ef7eb2e8f9f7 332 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
<> 144:ef7eb2e8f9f7 333 {
<> 144:ef7eb2e8f9f7 334 if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 337 }
<> 144:ef7eb2e8f9f7 338 }
<> 144:ef7eb2e8f9f7 339 }
<> 144:ef7eb2e8f9f7 340 }
<> 144:ef7eb2e8f9f7 341 }
<> 144:ef7eb2e8f9f7 342 /*----------------------------- HSI Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 343 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
<> 144:ef7eb2e8f9f7 344 {
<> 144:ef7eb2e8f9f7 345 /* Check the parameters */
<> 144:ef7eb2e8f9f7 346 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
<> 144:ef7eb2e8f9f7 347 assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
<> 144:ef7eb2e8f9f7 350 if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 351 || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
<> 144:ef7eb2e8f9f7 352 {
<> 144:ef7eb2e8f9f7 353 /* When HSI is used as system clock it will not disabled */
<> 144:ef7eb2e8f9f7 354 if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
<> 144:ef7eb2e8f9f7 355 {
<> 144:ef7eb2e8f9f7 356 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 357 }
<> 144:ef7eb2e8f9f7 358 /* Otherwise, just the calibration is allowed */
<> 144:ef7eb2e8f9f7 359 else
<> 144:ef7eb2e8f9f7 360 {
<> 144:ef7eb2e8f9f7 361 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 362 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 363 }
<> 144:ef7eb2e8f9f7 364 }
<> 144:ef7eb2e8f9f7 365 else
<> 144:ef7eb2e8f9f7 366 {
<> 144:ef7eb2e8f9f7 367 /* Check the HSI State */
<> 144:ef7eb2e8f9f7 368 if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
<> 144:ef7eb2e8f9f7 369 {
<> 144:ef7eb2e8f9f7 370 /* Enable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 371 __HAL_RCC_HSI_ENABLE();
<> 144:ef7eb2e8f9f7 372
<> 144:ef7eb2e8f9f7 373 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 374 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 /* Wait till HSI is ready */
<> 144:ef7eb2e8f9f7 377 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 378 {
<> 144:ef7eb2e8f9f7 379 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 380 {
<> 144:ef7eb2e8f9f7 381 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 382 }
<> 144:ef7eb2e8f9f7 383 }
<> 144:ef7eb2e8f9f7 384
<> 144:ef7eb2e8f9f7 385 /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
<> 144:ef7eb2e8f9f7 386 __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
<> 144:ef7eb2e8f9f7 387 }
<> 144:ef7eb2e8f9f7 388 else
<> 144:ef7eb2e8f9f7 389 {
<> 144:ef7eb2e8f9f7 390 /* Disable the Internal High Speed oscillator (HSI). */
<> 144:ef7eb2e8f9f7 391 __HAL_RCC_HSI_DISABLE();
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 394 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 /* Wait till HSI is disabled */
<> 144:ef7eb2e8f9f7 397 while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 400 {
<> 144:ef7eb2e8f9f7 401 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 402 }
<> 144:ef7eb2e8f9f7 403 }
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 }
<> 144:ef7eb2e8f9f7 407 /*------------------------------ LSI Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 408 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
<> 144:ef7eb2e8f9f7 409 {
<> 144:ef7eb2e8f9f7 410 /* Check the parameters */
<> 144:ef7eb2e8f9f7 411 assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
<> 144:ef7eb2e8f9f7 412
<> 144:ef7eb2e8f9f7 413 /* Check the LSI State */
<> 144:ef7eb2e8f9f7 414 if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
<> 144:ef7eb2e8f9f7 415 {
<> 144:ef7eb2e8f9f7 416 /* Enable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 417 __HAL_RCC_LSI_ENABLE();
<> 144:ef7eb2e8f9f7 418
<> 144:ef7eb2e8f9f7 419 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 420 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 421
<> 144:ef7eb2e8f9f7 422 /* Wait till LSI is ready */
<> 144:ef7eb2e8f9f7 423 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 424 {
<> 144:ef7eb2e8f9f7 425 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 426 {
<> 144:ef7eb2e8f9f7 427 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 428 }
<> 144:ef7eb2e8f9f7 429 }
<> 144:ef7eb2e8f9f7 430 }
<> 144:ef7eb2e8f9f7 431 else
<> 144:ef7eb2e8f9f7 432 {
<> 144:ef7eb2e8f9f7 433 /* Disable the Internal Low Speed oscillator (LSI). */
<> 144:ef7eb2e8f9f7 434 __HAL_RCC_LSI_DISABLE();
<> 144:ef7eb2e8f9f7 435
<> 144:ef7eb2e8f9f7 436 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 437 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Wait till LSI is disabled */
<> 144:ef7eb2e8f9f7 440 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
<> 144:ef7eb2e8f9f7 441 {
<> 144:ef7eb2e8f9f7 442 if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 443 {
<> 144:ef7eb2e8f9f7 444 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 445 }
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447 }
<> 144:ef7eb2e8f9f7 448 }
<> 144:ef7eb2e8f9f7 449 /*------------------------------ LSE Configuration -------------------------*/
<> 144:ef7eb2e8f9f7 450 if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
<> 144:ef7eb2e8f9f7 451 {
<> 144:ef7eb2e8f9f7 452 FlagStatus pwrclkchanged = RESET;
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /* Check the parameters */
<> 144:ef7eb2e8f9f7 455 assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /* Update LSE configuration in Backup Domain control register */
<> 144:ef7eb2e8f9f7 458 /* Requires to enable write access to Backup Domain of necessary */
<> 144:ef7eb2e8f9f7 459 if(__HAL_RCC_PWR_IS_CLK_DISABLED())
<> 144:ef7eb2e8f9f7 460 {
<> 144:ef7eb2e8f9f7 461 __HAL_RCC_PWR_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 462 pwrclkchanged = SET;
<> 144:ef7eb2e8f9f7 463 }
<> 144:ef7eb2e8f9f7 464
<> 144:ef7eb2e8f9f7 465 if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 466 {
<> 144:ef7eb2e8f9f7 467 /* Enable write access to Backup domain */
<> 144:ef7eb2e8f9f7 468 SET_BIT(PWR->CR, PWR_CR_DBP);
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470 /* Wait for Backup domain Write protection disable */
<> 144:ef7eb2e8f9f7 471 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
<> 144:ef7eb2e8f9f7 474 {
<> 144:ef7eb2e8f9f7 475 if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 476 {
<> 144:ef7eb2e8f9f7 477 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 478 }
<> 144:ef7eb2e8f9f7 479 }
<> 144:ef7eb2e8f9f7 480 }
<> 144:ef7eb2e8f9f7 481
<> 144:ef7eb2e8f9f7 482 /* Set the new LSE configuration -----------------------------------------*/
<> 144:ef7eb2e8f9f7 483 __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
<> 144:ef7eb2e8f9f7 484 /* Check the LSE State */
<> 144:ef7eb2e8f9f7 485 if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
<> 144:ef7eb2e8f9f7 486 {
<> 144:ef7eb2e8f9f7 487 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 488 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490 /* Wait till LSE is ready */
<> 144:ef7eb2e8f9f7 491 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
<> 144:ef7eb2e8f9f7 492 {
<> 144:ef7eb2e8f9f7 493 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 494 {
<> 144:ef7eb2e8f9f7 495 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 496 }
<> 144:ef7eb2e8f9f7 497 }
<> 144:ef7eb2e8f9f7 498 }
<> 144:ef7eb2e8f9f7 499 else
<> 144:ef7eb2e8f9f7 500 {
<> 144:ef7eb2e8f9f7 501 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 502 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Wait till LSE is disabled */
<> 144:ef7eb2e8f9f7 505 while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
<> 144:ef7eb2e8f9f7 506 {
<> 144:ef7eb2e8f9f7 507 if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 510 }
<> 144:ef7eb2e8f9f7 511 }
<> 144:ef7eb2e8f9f7 512 }
<> 144:ef7eb2e8f9f7 513
<> 144:ef7eb2e8f9f7 514 /* Require to disable power clock if necessary */
<> 144:ef7eb2e8f9f7 515 if(pwrclkchanged == SET)
<> 144:ef7eb2e8f9f7 516 {
<> 144:ef7eb2e8f9f7 517 __HAL_RCC_PWR_CLK_DISABLE();
<> 144:ef7eb2e8f9f7 518 }
<> 144:ef7eb2e8f9f7 519 }
<> 144:ef7eb2e8f9f7 520
<> 144:ef7eb2e8f9f7 521 /*-------------------------------- PLL Configuration -----------------------*/
<> 144:ef7eb2e8f9f7 522 /* Check the parameters */
<> 144:ef7eb2e8f9f7 523 assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
<> 144:ef7eb2e8f9f7 524 if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
<> 144:ef7eb2e8f9f7 525 {
<> 144:ef7eb2e8f9f7 526 /* Check if the PLL is used as system clock or not */
<> 144:ef7eb2e8f9f7 527 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 528 {
<> 144:ef7eb2e8f9f7 529 if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
<> 144:ef7eb2e8f9f7 530 {
<> 144:ef7eb2e8f9f7 531 /* Check the parameters */
<> 144:ef7eb2e8f9f7 532 assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
<> 144:ef7eb2e8f9f7 533 assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
<> 144:ef7eb2e8f9f7 534 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
<> 144:ef7eb2e8f9f7 535 assert_param(IS_RCC_PREDIV(RCC_OscInitStruct->PLL.PREDIV));
<> 144:ef7eb2e8f9f7 536 #endif
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 539 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 542 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 /* Wait till PLL is disabled */
<> 144:ef7eb2e8f9f7 545 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 546 {
<> 144:ef7eb2e8f9f7 547 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 548 {
<> 144:ef7eb2e8f9f7 549 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 550 }
<> 144:ef7eb2e8f9f7 551 }
<> 144:ef7eb2e8f9f7 552
<> 144:ef7eb2e8f9f7 553 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
<> 144:ef7eb2e8f9f7 554 /* Configure the main PLL clock source, predivider and multiplication factor. */
<> 144:ef7eb2e8f9f7 555 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<> 144:ef7eb2e8f9f7 556 RCC_OscInitStruct->PLL.PREDIV,
<> 144:ef7eb2e8f9f7 557 RCC_OscInitStruct->PLL.PLLMUL);
<> 144:ef7eb2e8f9f7 558 #else
<> 144:ef7eb2e8f9f7 559 /* Configure the main PLL clock source and multiplication factor. */
<> 144:ef7eb2e8f9f7 560 __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
<> 144:ef7eb2e8f9f7 561 RCC_OscInitStruct->PLL.PLLMUL);
<> 144:ef7eb2e8f9f7 562 #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
<> 144:ef7eb2e8f9f7 563 /* Enable the main PLL. */
<> 144:ef7eb2e8f9f7 564 __HAL_RCC_PLL_ENABLE();
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 567 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 568
<> 144:ef7eb2e8f9f7 569 /* Wait till PLL is ready */
<> 144:ef7eb2e8f9f7 570 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 571 {
<> 144:ef7eb2e8f9f7 572 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 573 {
<> 144:ef7eb2e8f9f7 574 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 575 }
<> 144:ef7eb2e8f9f7 576 }
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 else
<> 144:ef7eb2e8f9f7 579 {
<> 144:ef7eb2e8f9f7 580 /* Disable the main PLL. */
<> 144:ef7eb2e8f9f7 581 __HAL_RCC_PLL_DISABLE();
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 584 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 585
<> 144:ef7eb2e8f9f7 586 /* Wait till PLL is disabled */
<> 144:ef7eb2e8f9f7 587 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
<> 144:ef7eb2e8f9f7 588 {
<> 144:ef7eb2e8f9f7 589 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 590 {
<> 144:ef7eb2e8f9f7 591 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 592 }
<> 144:ef7eb2e8f9f7 593 }
<> 144:ef7eb2e8f9f7 594 }
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596 else
<> 144:ef7eb2e8f9f7 597 {
<> 144:ef7eb2e8f9f7 598 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 599 }
<> 144:ef7eb2e8f9f7 600 }
<> 144:ef7eb2e8f9f7 601
<> 144:ef7eb2e8f9f7 602 return HAL_OK;
<> 144:ef7eb2e8f9f7 603 }
<> 144:ef7eb2e8f9f7 604
<> 144:ef7eb2e8f9f7 605 /**
<> 144:ef7eb2e8f9f7 606 * @brief Initializes the CPU, AHB and APB buses clocks according to the specified
<> 144:ef7eb2e8f9f7 607 * parameters in the RCC_ClkInitStruct.
<> 144:ef7eb2e8f9f7 608 * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 609 * contains the configuration information for the RCC peripheral.
<> 144:ef7eb2e8f9f7 610 * @param FLatency FLASH Latency
<> 144:ef7eb2e8f9f7 611 * The value of this parameter depend on device used within the same series
<> 144:ef7eb2e8f9f7 612 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 613 * and updated by @ref HAL_RCC_GetHCLKFreq() function called within this function
<> 144:ef7eb2e8f9f7 614 *
<> 144:ef7eb2e8f9f7 615 * @note The HSI is used (enabled by hardware) as system clock source after
<> 144:ef7eb2e8f9f7 616 * start-up from Reset, wake-up from STOP and STANDBY mode, or in case
<> 144:ef7eb2e8f9f7 617 * of failure of the HSE used directly or indirectly as system clock
<> 144:ef7eb2e8f9f7 618 * (if the Clock Security System CSS is enabled).
<> 144:ef7eb2e8f9f7 619 *
<> 144:ef7eb2e8f9f7 620 * @note A switch from one clock source to another occurs only if the target
<> 144:ef7eb2e8f9f7 621 * clock source is ready (clock stable after start-up delay or PLL locked).
<> 144:ef7eb2e8f9f7 622 * If a clock source which is not yet ready is selected, the switch will
<> 144:ef7eb2e8f9f7 623 * occur when the clock source will be ready.
<> 144:ef7eb2e8f9f7 624 * You can use @ref HAL_RCC_GetClockConfig() function to know which clock is
<> 144:ef7eb2e8f9f7 625 * currently used as system clock source.
<> 144:ef7eb2e8f9f7 626 * @retval HAL status
<> 144:ef7eb2e8f9f7 627 */
<> 144:ef7eb2e8f9f7 628 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
<> 144:ef7eb2e8f9f7 629 {
<> 144:ef7eb2e8f9f7 630 uint32_t tickstart = 0U;
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632 /* Check the parameters */
<> 144:ef7eb2e8f9f7 633 assert_param(RCC_ClkInitStruct != NULL);
<> 144:ef7eb2e8f9f7 634 assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
<> 144:ef7eb2e8f9f7 635 assert_param(IS_FLASH_LATENCY(FLatency));
<> 144:ef7eb2e8f9f7 636
<> 144:ef7eb2e8f9f7 637 /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
<> 144:ef7eb2e8f9f7 638 must be correctly programmed according to the frequency of the CPU clock
<> 144:ef7eb2e8f9f7 639 (HCLK) of the device. */
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 /* Increasing the number of wait states because of higher CPU frequency */
<> 144:ef7eb2e8f9f7 642 if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 643 {
<> 144:ef7eb2e8f9f7 644 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 645 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 646
<> 144:ef7eb2e8f9f7 647 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 648 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 649 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 650 {
<> 144:ef7eb2e8f9f7 651 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 /*-------------------------- HCLK Configuration --------------------------*/
<> 144:ef7eb2e8f9f7 656 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
<> 144:ef7eb2e8f9f7 657 {
<> 144:ef7eb2e8f9f7 658 assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
<> 144:ef7eb2e8f9f7 659 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
<> 144:ef7eb2e8f9f7 660 }
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /*------------------------- SYSCLK Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 663 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /* HSE is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 668 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 669 {
<> 144:ef7eb2e8f9f7 670 /* Check the HSE ready flag */
<> 144:ef7eb2e8f9f7 671 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
<> 144:ef7eb2e8f9f7 672 {
<> 144:ef7eb2e8f9f7 673 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 674 }
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676 /* PLL is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 677 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 678 {
<> 144:ef7eb2e8f9f7 679 /* Check the PLL ready flag */
<> 144:ef7eb2e8f9f7 680 if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
<> 144:ef7eb2e8f9f7 681 {
<> 144:ef7eb2e8f9f7 682 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 683 }
<> 144:ef7eb2e8f9f7 684 }
<> 144:ef7eb2e8f9f7 685 /* HSI is selected as System Clock Source */
<> 144:ef7eb2e8f9f7 686 else
<> 144:ef7eb2e8f9f7 687 {
<> 144:ef7eb2e8f9f7 688 /* Check the HSI ready flag */
<> 144:ef7eb2e8f9f7 689 if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
<> 144:ef7eb2e8f9f7 690 {
<> 144:ef7eb2e8f9f7 691 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 692 }
<> 144:ef7eb2e8f9f7 693 }
<> 144:ef7eb2e8f9f7 694 __HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /* Get Start Tick */
<> 144:ef7eb2e8f9f7 697 tickstart = HAL_GetTick();
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
<> 144:ef7eb2e8f9f7 700 {
<> 144:ef7eb2e8f9f7 701 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 704 {
<> 144:ef7eb2e8f9f7 705 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 706 }
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 }
<> 144:ef7eb2e8f9f7 709 else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
<> 144:ef7eb2e8f9f7 710 {
<> 144:ef7eb2e8f9f7 711 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
<> 144:ef7eb2e8f9f7 712 {
<> 144:ef7eb2e8f9f7 713 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 716 }
<> 144:ef7eb2e8f9f7 717 }
<> 144:ef7eb2e8f9f7 718 }
<> 144:ef7eb2e8f9f7 719 else
<> 144:ef7eb2e8f9f7 720 {
<> 144:ef7eb2e8f9f7 721 while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
<> 144:ef7eb2e8f9f7 722 {
<> 144:ef7eb2e8f9f7 723 if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
<> 144:ef7eb2e8f9f7 724 {
<> 144:ef7eb2e8f9f7 725 return HAL_TIMEOUT;
<> 144:ef7eb2e8f9f7 726 }
<> 144:ef7eb2e8f9f7 727 }
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 }
<> 144:ef7eb2e8f9f7 730 /* Decreasing the number of wait states because of lower CPU frequency */
<> 144:ef7eb2e8f9f7 731 if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 734 __HAL_FLASH_SET_LATENCY(FLatency);
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Check that the new number of wait states is taken into account to access the Flash
<> 144:ef7eb2e8f9f7 737 memory by reading the FLASH_ACR register */
<> 144:ef7eb2e8f9f7 738 if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
<> 144:ef7eb2e8f9f7 739 {
<> 144:ef7eb2e8f9f7 740 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 741 }
<> 144:ef7eb2e8f9f7 742 }
<> 144:ef7eb2e8f9f7 743
<> 144:ef7eb2e8f9f7 744 /*-------------------------- PCLK1 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 745 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
<> 144:ef7eb2e8f9f7 748 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
<> 144:ef7eb2e8f9f7 749 }
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /*-------------------------- PCLK2 Configuration ---------------------------*/
<> 144:ef7eb2e8f9f7 752 if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
<> 144:ef7eb2e8f9f7 753 {
<> 144:ef7eb2e8f9f7 754 assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
<> 144:ef7eb2e8f9f7 755 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
<> 144:ef7eb2e8f9f7 756 }
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Update the SystemCoreClock global variable */
<> 144:ef7eb2e8f9f7 759 SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_BITNUMBER];
<> 144:ef7eb2e8f9f7 760
<> 144:ef7eb2e8f9f7 761 /* Configure the source of time base considering new system clocks settings*/
<> 144:ef7eb2e8f9f7 762 HAL_InitTick (TICK_INT_PRIORITY);
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764 return HAL_OK;
<> 144:ef7eb2e8f9f7 765 }
<> 144:ef7eb2e8f9f7 766
<> 144:ef7eb2e8f9f7 767 /**
<> 144:ef7eb2e8f9f7 768 * @}
<> 144:ef7eb2e8f9f7 769 */
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
<> 144:ef7eb2e8f9f7 772 * @brief RCC clocks control functions
<> 144:ef7eb2e8f9f7 773 *
<> 144:ef7eb2e8f9f7 774 @verbatim
<> 144:ef7eb2e8f9f7 775 ===============================================================================
<> 144:ef7eb2e8f9f7 776 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 777 ===============================================================================
<> 144:ef7eb2e8f9f7 778 [..]
<> 144:ef7eb2e8f9f7 779 This subsection provides a set of functions allowing to control the RCC Clocks
<> 144:ef7eb2e8f9f7 780 frequencies.
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 @endverbatim
<> 144:ef7eb2e8f9f7 783 * @{
<> 144:ef7eb2e8f9f7 784 */
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 #if defined(RCC_CFGR_MCOPRE)
<> 144:ef7eb2e8f9f7 787 /**
<> 144:ef7eb2e8f9f7 788 * @brief Selects the clock source to output on MCO pin.
<> 144:ef7eb2e8f9f7 789 * @note MCO pin should be configured in alternate function mode.
<> 144:ef7eb2e8f9f7 790 * @param RCC_MCOx specifies the output direction for the clock source.
<> 144:ef7eb2e8f9f7 791 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 792 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
<> 144:ef7eb2e8f9f7 793 * @param RCC_MCOSource specifies the clock source to output.
<> 144:ef7eb2e8f9f7 794 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 795 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected
<> 144:ef7eb2e8f9f7 796 * @arg @ref RCC_MCO1SOURCE_SYSCLK System Clock selected as MCO clock
<> 144:ef7eb2e8f9f7 797 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<> 144:ef7eb2e8f9f7 798 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<> 144:ef7eb2e8f9f7 799 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
<> 144:ef7eb2e8f9f7 800 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
<> 144:ef7eb2e8f9f7 801 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLLCLK selected as MCO clock
<> 144:ef7eb2e8f9f7 802 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
<> 144:ef7eb2e8f9f7 803 * @param RCC_MCODiv specifies the MCO DIV.
<> 144:ef7eb2e8f9f7 804 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 805 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
<> 144:ef7eb2e8f9f7 806 * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock
<> 144:ef7eb2e8f9f7 807 * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock
<> 144:ef7eb2e8f9f7 808 * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock
<> 144:ef7eb2e8f9f7 809 * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock
<> 144:ef7eb2e8f9f7 810 * @arg @ref RCC_MCODIV_32 division by 32 applied to MCO clock
<> 144:ef7eb2e8f9f7 811 * @arg @ref RCC_MCODIV_64 division by 64 applied to MCO clock
<> 144:ef7eb2e8f9f7 812 * @arg @ref RCC_MCODIV_128 division by 128 applied to MCO clock
<> 144:ef7eb2e8f9f7 813 * @retval None
<> 144:ef7eb2e8f9f7 814 */
<> 144:ef7eb2e8f9f7 815 #else
<> 144:ef7eb2e8f9f7 816 /**
<> 144:ef7eb2e8f9f7 817 * @brief Selects the clock source to output on MCO pin.
<> 144:ef7eb2e8f9f7 818 * @note MCO pin should be configured in alternate function mode.
<> 144:ef7eb2e8f9f7 819 * @param RCC_MCOx specifies the output direction for the clock source.
<> 144:ef7eb2e8f9f7 820 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 821 * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8).
<> 144:ef7eb2e8f9f7 822 * @param RCC_MCOSource specifies the clock source to output.
<> 144:ef7eb2e8f9f7 823 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 824 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
<> 144:ef7eb2e8f9f7 825 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO clock
<> 144:ef7eb2e8f9f7 826 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
<> 144:ef7eb2e8f9f7 827 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
<> 144:ef7eb2e8f9f7 828 * @arg @ref RCC_MCO1SOURCE_LSI LSI selected as MCO clock
<> 144:ef7eb2e8f9f7 829 * @arg @ref RCC_MCO1SOURCE_LSE LSE selected as MCO clock
<> 144:ef7eb2e8f9f7 830 * @arg @ref RCC_MCO1SOURCE_PLLCLK_DIV2 PLLCLK Divided by 2 selected as MCO clock
<> 144:ef7eb2e8f9f7 831 * @param RCC_MCODiv specifies the MCO DIV.
<> 144:ef7eb2e8f9f7 832 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 833 * @arg @ref RCC_MCODIV_1 no division applied to MCO clock
<> 144:ef7eb2e8f9f7 834 * @retval None
<> 144:ef7eb2e8f9f7 835 */
<> 144:ef7eb2e8f9f7 836 #endif
<> 144:ef7eb2e8f9f7 837 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 GPIO_InitTypeDef gpio = {0};
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /* Check the parameters */
<> 144:ef7eb2e8f9f7 842 assert_param(IS_RCC_MCO(RCC_MCOx));
<> 144:ef7eb2e8f9f7 843 assert_param(IS_RCC_MCODIV(RCC_MCODiv));
<> 144:ef7eb2e8f9f7 844 assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 /* Configure the MCO1 pin in alternate function mode */
<> 144:ef7eb2e8f9f7 847 gpio.Mode = GPIO_MODE_AF_PP;
<> 144:ef7eb2e8f9f7 848 gpio.Speed = GPIO_SPEED_FREQ_HIGH;
<> 144:ef7eb2e8f9f7 849 gpio.Pull = GPIO_NOPULL;
<> 144:ef7eb2e8f9f7 850 gpio.Pin = MCO1_PIN;
<> 144:ef7eb2e8f9f7 851 gpio.Alternate = GPIO_AF0_MCO;
<> 144:ef7eb2e8f9f7 852
<> 144:ef7eb2e8f9f7 853 /* MCO1 Clock Enable */
<> 144:ef7eb2e8f9f7 854 MCO1_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 855
<> 144:ef7eb2e8f9f7 856 HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
<> 144:ef7eb2e8f9f7 857
<> 144:ef7eb2e8f9f7 858 /* Configure the MCO clock source */
<> 144:ef7eb2e8f9f7 859 __HAL_RCC_MCO1_CONFIG(RCC_MCOSource, RCC_MCODiv);
<> 144:ef7eb2e8f9f7 860 }
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 /**
<> 144:ef7eb2e8f9f7 863 * @brief Enables the Clock Security System.
<> 144:ef7eb2e8f9f7 864 * @note If a failure is detected on the HSE oscillator clock, this oscillator
<> 144:ef7eb2e8f9f7 865 * is automatically disabled and an interrupt is generated to inform the
<> 144:ef7eb2e8f9f7 866 * software about the failure (Clock Security System Interrupt, CSSI),
<> 144:ef7eb2e8f9f7 867 * allowing the MCU to perform rescue operations. The CSSI is linked to
<> 144:ef7eb2e8f9f7 868 * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
<> 144:ef7eb2e8f9f7 869 * @retval None
<> 144:ef7eb2e8f9f7 870 */
<> 144:ef7eb2e8f9f7 871 void HAL_RCC_EnableCSS(void)
<> 144:ef7eb2e8f9f7 872 {
<> 144:ef7eb2e8f9f7 873 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)ENABLE;
<> 144:ef7eb2e8f9f7 874 }
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 /**
<> 144:ef7eb2e8f9f7 877 * @brief Disables the Clock Security System.
<> 144:ef7eb2e8f9f7 878 * @retval None
<> 144:ef7eb2e8f9f7 879 */
<> 144:ef7eb2e8f9f7 880 void HAL_RCC_DisableCSS(void)
<> 144:ef7eb2e8f9f7 881 {
<> 144:ef7eb2e8f9f7 882 *(__IO uint32_t *) RCC_CR_CSSON_BB = (uint32_t)DISABLE;
<> 144:ef7eb2e8f9f7 883 }
<> 144:ef7eb2e8f9f7 884
<> 144:ef7eb2e8f9f7 885 /**
<> 144:ef7eb2e8f9f7 886 * @brief Returns the SYSCLK frequency
<> 144:ef7eb2e8f9f7 887 * @note The system frequency computed by this function is not the real
<> 144:ef7eb2e8f9f7 888 * frequency in the chip. It is calculated based on the predefined
<> 144:ef7eb2e8f9f7 889 * constant and the selected clock source:
<> 144:ef7eb2e8f9f7 890 * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
<> 144:ef7eb2e8f9f7 891 * @note If SYSCLK source is HSE, function returns a value based on HSE_VALUE
<> 144:ef7eb2e8f9f7 892 * divided by PREDIV factor(**)
<> 144:ef7eb2e8f9f7 893 * @note If SYSCLK source is PLL, function returns a value based on HSE_VALUE
<> 144:ef7eb2e8f9f7 894 * divided by PREDIV factor(**) or HSI_VALUE(*) multiplied by the PLL factor.
<> 144:ef7eb2e8f9f7 895 * @note (*) HSI_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 896 * 8 MHz) but the real value may vary depending on the variations
<> 144:ef7eb2e8f9f7 897 * in voltage and temperature.
<> 144:ef7eb2e8f9f7 898 * @note (**) HSE_VALUE is a constant defined in stm32f3xx_hal_conf.h file (default value
<> 144:ef7eb2e8f9f7 899 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
<> 144:ef7eb2e8f9f7 900 * frequency of the crystal used. Otherwise, this function may
<> 144:ef7eb2e8f9f7 901 * have wrong result.
<> 144:ef7eb2e8f9f7 902 *
<> 144:ef7eb2e8f9f7 903 * @note The result of this function could be not correct when using fractional
<> 144:ef7eb2e8f9f7 904 * value for HSE crystal.
<> 144:ef7eb2e8f9f7 905 *
<> 144:ef7eb2e8f9f7 906 * @note This function can be used by the user application to compute the
<> 144:ef7eb2e8f9f7 907 * baud-rate for the communication peripherals or configure other parameters.
<> 144:ef7eb2e8f9f7 908 *
<> 144:ef7eb2e8f9f7 909 * @note Each time SYSCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 910 * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 911 *
<> 144:ef7eb2e8f9f7 912 * @retval SYSCLK frequency
<> 144:ef7eb2e8f9f7 913 */
<> 144:ef7eb2e8f9f7 914 uint32_t HAL_RCC_GetSysClockFreq(void)
<> 144:ef7eb2e8f9f7 915 {
<> 144:ef7eb2e8f9f7 916 uint32_t tmpreg = 0, prediv = 0, pllclk = 0, pllmul = 0;
<> 144:ef7eb2e8f9f7 917 uint32_t sysclockfreq = 0;
<> 144:ef7eb2e8f9f7 918
<> 144:ef7eb2e8f9f7 919 tmpreg = RCC->CFGR;
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /* Get SYSCLK source -------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 922 switch (tmpreg & RCC_CFGR_SWS)
<> 144:ef7eb2e8f9f7 923 {
<> 144:ef7eb2e8f9f7 924 case RCC_SYSCLKSOURCE_STATUS_HSE: /* HSE used as system clock */
<> 144:ef7eb2e8f9f7 925 {
<> 144:ef7eb2e8f9f7 926 sysclockfreq = HSE_VALUE;
<> 144:ef7eb2e8f9f7 927 break;
<> 144:ef7eb2e8f9f7 928 }
<> 144:ef7eb2e8f9f7 929 case RCC_SYSCLKSOURCE_STATUS_PLLCLK: /* PLL used as system clock */
<> 144:ef7eb2e8f9f7 930 {
<> 144:ef7eb2e8f9f7 931 pllmul = aPLLMULFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
<> 144:ef7eb2e8f9f7 932 prediv = aPredivFactorTable[(uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV) >> POSITION_VAL(RCC_CFGR2_PREDIV)];
<> 144:ef7eb2e8f9f7 933 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
<> 144:ef7eb2e8f9f7 934 if ((tmpreg & RCC_CFGR_PLLSRC) != RCC_PLLSOURCE_HSI)
<> 144:ef7eb2e8f9f7 935 {
<> 144:ef7eb2e8f9f7 936 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 937 pllclk = (HSE_VALUE / prediv) * pllmul;
<> 144:ef7eb2e8f9f7 938 }
<> 144:ef7eb2e8f9f7 939 else
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 /* HSI used as PLL clock source : PLLCLK = HSI/2 * PLLMUL */
<> 144:ef7eb2e8f9f7 942 pllclk = (HSI_VALUE >> 1) * pllmul;
<> 144:ef7eb2e8f9f7 943 }
<> 144:ef7eb2e8f9f7 944 #else
<> 144:ef7eb2e8f9f7 945 if ((tmpreg & RCC_CFGR_PLLSRC_HSE_PREDIV) == RCC_CFGR_PLLSRC_HSE_PREDIV)
<> 144:ef7eb2e8f9f7 946 {
<> 144:ef7eb2e8f9f7 947 /* HSE used as PLL clock source : PLLCLK = HSE/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 948 pllclk = (HSE_VALUE / prediv) * pllmul;
<> 144:ef7eb2e8f9f7 949 }
<> 144:ef7eb2e8f9f7 950 else
<> 144:ef7eb2e8f9f7 951 {
<> 144:ef7eb2e8f9f7 952 /* HSI used as PLL clock source : PLLCLK = HSI/PREDIV * PLLMUL */
<> 144:ef7eb2e8f9f7 953 pllclk = (HSI_VALUE / prediv) * pllmul;
<> 144:ef7eb2e8f9f7 954 }
<> 144:ef7eb2e8f9f7 955 #endif /* RCC_CFGR_PLLSRC_HSI_DIV2 */
<> 144:ef7eb2e8f9f7 956 sysclockfreq = pllclk;
<> 144:ef7eb2e8f9f7 957 break;
<> 144:ef7eb2e8f9f7 958 }
<> 144:ef7eb2e8f9f7 959 case RCC_SYSCLKSOURCE_STATUS_HSI: /* HSI used as system clock source */
<> 144:ef7eb2e8f9f7 960 default: /* HSI used as system clock */
<> 144:ef7eb2e8f9f7 961 {
<> 144:ef7eb2e8f9f7 962 sysclockfreq = HSI_VALUE;
<> 144:ef7eb2e8f9f7 963 break;
<> 144:ef7eb2e8f9f7 964 }
<> 144:ef7eb2e8f9f7 965 }
<> 144:ef7eb2e8f9f7 966 return sysclockfreq;
<> 144:ef7eb2e8f9f7 967 }
<> 144:ef7eb2e8f9f7 968
<> 144:ef7eb2e8f9f7 969 /**
<> 144:ef7eb2e8f9f7 970 * @brief Returns the HCLK frequency
<> 144:ef7eb2e8f9f7 971 * @note Each time HCLK changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 972 * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 973 *
<> 144:ef7eb2e8f9f7 974 * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
<> 144:ef7eb2e8f9f7 975 * and updated within this function
<> 144:ef7eb2e8f9f7 976 * @retval HCLK frequency
<> 144:ef7eb2e8f9f7 977 */
<> 144:ef7eb2e8f9f7 978 uint32_t HAL_RCC_GetHCLKFreq(void)
<> 144:ef7eb2e8f9f7 979 {
<> 144:ef7eb2e8f9f7 980 return SystemCoreClock;
<> 144:ef7eb2e8f9f7 981 }
<> 144:ef7eb2e8f9f7 982
<> 144:ef7eb2e8f9f7 983 /**
<> 144:ef7eb2e8f9f7 984 * @brief Returns the PCLK1 frequency
<> 144:ef7eb2e8f9f7 985 * @note Each time PCLK1 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 986 * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 987 * @retval PCLK1 frequency
<> 144:ef7eb2e8f9f7 988 */
<> 144:ef7eb2e8f9f7 989 uint32_t HAL_RCC_GetPCLK1Freq(void)
<> 144:ef7eb2e8f9f7 990 {
<> 144:ef7eb2e8f9f7 991 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
<> 144:ef7eb2e8f9f7 992 return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_BITNUMBER]);
<> 144:ef7eb2e8f9f7 993 }
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /**
<> 144:ef7eb2e8f9f7 996 * @brief Returns the PCLK2 frequency
<> 144:ef7eb2e8f9f7 997 * @note Each time PCLK2 changes, this function must be called to update the
<> 144:ef7eb2e8f9f7 998 * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
<> 144:ef7eb2e8f9f7 999 * @retval PCLK2 frequency
<> 144:ef7eb2e8f9f7 1000 */
<> 144:ef7eb2e8f9f7 1001 uint32_t HAL_RCC_GetPCLK2Freq(void)
<> 144:ef7eb2e8f9f7 1002 {
<> 144:ef7eb2e8f9f7 1003 /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
<> 144:ef7eb2e8f9f7 1004 return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_BITNUMBER]);
<> 144:ef7eb2e8f9f7 1005 }
<> 144:ef7eb2e8f9f7 1006
<> 144:ef7eb2e8f9f7 1007 /**
<> 144:ef7eb2e8f9f7 1008 * @brief Configures the RCC_OscInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1009 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1010 * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1011 * will be configured.
<> 144:ef7eb2e8f9f7 1012 * @retval None
<> 144:ef7eb2e8f9f7 1013 */
<> 144:ef7eb2e8f9f7 1014 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
<> 144:ef7eb2e8f9f7 1015 {
<> 144:ef7eb2e8f9f7 1016 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1017 assert_param(RCC_OscInitStruct != NULL);
<> 144:ef7eb2e8f9f7 1018
<> 144:ef7eb2e8f9f7 1019 /* Set all possible values for the Oscillator type parameter ---------------*/
<> 144:ef7eb2e8f9f7 1020 RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI \
<> 144:ef7eb2e8f9f7 1021 | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
<> 144:ef7eb2e8f9f7 1022
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /* Get the HSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1025 if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
<> 144:ef7eb2e8f9f7 1026 {
<> 144:ef7eb2e8f9f7 1027 RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
<> 144:ef7eb2e8f9f7 1028 }
<> 144:ef7eb2e8f9f7 1029 else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
<> 144:ef7eb2e8f9f7 1030 {
<> 144:ef7eb2e8f9f7 1031 RCC_OscInitStruct->HSEState = RCC_HSE_ON;
<> 144:ef7eb2e8f9f7 1032 }
<> 144:ef7eb2e8f9f7 1033 else
<> 144:ef7eb2e8f9f7 1034 {
<> 144:ef7eb2e8f9f7 1035 RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
<> 144:ef7eb2e8f9f7 1036 }
<> 144:ef7eb2e8f9f7 1037 #if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
<> 144:ef7eb2e8f9f7 1038 RCC_OscInitStruct->HSEPredivValue = __HAL_RCC_HSE_GET_PREDIV();
<> 144:ef7eb2e8f9f7 1039 #endif
<> 144:ef7eb2e8f9f7 1040
<> 144:ef7eb2e8f9f7 1041 /* Get the HSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1042 if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
<> 144:ef7eb2e8f9f7 1043 {
<> 144:ef7eb2e8f9f7 1044 RCC_OscInitStruct->HSIState = RCC_HSI_ON;
<> 144:ef7eb2e8f9f7 1045 }
<> 144:ef7eb2e8f9f7 1046 else
<> 144:ef7eb2e8f9f7 1047 {
<> 144:ef7eb2e8f9f7 1048 RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
<> 144:ef7eb2e8f9f7 1049 }
<> 144:ef7eb2e8f9f7 1050
<> 144:ef7eb2e8f9f7 1051 RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR & RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
<> 144:ef7eb2e8f9f7 1052
<> 144:ef7eb2e8f9f7 1053 /* Get the LSE configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1054 if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
<> 144:ef7eb2e8f9f7 1055 {
<> 144:ef7eb2e8f9f7 1056 RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
<> 144:ef7eb2e8f9f7 1057 }
<> 144:ef7eb2e8f9f7 1058 else if((RCC->BDCR &RCC_BDCR_LSEON) == RCC_BDCR_LSEON)
<> 144:ef7eb2e8f9f7 1059 {
<> 144:ef7eb2e8f9f7 1060 RCC_OscInitStruct->LSEState = RCC_LSE_ON;
<> 144:ef7eb2e8f9f7 1061 }
<> 144:ef7eb2e8f9f7 1062 else
<> 144:ef7eb2e8f9f7 1063 {
<> 144:ef7eb2e8f9f7 1064 RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
<> 144:ef7eb2e8f9f7 1065 }
<> 144:ef7eb2e8f9f7 1066
<> 144:ef7eb2e8f9f7 1067 /* Get the LSI configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1068 if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
<> 144:ef7eb2e8f9f7 1069 {
<> 144:ef7eb2e8f9f7 1070 RCC_OscInitStruct->LSIState = RCC_LSI_ON;
<> 144:ef7eb2e8f9f7 1071 }
<> 144:ef7eb2e8f9f7 1072 else
<> 144:ef7eb2e8f9f7 1073 {
<> 144:ef7eb2e8f9f7 1074 RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
<> 144:ef7eb2e8f9f7 1075 }
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077
<> 144:ef7eb2e8f9f7 1078 /* Get the PLL configuration -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1079 if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
<> 144:ef7eb2e8f9f7 1080 {
<> 144:ef7eb2e8f9f7 1081 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
<> 144:ef7eb2e8f9f7 1082 }
<> 144:ef7eb2e8f9f7 1083 else
<> 144:ef7eb2e8f9f7 1084 {
<> 144:ef7eb2e8f9f7 1085 RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
<> 144:ef7eb2e8f9f7 1086 }
<> 144:ef7eb2e8f9f7 1087 RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
<> 144:ef7eb2e8f9f7 1088 RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
<> 144:ef7eb2e8f9f7 1089 #if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
<> 144:ef7eb2e8f9f7 1090 RCC_OscInitStruct->PLL.PREDIV = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PREDIV);
<> 144:ef7eb2e8f9f7 1091 #endif /* RCC_CFGR_PLLSRC_HSI_PREDIV */
<> 144:ef7eb2e8f9f7 1092 }
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /**
<> 144:ef7eb2e8f9f7 1095 * @brief Get the RCC_ClkInitStruct according to the internal
<> 144:ef7eb2e8f9f7 1096 * RCC configuration registers.
<> 144:ef7eb2e8f9f7 1097 * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
<> 144:ef7eb2e8f9f7 1098 * contains the current clock configuration.
<> 144:ef7eb2e8f9f7 1099 * @param pFLatency Pointer on the Flash Latency.
<> 144:ef7eb2e8f9f7 1100 * @retval None
<> 144:ef7eb2e8f9f7 1101 */
<> 144:ef7eb2e8f9f7 1102 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
<> 144:ef7eb2e8f9f7 1103 {
<> 144:ef7eb2e8f9f7 1104 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1105 assert_param(RCC_ClkInitStruct != NULL);
<> 144:ef7eb2e8f9f7 1106 assert_param(pFLatency != NULL);
<> 144:ef7eb2e8f9f7 1107
<> 144:ef7eb2e8f9f7 1108 /* Set all possible values for the Clock type parameter --------------------*/
<> 144:ef7eb2e8f9f7 1109 RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /* Get the SYSCLK configuration --------------------------------------------*/
<> 144:ef7eb2e8f9f7 1112 RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
<> 144:ef7eb2e8f9f7 1113
<> 144:ef7eb2e8f9f7 1114 /* Get the HCLK configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1115 RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
<> 144:ef7eb2e8f9f7 1116
<> 144:ef7eb2e8f9f7 1117 /* Get the APB1 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1118 RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
<> 144:ef7eb2e8f9f7 1119
<> 144:ef7eb2e8f9f7 1120 /* Get the APB2 configuration ----------------------------------------------*/
<> 144:ef7eb2e8f9f7 1121 RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
<> 144:ef7eb2e8f9f7 1122
<> 144:ef7eb2e8f9f7 1123 /* Get the Flash Wait State (Latency) configuration ------------------------*/
<> 144:ef7eb2e8f9f7 1124 *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126
<> 144:ef7eb2e8f9f7 1127 /**
<> 144:ef7eb2e8f9f7 1128 * @brief This function handles the RCC CSS interrupt request.
<> 144:ef7eb2e8f9f7 1129 * @note This API should be called under the NMI_Handler().
<> 144:ef7eb2e8f9f7 1130 * @retval None
<> 144:ef7eb2e8f9f7 1131 */
<> 144:ef7eb2e8f9f7 1132 void HAL_RCC_NMI_IRQHandler(void)
<> 144:ef7eb2e8f9f7 1133 {
<> 144:ef7eb2e8f9f7 1134 /* Check RCC CSSF flag */
<> 144:ef7eb2e8f9f7 1135 if(__HAL_RCC_GET_IT(RCC_IT_CSS))
<> 144:ef7eb2e8f9f7 1136 {
<> 144:ef7eb2e8f9f7 1137 /* RCC Clock Security System interrupt user callback */
<> 144:ef7eb2e8f9f7 1138 HAL_RCC_CSSCallback();
<> 144:ef7eb2e8f9f7 1139
<> 144:ef7eb2e8f9f7 1140 /* Clear RCC CSS pending bit */
<> 144:ef7eb2e8f9f7 1141 __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
<> 144:ef7eb2e8f9f7 1142 }
<> 144:ef7eb2e8f9f7 1143 }
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 /**
<> 144:ef7eb2e8f9f7 1146 * @brief RCC Clock Security System interrupt callback
<> 144:ef7eb2e8f9f7 1147 * @retval none
<> 144:ef7eb2e8f9f7 1148 */
<> 144:ef7eb2e8f9f7 1149 __weak void HAL_RCC_CSSCallback(void)
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1152 the HAL_RCC_CSSCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154 }
<> 144:ef7eb2e8f9f7 1155
<> 144:ef7eb2e8f9f7 1156 /**
<> 144:ef7eb2e8f9f7 1157 * @}
<> 144:ef7eb2e8f9f7 1158 */
<> 144:ef7eb2e8f9f7 1159
<> 144:ef7eb2e8f9f7 1160 /**
<> 144:ef7eb2e8f9f7 1161 * @}
<> 144:ef7eb2e8f9f7 1162 */
<> 144:ef7eb2e8f9f7 1163
<> 144:ef7eb2e8f9f7 1164 #endif /* HAL_RCC_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1165 /**
<> 144:ef7eb2e8f9f7 1166 * @}
<> 144:ef7eb2e8f9f7 1167 */
<> 144:ef7eb2e8f9f7 1168
<> 144:ef7eb2e8f9f7 1169 /**
<> 144:ef7eb2e8f9f7 1170 * @}
<> 144:ef7eb2e8f9f7 1171 */
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/