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MPU6050.h@7:1f92801f7b0f, 2018-12-01 (annotated)
- Committer:
- Stas285
- Date:
- Sat Dec 01 14:20:24 2018 +0000
- Revision:
- 7:1f92801f7b0f
- Parent:
- 1:cf3a9ec7205e
Coord_ready
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
ritarosakai | 0:6d1b9bcd64ca | 1 | #ifndef __MPU6050_H |
ritarosakai | 0:6d1b9bcd64ca | 2 | #define __MPU6050_H |
ritarosakai | 0:6d1b9bcd64ca | 3 | |
ritarosakai | 0:6d1b9bcd64ca | 4 | #include "mbed.h" |
ritarosakai | 0:6d1b9bcd64ca | 5 | |
ritarosakai | 0:6d1b9bcd64ca | 6 | #define MPU6050_XG_OFFS_TC 0x00 |
ritarosakai | 0:6d1b9bcd64ca | 7 | #define MPU6050_YG_OFFS_TC 0x01 |
ritarosakai | 0:6d1b9bcd64ca | 8 | #define MPU6050_ZG_OFFS_TC 0x02 |
ritarosakai | 0:6d1b9bcd64ca | 9 | #define MPU6050_X_FINE_GAIN 0x03 |
ritarosakai | 0:6d1b9bcd64ca | 10 | #define MPU6050_Y_FINE_GAIN 0x04 |
ritarosakai | 0:6d1b9bcd64ca | 11 | #define MPU6050_Z_FINE_GAIN 0x05 |
ritarosakai | 0:6d1b9bcd64ca | 12 | #define MPU6050_XA_OFFS_H 0x06 |
ritarosakai | 0:6d1b9bcd64ca | 13 | #define MPU6050_XA_OFFS_L_TC 0x07 |
ritarosakai | 0:6d1b9bcd64ca | 14 | #define MPU6050_YA_OFFS_H 0x08 |
ritarosakai | 0:6d1b9bcd64ca | 15 | #define MPU6050_YA_OFFS_L_TC 0x09 |
ritarosakai | 0:6d1b9bcd64ca | 16 | #define MPU6050_ZA_OFFS_H 0x0A |
ritarosakai | 0:6d1b9bcd64ca | 17 | #define MPU6050_ZA_OFFS_L_TC 0x0B |
ritarosakai | 0:6d1b9bcd64ca | 18 | #define MPU6050_XG_OFFS_USRH 0x13 |
ritarosakai | 0:6d1b9bcd64ca | 19 | #define MPU6050_XG_OFFS_USRL 0x14 |
ritarosakai | 0:6d1b9bcd64ca | 20 | #define MPU6050_YG_OFFS_USRH 0x15 |
ritarosakai | 0:6d1b9bcd64ca | 21 | #define MPU6050_YG_OFFS_USRL 0x16 |
ritarosakai | 0:6d1b9bcd64ca | 22 | #define MPU6050_ZG_OFFS_USRH 0x17 |
ritarosakai | 0:6d1b9bcd64ca | 23 | #define MPU6050_ZG_OFFS_USRL 0x18 |
ritarosakai | 0:6d1b9bcd64ca | 24 | #define MPU6050_SMPLRT_DIV 0x19 |
ritarosakai | 0:6d1b9bcd64ca | 25 | #define MPU6050_CONFIG 0x1A |
ritarosakai | 0:6d1b9bcd64ca | 26 | #define MPU6050_GYRO_CONFIG 0x1B |
ritarosakai | 0:6d1b9bcd64ca | 27 | #define MPU6050_ACCEL_CONFIG 0x1C |
ritarosakai | 0:6d1b9bcd64ca | 28 | #define MPU6050_FF_THR 0x1D |
ritarosakai | 0:6d1b9bcd64ca | 29 | #define MPU6050_FF_DUR 0x1E |
ritarosakai | 0:6d1b9bcd64ca | 30 | #define MPU6050_MOT_THR 0x1F |
ritarosakai | 0:6d1b9bcd64ca | 31 | #define MPU6050_MOT_DUR 0x20 |
ritarosakai | 0:6d1b9bcd64ca | 32 | #define MPU6050_ZRMOT_THR 0x21 |
ritarosakai | 0:6d1b9bcd64ca | 33 | #define MPU6050_ZRMOT_DUR 0x22 |
ritarosakai | 0:6d1b9bcd64ca | 34 | #define MPU6050_FIFO_EN 0x23 |
ritarosakai | 0:6d1b9bcd64ca | 35 | #define MPU6050_I2C_MST_CTRL 0x24 |
ritarosakai | 0:6d1b9bcd64ca | 36 | #define MPU6050_I2C_SLV0_ADDR 0x25 |
ritarosakai | 0:6d1b9bcd64ca | 37 | #define MPU6050_I2C_SLV0_REG 0x26 |
ritarosakai | 0:6d1b9bcd64ca | 38 | #define MPU6050_I2C_SLV0_CTRL 0x27 |
ritarosakai | 0:6d1b9bcd64ca | 39 | #define MPU6050_I2C_SLV1_ADDR 0x28 |
ritarosakai | 0:6d1b9bcd64ca | 40 | #define MPU6050_I2C_SLV1_REG 0x29 |
ritarosakai | 0:6d1b9bcd64ca | 41 | #define MPU6050_I2C_SLV1_CTRL 0x2A |
ritarosakai | 0:6d1b9bcd64ca | 42 | #define MPU6050_I2C_SLV2_ADDR 0x2B |
ritarosakai | 0:6d1b9bcd64ca | 43 | #define MPU6050_I2C_SLV2_REG 0x2C |
ritarosakai | 0:6d1b9bcd64ca | 44 | #define MPU6050_I2C_SLV2_CTRL 0x2D |
ritarosakai | 0:6d1b9bcd64ca | 45 | #define MPU6050_I2C_SLV3_ADDR 0x2E |
ritarosakai | 0:6d1b9bcd64ca | 46 | #define MPU6050_I2C_SLV3_REG 0x2F |
ritarosakai | 0:6d1b9bcd64ca | 47 | #define MPU6050_I2C_SLV3_CTRL 0x30 |
ritarosakai | 0:6d1b9bcd64ca | 48 | #define MPU6050_I2C_SLV4_ADDR 0x31 |
ritarosakai | 0:6d1b9bcd64ca | 49 | #define MPU6050_I2C_SLV4_REG 0x32 |
ritarosakai | 0:6d1b9bcd64ca | 50 | #define MPU6050_I2C_SLV4_DO 0x33 |
ritarosakai | 0:6d1b9bcd64ca | 51 | #define MPU6050_I2C_SLV4_CTRL 0x34 |
ritarosakai | 0:6d1b9bcd64ca | 52 | #define MPU6050_I2C_SLV4_DI 0x35 |
ritarosakai | 0:6d1b9bcd64ca | 53 | #define MPU6050_I2C_MST_STATUS 0x36 |
ritarosakai | 0:6d1b9bcd64ca | 54 | #define MPU6050_INT_PIN_CFG 0x37 |
ritarosakai | 0:6d1b9bcd64ca | 55 | #define MPU6050_INT_ENABLE 0x38 |
ritarosakai | 0:6d1b9bcd64ca | 56 | #define MPU6050_DMP_INT_STATUS 0x39 |
ritarosakai | 0:6d1b9bcd64ca | 57 | #define MPU6050_INT_STATUS 0x3A |
ritarosakai | 0:6d1b9bcd64ca | 58 | #define MPU6050_ACCEL_XOUT_H 0x3B |
ritarosakai | 0:6d1b9bcd64ca | 59 | #define MPU6050_ACCEL_XOUT_L 0x3C |
ritarosakai | 0:6d1b9bcd64ca | 60 | #define MPU6050_ACCEL_YOUT_H 0x3D |
ritarosakai | 0:6d1b9bcd64ca | 61 | #define MPU6050_ACCEL_YOUT_L 0x3E |
ritarosakai | 0:6d1b9bcd64ca | 62 | #define MPU6050_ACCEL_ZOUT_H 0x3F |
ritarosakai | 0:6d1b9bcd64ca | 63 | #define MPU6050_ACCEL_ZOUT_L 0x40 |
ritarosakai | 0:6d1b9bcd64ca | 64 | #define MPU6050_TEMP_OUT_H 0x41 |
ritarosakai | 0:6d1b9bcd64ca | 65 | #define MPU6050_TEMP_OUT_L 0x42 |
ritarosakai | 0:6d1b9bcd64ca | 66 | #define MPU6050_GYRO_XOUT_H 0x43 |
ritarosakai | 0:6d1b9bcd64ca | 67 | #define MPU6050_GYRO_XOUT_L 0x44 |
ritarosakai | 0:6d1b9bcd64ca | 68 | #define MPU6050_GYRO_YOUT_H 0x45 |
ritarosakai | 0:6d1b9bcd64ca | 69 | #define MPU6050_GYRO_YOUT_L 0x46 |
ritarosakai | 0:6d1b9bcd64ca | 70 | #define MPU6050_GYRO_ZOUT_H 0x47 |
ritarosakai | 0:6d1b9bcd64ca | 71 | #define MPU6050_GYRO_ZOUT_L 0x48 |
ritarosakai | 0:6d1b9bcd64ca | 72 | #define MPU6050_EXT_SENS_DATA_00 0x49 |
ritarosakai | 0:6d1b9bcd64ca | 73 | #define MPU6050_EXT_SENS_DATA_01 0x4A |
ritarosakai | 0:6d1b9bcd64ca | 74 | #define MPU6050_EXT_SENS_DATA_02 0x4B |
ritarosakai | 0:6d1b9bcd64ca | 75 | #define MPU6050_EXT_SENS_DATA_03 0x4C |
ritarosakai | 0:6d1b9bcd64ca | 76 | #define MPU6050_EXT_SENS_DATA_04 0x4D |
ritarosakai | 0:6d1b9bcd64ca | 77 | #define MPU6050_EXT_SENS_DATA_05 0x4E |
ritarosakai | 0:6d1b9bcd64ca | 78 | #define MPU6050_EXT_SENS_DATA_06 0x4F |
ritarosakai | 0:6d1b9bcd64ca | 79 | #define MPU6050_EXT_SENS_DATA_07 0x50 |
ritarosakai | 0:6d1b9bcd64ca | 80 | #define MPU6050_EXT_SENS_DATA_08 0x51 |
ritarosakai | 0:6d1b9bcd64ca | 81 | #define MPU6050_EXT_SENS_DATA_09 0x52 |
ritarosakai | 0:6d1b9bcd64ca | 82 | #define MPU6050_EXT_SENS_DATA_10 0x53 |
ritarosakai | 0:6d1b9bcd64ca | 83 | #define MPU6050_EXT_SENS_DATA_11 0x54 |
ritarosakai | 0:6d1b9bcd64ca | 84 | #define MPU6050_EXT_SENS_DATA_12 0x55 |
ritarosakai | 0:6d1b9bcd64ca | 85 | #define MPU6050_EXT_SENS_DATA_13 0x56 |
ritarosakai | 0:6d1b9bcd64ca | 86 | #define MPU6050_EXT_SENS_DATA_14 0x57 |
ritarosakai | 0:6d1b9bcd64ca | 87 | #define MPU6050_EXT_SENS_DATA_15 0x58 |
ritarosakai | 0:6d1b9bcd64ca | 88 | #define MPU6050_EXT_SENS_DATA_16 0x59 |
ritarosakai | 0:6d1b9bcd64ca | 89 | #define MPU6050_EXT_SENS_DATA_17 0x5A |
ritarosakai | 0:6d1b9bcd64ca | 90 | #define MPU6050_EXT_SENS_DATA_18 0x5B |
ritarosakai | 0:6d1b9bcd64ca | 91 | #define MPU6050_EXT_SENS_DATA_19 0x5C |
ritarosakai | 0:6d1b9bcd64ca | 92 | #define MPU6050_EXT_SENS_DATA_20 0x5D |
ritarosakai | 0:6d1b9bcd64ca | 93 | #define MPU6050_EXT_SENS_DATA_21 0x5E |
ritarosakai | 0:6d1b9bcd64ca | 94 | #define MPU6050_EXT_SENS_DATA_22 0x5F |
ritarosakai | 0:6d1b9bcd64ca | 95 | #define MPU6050_EXT_SENS_DATA_23 0x60 |
ritarosakai | 0:6d1b9bcd64ca | 96 | #define MPU6050_MOT_DETECT_STATUS 0x61 |
ritarosakai | 0:6d1b9bcd64ca | 97 | #define MPU6050_I2C_SLV0_DO 0x63 |
ritarosakai | 0:6d1b9bcd64ca | 98 | #define MPU6050_I2C_SLV1_DO 0x64 |
ritarosakai | 0:6d1b9bcd64ca | 99 | #define MPU6050_I2C_SLV2_DO 0x65 |
ritarosakai | 0:6d1b9bcd64ca | 100 | #define MPU6050_I2C_SLV3_DO 0x66 |
ritarosakai | 0:6d1b9bcd64ca | 101 | #define MPU6050_I2C_MST_DELAY_CTRL 0x67 |
ritarosakai | 0:6d1b9bcd64ca | 102 | #define MPU6050_SIGNAL_PATH_RESET 0x68 |
ritarosakai | 0:6d1b9bcd64ca | 103 | #define MPU6050_MOT_DETECT_CTRL 0x69 |
ritarosakai | 0:6d1b9bcd64ca | 104 | #define MPU6050_USER_CTRL 0x6A |
ritarosakai | 0:6d1b9bcd64ca | 105 | #define MPU6050_PWR_MGMT_1 0x6B |
ritarosakai | 0:6d1b9bcd64ca | 106 | #define MPU6050_PWR_MGMT_2 0x6C |
ritarosakai | 0:6d1b9bcd64ca | 107 | #define MPU6050_BANK_SEL 0x6D |
ritarosakai | 0:6d1b9bcd64ca | 108 | #define MPU6050_MEM_START_ADDR 0x6E |
ritarosakai | 0:6d1b9bcd64ca | 109 | #define MPU6050_MEM_R_W 0x6F |
ritarosakai | 0:6d1b9bcd64ca | 110 | #define MPU6050_DMP_CFG_1 0x70 |
ritarosakai | 0:6d1b9bcd64ca | 111 | #define MPU6050_DMP_CFG_2 0x71 |
ritarosakai | 0:6d1b9bcd64ca | 112 | #define MPU6050_FIFO_COUNTH 0x72 |
ritarosakai | 0:6d1b9bcd64ca | 113 | #define MPU6050_FIFO_COUNTL 0x73 |
ritarosakai | 0:6d1b9bcd64ca | 114 | #define MPU6050_FIFO_R_W 0x74 |
ritarosakai | 0:6d1b9bcd64ca | 115 | #define MPU6050_WHO_AM_I 0x75 |
ritarosakai | 0:6d1b9bcd64ca | 116 | class MPU6050 |
ritarosakai | 0:6d1b9bcd64ca | 117 | { |
ritarosakai | 0:6d1b9bcd64ca | 118 | public: |
ritarosakai | 0:6d1b9bcd64ca | 119 | MPU6050(PinName sda, PinName scl); |
ritarosakai | 0:6d1b9bcd64ca | 120 | void start(void); |
ritarosakai | 0:6d1b9bcd64ca | 121 | char getID(void); |
ritarosakai | 0:6d1b9bcd64ca | 122 | bool read(float *gx, float *gy, float *gz,float *ax, float *ay, float *az); |
ritarosakai | 1:cf3a9ec7205e | 123 | bool readraw(int *gx, int *gy, int *gz,int *ax, int *ay, int *az); |
ritarosakai | 0:6d1b9bcd64ca | 124 | private: |
ritarosakai | 0:6d1b9bcd64ca | 125 | I2C _MPU6050; |
ritarosakai | 0:6d1b9bcd64ca | 126 | float gx, gy, gz,ax,ay,az; |
ritarosakai | 0:6d1b9bcd64ca | 127 | bool write_reg(int addr_i2c,int addr_reg, char v); |
ritarosakai | 0:6d1b9bcd64ca | 128 | bool read_reg(int addr_i2c,int addr_reg, char *v); |
ritarosakai | 0:6d1b9bcd64ca | 129 | bool read_data(char sad, char sub, char *buf, int length); |
ritarosakai | 0:6d1b9bcd64ca | 130 | }; |
ritarosakai | 0:6d1b9bcd64ca | 131 | |
ritarosakai | 0:6d1b9bcd64ca | 132 | #endif |