Andrew Lindsay / RF12B

RFM12B radio module driver library

Dependents:   IoTGateway_Basic

RF12B.cpp@0:e724d8251cdc, 2012-03-31 (annotated)

Committer:
SomeRandomBloke
Date:
Sat Mar 31 07:11:16 2012 +0000
Revision:
0:e724d8251cdc
Updated and cleaned up

Who changed what in which revision?

UserRevisionLine numberNew contents of line
SomeRandomBloke 0:e724d8251cdc 1 /* RF12B Library. Based on work done by JeeLabs.org ported to mbed by SK Pang.
SomeRandomBloke 0:e724d8251cdc 2 http://jeelabs.net/projects/cafe/wiki/RF12
SomeRandomBloke 0:e724d8251cdc 3
SomeRandomBloke 0:e724d8251cdc 4 http://opensource.org/licenses/mit-license.php
SomeRandomBloke 0:e724d8251cdc 5
SomeRandomBloke 0:e724d8251cdc 6 Jan 2012 skpang.co.uk
SomeRandomBloke 0:e724d8251cdc 7
SomeRandomBloke 0:e724d8251cdc 8 Modified by Andrew Lindsay (andrew [at] thiseldo [dot] co [dot] uk)
SomeRandomBloke 0:e724d8251cdc 9
SomeRandomBloke 0:e724d8251cdc 10 Permission is hereby granted, free of charge, to any person obtaining a copy
SomeRandomBloke 0:e724d8251cdc 11 of this software and associated documentation files (the "Software"), to deal
SomeRandomBloke 0:e724d8251cdc 12 in the Software without restriction, including without limitation the rights
SomeRandomBloke 0:e724d8251cdc 13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
SomeRandomBloke 0:e724d8251cdc 14 copies of the Software, and to permit persons to whom the Software is
SomeRandomBloke 0:e724d8251cdc 15 furnished to do so, subject to the following conditions:
SomeRandomBloke 0:e724d8251cdc 16
SomeRandomBloke 0:e724d8251cdc 17 The above copyright notice and this permission notice shall be included in
SomeRandomBloke 0:e724d8251cdc 18 all copies or substantial portions of the Software.
SomeRandomBloke 0:e724d8251cdc 19
SomeRandomBloke 0:e724d8251cdc 20 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
SomeRandomBloke 0:e724d8251cdc 21 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
SomeRandomBloke 0:e724d8251cdc 22 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
SomeRandomBloke 0:e724d8251cdc 23 AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
SomeRandomBloke 0:e724d8251cdc 24 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
SomeRandomBloke 0:e724d8251cdc 25 OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
SomeRandomBloke 0:e724d8251cdc 26 THE SOFTWARE.
SomeRandomBloke 0:e724d8251cdc 27 */
SomeRandomBloke 0:e724d8251cdc 28
SomeRandomBloke 0:e724d8251cdc 29 #include "RF12B.h"
SomeRandomBloke 0:e724d8251cdc 30
SomeRandomBloke 0:e724d8251cdc 31 DigitalOut led4(LED4, "led4");
SomeRandomBloke 0:e724d8251cdc 32
SomeRandomBloke 0:e724d8251cdc 33 // RF12 command codes
SomeRandomBloke 0:e724d8251cdc 34 #define RF_RECEIVER_ON 0x82DD
SomeRandomBloke 0:e724d8251cdc 35 #define RF_XMITTER_ON 0x823D
SomeRandomBloke 0:e724d8251cdc 36 #define RF_IDLE_MODE 0x820D
SomeRandomBloke 0:e724d8251cdc 37 #define RF_SLEEP_MODE 0x8205
SomeRandomBloke 0:e724d8251cdc 38 #define RF_WAKEUP_MODE 0x8207
SomeRandomBloke 0:e724d8251cdc 39 #define RF_TXREG_WRITE 0xB800
SomeRandomBloke 0:e724d8251cdc 40 #define RF_RX_FIFO_READ 0xB000
SomeRandomBloke 0:e724d8251cdc 41 #define RF_WAKEUP_TIMER 0xE000
SomeRandomBloke 0:e724d8251cdc 42
SomeRandomBloke 0:e724d8251cdc 43 // RF12 status bits
SomeRandomBloke 0:e724d8251cdc 44 #define RF_LBD_BIT 0x0400
SomeRandomBloke 0:e724d8251cdc 45 #define RF_RSSI_BIT 0x0100
SomeRandomBloke 0:e724d8251cdc 46
SomeRandomBloke 0:e724d8251cdc 47 // bits in the node id configuration byte
SomeRandomBloke 0:e724d8251cdc 48 #define NODE_BAND 0xC0 // frequency band
SomeRandomBloke 0:e724d8251cdc 49 #define NODE_ACKANY 0x20 // ack on broadcast packets if set
SomeRandomBloke 0:e724d8251cdc 50 #define NODE_ID 0x1F // id of this node, as A..Z or 1..31
SomeRandomBloke 0:e724d8251cdc 51
SomeRandomBloke 0:e724d8251cdc 52 // transceiver states, these determine what to do with each interrupt
SomeRandomBloke 0:e724d8251cdc 53 enum {
SomeRandomBloke 0:e724d8251cdc 54 TXCRC1, TXCRC2, TXTAIL, TXDONE, TXIDLE,
SomeRandomBloke 0:e724d8251cdc 55 TXRECV,
SomeRandomBloke 0:e724d8251cdc 56 TXPRE1, TXPRE2, TXPRE3, TXSYN1, TXSYN2,
SomeRandomBloke 0:e724d8251cdc 57 };
SomeRandomBloke 0:e724d8251cdc 58
SomeRandomBloke 0:e724d8251cdc 59 RF12B::RF12B(PinName _SDI,
SomeRandomBloke 0:e724d8251cdc 60 PinName _SDO,
SomeRandomBloke 0:e724d8251cdc 61 PinName _SCK,
SomeRandomBloke 0:e724d8251cdc 62 PinName _NCS,
SomeRandomBloke 0:e724d8251cdc 63 PinName _NIRQ):spi(_SDI, _SDO, _SCK),
SomeRandomBloke 0:e724d8251cdc 64 NCS(_NCS), NIRQ(_NIRQ), NIRQ_in(_NIRQ) {
SomeRandomBloke 0:e724d8251cdc 65
SomeRandomBloke 0:e724d8251cdc 66 /* SPI frequency, 8 bit word length, polarity and phase */
SomeRandomBloke 0:e724d8251cdc 67 spi.format(8,0);
SomeRandomBloke 0:e724d8251cdc 68 spi.frequency(2000000);
SomeRandomBloke 0:e724d8251cdc 69
SomeRandomBloke 0:e724d8251cdc 70 /* Set ~CS high */
SomeRandomBloke 0:e724d8251cdc 71 NCS = 1;
SomeRandomBloke 0:e724d8251cdc 72
SomeRandomBloke 0:e724d8251cdc 73 /* Setup interrupt to happen on falling edge of NIRQ */
SomeRandomBloke 0:e724d8251cdc 74 NIRQ.fall(this, &RF12B::rxISR);
SomeRandomBloke 0:e724d8251cdc 75 }
SomeRandomBloke 0:e724d8251cdc 76
SomeRandomBloke 0:e724d8251cdc 77
SomeRandomBloke 0:e724d8251cdc 78 /**********************************************************************
SomeRandomBloke 0:e724d8251cdc 79 * PRIVATE FUNCTIONS
SomeRandomBloke 0:e724d8251cdc 80 *********************************************************************/
SomeRandomBloke 0:e724d8251cdc 81
SomeRandomBloke 0:e724d8251cdc 82 /* Initialises the RF12B module */
SomeRandomBloke 0:e724d8251cdc 83 void RF12B::init(uint8_t id, uint8_t band, uint8_t g) {
SomeRandomBloke 0:e724d8251cdc 84
SomeRandomBloke 0:e724d8251cdc 85 nodeid = id;
SomeRandomBloke 0:e724d8251cdc 86 group = g;
SomeRandomBloke 0:e724d8251cdc 87 rf12_grp = g;
SomeRandomBloke 0:e724d8251cdc 88
SomeRandomBloke 0:e724d8251cdc 89 writeCmd(0x0000); // intitial SPI transfer added to avoid power-up problem
SomeRandomBloke 0:e724d8251cdc 90 writeCmd(RF_SLEEP_MODE); // DC (disable clk pin), enable lbd
SomeRandomBloke 0:e724d8251cdc 91
SomeRandomBloke 0:e724d8251cdc 92 // wait until RFM12B is out of power-up reset, this takes several *seconds*
SomeRandomBloke 0:e724d8251cdc 93 writeCmd(RF_TXREG_WRITE); // in case we're still in OOK mode
SomeRandomBloke 0:e724d8251cdc 94
SomeRandomBloke 0:e724d8251cdc 95 while (NIRQ == 0) writeCmd(0x0000);
SomeRandomBloke 0:e724d8251cdc 96
SomeRandomBloke 0:e724d8251cdc 97 // TODO: Have band specific parameters to optimise settings
SomeRandomBloke 0:e724d8251cdc 98
SomeRandomBloke 0:e724d8251cdc 99 writeCmd(0x80C7 | (band << 4)); // EL (ena TX), EF (ena RX FIFO), 12.0pF
SomeRandomBloke 0:e724d8251cdc 100 writeCmd(0xA640); // 868MHz
SomeRandomBloke 0:e724d8251cdc 101 writeCmd(0xC606); // approx 49.2 Kbps, i.e. 10000/29/(1+6) Kbps
SomeRandomBloke 0:e724d8251cdc 102 writeCmd(0x94A2); // VDI,FAST,134kHz,0dBm,-91dBm
SomeRandomBloke 0:e724d8251cdc 103 writeCmd(0xC2AC); // AL,!ml,DIG,DQD4
SomeRandomBloke 0:e724d8251cdc 104 if (group != 0) {
SomeRandomBloke 0:e724d8251cdc 105 writeCmd(0xCA83); // FIFO8,2-SYNC,!ff,DR
SomeRandomBloke 0:e724d8251cdc 106 writeCmd(0xCE00 | group); // SYNC=2DXX
SomeRandomBloke 0:e724d8251cdc 107 } else {
SomeRandomBloke 0:e724d8251cdc 108 writeCmd(0xCA8B); // FIFO8,1-SYNC,!ff,DR
SomeRandomBloke 0:e724d8251cdc 109 writeCmd(0xCE2D); // SYNC=2D
SomeRandomBloke 0:e724d8251cdc 110 }
SomeRandomBloke 0:e724d8251cdc 111
SomeRandomBloke 0:e724d8251cdc 112 writeCmd(0xC483); // @PWR,NO RSTRIC,!st,!fi,OE,EN
SomeRandomBloke 0:e724d8251cdc 113 writeCmd(0x9850); // !mp,90kHz,MAX OUT
SomeRandomBloke 0:e724d8251cdc 114 writeCmd(0xCC77); // OB1, OB0, LPX, ddy, DDIT, BW0
SomeRandomBloke 0:e724d8251cdc 115 writeCmd(0xE000); // NOT USE
SomeRandomBloke 0:e724d8251cdc 116 writeCmd(0xC800); // NOT USE
SomeRandomBloke 0:e724d8251cdc 117 writeCmd(0xC049); // 1.66MHz,3.1V
SomeRandomBloke 0:e724d8251cdc 118
SomeRandomBloke 0:e724d8251cdc 119 rxstate = TXIDLE;
SomeRandomBloke 0:e724d8251cdc 120
SomeRandomBloke 0:e724d8251cdc 121 }
SomeRandomBloke 0:e724d8251cdc 122
SomeRandomBloke 0:e724d8251cdc 123 int RF12B::available( void ) {
SomeRandomBloke 0:e724d8251cdc 124
SomeRandomBloke 0:e724d8251cdc 125 return (rf12_recvDone() && (check_crc() == 0) && length() < 66) ? length() : 0;
SomeRandomBloke 0:e724d8251cdc 126 }
SomeRandomBloke 0:e724d8251cdc 127
SomeRandomBloke 0:e724d8251cdc 128 /* Write a command to the RF Module */
SomeRandomBloke 0:e724d8251cdc 129 int RF12B::writeCmd(int cmd) {
SomeRandomBloke 0:e724d8251cdc 130 NCS = 0;
SomeRandomBloke 0:e724d8251cdc 131 int recv = spi.write(cmd >>8);
SomeRandomBloke 0:e724d8251cdc 132 recv = spi.write(cmd);
SomeRandomBloke 0:e724d8251cdc 133 NCS = 1;
SomeRandomBloke 0:e724d8251cdc 134 return recv;
SomeRandomBloke 0:e724d8251cdc 135 }
SomeRandomBloke 0:e724d8251cdc 136
SomeRandomBloke 0:e724d8251cdc 137 /* Sends a byte of data across RF */
SomeRandomBloke 0:e724d8251cdc 138 void RF12B::send(uint8_t data) {
SomeRandomBloke 0:e724d8251cdc 139 while (NIRQ);
SomeRandomBloke 0:e724d8251cdc 140 writeCmd(0xB800 + data);
SomeRandomBloke 0:e724d8251cdc 141 }
SomeRandomBloke 0:e724d8251cdc 142
SomeRandomBloke 0:e724d8251cdc 143
SomeRandomBloke 0:e724d8251cdc 144 /* Interrupt routine for data reception and Txing */
SomeRandomBloke 0:e724d8251cdc 145 void RF12B::rxISR() {
SomeRandomBloke 0:e724d8251cdc 146 led4 = 1;
SomeRandomBloke 0:e724d8251cdc 147 // a transfer of 2x 16 bits @ 2 MHz over SPI takes 2x 8 us inside this ISR
SomeRandomBloke 0:e724d8251cdc 148 writeCmd(0x0000);
SomeRandomBloke 0:e724d8251cdc 149
SomeRandomBloke 0:e724d8251cdc 150 if (rxstate == TXRECV) {
SomeRandomBloke 0:e724d8251cdc 151 uint8_t in = rf12_xfer(RF_RX_FIFO_READ);
SomeRandomBloke 0:e724d8251cdc 152
SomeRandomBloke 0:e724d8251cdc 153 if (rxfill == 0 && group != 0)
SomeRandomBloke 0:e724d8251cdc 154 rf12_buf[rxfill++] = group;
SomeRandomBloke 0:e724d8251cdc 155
SomeRandomBloke 0:e724d8251cdc 156 rf12_buf[rxfill++] = in;
SomeRandomBloke 0:e724d8251cdc 157 rf12_crc = _crc16_update(rf12_crc, in);
SomeRandomBloke 0:e724d8251cdc 158
SomeRandomBloke 0:e724d8251cdc 159 if (rxfill >= rf12_len + 5 || rxfill >= RF_MAX)
SomeRandomBloke 0:e724d8251cdc 160 rf12_xfer(RF_IDLE_MODE);
SomeRandomBloke 0:e724d8251cdc 161 } else {
SomeRandomBloke 0:e724d8251cdc 162 uint8_t out;
SomeRandomBloke 0:e724d8251cdc 163
SomeRandomBloke 0:e724d8251cdc 164 if (rxstate < 0) {
SomeRandomBloke 0:e724d8251cdc 165 uint8_t pos = 3 + rf12_len + rxstate++;
SomeRandomBloke 0:e724d8251cdc 166 out = rf12_buf[pos];
SomeRandomBloke 0:e724d8251cdc 167 rf12_crc = _crc16_update(rf12_crc, out);
SomeRandomBloke 0:e724d8251cdc 168 } else {
SomeRandomBloke 0:e724d8251cdc 169 switch (rxstate++) {
SomeRandomBloke 0:e724d8251cdc 170 case TXSYN1:
SomeRandomBloke 0:e724d8251cdc 171 out = 0x2D;
SomeRandomBloke 0:e724d8251cdc 172 break;
SomeRandomBloke 0:e724d8251cdc 173 case TXSYN2:
SomeRandomBloke 0:e724d8251cdc 174 out = rf12_grp;
SomeRandomBloke 0:e724d8251cdc 175 rxstate = - (2 + rf12_len);
SomeRandomBloke 0:e724d8251cdc 176 break;
SomeRandomBloke 0:e724d8251cdc 177 case TXCRC1:
SomeRandomBloke 0:e724d8251cdc 178 out = rf12_crc;
SomeRandomBloke 0:e724d8251cdc 179 break;
SomeRandomBloke 0:e724d8251cdc 180 case TXCRC2:
SomeRandomBloke 0:e724d8251cdc 181 out = rf12_crc >> 8;
SomeRandomBloke 0:e724d8251cdc 182 break;
SomeRandomBloke 0:e724d8251cdc 183 case TXDONE:
SomeRandomBloke 0:e724d8251cdc 184 rf12_xfer(RF_IDLE_MODE); // fall through
SomeRandomBloke 0:e724d8251cdc 185 default:
SomeRandomBloke 0:e724d8251cdc 186 out = 0xAA;
SomeRandomBloke 0:e724d8251cdc 187 }
SomeRandomBloke 0:e724d8251cdc 188 }
SomeRandomBloke 0:e724d8251cdc 189 rf12_xfer(RF_TXREG_WRITE + out);
SomeRandomBloke 0:e724d8251cdc 190 }
SomeRandomBloke 0:e724d8251cdc 191 led4 = 0;
SomeRandomBloke 0:e724d8251cdc 192 }
SomeRandomBloke 0:e724d8251cdc 193
SomeRandomBloke 0:e724d8251cdc 194
SomeRandomBloke 0:e724d8251cdc 195 void RF12B::rf12_sendStart (uint8_t hdr, const void* ptr, uint8_t len) {
SomeRandomBloke 0:e724d8251cdc 196 rf12_len = len;
SomeRandomBloke 0:e724d8251cdc 197 memcpy((void*) rf12_data, ptr, len);
SomeRandomBloke 0:e724d8251cdc 198 rf12_sendStart(hdr);
SomeRandomBloke 0:e724d8251cdc 199 }
SomeRandomBloke 0:e724d8251cdc 200
SomeRandomBloke 0:e724d8251cdc 201 //void RF12B::rf12_sendStart2 (uint8_t hdr) {
SomeRandomBloke 0:e724d8251cdc 202 void RF12B::rf12_sendStart (uint8_t hdr) {
SomeRandomBloke 0:e724d8251cdc 203 rf12_hdr = hdr & RF12_HDR_DST ? hdr :
SomeRandomBloke 0:e724d8251cdc 204 (hdr & ~RF12_HDR_MASK) + (nodeid & NODE_ID);
SomeRandomBloke 0:e724d8251cdc 205
SomeRandomBloke 0:e724d8251cdc 206 /*
SomeRandomBloke 0:e724d8251cdc 207 if (crypter != 0)
SomeRandomBloke 0:e724d8251cdc 208 crypter(1);
SomeRandomBloke 0:e724d8251cdc 209 */
SomeRandomBloke 0:e724d8251cdc 210 rf12_crc = ~0;
SomeRandomBloke 0:e724d8251cdc 211
SomeRandomBloke 0:e724d8251cdc 212 rf12_crc = _crc16_update(rf12_crc, rf12_grp);
SomeRandomBloke 0:e724d8251cdc 213 rxstate = TXPRE1;
SomeRandomBloke 0:e724d8251cdc 214
SomeRandomBloke 0:e724d8251cdc 215 rf12_xfer(RF_XMITTER_ON); // bytes will be fed via interrupts
SomeRandomBloke 0:e724d8251cdc 216 }
SomeRandomBloke 0:e724d8251cdc 217
SomeRandomBloke 0:e724d8251cdc 218
SomeRandomBloke 0:e724d8251cdc 219 uint16_t RF12B::rf12_xfer (uint16_t cmd) {
SomeRandomBloke 0:e724d8251cdc 220 NCS = 0;
SomeRandomBloke 0:e724d8251cdc 221 uint16_t reply = rf12_byte(cmd >> 8) << 8;
SomeRandomBloke 0:e724d8251cdc 222 reply |= rf12_byte(cmd);
SomeRandomBloke 0:e724d8251cdc 223 NCS = 1;
SomeRandomBloke 0:e724d8251cdc 224 return reply;
SomeRandomBloke 0:e724d8251cdc 225 }
SomeRandomBloke 0:e724d8251cdc 226
SomeRandomBloke 0:e724d8251cdc 227 void RF12B::rf12_recvStart (void) {
SomeRandomBloke 0:e724d8251cdc 228 rxfill = rf12_len = 0;
SomeRandomBloke 0:e724d8251cdc 229 rf12_crc = ~0;
SomeRandomBloke 0:e724d8251cdc 230
SomeRandomBloke 0:e724d8251cdc 231 if (group != 0)
SomeRandomBloke 0:e724d8251cdc 232 rf12_crc = _crc16_update(~0, group);
SomeRandomBloke 0:e724d8251cdc 233
SomeRandomBloke 0:e724d8251cdc 234 rxstate = TXRECV;
SomeRandomBloke 0:e724d8251cdc 235 rf12_xfer(RF_RECEIVER_ON);
SomeRandomBloke 0:e724d8251cdc 236 }
SomeRandomBloke 0:e724d8251cdc 237
SomeRandomBloke 0:e724d8251cdc 238 uint16_t RF12B::check_crc(void) {
SomeRandomBloke 0:e724d8251cdc 239 return rf12_crc;
SomeRandomBloke 0:e724d8251cdc 240 }
SomeRandomBloke 0:e724d8251cdc 241
SomeRandomBloke 0:e724d8251cdc 242 uint8_t RF12B::length(void) {
SomeRandomBloke 0:e724d8251cdc 243 return rf12_len;
SomeRandomBloke 0:e724d8251cdc 244 }
SomeRandomBloke 0:e724d8251cdc 245
SomeRandomBloke 0:e724d8251cdc 246 uint8_t* RF12B::get_data(void) {
SomeRandomBloke 0:e724d8251cdc 247 return (uint8_t*)rf12_buf;
SomeRandomBloke 0:e724d8251cdc 248 }
SomeRandomBloke 0:e724d8251cdc 249
SomeRandomBloke 0:e724d8251cdc 250 uint8_t* RF12B::get_payload(void) {
SomeRandomBloke 0:e724d8251cdc 251 return (uint8_t*)rf12_data;
SomeRandomBloke 0:e724d8251cdc 252 }
SomeRandomBloke 0:e724d8251cdc 253
SomeRandomBloke 0:e724d8251cdc 254 uint8_t RF12B::rf12_recvDone (void) {
SomeRandomBloke 0:e724d8251cdc 255
SomeRandomBloke 0:e724d8251cdc 256 if (rxstate == TXRECV && (rxfill >= rf12_len + 5 || rxfill >= RF_MAX)) {
SomeRandomBloke 0:e724d8251cdc 257 rxstate = TXIDLE;
SomeRandomBloke 0:e724d8251cdc 258
SomeRandomBloke 0:e724d8251cdc 259 if (rf12_len > RF12_MAXDATA)
SomeRandomBloke 0:e724d8251cdc 260 rf12_crc = 1; // force bad crc if packet length is invalid
SomeRandomBloke 0:e724d8251cdc 261 if (!(rf12_hdr & RF12_HDR_DST) || (nodeid & NODE_ID) == 31 ||
SomeRandomBloke 0:e724d8251cdc 262 (rf12_hdr & RF12_HDR_MASK) == (nodeid & NODE_ID)) {
SomeRandomBloke 0:e724d8251cdc 263 /*
SomeRandomBloke 0:e724d8251cdc 264 printf("RX Len: %d ", rf12_len+6);
SomeRandomBloke 0:e724d8251cdc 265 for (int i=0; i<rf12_len+6; i++) {
SomeRandomBloke 0:e724d8251cdc 266 printf("%02X ",rf12_buf[i]);
SomeRandomBloke 0:e724d8251cdc 267 }
SomeRandomBloke 0:e724d8251cdc 268 printf(" crc:%x\n",rf12_crc);
SomeRandomBloke 0:e724d8251cdc 269 */
SomeRandomBloke 0:e724d8251cdc 270 /*
SomeRandomBloke 0:e724d8251cdc 271 if (rf12_crc == 0 && crypter != 0)
SomeRandomBloke 0:e724d8251cdc 272 crypter(0);
SomeRandomBloke 0:e724d8251cdc 273 else
SomeRandomBloke 0:e724d8251cdc 274 rf12_seq = -1;
SomeRandomBloke 0:e724d8251cdc 275 */
SomeRandomBloke 0:e724d8251cdc 276 return 1; // it's a broadcast packet or it's addressed to this node
SomeRandomBloke 0:e724d8251cdc 277
SomeRandomBloke 0:e724d8251cdc 278 }
SomeRandomBloke 0:e724d8251cdc 279 }
SomeRandomBloke 0:e724d8251cdc 280 if (rxstate == TXIDLE)
SomeRandomBloke 0:e724d8251cdc 281 rf12_recvStart();
SomeRandomBloke 0:e724d8251cdc 282 return 0;
SomeRandomBloke 0:e724d8251cdc 283 }
SomeRandomBloke 0:e724d8251cdc 284
SomeRandomBloke 0:e724d8251cdc 285 uint8_t RF12B::rf12_byte(uint8_t out) {
SomeRandomBloke 0:e724d8251cdc 286 // unsigned char recv = spi.write(out);
SomeRandomBloke 0:e724d8251cdc 287 // return recv;
SomeRandomBloke 0:e724d8251cdc 288 return spi.write(out);
SomeRandomBloke 0:e724d8251cdc 289 }
SomeRandomBloke 0:e724d8251cdc 290
SomeRandomBloke 0:e724d8251cdc 291 uint16_t RF12B::_crc16_update(uint16_t crc, uint8_t data) {
SomeRandomBloke 0:e724d8251cdc 292 int i;
SomeRandomBloke 0:e724d8251cdc 293
SomeRandomBloke 0:e724d8251cdc 294 crc ^= data;
SomeRandomBloke 0:e724d8251cdc 295 for (i = 0; i < 8; ++i) {
SomeRandomBloke 0:e724d8251cdc 296 if (crc & 1)
SomeRandomBloke 0:e724d8251cdc 297 crc = (crc >> 1) ^ 0xA001;
SomeRandomBloke 0:e724d8251cdc 298 else
SomeRandomBloke 0:e724d8251cdc 299 crc = (crc >> 1);
SomeRandomBloke 0:e724d8251cdc 300 }
SomeRandomBloke 0:e724d8251cdc 301
SomeRandomBloke 0:e724d8251cdc 302 return crc;
SomeRandomBloke 0:e724d8251cdc 303 }