Andrew Lindsay / BSP_DISCO_F429ZI

Additional font macro

Dependents:   EspSerial

STM32F429I-Discovery/stm32f429i_discovery_sdram.h@1:a6fd0931a9e9, 2016-02-05 (annotated)

Committer:
SomeRandomBloke
Date:
Fri Feb 05 09:20:30 2016 +0000
Revision:
1:a6fd0931a9e9
Parent:
0:e1d164542663 
Added additional font macro

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bcostm 0:e1d164542663 1 /**
bcostm 0:e1d164542663 2 ******************************************************************************
bcostm 0:e1d164542663 3 * @file stm32f429i_discovery_sdram.h
bcostm 0:e1d164542663 4 * @author MCD Application Team
bcostm 0:e1d164542663 5 * @version V2.1.2
bcostm 0:e1d164542663 6 * @date 02-March-2015
bcostm 0:e1d164542663 7 * @brief This file contains all the functions prototypes for the
bcostm 0:e1d164542663 8 * stm32f429i_discovery_sdram.c driver.
bcostm 0:e1d164542663 9 ******************************************************************************
bcostm 0:e1d164542663 10 * @attention
bcostm 0:e1d164542663 11 *
bcostm 0:e1d164542663 12 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bcostm 0:e1d164542663 13 *
bcostm 0:e1d164542663 14 * Redistribution and use in source and binary forms, with or without modification,
bcostm 0:e1d164542663 15 * are permitted provided that the following conditions are met:
bcostm 0:e1d164542663 16 * 1. Redistributions of source code must retain the above copyright notice,
bcostm 0:e1d164542663 17 * this list of conditions and the following disclaimer.
bcostm 0:e1d164542663 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
bcostm 0:e1d164542663 19 * this list of conditions and the following disclaimer in the documentation
bcostm 0:e1d164542663 20 * and/or other materials provided with the distribution.
bcostm 0:e1d164542663 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bcostm 0:e1d164542663 22 * may be used to endorse or promote products derived from this software
bcostm 0:e1d164542663 23 * without specific prior written permission.
bcostm 0:e1d164542663 24 *
bcostm 0:e1d164542663 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bcostm 0:e1d164542663 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bcostm 0:e1d164542663 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bcostm 0:e1d164542663 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bcostm 0:e1d164542663 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bcostm 0:e1d164542663 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bcostm 0:e1d164542663 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bcostm 0:e1d164542663 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bcostm 0:e1d164542663 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bcostm 0:e1d164542663 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bcostm 0:e1d164542663 35 *
bcostm 0:e1d164542663 36 ******************************************************************************
bcostm 0:e1d164542663 37 */
bcostm 0:e1d164542663 38
bcostm 0:e1d164542663 39 /* Define to prevent recursive inclusion -------------------------------------*/
bcostm 0:e1d164542663 40 #ifndef __STM32F429I_DISCOVERY_SDRAM_H
bcostm 0:e1d164542663 41 #define __STM32F429I_DISCOVERY_SDRAM_H
bcostm 0:e1d164542663 42
bcostm 0:e1d164542663 43 #ifdef __cplusplus
bcostm 0:e1d164542663 44 extern "C" {
bcostm 0:e1d164542663 45 #endif
bcostm 0:e1d164542663 46
bcostm 0:e1d164542663 47 /* Includes ------------------------------------------------------------------*/
bcostm 0:e1d164542663 48 #include "stm32f429i_discovery.h"
bcostm 0:e1d164542663 49
bcostm 0:e1d164542663 50 /** @addtogroup BSP
bcostm 0:e1d164542663 51 * @{
bcostm 0:e1d164542663 52 */
bcostm 0:e1d164542663 53
bcostm 0:e1d164542663 54 /** @addtogroup STM32F429I_DISCOVERY
bcostm 0:e1d164542663 55 * @{
bcostm 0:e1d164542663 56 */
bcostm 0:e1d164542663 57
bcostm 0:e1d164542663 58 /** @defgroup STM32F429I_DISCOVERY_SDRAM
bcostm 0:e1d164542663 59 * @{
bcostm 0:e1d164542663 60 */
bcostm 0:e1d164542663 61
bcostm 0:e1d164542663 62 /** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Types
bcostm 0:e1d164542663 63 * @{
bcostm 0:e1d164542663 64 */
bcostm 0:e1d164542663 65 /**
bcostm 0:e1d164542663 66 * @}
bcostm 0:e1d164542663 67 */
bcostm 0:e1d164542663 68
bcostm 0:e1d164542663 69 /** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Constants
bcostm 0:e1d164542663 70 * @{
bcostm 0:e1d164542663 71 */
bcostm 0:e1d164542663 72 /**
bcostm 0:e1d164542663 73 * @brief FMC SDRAM Bank address
bcostm 0:e1d164542663 74 */
bcostm 0:e1d164542663 75 #define SDRAM_DEVICE_ADDR ((uint32_t)0xD0000000)
bcostm 0:e1d164542663 76 #define SDRAM_DEVICE_SIZE ((uint32_t)0x800000) /* SDRAM device size in MBytes */
bcostm 0:e1d164542663 77
bcostm 0:e1d164542663 78 /**
bcostm 0:e1d164542663 79 * @brief FMC SDRAM Memory Width
bcostm 0:e1d164542663 80 */
bcostm 0:e1d164542663 81 /* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
bcostm 0:e1d164542663 82 #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
bcostm 0:e1d164542663 83
bcostm 0:e1d164542663 84 /**
bcostm 0:e1d164542663 85 * @brief FMC SDRAM CAS Latency
bcostm 0:e1d164542663 86 */
bcostm 0:e1d164542663 87 /* #define SDRAM_CAS_LATENCY FMC_SDRAM_CAS_LATENCY_2 */
bcostm 0:e1d164542663 88 #define SDRAM_CAS_LATENCY FMC_SDRAM_CAS_LATENCY_3
bcostm 0:e1d164542663 89
bcostm 0:e1d164542663 90 /**
bcostm 0:e1d164542663 91 * @brief FMC SDRAM Memory clock period
bcostm 0:e1d164542663 92 */
bcostm 0:e1d164542663 93 #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_2 /* Default configuration used with LCD */
bcostm 0:e1d164542663 94 /* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
bcostm 0:e1d164542663 95
bcostm 0:e1d164542663 96 /**
bcostm 0:e1d164542663 97 * @brief FMC SDRAM Memory Read Burst feature
bcostm 0:e1d164542663 98 */
bcostm 0:e1d164542663 99 #define SDRAM_READBURST FMC_SDRAM_RBURST_DISABLE /* Default configuration used with LCD */
bcostm 0:e1d164542663 100 /* #define SDRAM_READBURST FMC_SDRAM_RBURST_ENABLE */
bcostm 0:e1d164542663 101
bcostm 0:e1d164542663 102 /**
bcostm 0:e1d164542663 103 * @brief FMC SDRAM Bank Remap
bcostm 0:e1d164542663 104 */
bcostm 0:e1d164542663 105 /* #define SDRAM_BANK_REMAP */
bcostm 0:e1d164542663 106
bcostm 0:e1d164542663 107 /* Set the refresh rate counter */
bcostm 0:e1d164542663 108 /* (15.62 us x Freq) - 20 */
bcostm 0:e1d164542663 109 #define REFRESH_COUNT ((uint32_t)1386) /* SDRAM refresh counter */
bcostm 0:e1d164542663 110 #define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
bcostm 0:e1d164542663 111
bcostm 0:e1d164542663 112 /* DMA definitions for SDRAM DMA transfer */
bcostm 0:e1d164542663 113 #define __DMAx_CLK_ENABLE __DMA2_CLK_ENABLE
bcostm 0:e1d164542663 114 #define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
bcostm 0:e1d164542663 115 #define SDRAM_DMAx_STREAM DMA2_Stream0
bcostm 0:e1d164542663 116 #define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
bcostm 0:e1d164542663 117 #define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
bcostm 0:e1d164542663 118
bcostm 0:e1d164542663 119 /**
bcostm 0:e1d164542663 120 * @brief FMC SDRAM Mode definition register defines
bcostm 0:e1d164542663 121 */
bcostm 0:e1d164542663 122 #define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
bcostm 0:e1d164542663 123 #define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
bcostm 0:e1d164542663 124 #define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
bcostm 0:e1d164542663 125 #define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
bcostm 0:e1d164542663 126 #define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
bcostm 0:e1d164542663 127 #define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
bcostm 0:e1d164542663 128 #define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
bcostm 0:e1d164542663 129 #define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
bcostm 0:e1d164542663 130 #define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
bcostm 0:e1d164542663 131 #define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
bcostm 0:e1d164542663 132 #define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
bcostm 0:e1d164542663 133 /**
bcostm 0:e1d164542663 134 * @}
bcostm 0:e1d164542663 135 */
bcostm 0:e1d164542663 136
bcostm 0:e1d164542663 137 /** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Macro
bcostm 0:e1d164542663 138 * @{
bcostm 0:e1d164542663 139 */
bcostm 0:e1d164542663 140 /**
bcostm 0:e1d164542663 141 * @}
bcostm 0:e1d164542663 142 */
bcostm 0:e1d164542663 143
bcostm 0:e1d164542663 144 /** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Functions
bcostm 0:e1d164542663 145 * @{
bcostm 0:e1d164542663 146 */
bcostm 0:e1d164542663 147 void BSP_SDRAM_Init(void);
bcostm 0:e1d164542663 148 void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
bcostm 0:e1d164542663 149 void BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t* pData, uint32_t uwDataSize);
bcostm 0:e1d164542663 150 void BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t* pData, uint32_t uwDataSize);
bcostm 0:e1d164542663 151 void BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t* pData, uint32_t uwDataSize);
bcostm 0:e1d164542663 152 void BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t* pData, uint32_t uwDataSize);
bcostm 0:e1d164542663 153 HAL_StatusTypeDef BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef *SdramCmd);
bcostm 0:e1d164542663 154 void BSP_SDRAM_DMA_IRQHandler(void);
bcostm 0:e1d164542663 155
bcostm 0:e1d164542663 156 /**
bcostm 0:e1d164542663 157 * @}
bcostm 0:e1d164542663 158 */
bcostm 0:e1d164542663 159
bcostm 0:e1d164542663 160 /**
bcostm 0:e1d164542663 161 * @}
bcostm 0:e1d164542663 162 */
bcostm 0:e1d164542663 163
bcostm 0:e1d164542663 164 /**
bcostm 0:e1d164542663 165 * @}
bcostm 0:e1d164542663 166 */
bcostm 0:e1d164542663 167
bcostm 0:e1d164542663 168 /**
bcostm 0:e1d164542663 169 * @}
bcostm 0:e1d164542663 170 */
bcostm 0:e1d164542663 171
bcostm 0:e1d164542663 172 #ifdef __cplusplus
bcostm 0:e1d164542663 173 }
bcostm 0:e1d164542663 174 #endif
bcostm 0:e1d164542663 175
bcostm 0:e1d164542663 176 #endif /* __STM32F429I_DISCOVERY_SDRAM_H */
bcostm 0:e1d164542663 177
bcostm 0:e1d164542663 178 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/