Simon Yang
/
BenchCoreMark
RunCoreMark on STM32F091
Fork of ClockControl by
Diff: ClockControl/ClockControl.cpp
- Revision:
- 1:7d0a41d6624f
- Parent:
- 0:b5d3bd64d2dc
diff -r b5d3bd64d2dc -r 7d0a41d6624f ClockControl/ClockControl.cpp --- a/ClockControl/ClockControl.cpp Sun Jan 24 15:46:26 2010 +0000 +++ b/ClockControl/ClockControl.cpp Thu Sep 03 08:50:31 2015 +0000 @@ -2,36 +2,16 @@ void setPLL0Frequency(unsigned char clkSrc, unsigned short M, unsigned char N) { - LPC_SC->CLKSRCSEL = clkSrc; - LPC_SC->PLL0CFG = (((unsigned int)N-1) << 16) | M-1; - LPC_SC->PLL0CON = 0x01; - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; - while (!(LPC_SC->PLL0STAT & (1<<26))); - - LPC_SC->PLL0CON = 0x03; - LPC_SC->PLL0FEED = 0xAA; - LPC_SC->PLL0FEED = 0x55; + } void setPLL1Frequency(unsigned char clkSrc, unsigned short M, unsigned char N) { - LPC_SC->CLKSRCSEL = clkSrc; - LPC_SC->PLL1CFG = (((unsigned int)N-1) << 16) | M-1; - LPC_SC->PLL1CON = 0x01; - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; - while (!(LPC_SC->PLL1STAT & (1<<26))); - - LPC_SC->PLL1CON = 0x03; - LPC_SC->PLL1FEED = 0xAA; - LPC_SC->PLL1FEED = 0x55; + } unsigned int setSystemFrequency(unsigned char clkDivider, unsigned char clkSrc, unsigned short M, unsigned char N) { - setPLL0Frequency(clkSrc, M, N); - LPC_SC->CCLKCFG = clkDivider - 1; - SystemCoreClockUpdate(); - return SystemCoreClock; + +return 0; } \ No newline at end of file