system_MKL25Z4.c

00001 /*
00002 ** ###################################################################
00003 **     Processor:           MKL25Z128VLK4
00004 **     Compilers:           ARM Compiler
00005 **                          Freescale C/C++ for Embedded ARM
00006 **                          GNU C Compiler
00007 **                          IAR ANSI C/C++ Compiler for ARM
00008 **
00009 **     Reference manual:    KL25RM, Rev.1, Jun 2012
00010 **     Version:             rev. 1.1, 2012-06-21
00011 **
00012 **     Abstract:
00013 **         Provides a system configuration function and a global variable that
00014 **         contains the system frequency. It configures the device and initializes
00015 **         the oscillator (PLL) that is part of the microcontroller device.
00016 **
00017 **     Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved.
00018 **
00019 **     http:                 www.freescale.com
00020 **     mail:                 support@freescale.com
00021 **
00022 **     Revisions:
00023 **     - rev. 1.0 (2012-06-13)
00024 **         Initial version.
00025 **     - rev. 1.1 (2012-06-21)
00026 **         Update according to reference manual rev. 1.
00027 **
00028 ** ###################################################################
00029 */
00030 
00031 /**
00032  * @file MKL25Z4
00033  * @version 1.1
00034  * @date 2012-06-21
00035  * @brief Device specific configuration file for MKL25Z4 (implementation file)
00036  *
00037  * Provides a system configuration function and a global variable that contains
00038  * the system frequency. It configures the device and initializes the oscillator
00039  * (PLL) that is part of the microcontroller device.
00040  */
00041 
00042 #include <stdint.h>
00043 #include "MKL25Z4.h"
00044 
00045 #define DISABLE_WDOG    1
00046 
00047 #define CLOCK_SETUP     1
00048 /* Predefined clock setups
00049    0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
00050          Reference clock source for MCG module is the slow internal clock source 32.768kHz
00051          Core clock = 41.94MHz, BusClock = 13.98MHz
00052    1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode
00053          Reference clock source for MCG module is an external crystal 8MHz
00054          Core clock = 48MHz, BusClock = 24MHz
00055    2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode
00056          Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication
00057          Core clock = 8MHz, BusClock = 8MHz
00058 */
00059 
00060 /*----------------------------------------------------------------------------
00061   Define clock source values
00062  *----------------------------------------------------------------------------*/
00063 #if (CLOCK_SETUP == 0)
00064     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00065     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00066     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00067     #define DEFAULT_SYSTEM_CLOCK            41943040u /* Default System clock value */
00068 #elif (CLOCK_SETUP == 1)
00069     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00070     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00071     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00072     #define DEFAULT_SYSTEM_CLOCK            48000000u /* Default System clock value */
00073 #elif (CLOCK_SETUP == 2)
00074     #define CPU_XTAL_CLK_HZ                 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */
00075     #define CPU_INT_SLOW_CLK_HZ             32768u   /* Value of the slow internal oscillator clock frequency in Hz  */
00076     #define CPU_INT_FAST_CLK_HZ             4000000u /* Value of the fast internal oscillator clock frequency in Hz  */
00077     #define DEFAULT_SYSTEM_CLOCK            8000000u /* Default System clock value */
00078 #endif /* (CLOCK_SETUP == 2) */
00079 
00080 
00081 /* ----------------------------------------------------------------------------
00082    -- Core clock
00083    ---------------------------------------------------------------------------- */
00084 
00085 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
00086 
00087 /* ----------------------------------------------------------------------------
00088    -- SystemInit()
00089    ---------------------------------------------------------------------------- */
00090 
00091 void SystemInit (void) {
00092 #if (DISABLE_WDOG)
00093   /* Disable the WDOG module */
00094   /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
00095   SIM->COPC = (uint32_t)0x00u;
00096 #endif /* (DISABLE_WDOG) */
00097 #if (CLOCK_SETUP == 0)
00098   /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=2,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
00099   SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */
00100   /* Switch to FEI Mode */
00101   /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
00102   MCG->C1 = (uint8_t)0x06U;
00103   /* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
00104   MCG->C2 = (uint8_t)0x00U;
00105   /* MCG->C4: DMX32=0,DRST_DRS=1 */
00106   MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U);
00107   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
00108   OSC0->CR = (uint8_t)0x80U;
00109   /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
00110   MCG->C5 = (uint8_t)0x00U;
00111   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00112   MCG->C6 = (uint8_t)0x00U;
00113   while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
00114   }
00115   while((MCG->S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
00116   }
00117 #elif (CLOCK_SETUP == 1)
00118   /* SIM->SCGC5: PORTA=1 */
00119   SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
00120   /* SIM->CLKDIV1: OUTDIV1=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
00121   SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */
00122   /* PORTA->PCR18: ISF=0,MUX=0 */
00123   PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
00124   /* PORTA->PCR19: ISF=0,MUX=0 */
00125   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
00126   /* Switch to FBE Mode */
00127   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
00128   OSC0->CR = (uint8_t)0x89U;
00129   /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
00130   MCG->C2 = (uint8_t)0x24U;
00131   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00132   MCG->C1 = (uint8_t)0x9AU;
00133   /* MCG->C4: DMX32=0,DRST_DRS=0 */
00134   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
00135   /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
00136   MCG->C5 = (uint8_t)0x01U;
00137   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00138   MCG->C6 = (uint8_t)0x00U;
00139   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
00140   }
00141   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00142   }
00143   /* Switch to PBE Mode */
00144   /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */
00145   MCG->C6 = (uint8_t)0x40U;
00146   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00147   }
00148   while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
00149   }
00150   /* Switch to PEE Mode */
00151   /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00152   MCG->C1 = (uint8_t)0x1AU;
00153   while((MCG->S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
00154   }
00155 #elif (CLOCK_SETUP == 2)
00156   /* SIM->SCGC5: PORTA=1 */
00157   SIM->SCGC5 |= (uint32_t)0x0200UL;     /* Enable clock gate for ports to enable pin routing */
00158   /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
00159   SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */
00160   /* PORTA->PCR18: ISF=0,MUX=0 */
00161   PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
00162   /* PORTA->PCR19: ISF=0,MUX=0 */
00163   PORTA->PCR[19] &= (uint32_t)~0x01000700UL;
00164   /* Switch to FBE Mode */
00165   /* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */
00166   OSC0->CR = (uint8_t)0x89U;
00167   /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
00168   MCG->C2 = (uint8_t)0x24U;
00169   /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
00170   MCG->C1 = (uint8_t)0x9AU;
00171   /* MCG->C4: DMX32=0,DRST_DRS=0 */
00172   MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
00173   /* MCG->C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
00174   MCG->C5 = (uint8_t)0x00U;
00175   /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
00176   MCG->C6 = (uint8_t)0x00U;
00177   while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
00178   }
00179   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00180   }
00181   /* Switch to BLPE Mode */
00182   /* MCG->C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */
00183   MCG->C2 = (uint8_t)0x26U;
00184   while((MCG->S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
00185   }
00186 #endif /* (CLOCK_SETUP == 2) */
00187 }
00188 
00189 /* ----------------------------------------------------------------------------
00190    -- SystemCoreClockUpdate()
00191    ---------------------------------------------------------------------------- */
00192 
00193 void SystemCoreClockUpdate (void) {
00194   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
00195   uint8_t Divider;
00196 
00197   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
00198     /* Output of FLL or PLL is selected */
00199     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) {
00200       /* FLL is selected */
00201       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
00202         /* External reference clock is selected */
00203         MCGOUTClock = CPU_XTAL_CLK_HZ;                                       /* System oscillator drives MCG clock */
00204         Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
00205         MCGOUTClock = (MCGOUTClock / Divider);  /* Calculate the divided FLL reference clock */
00206         if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) {
00207           MCGOUTClock /= 32u;                                                  /* If high range is enabled, additional 32 divider is active */
00208         } /* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) */
00209       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
00210         MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                     /* The slow internal reference clock is selected */
00211       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
00212       /* Select correct multiplier to calculate the MCG output clock  */
00213       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
00214         case 0x0u:
00215           MCGOUTClock *= 640u;
00216           break;
00217         case 0x20u:
00218           MCGOUTClock *= 1280u;
00219           break;
00220         case 0x40u:
00221           MCGOUTClock *= 1920u;
00222           break;
00223         case 0x60u:
00224           MCGOUTClock *= 2560u;
00225           break;
00226         case 0x80u:
00227           MCGOUTClock *= 732u;
00228           break;
00229         case 0xA0u:
00230           MCGOUTClock *= 1464u;
00231           break;
00232         case 0xC0u:
00233           MCGOUTClock *= 2197u;
00234           break;
00235         case 0xE0u:
00236           MCGOUTClock *= 2929u;
00237           break;
00238         default:
00239           break;
00240       }
00241     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
00242       /* PLL is selected */
00243       Divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
00244       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider);                     /* Calculate the PLL reference clock */
00245       Divider = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
00246       MCGOUTClock *= Divider;                       /* Calculate the MCG output clock */
00247     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u)) */
00248   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40u) {
00249     /* Internal reference clock is selected */
00250     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
00251       MCGOUTClock = CPU_INT_SLOW_CLK_HZ;                                       /* Slow internal reference clock selected */
00252     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
00253       MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));  /* Fast internal reference clock selected */
00254     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
00255   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
00256     /* External reference clock is selected */
00257     MCGOUTClock = CPU_XTAL_CLK_HZ;                                           /* System oscillator drives MCG clock */
00258   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
00259     /* Reserved value */
00260     return;
00261   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
00262   SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
00263 }