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fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088
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core_cm0.h
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00001 /**************************************************************************//** 00002 * @file core_cm0.h 00003 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File 00004 * @version V3.02 00005 * @date 05. November 2012 00006 * 00007 * @note 00008 * Copyright (C) 2009-2012 ARM Limited. All rights reserved. 00009 * 00010 * @par 00011 * ARM Limited (ARM) is supplying this software for use with Cortex-M 00012 * processor based microcontrollers. This file can be freely distributed 00013 * within development tools that are supporting such ARM based processors. 00014 * 00015 * @par 00016 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED 00017 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF 00018 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. 00019 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR 00020 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 00021 * 00022 ******************************************************************************/ 00023 #if defined ( __ICCARM__ ) 00024 #pragma system_include /* treat file as system include file for MISRA check */ 00025 #endif 00026 00027 #ifdef __cplusplus 00028 extern "C" { 00029 #endif 00030 00031 #ifndef __CORE_CM0_H_GENERIC 00032 #define __CORE_CM0_H_GENERIC 00033 00034 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions 00035 CMSIS violates the following MISRA-C:2004 rules: 00036 00037 \li Required Rule 8.5, object/function definition in header file.<br> 00038 Function definitions in header files are used to allow 'inlining'. 00039 00040 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> 00041 Unions are used for effective representation of core registers. 00042 00043 \li Advisory Rule 19.7, Function-like macro defined.<br> 00044 Function-like macros are used to allow more efficient code. 00045 */ 00046 00047 00048 /******************************************************************************* 00049 * CMSIS definitions 00050 ******************************************************************************/ 00051 /** \ingroup Cortex_M0 00052 @{ 00053 */ 00054 00055 /* CMSIS CM0 definitions */ 00056 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ 00057 #define __CM0_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */ 00058 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \ 00059 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */ 00060 00061 #define __CORTEX_M (0x00) /*!< Cortex-M Core */ 00062 00063 00064 #if defined ( __CC_ARM ) 00065 #define __ASM __asm /*!< asm keyword for ARM Compiler */ 00066 #define __INLINE __inline /*!< inline keyword for ARM Compiler */ 00067 #define __STATIC_INLINE static __inline 00068 00069 #elif defined ( __ICCARM__ ) 00070 #define __ASM __asm /*!< asm keyword for IAR Compiler */ 00071 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ 00072 #define __STATIC_INLINE static inline 00073 00074 #elif defined ( __GNUC__ ) 00075 #define __ASM __asm /*!< asm keyword for GNU Compiler */ 00076 #define __INLINE inline /*!< inline keyword for GNU Compiler */ 00077 #define __STATIC_INLINE static inline 00078 00079 #elif defined ( __TASKING__ ) 00080 #define __ASM __asm /*!< asm keyword for TASKING Compiler */ 00081 #define __INLINE inline /*!< inline keyword for TASKING Compiler */ 00082 #define __STATIC_INLINE static inline 00083 00084 #endif 00085 00086 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all 00087 */ 00088 #define __FPU_USED 0 00089 00090 #if defined ( __CC_ARM ) 00091 #if defined __TARGET_FPU_VFP 00092 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00093 #endif 00094 00095 #elif defined ( __ICCARM__ ) 00096 #if defined __ARMVFP__ 00097 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00098 #endif 00099 00100 #elif defined ( __GNUC__ ) 00101 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00102 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00103 #endif 00104 00105 #elif defined ( __TASKING__ ) 00106 #if defined __FPU_VFP__ 00107 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00108 #endif 00109 #endif 00110 00111 #include <stdint.h> /* standard types definitions */ 00112 #include <core_cmInstr.h> /* Core Instruction Access */ 00113 #include <core_cmFunc.h> /* Core Function Access */ 00114 00115 #endif /* __CORE_CM0_H_GENERIC */ 00116 00117 #ifndef __CMSIS_GENERIC 00118 00119 #ifndef __CORE_CM0_H_DEPENDANT 00120 #define __CORE_CM0_H_DEPENDANT 00121 00122 /* check device defines and use defaults */ 00123 #if defined __CHECK_DEVICE_DEFINES 00124 #ifndef __CM0_REV 00125 #define __CM0_REV 0x0000 00126 #warning "__CM0_REV not defined in device header file; using default!" 00127 #endif 00128 00129 #ifndef __NVIC_PRIO_BITS 00130 #define __NVIC_PRIO_BITS 2 00131 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00132 #endif 00133 00134 #ifndef __Vendor_SysTickConfig 00135 #define __Vendor_SysTickConfig 0 00136 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00137 #endif 00138 #endif 00139 00140 /* IO definitions (access restrictions to peripheral registers) */ 00141 /** 00142 \defgroup CMSIS_glob_defs CMSIS Global Defines 00143 00144 <strong>IO Type Qualifiers</strong> are used 00145 \li to specify the access to peripheral variables. 00146 \li for automatic generation of peripheral register debug information. 00147 */ 00148 #ifdef __cplusplus 00149 #define __I volatile /*!< Defines 'read only' permissions */ 00150 #else 00151 #define __I volatile const /*!< Defines 'read only' permissions */ 00152 #endif 00153 #define __O volatile /*!< Defines 'write only' permissions */ 00154 #define __IO volatile /*!< Defines 'read / write' permissions */ 00155 00156 /*@} end of group Cortex_M0 */ 00157 00158 00159 00160 /******************************************************************************* 00161 * Register Abstraction 00162 Core Register contain: 00163 - Core Register 00164 - Core NVIC Register 00165 - Core SCB Register 00166 - Core SysTick Register 00167 ******************************************************************************/ 00168 /** \defgroup CMSIS_core_register Defines and Type Definitions 00169 \brief Type definitions and defines for Cortex-M processor based devices. 00170 */ 00171 00172 /** \ingroup CMSIS_core_register 00173 \defgroup CMSIS_CORE Status and Control Registers 00174 \brief Core Register type definitions. 00175 @{ 00176 */ 00177 00178 /** \brief Union type to access the Application Program Status Register (APSR). 00179 */ 00180 typedef union 00181 { 00182 struct 00183 { 00184 #if (__CORTEX_M != 0x04) 00185 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ 00186 #else 00187 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ 00188 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00189 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ 00190 #endif 00191 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00192 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00193 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00194 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00195 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00196 } b; /*!< Structure used for bit access */ 00197 uint32_t w; /*!< Type used for word access */ 00198 } APSR_Type; 00199 00200 00201 /** \brief Union type to access the Interrupt Program Status Register (IPSR). 00202 */ 00203 typedef union 00204 { 00205 struct 00206 { 00207 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00208 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ 00209 } b; /*!< Structure used for bit access */ 00210 uint32_t w; /*!< Type used for word access */ 00211 } IPSR_Type; 00212 00213 00214 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). 00215 */ 00216 typedef union 00217 { 00218 struct 00219 { 00220 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ 00221 #if (__CORTEX_M != 0x04) 00222 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ 00223 #else 00224 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ 00225 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ 00226 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ 00227 #endif 00228 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ 00229 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ 00230 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ 00231 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ 00232 uint32_t C:1; /*!< bit: 29 Carry condition code flag */ 00233 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ 00234 uint32_t N:1; /*!< bit: 31 Negative condition code flag */ 00235 } b; /*!< Structure used for bit access */ 00236 uint32_t w; /*!< Type used for word access */ 00237 } xPSR_Type; 00238 00239 00240 /** \brief Union type to access the Control Registers (CONTROL). 00241 */ 00242 typedef union 00243 { 00244 struct 00245 { 00246 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ 00247 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ 00248 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ 00249 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ 00250 } b; /*!< Structure used for bit access */ 00251 uint32_t w; /*!< Type used for word access */ 00252 } CONTROL_Type; 00253 00254 /*@} end of group CMSIS_CORE */ 00255 00256 00257 /** \ingroup CMSIS_core_register 00258 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) 00259 \brief Type definitions for the NVIC Registers 00260 @{ 00261 */ 00262 00263 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). 00264 */ 00265 typedef struct 00266 { 00267 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ 00268 uint32_t RESERVED0[31]; 00269 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ 00270 uint32_t RSERVED1[31]; 00271 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ 00272 uint32_t RESERVED2[31]; 00273 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ 00274 uint32_t RESERVED3[31]; 00275 uint32_t RESERVED4[64]; 00276 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ 00277 } NVIC_Type; 00278 00279 /*@} end of group CMSIS_NVIC */ 00280 00281 00282 /** \ingroup CMSIS_core_register 00283 \defgroup CMSIS_SCB System Control Block (SCB) 00284 \brief Type definitions for the System Control Block Registers 00285 @{ 00286 */ 00287 00288 /** \brief Structure type to access the System Control Block (SCB). 00289 */ 00290 typedef struct 00291 { 00292 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ 00293 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ 00294 uint32_t RESERVED0; 00295 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ 00296 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ 00297 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ 00298 uint32_t RESERVED1; 00299 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ 00300 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ 00301 } SCB_Type; 00302 00303 /* SCB CPUID Register Definitions */ 00304 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ 00305 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ 00306 00307 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ 00308 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ 00309 00310 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ 00311 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ 00312 00313 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ 00314 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ 00315 00316 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ 00317 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ 00318 00319 /* SCB Interrupt Control State Register Definitions */ 00320 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ 00321 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ 00322 00323 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ 00324 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ 00325 00326 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ 00327 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ 00328 00329 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ 00330 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ 00331 00332 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ 00333 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ 00334 00335 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ 00336 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ 00337 00338 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ 00339 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ 00340 00341 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ 00342 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ 00343 00344 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ 00345 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ 00346 00347 /* SCB Application Interrupt and Reset Control Register Definitions */ 00348 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ 00349 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ 00350 00351 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ 00352 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ 00353 00354 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ 00355 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ 00356 00357 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ 00358 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ 00359 00360 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ 00361 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ 00362 00363 /* SCB System Control Register Definitions */ 00364 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ 00365 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ 00366 00367 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ 00368 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ 00369 00370 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ 00371 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ 00372 00373 /* SCB Configuration Control Register Definitions */ 00374 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ 00375 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ 00376 00377 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ 00378 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ 00379 00380 /* SCB System Handler Control and State Register Definitions */ 00381 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ 00382 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ 00383 00384 /*@} end of group CMSIS_SCB */ 00385 00386 00387 /** \ingroup CMSIS_core_register 00388 \defgroup CMSIS_SysTick System Tick Timer (SysTick) 00389 \brief Type definitions for the System Timer Registers. 00390 @{ 00391 */ 00392 00393 /** \brief Structure type to access the System Timer (SysTick). 00394 */ 00395 typedef struct 00396 { 00397 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ 00398 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ 00399 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ 00400 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ 00401 } SysTick_Type; 00402 00403 /* SysTick Control / Status Register Definitions */ 00404 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ 00405 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ 00406 00407 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ 00408 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ 00409 00410 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ 00411 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ 00412 00413 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ 00414 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ 00415 00416 /* SysTick Reload Register Definitions */ 00417 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ 00418 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ 00419 00420 /* SysTick Current Register Definitions */ 00421 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ 00422 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ 00423 00424 /* SysTick Calibration Register Definitions */ 00425 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ 00426 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ 00427 00428 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ 00429 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ 00430 00431 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ 00432 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ 00433 00434 /*@} end of group CMSIS_SysTick */ 00435 00436 00437 /** \ingroup CMSIS_core_register 00438 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) 00439 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) 00440 are only accessible over DAP and not via processor. Therefore 00441 they are not covered by the Cortex-M0 header file. 00442 @{ 00443 */ 00444 /*@} end of group CMSIS_CoreDebug */ 00445 00446 00447 /** \ingroup CMSIS_core_register 00448 \defgroup CMSIS_core_base Core Definitions 00449 \brief Definitions for base addresses, unions, and structures. 00450 @{ 00451 */ 00452 00453 /* Memory mapping of Cortex-M0 Hardware */ 00454 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ 00455 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ 00456 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ 00457 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ 00458 00459 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ 00460 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ 00461 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ 00462 00463 00464 /*@} */ 00465 00466 00467 00468 /******************************************************************************* 00469 * Hardware Abstraction Layer 00470 Core Function Interface contains: 00471 - Core NVIC Functions 00472 - Core SysTick Functions 00473 - Core Register Access Functions 00474 ******************************************************************************/ 00475 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference 00476 */ 00477 00478 00479 00480 /* ########################## NVIC functions #################################### */ 00481 /** \ingroup CMSIS_Core_FunctionInterface 00482 \defgroup CMSIS_Core_NVICFunctions NVIC Functions 00483 \brief Functions that manage interrupts and exceptions via the NVIC. 00484 @{ 00485 */ 00486 00487 /* Interrupt Priorities are WORD accessible only under ARMv6M */ 00488 /* The following MACROS handle generation of the register offset and byte masks */ 00489 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) 00490 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) 00491 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) 00492 00493 00494 /** \brief Enable External Interrupt 00495 00496 The function enables a device-specific interrupt in the NVIC interrupt controller. 00497 00498 \param [in] IRQn External interrupt number. Value cannot be negative. 00499 */ 00500 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 00501 { 00502 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00503 } 00504 00505 00506 /** \brief Disable External Interrupt 00507 00508 The function disables a device-specific interrupt in the NVIC interrupt controller. 00509 00510 \param [in] IRQn External interrupt number. Value cannot be negative. 00511 */ 00512 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 00513 { 00514 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00515 } 00516 00517 00518 /** \brief Get Pending Interrupt 00519 00520 The function reads the pending register in the NVIC and returns the pending bit 00521 for the specified interrupt. 00522 00523 \param [in] IRQn Interrupt number. 00524 00525 \return 0 Interrupt status is not pending. 00526 \return 1 Interrupt status is pending. 00527 */ 00528 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 00529 { 00530 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); 00531 } 00532 00533 00534 /** \brief Set Pending Interrupt 00535 00536 The function sets the pending bit of an external interrupt. 00537 00538 \param [in] IRQn Interrupt number. Value cannot be negative. 00539 */ 00540 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 00541 { 00542 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); 00543 } 00544 00545 00546 /** \brief Clear Pending Interrupt 00547 00548 The function clears the pending bit of an external interrupt. 00549 00550 \param [in] IRQn External interrupt number. Value cannot be negative. 00551 */ 00552 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00553 { 00554 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 00555 } 00556 00557 00558 /** \brief Set Interrupt Priority 00559 00560 The function sets the priority of an interrupt. 00561 00562 \note The priority cannot be set for every core interrupt. 00563 00564 \param [in] IRQn Interrupt number. 00565 \param [in] priority Priority to set. 00566 */ 00567 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 00568 { 00569 if(IRQn < 0) { 00570 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00571 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00572 else { 00573 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | 00574 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } 00575 } 00576 00577 00578 /** \brief Get Interrupt Priority 00579 00580 The function reads the priority of an interrupt. The interrupt 00581 number can be positive to specify an external (device specific) 00582 interrupt, or negative to specify an internal (core) interrupt. 00583 00584 00585 \param [in] IRQn Interrupt number. 00586 \return Interrupt Priority. Value is aligned automatically to the implemented 00587 priority bits of the microcontroller. 00588 */ 00589 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 00590 { 00591 00592 if(IRQn < 0) { 00593 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ 00594 else { 00595 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 00596 } 00597 00598 00599 /** \brief System Reset 00600 00601 The function initiates a system reset request to reset the MCU. 00602 */ 00603 __STATIC_INLINE void NVIC_SystemReset(void) 00604 { 00605 __DSB(); /* Ensure all outstanding memory accesses included 00606 buffered write are completed before reset */ 00607 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 00608 SCB_AIRCR_SYSRESETREQ_Msk); 00609 __DSB(); /* Ensure completion of memory access */ 00610 while(1); /* wait until reset */ 00611 } 00612 00613 /*@} end of CMSIS_Core_NVICFunctions */ 00614 00615 00616 00617 /* ################################## SysTick function ############################################ */ 00618 /** \ingroup CMSIS_Core_FunctionInterface 00619 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions 00620 \brief Functions that configure the System. 00621 @{ 00622 */ 00623 00624 #if (__Vendor_SysTickConfig == 0) 00625 00626 /** \brief System Tick Configuration 00627 00628 The function initializes the System Timer and its interrupt, and starts the System Tick Timer. 00629 Counter is in free running mode to generate periodic interrupts. 00630 00631 \param [in] ticks Number of ticks between two interrupts. 00632 00633 \return 0 Function succeeded. 00634 \return 1 Function failed. 00635 00636 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the 00637 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> 00638 must contain a vendor-specific implementation of this function. 00639 00640 */ 00641 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 00642 { 00643 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 00644 00645 SysTick->LOAD = ticks - 1; /* set reload register */ 00646 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 00647 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 00648 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 00649 SysTick_CTRL_TICKINT_Msk | 00650 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 00651 return (0); /* Function successful */ 00652 } 00653 00654 #endif 00655 00656 /*@} end of CMSIS_Core_SysTickFunctions */ 00657 00658 00659 00660 00661 #endif /* __CORE_CM0_H_DEPENDANT */ 00662 00663 #endif /* __CMSIS_GENERIC */ 00664 00665 #ifdef __cplusplus 00666 } 00667 #endif
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