rau cha / mbed-src-I2CWaitFix

fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088

Fork of mbed-src by mbed official

vendor/NXP/LPC2368/hal/i2c_api.c@13:bd9ff402dd42, 2013-08-05 (annotated)

Committer:
Shikaneo
Date:
Mon Aug 05 02:27:27 2013 +0000
Revision:
13:bd9ff402dd42
Parent:
11:f9e72c209510 
equipped timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include "i2c_api.h"
emilmont 10:3bc89ef62ce7 17 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 18 #include "pinmap.h"
emilmont 10:3bc89ef62ce7 19 #include "error.h"
emilmont 10:3bc89ef62ce7 20
emilmont 10:3bc89ef62ce7 21 static const PinMap PinMap_I2C_SDA[] = {
emilmont 10:3bc89ef62ce7 22 {P0_0 , I2C_1, 3},
emilmont 10:3bc89ef62ce7 23 {P0_10, I2C_2, 2},
emilmont 10:3bc89ef62ce7 24 {P0_19, I2C_1, 3},
emilmont 10:3bc89ef62ce7 25 {P0_27, I2C_0, 1},
emilmont 10:3bc89ef62ce7 26 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 27 };
emilmont 10:3bc89ef62ce7 28
emilmont 10:3bc89ef62ce7 29 static const PinMap PinMap_I2C_SCL[] = {
emilmont 10:3bc89ef62ce7 30 {P0_1 , I2C_1, 3},
emilmont 10:3bc89ef62ce7 31 {P0_11, I2C_2, 2},
emilmont 10:3bc89ef62ce7 32 {P0_20, I2C_1, 3},
emilmont 10:3bc89ef62ce7 33 {P0_28, I2C_0, 1},
emilmont 10:3bc89ef62ce7 34 {NC , NC, 0}
emilmont 10:3bc89ef62ce7 35 };
emilmont 10:3bc89ef62ce7 36
emilmont 10:3bc89ef62ce7 37 #define I2C_CONSET(x) (x->i2c->I2CONSET)
emilmont 10:3bc89ef62ce7 38 #define I2C_CONCLR(x) (x->i2c->I2CONCLR)
emilmont 10:3bc89ef62ce7 39 #define I2C_STAT(x) (x->i2c->I2STAT)
emilmont 10:3bc89ef62ce7 40 #define I2C_DAT(x) (x->i2c->I2DAT)
emilmont 10:3bc89ef62ce7 41 #define I2C_SCLL(x, val) (x->i2c->I2SCLL = val)
emilmont 10:3bc89ef62ce7 42 #define I2C_SCLH(x, val) (x->i2c->I2SCLH = val)
emilmont 10:3bc89ef62ce7 43
emilmont 10:3bc89ef62ce7 44 static const uint32_t I2C_addr_offset[2][4] = {
emilmont 10:3bc89ef62ce7 45 {0x0C, 0x20, 0x24, 0x28},
emilmont 10:3bc89ef62ce7 46 {0x30, 0x34, 0x38, 0x3C}
emilmont 10:3bc89ef62ce7 47 };
emilmont 10:3bc89ef62ce7 48
emilmont 10:3bc89ef62ce7 49 static inline void i2c_conclr(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
emilmont 10:3bc89ef62ce7 50 I2C_CONCLR(obj) = (start << 5)
emilmont 10:3bc89ef62ce7 51 | (stop << 4)
emilmont 10:3bc89ef62ce7 52 | (interrupt << 3)
emilmont 10:3bc89ef62ce7 53 | (acknowledge << 2);
emilmont 10:3bc89ef62ce7 54 }
emilmont 10:3bc89ef62ce7 55
emilmont 10:3bc89ef62ce7 56 static inline void i2c_conset(i2c_t *obj, int start, int stop, int interrupt, int acknowledge) {
emilmont 10:3bc89ef62ce7 57 I2C_CONSET(obj) = (start << 5)
emilmont 10:3bc89ef62ce7 58 | (stop << 4)
emilmont 10:3bc89ef62ce7 59 | (interrupt << 3)
emilmont 10:3bc89ef62ce7 60 | (acknowledge << 2);
emilmont 10:3bc89ef62ce7 61 }
emilmont 10:3bc89ef62ce7 62
emilmont 10:3bc89ef62ce7 63 // Clear the Serial Interrupt (SI)
emilmont 10:3bc89ef62ce7 64 static inline void i2c_clear_SI(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 65 i2c_conclr(obj, 0, 0, 1, 0);
emilmont 10:3bc89ef62ce7 66 }
emilmont 10:3bc89ef62ce7 67
emilmont 10:3bc89ef62ce7 68 static inline int i2c_status(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 69 return I2C_STAT(obj);
emilmont 10:3bc89ef62ce7 70 }
emilmont 10:3bc89ef62ce7 71
emilmont 10:3bc89ef62ce7 72 // Wait until the Serial Interrupt (SI) is set
emilmont 10:3bc89ef62ce7 73 static int i2c_wait_SI(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 74 int timeout = 0;
emilmont 10:3bc89ef62ce7 75 while (!(I2C_CONSET(obj) & (1 << 3))) {
emilmont 10:3bc89ef62ce7 76 timeout++;
emilmont 10:3bc89ef62ce7 77 if (timeout > 100000) return -1;
emilmont 10:3bc89ef62ce7 78 }
emilmont 10:3bc89ef62ce7 79 return 0;
emilmont 10:3bc89ef62ce7 80 }
emilmont 10:3bc89ef62ce7 81
emilmont 10:3bc89ef62ce7 82 static inline void i2c_interface_enable(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 83 I2C_CONSET(obj) = 0x40;
emilmont 10:3bc89ef62ce7 84 }
emilmont 10:3bc89ef62ce7 85
emilmont 10:3bc89ef62ce7 86 static inline void i2c_power_enable(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 87 switch ((int)obj->i2c) {
emilmont 10:3bc89ef62ce7 88 case I2C_0: LPC_SC->PCONP |= 1 << 7; break;
emilmont 10:3bc89ef62ce7 89 case I2C_1: LPC_SC->PCONP |= 1 << 19; break;
emilmont 10:3bc89ef62ce7 90 case I2C_2: LPC_SC->PCONP |= 1 << 26; break;
emilmont 10:3bc89ef62ce7 91 }
emilmont 10:3bc89ef62ce7 92 }
emilmont 10:3bc89ef62ce7 93
emilmont 10:3bc89ef62ce7 94 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
emilmont 10:3bc89ef62ce7 95 // determine the SPI to use
emilmont 10:3bc89ef62ce7 96 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
emilmont 10:3bc89ef62ce7 97 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
emilmont 10:3bc89ef62ce7 98 obj->i2c = (LPC_I2C_TypeDef *)pinmap_merge(i2c_sda, i2c_scl);
emilmont 10:3bc89ef62ce7 99
emilmont 10:3bc89ef62ce7 100 if ((int)obj->i2c == NC) {
emilmont 10:3bc89ef62ce7 101 error("I2C pin mapping failed");
emilmont 10:3bc89ef62ce7 102 }
emilmont 10:3bc89ef62ce7 103
emilmont 10:3bc89ef62ce7 104 // enable power
emilmont 10:3bc89ef62ce7 105 i2c_power_enable(obj);
emilmont 10:3bc89ef62ce7 106
emilmont 10:3bc89ef62ce7 107 // set default frequency at 100k
emilmont 10:3bc89ef62ce7 108 i2c_frequency(obj, 100000);
emilmont 10:3bc89ef62ce7 109 i2c_conclr(obj, 1, 1, 1, 1);
emilmont 10:3bc89ef62ce7 110 i2c_interface_enable(obj);
emilmont 10:3bc89ef62ce7 111
emilmont 10:3bc89ef62ce7 112 pinmap_pinout(sda, PinMap_I2C_SDA);
emilmont 10:3bc89ef62ce7 113 pinmap_pinout(scl, PinMap_I2C_SCL);
emilmont 10:3bc89ef62ce7 114 }
emilmont 10:3bc89ef62ce7 115
emilmont 10:3bc89ef62ce7 116 inline int i2c_start(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 117 int status = 0;
emilmont 10:3bc89ef62ce7 118 // 8.1 Before master mode can be entered, I2CON must be initialised to:
emilmont 10:3bc89ef62ce7 119 // - I2EN STA STO SI AA - -
emilmont 10:3bc89ef62ce7 120 // - 1 0 0 0 x - -
emilmont 10:3bc89ef62ce7 121 // if AA = 0, it can't enter slave mode
emilmont 10:3bc89ef62ce7 122 i2c_conclr(obj, 1, 1, 1, 1);
emilmont 10:3bc89ef62ce7 123
emilmont 10:3bc89ef62ce7 124 // The master mode may now be entered by setting the STA bit
emilmont 10:3bc89ef62ce7 125 // this will generate a start condition when the bus becomes free
emilmont 10:3bc89ef62ce7 126 i2c_conset(obj, 1, 0, 0, 1);
emilmont 10:3bc89ef62ce7 127
emilmont 10:3bc89ef62ce7 128 i2c_wait_SI(obj);
emilmont 10:3bc89ef62ce7 129 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 130
emilmont 10:3bc89ef62ce7 131 // Clear start bit now transmitted, and interrupt bit
emilmont 10:3bc89ef62ce7 132 i2c_conclr(obj, 1, 0, 0, 0);
emilmont 10:3bc89ef62ce7 133 return status;
emilmont 10:3bc89ef62ce7 134 }
emilmont 10:3bc89ef62ce7 135
Shikaneo 13:bd9ff402dd42 136 inline int i2c_stop(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 137 // write the stop bit
emilmont 10:3bc89ef62ce7 138 i2c_conset(obj, 0, 1, 0, 0);
emilmont 10:3bc89ef62ce7 139 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 140
emilmont 10:3bc89ef62ce7 141 // wait for STO bit to reset
Shikaneo 13:bd9ff402dd42 142 int timeout = 0;
Shikaneo 13:bd9ff402dd42 143 while (I2C_CONSET(obj) & (1 << 4)){
Shikaneo 13:bd9ff402dd42 144 timeout++;
Shikaneo 13:bd9ff402dd42 145 if(timeout > 10000) return -1;
Shikaneo 13:bd9ff402dd42 146 }
Shikaneo 13:bd9ff402dd42 147 return 0;
emilmont 10:3bc89ef62ce7 148 }
emilmont 10:3bc89ef62ce7 149
emilmont 10:3bc89ef62ce7 150 static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) {
emilmont 10:3bc89ef62ce7 151 // write the data
emilmont 10:3bc89ef62ce7 152 I2C_DAT(obj) = value;
emilmont 10:3bc89ef62ce7 153
emilmont 10:3bc89ef62ce7 154 // clear SI to init a send
emilmont 10:3bc89ef62ce7 155 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 156
emilmont 10:3bc89ef62ce7 157 // wait and return status
emilmont 10:3bc89ef62ce7 158 i2c_wait_SI(obj);
emilmont 10:3bc89ef62ce7 159 return i2c_status(obj);
emilmont 10:3bc89ef62ce7 160 }
emilmont 10:3bc89ef62ce7 161
emilmont 10:3bc89ef62ce7 162 static inline int i2c_do_read(i2c_t *obj, int last) {
emilmont 10:3bc89ef62ce7 163 // we are in state 0x40 (SLA+R tx'd) or 0x50 (data rx'd and ack)
emilmont 10:3bc89ef62ce7 164 if (last) {
emilmont 10:3bc89ef62ce7 165 i2c_conclr(obj, 0, 0, 0, 1); // send a NOT ACK
emilmont 10:3bc89ef62ce7 166 } else {
emilmont 10:3bc89ef62ce7 167 i2c_conset(obj, 0, 0, 0, 1); // send a ACK
emilmont 10:3bc89ef62ce7 168 }
emilmont 10:3bc89ef62ce7 169
emilmont 10:3bc89ef62ce7 170 // accept byte
emilmont 10:3bc89ef62ce7 171 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 172
emilmont 10:3bc89ef62ce7 173 // wait for it to arrive
emilmont 10:3bc89ef62ce7 174 i2c_wait_SI(obj);
emilmont 10:3bc89ef62ce7 175
emilmont 10:3bc89ef62ce7 176 // return the data
emilmont 10:3bc89ef62ce7 177 return (I2C_DAT(obj) & 0xFF);
emilmont 10:3bc89ef62ce7 178 }
emilmont 10:3bc89ef62ce7 179
emilmont 10:3bc89ef62ce7 180 void i2c_frequency(i2c_t *obj, int hz) {
emilmont 10:3bc89ef62ce7 181 // [TODO] set pclk to /4
emilmont 10:3bc89ef62ce7 182 uint32_t PCLK = SystemCoreClock / 4;
emilmont 10:3bc89ef62ce7 183
emilmont 10:3bc89ef62ce7 184 uint32_t pulse = PCLK / (hz * 2);
emilmont 10:3bc89ef62ce7 185
emilmont 10:3bc89ef62ce7 186 // I2C Rate
emilmont 10:3bc89ef62ce7 187 I2C_SCLL(obj, pulse);
emilmont 10:3bc89ef62ce7 188 I2C_SCLH(obj, pulse);
emilmont 10:3bc89ef62ce7 189 }
emilmont 10:3bc89ef62ce7 190
emilmont 10:3bc89ef62ce7 191 // The I2C does a read or a write as a whole operation
emilmont 10:3bc89ef62ce7 192 // There are two types of error conditions it can encounter
emilmont 10:3bc89ef62ce7 193 // 1) it can not obtain the bus
emilmont 10:3bc89ef62ce7 194 // 2) it gets error responses at part of the transmission
emilmont 10:3bc89ef62ce7 195 //
emilmont 10:3bc89ef62ce7 196 // We tackle them as follows:
emilmont 10:3bc89ef62ce7 197 // 1) we retry until we get the bus. we could have a "timeout" if we can not get it
emilmont 10:3bc89ef62ce7 198 // which basically turns it in to a 2)
emilmont 10:3bc89ef62ce7 199 // 2) on error, we use the standard error mechanisms to report/debug
emilmont 10:3bc89ef62ce7 200 //
emilmont 10:3bc89ef62ce7 201 // Therefore an I2C transaction should always complete. If it doesn't it is usually
emilmont 10:3bc89ef62ce7 202 // because something is setup wrong (e.g. wiring), and we don't need to programatically
emilmont 10:3bc89ef62ce7 203 // check for that
emilmont 10:3bc89ef62ce7 204 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
emilmont 10:3bc89ef62ce7 205 int count, status;
emilmont 10:3bc89ef62ce7 206
emilmont 10:3bc89ef62ce7 207 status = i2c_start(obj);
emilmont 10:3bc89ef62ce7 208
emilmont 10:3bc89ef62ce7 209 if ((status != 0x10) && (status != 0x08)) {
emilmont 10:3bc89ef62ce7 210 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 211 return status;
emilmont 10:3bc89ef62ce7 212 }
emilmont 10:3bc89ef62ce7 213
emilmont 10:3bc89ef62ce7 214 status = i2c_do_write(obj, (address | 0x01), 1);
emilmont 10:3bc89ef62ce7 215 if (status != 0x40) {
emilmont 10:3bc89ef62ce7 216 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 217 return status;
emilmont 10:3bc89ef62ce7 218 }
emilmont 10:3bc89ef62ce7 219
emilmont 10:3bc89ef62ce7 220 // Read in all except last byte
emilmont 10:3bc89ef62ce7 221 for (count = 0; count < (length - 1); count++) {
emilmont 10:3bc89ef62ce7 222 int value = i2c_do_read(obj, 0);
emilmont 10:3bc89ef62ce7 223 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 224 if (status != 0x50) {
emilmont 10:3bc89ef62ce7 225 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 226 return status;
emilmont 10:3bc89ef62ce7 227 }
emilmont 10:3bc89ef62ce7 228 data[count] = (char) value;
emilmont 10:3bc89ef62ce7 229 }
emilmont 10:3bc89ef62ce7 230
emilmont 10:3bc89ef62ce7 231 // read in last byte
emilmont 10:3bc89ef62ce7 232 int value = i2c_do_read(obj, 1);
emilmont 10:3bc89ef62ce7 233 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 234 if (status != 0x58) {
emilmont 10:3bc89ef62ce7 235 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 236 return status;
emilmont 10:3bc89ef62ce7 237 }
emilmont 10:3bc89ef62ce7 238
emilmont 10:3bc89ef62ce7 239 data[count] = (char) value;
emilmont 10:3bc89ef62ce7 240
emilmont 10:3bc89ef62ce7 241 // If not repeated start, send stop.
emilmont 10:3bc89ef62ce7 242 if (stop) {
emilmont 10:3bc89ef62ce7 243 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 244 }
emilmont 10:3bc89ef62ce7 245
emilmont 10:3bc89ef62ce7 246 return 0;
emilmont 10:3bc89ef62ce7 247 }
emilmont 10:3bc89ef62ce7 248
emilmont 10:3bc89ef62ce7 249 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
emilmont 10:3bc89ef62ce7 250 int i, status;
emilmont 10:3bc89ef62ce7 251
emilmont 10:3bc89ef62ce7 252 status = i2c_start(obj);
emilmont 10:3bc89ef62ce7 253
emilmont 10:3bc89ef62ce7 254 if ((status != 0x10) && (status != 0x08)) {
emilmont 10:3bc89ef62ce7 255 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 256 return status;
emilmont 10:3bc89ef62ce7 257 }
emilmont 10:3bc89ef62ce7 258
emilmont 10:3bc89ef62ce7 259 status = i2c_do_write(obj, (address & 0xFE), 1);
emilmont 10:3bc89ef62ce7 260 if (status != 0x18) {
emilmont 10:3bc89ef62ce7 261 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 262 return status;
emilmont 10:3bc89ef62ce7 263 }
emilmont 10:3bc89ef62ce7 264
emilmont 10:3bc89ef62ce7 265 for (i=0; i<length; i++) {
emilmont 10:3bc89ef62ce7 266 status = i2c_do_write(obj, data[i], 0);
emilmont 10:3bc89ef62ce7 267 if (status != 0x28) {
emilmont 10:3bc89ef62ce7 268 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 269 return status;
emilmont 10:3bc89ef62ce7 270 }
emilmont 10:3bc89ef62ce7 271 }
emilmont 10:3bc89ef62ce7 272
humlet 11:f9e72c209510 273 // clearing the serial interrupt here might cause an unintended rewrite of the last byte
humlet 11:f9e72c209510 274 // see also issue report https://mbed.org/users/mbed_official/code/mbed/issues/1
humlet 11:f9e72c209510 275 // i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 276
emilmont 10:3bc89ef62ce7 277 // If not repeated start, send stop.
emilmont 10:3bc89ef62ce7 278 if (stop) {
emilmont 10:3bc89ef62ce7 279 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 280 }
emilmont 10:3bc89ef62ce7 281
emilmont 10:3bc89ef62ce7 282 return 0;
emilmont 10:3bc89ef62ce7 283 }
emilmont 10:3bc89ef62ce7 284
emilmont 10:3bc89ef62ce7 285 void i2c_reset(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 286 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 287 }
emilmont 10:3bc89ef62ce7 288
emilmont 10:3bc89ef62ce7 289 int i2c_byte_read(i2c_t *obj, int last) {
emilmont 10:3bc89ef62ce7 290 return (i2c_do_read(obj, last) & 0xFF);
emilmont 10:3bc89ef62ce7 291 }
emilmont 10:3bc89ef62ce7 292
emilmont 10:3bc89ef62ce7 293 int i2c_byte_write(i2c_t *obj, int data) {
emilmont 10:3bc89ef62ce7 294 int ack;
emilmont 10:3bc89ef62ce7 295 int status = i2c_do_write(obj, (data & 0xFF), 0);
emilmont 10:3bc89ef62ce7 296
emilmont 10:3bc89ef62ce7 297 switch(status) {
emilmont 10:3bc89ef62ce7 298 case 0x18: case 0x28: // Master transmit ACKs
emilmont 10:3bc89ef62ce7 299 ack = 1;
emilmont 10:3bc89ef62ce7 300 break;
emilmont 10:3bc89ef62ce7 301
emilmont 10:3bc89ef62ce7 302 case 0x40: // Master receive address transmitted ACK
emilmont 10:3bc89ef62ce7 303 ack = 1;
emilmont 10:3bc89ef62ce7 304 break;
emilmont 10:3bc89ef62ce7 305
emilmont 10:3bc89ef62ce7 306 case 0xB8: // Slave transmit ACK
emilmont 10:3bc89ef62ce7 307 ack = 1;
emilmont 10:3bc89ef62ce7 308 break;
emilmont 10:3bc89ef62ce7 309
emilmont 10:3bc89ef62ce7 310 default:
emilmont 10:3bc89ef62ce7 311 ack = 0;
emilmont 10:3bc89ef62ce7 312 break;
emilmont 10:3bc89ef62ce7 313 }
emilmont 10:3bc89ef62ce7 314
emilmont 10:3bc89ef62ce7 315 return ack;
emilmont 10:3bc89ef62ce7 316 }
emilmont 10:3bc89ef62ce7 317
emilmont 10:3bc89ef62ce7 318 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
emilmont 10:3bc89ef62ce7 319 if (enable_slave != 0) {
emilmont 10:3bc89ef62ce7 320 i2c_conclr(obj, 1, 1, 1, 0);
emilmont 10:3bc89ef62ce7 321 i2c_conset(obj, 0, 0, 0, 1);
emilmont 10:3bc89ef62ce7 322 } else {
emilmont 10:3bc89ef62ce7 323 i2c_conclr(obj, 1, 1, 1, 1);
emilmont 10:3bc89ef62ce7 324 }
emilmont 10:3bc89ef62ce7 325 }
emilmont 10:3bc89ef62ce7 326
emilmont 10:3bc89ef62ce7 327 int i2c_slave_receive(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 328 int status;
emilmont 10:3bc89ef62ce7 329 int retval;
emilmont 10:3bc89ef62ce7 330
emilmont 10:3bc89ef62ce7 331 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 332 switch(status) {
emilmont 10:3bc89ef62ce7 333 case 0x60: retval = 3; break;
emilmont 10:3bc89ef62ce7 334 case 0x70: retval = 2; break;
emilmont 10:3bc89ef62ce7 335 case 0xA8: retval = 1; break;
emilmont 10:3bc89ef62ce7 336 default : retval = 0; break;
emilmont 10:3bc89ef62ce7 337 }
emilmont 10:3bc89ef62ce7 338
emilmont 10:3bc89ef62ce7 339 return(retval);
emilmont 10:3bc89ef62ce7 340 }
emilmont 10:3bc89ef62ce7 341
emilmont 10:3bc89ef62ce7 342 int i2c_slave_read(i2c_t *obj, char *data, int length) {
emilmont 10:3bc89ef62ce7 343 int count = 0;
emilmont 10:3bc89ef62ce7 344 int status;
emilmont 10:3bc89ef62ce7 345
emilmont 10:3bc89ef62ce7 346 do {
emilmont 10:3bc89ef62ce7 347 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 348 i2c_wait_SI(obj);
emilmont 10:3bc89ef62ce7 349 status = i2c_status(obj);
emilmont 10:3bc89ef62ce7 350 if((status == 0x80) || (status == 0x90)) {
emilmont 10:3bc89ef62ce7 351 data[count] = I2C_DAT(obj) & 0xFF;
emilmont 10:3bc89ef62ce7 352 }
emilmont 10:3bc89ef62ce7 353 count++;
emilmont 10:3bc89ef62ce7 354 } while (((status == 0x80) || (status == 0x90) ||
emilmont 10:3bc89ef62ce7 355 (status == 0x060) || (status == 0x70)) && (count < length));
emilmont 10:3bc89ef62ce7 356
emilmont 10:3bc89ef62ce7 357 if(status != 0xA0) {
emilmont 10:3bc89ef62ce7 358 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 359 }
emilmont 10:3bc89ef62ce7 360
emilmont 10:3bc89ef62ce7 361 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 362
emilmont 10:3bc89ef62ce7 363 return (count - 1);
emilmont 10:3bc89ef62ce7 364 }
emilmont 10:3bc89ef62ce7 365
emilmont 10:3bc89ef62ce7 366 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
emilmont 10:3bc89ef62ce7 367 int count = 0;
emilmont 10:3bc89ef62ce7 368 int status;
emilmont 10:3bc89ef62ce7 369
emilmont 10:3bc89ef62ce7 370 if(length <= 0) {
emilmont 10:3bc89ef62ce7 371 return(0);
emilmont 10:3bc89ef62ce7 372 }
emilmont 10:3bc89ef62ce7 373
emilmont 10:3bc89ef62ce7 374 do {
emilmont 10:3bc89ef62ce7 375 status = i2c_do_write(obj, data[count], 0);
emilmont 10:3bc89ef62ce7 376 count++;
emilmont 10:3bc89ef62ce7 377 } while ((count < length) && (status == 0xB8));
emilmont 10:3bc89ef62ce7 378
emilmont 10:3bc89ef62ce7 379 if((status != 0xC0) && (status != 0xC8)) {
emilmont 10:3bc89ef62ce7 380 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 381 }
emilmont 10:3bc89ef62ce7 382
emilmont 10:3bc89ef62ce7 383 i2c_clear_SI(obj);
emilmont 10:3bc89ef62ce7 384
emilmont 10:3bc89ef62ce7 385 return(count);
emilmont 10:3bc89ef62ce7 386 }
emilmont 10:3bc89ef62ce7 387
emilmont 10:3bc89ef62ce7 388 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
emilmont 10:3bc89ef62ce7 389 uint32_t addr;
emilmont 10:3bc89ef62ce7 390
emilmont 10:3bc89ef62ce7 391 if ((idx >= 0) && (idx <= 3)) {
emilmont 10:3bc89ef62ce7 392 addr = ((uint32_t)obj->i2c) + I2C_addr_offset[0][idx];
emilmont 10:3bc89ef62ce7 393 *((uint32_t *) addr) = address & 0xFF;
emilmont 10:3bc89ef62ce7 394 }
emilmont 10:3bc89ef62ce7 395 }