rau cha / mbed-src-I2CWaitFix

fix for mbed lib issue 3 (i2c problem) see also https://mbed.org/users/mbed_official/code/mbed/issues/3 affected implementations: LPC812, LPC11U24, LPC1768, LPC2368, LPC4088

Fork of mbed-src by mbed official

vendor/Freescale/KL25Z/hal/i2c_api.c@13:bd9ff402dd42, 2013-08-05 (annotated)

Committer:
Shikaneo
Date:
Mon Aug 05 02:27:27 2013 +0000
Revision:
13:bd9ff402dd42
Parent:
10:3bc89ef62ce7 
equipped timeout

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 10:3bc89ef62ce7 1 /* mbed Microcontroller Library
emilmont 10:3bc89ef62ce7 2 * Copyright (c) 2006-2013 ARM Limited
emilmont 10:3bc89ef62ce7 3 *
emilmont 10:3bc89ef62ce7 4 * Licensed under the Apache License, Version 2.0 (the "License");
emilmont 10:3bc89ef62ce7 5 * you may not use this file except in compliance with the License.
emilmont 10:3bc89ef62ce7 6 * You may obtain a copy of the License at
emilmont 10:3bc89ef62ce7 7 *
emilmont 10:3bc89ef62ce7 8 * http://www.apache.org/licenses/LICENSE-2.0
emilmont 10:3bc89ef62ce7 9 *
emilmont 10:3bc89ef62ce7 10 * Unless required by applicable law or agreed to in writing, software
emilmont 10:3bc89ef62ce7 11 * distributed under the License is distributed on an "AS IS" BASIS,
emilmont 10:3bc89ef62ce7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont 10:3bc89ef62ce7 13 * See the License for the specific language governing permissions and
emilmont 10:3bc89ef62ce7 14 * limitations under the License.
emilmont 10:3bc89ef62ce7 15 */
emilmont 10:3bc89ef62ce7 16 #include "i2c_api.h"
emilmont 10:3bc89ef62ce7 17
emilmont 10:3bc89ef62ce7 18 #include "cmsis.h"
emilmont 10:3bc89ef62ce7 19 #include "pinmap.h"
emilmont 10:3bc89ef62ce7 20 #include "error.h"
emilmont 10:3bc89ef62ce7 21
emilmont 10:3bc89ef62ce7 22 static const PinMap PinMap_I2C_SDA[] = {
emilmont 10:3bc89ef62ce7 23 {PTE25, I2C_0, 5},
emilmont 10:3bc89ef62ce7 24 {PTC9, I2C_0, 2},
emilmont 10:3bc89ef62ce7 25 {PTE0, I2C_1, 6},
emilmont 10:3bc89ef62ce7 26 {PTB1, I2C_0, 2},
emilmont 10:3bc89ef62ce7 27 {PTB3, I2C_0, 2},
emilmont 10:3bc89ef62ce7 28 {NC , NC , 0}
emilmont 10:3bc89ef62ce7 29 };
emilmont 10:3bc89ef62ce7 30
emilmont 10:3bc89ef62ce7 31 static const PinMap PinMap_I2C_SCL[] = {
emilmont 10:3bc89ef62ce7 32 {PTE24, I2C_0, 5},
emilmont 10:3bc89ef62ce7 33 {PTC8, I2C_0, 2},
emilmont 10:3bc89ef62ce7 34 {PTE1, I2C_1, 6},
emilmont 10:3bc89ef62ce7 35 {PTB0, I2C_0, 2},
emilmont 10:3bc89ef62ce7 36 {PTB2, I2C_0, 2},
emilmont 10:3bc89ef62ce7 37 {NC , NC, 0}
emilmont 10:3bc89ef62ce7 38 };
emilmont 10:3bc89ef62ce7 39
emilmont 10:3bc89ef62ce7 40 static const uint16_t ICR[0x40] = {
emilmont 10:3bc89ef62ce7 41 20, 22, 24, 26, 28,
emilmont 10:3bc89ef62ce7 42 30, 34, 40, 28, 32,
emilmont 10:3bc89ef62ce7 43 36, 40, 44, 48, 56,
emilmont 10:3bc89ef62ce7 44 68, 48, 56, 64, 72,
emilmont 10:3bc89ef62ce7 45 80, 88, 104, 128, 80,
emilmont 10:3bc89ef62ce7 46 96, 112, 128, 144, 160,
emilmont 10:3bc89ef62ce7 47 192, 240, 160, 192, 224,
emilmont 10:3bc89ef62ce7 48 256, 288, 320, 384, 480,
emilmont 10:3bc89ef62ce7 49 320, 384, 448, 512, 576,
emilmont 10:3bc89ef62ce7 50 640, 768, 960, 640, 768,
emilmont 10:3bc89ef62ce7 51 896, 1024, 1152, 1280, 1536,
emilmont 10:3bc89ef62ce7 52 1920, 1280, 1536, 1792, 2048,
emilmont 10:3bc89ef62ce7 53 2304, 2560, 3072, 3840
emilmont 10:3bc89ef62ce7 54 };
emilmont 10:3bc89ef62ce7 55
emilmont 10:3bc89ef62ce7 56 static uint8_t first_read;
emilmont 10:3bc89ef62ce7 57
emilmont 10:3bc89ef62ce7 58
emilmont 10:3bc89ef62ce7 59 void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
emilmont 10:3bc89ef62ce7 60 // determine the I2C to use
emilmont 10:3bc89ef62ce7 61 I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
emilmont 10:3bc89ef62ce7 62 I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
emilmont 10:3bc89ef62ce7 63 obj->i2c = (I2C_Type*)pinmap_merge(i2c_sda, i2c_scl);
emilmont 10:3bc89ef62ce7 64 if ((int)obj->i2c == NC) {
emilmont 10:3bc89ef62ce7 65 error("I2C pin mapping failed");
emilmont 10:3bc89ef62ce7 66 }
emilmont 10:3bc89ef62ce7 67
emilmont 10:3bc89ef62ce7 68 // enable power
emilmont 10:3bc89ef62ce7 69 switch ((int)obj->i2c) {
emilmont 10:3bc89ef62ce7 70 case I2C_0: SIM->SCGC5 |= 1 << 13; SIM->SCGC4 |= 1 << 6; break;
emilmont 10:3bc89ef62ce7 71 case I2C_1: SIM->SCGC5 |= 1 << 11; SIM->SCGC4 |= 1 << 7; break;
emilmont 10:3bc89ef62ce7 72 }
emilmont 10:3bc89ef62ce7 73
emilmont 10:3bc89ef62ce7 74 // set default frequency at 100k
emilmont 10:3bc89ef62ce7 75 i2c_frequency(obj, 100000);
emilmont 10:3bc89ef62ce7 76
emilmont 10:3bc89ef62ce7 77 // enable I2C interface
emilmont 10:3bc89ef62ce7 78 obj->i2c->C1 |= 0x80;
emilmont 10:3bc89ef62ce7 79
emilmont 10:3bc89ef62ce7 80 pinmap_pinout(sda, PinMap_I2C_SDA);
emilmont 10:3bc89ef62ce7 81 pinmap_pinout(scl, PinMap_I2C_SCL);
emilmont 10:3bc89ef62ce7 82
emilmont 10:3bc89ef62ce7 83 first_read = 1;
emilmont 10:3bc89ef62ce7 84 }
emilmont 10:3bc89ef62ce7 85
emilmont 10:3bc89ef62ce7 86 int i2c_start(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 87 // if we are in the middle of a transaction
emilmont 10:3bc89ef62ce7 88 // activate the repeat_start flag
emilmont 10:3bc89ef62ce7 89 if (obj->i2c->S & I2C_S_BUSY_MASK) {
emilmont 10:3bc89ef62ce7 90 obj->i2c->C1 |= 0x04;
emilmont 10:3bc89ef62ce7 91 } else {
emilmont 10:3bc89ef62ce7 92 obj->i2c->C1 |= I2C_C1_MST_MASK;
emilmont 10:3bc89ef62ce7 93 obj->i2c->C1 |= I2C_C1_TX_MASK;
emilmont 10:3bc89ef62ce7 94 }
emilmont 10:3bc89ef62ce7 95 first_read = 1;
emilmont 10:3bc89ef62ce7 96 return 0;
emilmont 10:3bc89ef62ce7 97 }
emilmont 10:3bc89ef62ce7 98
Shikaneo 13:bd9ff402dd42 99 int i2c_stop(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 100 volatile uint32_t n = 0;
emilmont 10:3bc89ef62ce7 101 obj->i2c->C1 &= ~I2C_C1_MST_MASK;
emilmont 10:3bc89ef62ce7 102 obj->i2c->C1 &= ~I2C_C1_TX_MASK;
emilmont 10:3bc89ef62ce7 103
emilmont 10:3bc89ef62ce7 104 // It seems that there are timing problems
emilmont 10:3bc89ef62ce7 105 // when there is no waiting time after a STOP.
emilmont 10:3bc89ef62ce7 106 // This wait is also included on the samples
emilmont 10:3bc89ef62ce7 107 // code provided with the freedom board
emilmont 10:3bc89ef62ce7 108 for (n = 0; n < 100; n++) __NOP();
emilmont 10:3bc89ef62ce7 109 first_read = 1;
Shikaneo 13:bd9ff402dd42 110 return 0;
emilmont 10:3bc89ef62ce7 111 }
emilmont 10:3bc89ef62ce7 112
emilmont 10:3bc89ef62ce7 113 static int timeout_status_poll(i2c_t *obj, uint32_t mask) {
emilmont 10:3bc89ef62ce7 114 uint32_t i, timeout = 1000;
emilmont 10:3bc89ef62ce7 115
emilmont 10:3bc89ef62ce7 116 for (i = 0; i < timeout; i++) {
emilmont 10:3bc89ef62ce7 117 if (obj->i2c->S & mask)
emilmont 10:3bc89ef62ce7 118 return 0;
emilmont 10:3bc89ef62ce7 119 }
emilmont 10:3bc89ef62ce7 120
emilmont 10:3bc89ef62ce7 121 return 1;
emilmont 10:3bc89ef62ce7 122 }
emilmont 10:3bc89ef62ce7 123
emilmont 10:3bc89ef62ce7 124 // this function waits the end of a tx transfer and return the status of the transaction:
emilmont 10:3bc89ef62ce7 125 // 0: OK ack received
emilmont 10:3bc89ef62ce7 126 // 1: OK ack not received
emilmont 10:3bc89ef62ce7 127 // 2: failure
emilmont 10:3bc89ef62ce7 128 static int i2c_wait_end_tx_transfer(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 129
emilmont 10:3bc89ef62ce7 130 // wait for the interrupt flag
emilmont 10:3bc89ef62ce7 131 if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
emilmont 10:3bc89ef62ce7 132 return 2;
emilmont 10:3bc89ef62ce7 133 }
emilmont 10:3bc89ef62ce7 134
emilmont 10:3bc89ef62ce7 135 obj->i2c->S |= I2C_S_IICIF_MASK;
emilmont 10:3bc89ef62ce7 136
emilmont 10:3bc89ef62ce7 137 // wait transfer complete
emilmont 10:3bc89ef62ce7 138 if (timeout_status_poll(obj, I2C_S_TCF_MASK)) {
emilmont 10:3bc89ef62ce7 139 return 2;
emilmont 10:3bc89ef62ce7 140 }
emilmont 10:3bc89ef62ce7 141
emilmont 10:3bc89ef62ce7 142 // check if we received the ACK or not
emilmont 10:3bc89ef62ce7 143 return obj->i2c->S & I2C_S_RXAK_MASK ? 1 : 0;
emilmont 10:3bc89ef62ce7 144 }
emilmont 10:3bc89ef62ce7 145
emilmont 10:3bc89ef62ce7 146 // this function waits the end of a rx transfer and return the status of the transaction:
emilmont 10:3bc89ef62ce7 147 // 0: OK
emilmont 10:3bc89ef62ce7 148 // 1: failure
emilmont 10:3bc89ef62ce7 149 static int i2c_wait_end_rx_transfer(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 150 // wait for the end of the rx transfer
emilmont 10:3bc89ef62ce7 151 if (timeout_status_poll(obj, I2C_S_IICIF_MASK)) {
emilmont 10:3bc89ef62ce7 152 return 1;
emilmont 10:3bc89ef62ce7 153 }
emilmont 10:3bc89ef62ce7 154
emilmont 10:3bc89ef62ce7 155 obj->i2c->S |= I2C_S_IICIF_MASK;
emilmont 10:3bc89ef62ce7 156
emilmont 10:3bc89ef62ce7 157 return 0;
emilmont 10:3bc89ef62ce7 158 }
emilmont 10:3bc89ef62ce7 159
emilmont 10:3bc89ef62ce7 160 static void i2c_send_nack(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 161 obj->i2c->C1 |= I2C_C1_TXAK_MASK; // NACK
emilmont 10:3bc89ef62ce7 162 }
emilmont 10:3bc89ef62ce7 163
emilmont 10:3bc89ef62ce7 164 static void i2c_send_ack(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 165 obj->i2c->C1 &= ~I2C_C1_TXAK_MASK; // ACK
emilmont 10:3bc89ef62ce7 166 }
emilmont 10:3bc89ef62ce7 167
emilmont 10:3bc89ef62ce7 168 static int i2c_do_write(i2c_t *obj, int value) {
emilmont 10:3bc89ef62ce7 169 // write the data
emilmont 10:3bc89ef62ce7 170 obj->i2c->D = value;
emilmont 10:3bc89ef62ce7 171
emilmont 10:3bc89ef62ce7 172 // init and wait the end of the transfer
emilmont 10:3bc89ef62ce7 173 return i2c_wait_end_tx_transfer(obj);
emilmont 10:3bc89ef62ce7 174 }
emilmont 10:3bc89ef62ce7 175
emilmont 10:3bc89ef62ce7 176 static int i2c_do_read(i2c_t *obj, char * data, int last) {
emilmont 10:3bc89ef62ce7 177 if (last)
emilmont 10:3bc89ef62ce7 178 i2c_send_nack(obj);
emilmont 10:3bc89ef62ce7 179 else
emilmont 10:3bc89ef62ce7 180 i2c_send_ack(obj);
emilmont 10:3bc89ef62ce7 181
emilmont 10:3bc89ef62ce7 182 *data = (obj->i2c->D & 0xFF);
emilmont 10:3bc89ef62ce7 183
emilmont 10:3bc89ef62ce7 184 // start rx transfer and wait the end of the transfer
emilmont 10:3bc89ef62ce7 185 return i2c_wait_end_rx_transfer(obj);
emilmont 10:3bc89ef62ce7 186 }
emilmont 10:3bc89ef62ce7 187
emilmont 10:3bc89ef62ce7 188 void i2c_frequency(i2c_t *obj, int hz) {
emilmont 10:3bc89ef62ce7 189 uint8_t icr = 0;
emilmont 10:3bc89ef62ce7 190 uint8_t mult = 0;
emilmont 10:3bc89ef62ce7 191 uint32_t error = 0;
emilmont 10:3bc89ef62ce7 192 uint32_t p_error = 0xffffffff;
emilmont 10:3bc89ef62ce7 193 uint32_t ref = 0;
emilmont 10:3bc89ef62ce7 194 uint8_t i, j;
emilmont 10:3bc89ef62ce7 195 // bus clk
emilmont 10:3bc89ef62ce7 196 uint32_t PCLK = 24000000u;
emilmont 10:3bc89ef62ce7 197 uint32_t pulse = PCLK / (hz * 2);
emilmont 10:3bc89ef62ce7 198
emilmont 10:3bc89ef62ce7 199 // we look for the values that minimize the error
emilmont 10:3bc89ef62ce7 200
emilmont 10:3bc89ef62ce7 201 // test all the MULT values
emilmont 10:3bc89ef62ce7 202 for (i = 1; i < 5; i*=2) {
emilmont 10:3bc89ef62ce7 203 for (j = 0; j < 0x40; j++) {
emilmont 10:3bc89ef62ce7 204 ref = PCLK / (i*ICR[j]);
emilmont 10:3bc89ef62ce7 205 error = (ref > hz) ? ref - hz : hz - ref;
emilmont 10:3bc89ef62ce7 206 if (error < p_error) {
emilmont 10:3bc89ef62ce7 207 icr = j;
emilmont 10:3bc89ef62ce7 208 mult = i/2;
emilmont 10:3bc89ef62ce7 209 p_error = error;
emilmont 10:3bc89ef62ce7 210 }
emilmont 10:3bc89ef62ce7 211 }
emilmont 10:3bc89ef62ce7 212 }
emilmont 10:3bc89ef62ce7 213 pulse = icr | (mult << 6);
emilmont 10:3bc89ef62ce7 214
emilmont 10:3bc89ef62ce7 215 // I2C Rate
emilmont 10:3bc89ef62ce7 216 obj->i2c->F = pulse;
emilmont 10:3bc89ef62ce7 217 }
emilmont 10:3bc89ef62ce7 218
emilmont 10:3bc89ef62ce7 219 int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
emilmont 10:3bc89ef62ce7 220 uint8_t count;
emilmont 10:3bc89ef62ce7 221 char dummy_read, *ptr;
emilmont 10:3bc89ef62ce7 222
emilmont 10:3bc89ef62ce7 223 if (i2c_start(obj)) {
emilmont 10:3bc89ef62ce7 224 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 225 return 1;
emilmont 10:3bc89ef62ce7 226 }
emilmont 10:3bc89ef62ce7 227
emilmont 10:3bc89ef62ce7 228 if (i2c_do_write(obj, (address | 0x01))) {
emilmont 10:3bc89ef62ce7 229 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 230 return 1;
emilmont 10:3bc89ef62ce7 231 }
emilmont 10:3bc89ef62ce7 232
emilmont 10:3bc89ef62ce7 233 // set rx mode
emilmont 10:3bc89ef62ce7 234 obj->i2c->C1 &= ~I2C_C1_TX_MASK;
emilmont 10:3bc89ef62ce7 235
emilmont 10:3bc89ef62ce7 236 // Read in bytes
emilmont 10:3bc89ef62ce7 237 for (count = 0; count < (length); count++) {
emilmont 10:3bc89ef62ce7 238 ptr = (count == 0) ? &dummy_read : &data[count - 1];
emilmont 10:3bc89ef62ce7 239 uint8_t stop_ = (count == (length - 1)) ? 1 : 0;
emilmont 10:3bc89ef62ce7 240 if (i2c_do_read(obj, ptr, stop_)) {
emilmont 10:3bc89ef62ce7 241 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 242 return 1;
emilmont 10:3bc89ef62ce7 243 }
emilmont 10:3bc89ef62ce7 244 }
emilmont 10:3bc89ef62ce7 245
emilmont 10:3bc89ef62ce7 246 // If not repeated start, send stop.
emilmont 10:3bc89ef62ce7 247 if (stop) {
emilmont 10:3bc89ef62ce7 248 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 249 }
emilmont 10:3bc89ef62ce7 250
emilmont 10:3bc89ef62ce7 251 // last read
emilmont 10:3bc89ef62ce7 252 data[count-1] = obj->i2c->D;
emilmont 10:3bc89ef62ce7 253
emilmont 10:3bc89ef62ce7 254 return 0;
emilmont 10:3bc89ef62ce7 255 }
emilmont 10:3bc89ef62ce7 256 int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
emilmont 10:3bc89ef62ce7 257 int i;
emilmont 10:3bc89ef62ce7 258
emilmont 10:3bc89ef62ce7 259 if (i2c_start(obj)) {
emilmont 10:3bc89ef62ce7 260 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 261 return 1;
emilmont 10:3bc89ef62ce7 262 }
emilmont 10:3bc89ef62ce7 263
emilmont 10:3bc89ef62ce7 264 if (i2c_do_write(obj, (address & 0xFE))) {
emilmont 10:3bc89ef62ce7 265 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 266 return 1;
emilmont 10:3bc89ef62ce7 267 }
emilmont 10:3bc89ef62ce7 268
emilmont 10:3bc89ef62ce7 269 for (i = 0; i < length; i++) {
emilmont 10:3bc89ef62ce7 270 if(i2c_do_write(obj, data[i])) {
emilmont 10:3bc89ef62ce7 271 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 272 return 1;
emilmont 10:3bc89ef62ce7 273 }
emilmont 10:3bc89ef62ce7 274 }
emilmont 10:3bc89ef62ce7 275
emilmont 10:3bc89ef62ce7 276 if (stop) {
emilmont 10:3bc89ef62ce7 277 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 278 }
emilmont 10:3bc89ef62ce7 279
emilmont 10:3bc89ef62ce7 280 return 0;
emilmont 10:3bc89ef62ce7 281 }
emilmont 10:3bc89ef62ce7 282
emilmont 10:3bc89ef62ce7 283 void i2c_reset(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 284 i2c_stop(obj);
emilmont 10:3bc89ef62ce7 285 }
emilmont 10:3bc89ef62ce7 286
emilmont 10:3bc89ef62ce7 287 int i2c_byte_read(i2c_t *obj, int last) {
emilmont 10:3bc89ef62ce7 288 char data;
emilmont 10:3bc89ef62ce7 289
emilmont 10:3bc89ef62ce7 290 // set rx mode
emilmont 10:3bc89ef62ce7 291 obj->i2c->C1 &= ~I2C_C1_TX_MASK;
emilmont 10:3bc89ef62ce7 292
emilmont 10:3bc89ef62ce7 293 if(first_read) {
emilmont 10:3bc89ef62ce7 294 // first dummy read
emilmont 10:3bc89ef62ce7 295 i2c_do_read(obj, &data, 0);
emilmont 10:3bc89ef62ce7 296 first_read = 0;
emilmont 10:3bc89ef62ce7 297 }
emilmont 10:3bc89ef62ce7 298
emilmont 10:3bc89ef62ce7 299 if (last) {
emilmont 10:3bc89ef62ce7 300 // set tx mode
emilmont 10:3bc89ef62ce7 301 obj->i2c->C1 |= I2C_C1_TX_MASK;
emilmont 10:3bc89ef62ce7 302 return obj->i2c->D;
emilmont 10:3bc89ef62ce7 303 }
emilmont 10:3bc89ef62ce7 304
emilmont 10:3bc89ef62ce7 305 i2c_do_read(obj, &data, last);
emilmont 10:3bc89ef62ce7 306
emilmont 10:3bc89ef62ce7 307 return data;
emilmont 10:3bc89ef62ce7 308 }
emilmont 10:3bc89ef62ce7 309
emilmont 10:3bc89ef62ce7 310 int i2c_byte_write(i2c_t *obj, int data) {
emilmont 10:3bc89ef62ce7 311 first_read = 1;
emilmont 10:3bc89ef62ce7 312
emilmont 10:3bc89ef62ce7 313 // set tx mode
emilmont 10:3bc89ef62ce7 314 obj->i2c->C1 |= I2C_C1_TX_MASK;
emilmont 10:3bc89ef62ce7 315
emilmont 10:3bc89ef62ce7 316 return !i2c_do_write(obj, (data & 0xFF));
emilmont 10:3bc89ef62ce7 317 }
emilmont 10:3bc89ef62ce7 318
emilmont 10:3bc89ef62ce7 319
emilmont 10:3bc89ef62ce7 320 #if DEVICE_I2CSLAVE
emilmont 10:3bc89ef62ce7 321 void i2c_slave_mode(i2c_t *obj, int enable_slave) {
emilmont 10:3bc89ef62ce7 322 if (enable_slave) {
emilmont 10:3bc89ef62ce7 323 // set slave mode
emilmont 10:3bc89ef62ce7 324 obj->i2c->C1 &= ~I2C_C1_MST_MASK;
emilmont 10:3bc89ef62ce7 325 obj->i2c->C1 |= I2C_C1_IICIE_MASK;
emilmont 10:3bc89ef62ce7 326 } else {
emilmont 10:3bc89ef62ce7 327 // set master mode
emilmont 10:3bc89ef62ce7 328 obj->i2c->C1 |= I2C_C1_MST_MASK;
emilmont 10:3bc89ef62ce7 329 }
emilmont 10:3bc89ef62ce7 330 }
emilmont 10:3bc89ef62ce7 331
emilmont 10:3bc89ef62ce7 332 int i2c_slave_receive(i2c_t *obj) {
emilmont 10:3bc89ef62ce7 333 switch(obj->i2c->S) {
emilmont 10:3bc89ef62ce7 334 // read addressed
emilmont 10:3bc89ef62ce7 335 case 0xE6: return 1;
emilmont 10:3bc89ef62ce7 336
emilmont 10:3bc89ef62ce7 337 // write addressed
emilmont 10:3bc89ef62ce7 338 case 0xE2: return 3;
emilmont 10:3bc89ef62ce7 339
emilmont 10:3bc89ef62ce7 340 default: return 0;
emilmont 10:3bc89ef62ce7 341 }
emilmont 10:3bc89ef62ce7 342 }
emilmont 10:3bc89ef62ce7 343
emilmont 10:3bc89ef62ce7 344 int i2c_slave_read(i2c_t *obj, char *data, int length) {
emilmont 10:3bc89ef62ce7 345 uint8_t dummy_read, count;
emilmont 10:3bc89ef62ce7 346 uint8_t * ptr;
emilmont 10:3bc89ef62ce7 347
emilmont 10:3bc89ef62ce7 348 // set rx mode
emilmont 10:3bc89ef62ce7 349 obj->i2c->C1 &= ~I2C_C1_TX_MASK;
emilmont 10:3bc89ef62ce7 350
emilmont 10:3bc89ef62ce7 351 // first dummy read
emilmont 10:3bc89ef62ce7 352 dummy_read = obj->i2c->D;
emilmont 10:3bc89ef62ce7 353 if(i2c_wait_end_rx_transfer(obj)) {
emilmont 10:3bc89ef62ce7 354 return 0;
emilmont 10:3bc89ef62ce7 355 }
emilmont 10:3bc89ef62ce7 356
emilmont 10:3bc89ef62ce7 357 // read address
emilmont 10:3bc89ef62ce7 358 dummy_read = obj->i2c->D;
emilmont 10:3bc89ef62ce7 359 if(i2c_wait_end_rx_transfer(obj)) {
emilmont 10:3bc89ef62ce7 360 return 0;
emilmont 10:3bc89ef62ce7 361 }
emilmont 10:3bc89ef62ce7 362
emilmont 10:3bc89ef62ce7 363 // read (length - 1) bytes
emilmont 10:3bc89ef62ce7 364 for (count = 0; count < (length - 1); count++) {
emilmont 10:3bc89ef62ce7 365 data[count] = obj->i2c->D;
emilmont 10:3bc89ef62ce7 366 if(i2c_wait_end_rx_transfer(obj)) {
emilmont 10:3bc89ef62ce7 367 return 0;
emilmont 10:3bc89ef62ce7 368 }
emilmont 10:3bc89ef62ce7 369 }
emilmont 10:3bc89ef62ce7 370
emilmont 10:3bc89ef62ce7 371 // read last byte
emilmont 10:3bc89ef62ce7 372 ptr = (length == 0) ? &dummy_read : (uint8_t *)&data[count];
emilmont 10:3bc89ef62ce7 373 *ptr = obj->i2c->D;
emilmont 10:3bc89ef62ce7 374
emilmont 10:3bc89ef62ce7 375 return (length) ? (count + 1) : 0;
emilmont 10:3bc89ef62ce7 376 }
emilmont 10:3bc89ef62ce7 377
emilmont 10:3bc89ef62ce7 378 int i2c_slave_write(i2c_t *obj, const char *data, int length) {
emilmont 10:3bc89ef62ce7 379 uint32_t i, count = 0;
emilmont 10:3bc89ef62ce7 380
emilmont 10:3bc89ef62ce7 381 // set tx mode
emilmont 10:3bc89ef62ce7 382 obj->i2c->C1 |= I2C_C1_TX_MASK;
emilmont 10:3bc89ef62ce7 383
emilmont 10:3bc89ef62ce7 384 for (i = 0; i < length; i++) {
emilmont 10:3bc89ef62ce7 385 if(i2c_do_write(obj, data[count++]) == 2) {
emilmont 10:3bc89ef62ce7 386 return 0;
emilmont 10:3bc89ef62ce7 387 }
emilmont 10:3bc89ef62ce7 388 }
emilmont 10:3bc89ef62ce7 389
emilmont 10:3bc89ef62ce7 390 // set rx mode
emilmont 10:3bc89ef62ce7 391 obj->i2c->C1 &= ~I2C_C1_TX_MASK;
emilmont 10:3bc89ef62ce7 392
emilmont 10:3bc89ef62ce7 393 // dummy rx transfer needed
emilmont 10:3bc89ef62ce7 394 // otherwise the master cannot generate a stop bit
emilmont 10:3bc89ef62ce7 395 obj->i2c->D;
emilmont 10:3bc89ef62ce7 396 if(i2c_wait_end_rx_transfer(obj) == 2) {
emilmont 10:3bc89ef62ce7 397 return 0;
emilmont 10:3bc89ef62ce7 398 }
emilmont 10:3bc89ef62ce7 399
emilmont 10:3bc89ef62ce7 400 return count;
emilmont 10:3bc89ef62ce7 401 }
emilmont 10:3bc89ef62ce7 402
emilmont 10:3bc89ef62ce7 403 void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
emilmont 10:3bc89ef62ce7 404 obj->i2c->A1 = address & 0xfe;
emilmont 10:3bc89ef62ce7 405 }
emilmont 10:3bc89ef62ce7 406 #endif
emilmont 10:3bc89ef62ce7 407