grbl_1_ - I'm trying to port GRBL 1.1 to the STM32F746 chip…

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I'm trying to port GRBL 1.1 to the STM32F746 chip. Tell me the solution, thanks.

cmsis/core_cm3.h@0:9dcf85d9b2f3, 2017-09-04 (annotated)

Committer:: Sergunb
Date:: Mon Sep 04 12:05:05 2017 +0000
Revision:: 0:9dcf85d9b2f3

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
Sergunb	0:9dcf85d9b2f3	1	/************************************************************************//
Sergunb	0:9dcf85d9b2f3	2	* @file core_cm3.h
Sergunb	0:9dcf85d9b2f3	3	* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
Sergunb	0:9dcf85d9b2f3	4	* @version V3.01
Sergunb	0:9dcf85d9b2f3	5	* @date 22. March 2012
Sergunb	0:9dcf85d9b2f3	6	*
Sergunb	0:9dcf85d9b2f3	7	* @note
Sergunb	0:9dcf85d9b2f3	8	* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
Sergunb	0:9dcf85d9b2f3	9	*
Sergunb	0:9dcf85d9b2f3	10	* @par
Sergunb	0:9dcf85d9b2f3	11	* ARM Limited (ARM) is supplying this software for use with Cortex-M
Sergunb	0:9dcf85d9b2f3	12	* processor based microcontrollers. This file can be freely distributed
Sergunb	0:9dcf85d9b2f3	13	* within development tools that are supporting such ARM based processors.
Sergunb	0:9dcf85d9b2f3	14	*
Sergunb	0:9dcf85d9b2f3	15	* @par
Sergunb	0:9dcf85d9b2f3	16	* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Sergunb	0:9dcf85d9b2f3	17	* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Sergunb	0:9dcf85d9b2f3	18	* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Sergunb	0:9dcf85d9b2f3	19	* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Sergunb	0:9dcf85d9b2f3	20	* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Sergunb	0:9dcf85d9b2f3	21	*
Sergunb	0:9dcf85d9b2f3	22	******************************************************************************/
Sergunb	0:9dcf85d9b2f3	23	#if defined ( __ICCARM__ )
Sergunb	0:9dcf85d9b2f3	24	#pragma system_include /* treat file as system include file for MISRA check */
Sergunb	0:9dcf85d9b2f3	25	#endif
Sergunb	0:9dcf85d9b2f3	26
Sergunb	0:9dcf85d9b2f3	27	#ifdef __cplusplus
Sergunb	0:9dcf85d9b2f3	28	extern "C" {
Sergunb	0:9dcf85d9b2f3	29	#endif
Sergunb	0:9dcf85d9b2f3	30
Sergunb	0:9dcf85d9b2f3	31	#ifndef __CORE_CM3_H_GENERIC
Sergunb	0:9dcf85d9b2f3	32	#define __CORE_CM3_H_GENERIC
Sergunb	0:9dcf85d9b2f3	33
Sergunb	0:9dcf85d9b2f3	34	/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
Sergunb	0:9dcf85d9b2f3	35	CMSIS violates the following MISRA-C:2004 rules:
Sergunb	0:9dcf85d9b2f3	36
Sergunb	0:9dcf85d9b2f3	37	\li Required Rule 8.5, object/function definition in header file.<br>
Sergunb	0:9dcf85d9b2f3	38	Function definitions in header files are used to allow 'inlining'.
Sergunb	0:9dcf85d9b2f3	39
Sergunb	0:9dcf85d9b2f3	40	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Sergunb	0:9dcf85d9b2f3	41	Unions are used for effective representation of core registers.
Sergunb	0:9dcf85d9b2f3	42
Sergunb	0:9dcf85d9b2f3	43	\li Advisory Rule 19.7, Function-like macro defined.<br>
Sergunb	0:9dcf85d9b2f3	44	Function-like macros are used to allow more efficient code.
Sergunb	0:9dcf85d9b2f3	45	*/
Sergunb	0:9dcf85d9b2f3	46
Sergunb	0:9dcf85d9b2f3	47
Sergunb	0:9dcf85d9b2f3	48	/*******************************************************************************
Sergunb	0:9dcf85d9b2f3	49	* CMSIS definitions
Sergunb	0:9dcf85d9b2f3	50	******************************************************************************/
Sergunb	0:9dcf85d9b2f3	51	/** \ingroup Cortex_M3
Sergunb	0:9dcf85d9b2f3	52	@{
Sergunb	0:9dcf85d9b2f3	53	*/
Sergunb	0:9dcf85d9b2f3	54
Sergunb	0:9dcf85d9b2f3	55	/* CMSIS CM3 definitions */
Sergunb	0:9dcf85d9b2f3	56	#define __CM3_CMSIS_VERSION_MAIN (0x03) /!< [31:16] CMSIS HAL main version /
Sergunb	0:9dcf85d9b2f3	57	#define __CM3_CMSIS_VERSION_SUB (0x01) /!< [15:0] CMSIS HAL sub version /
Sergunb	0:9dcf85d9b2f3	58	#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) \| \
Sergunb	0:9dcf85d9b2f3	59	__CM3_CMSIS_VERSION_SUB ) /!< CMSIS HAL version number /
Sergunb	0:9dcf85d9b2f3	60
Sergunb	0:9dcf85d9b2f3	61	#define __CORTEX_M (0x03) /!< Cortex-M Core /
Sergunb	0:9dcf85d9b2f3	62
Sergunb	0:9dcf85d9b2f3	63
Sergunb	0:9dcf85d9b2f3	64	#if defined ( __CC_ARM )
Sergunb	0:9dcf85d9b2f3	65	#define __ASM __asm /!< asm keyword for ARM Compiler /
Sergunb	0:9dcf85d9b2f3	66	#define __INLINE __inline /!< inline keyword for ARM Compiler /
Sergunb	0:9dcf85d9b2f3	67	#define __STATIC_INLINE static __inline
Sergunb	0:9dcf85d9b2f3	68
Sergunb	0:9dcf85d9b2f3	69	#elif defined ( __ICCARM__ )
Sergunb	0:9dcf85d9b2f3	70	#define __ASM __asm /!< asm keyword for IAR Compiler /
Sergunb	0:9dcf85d9b2f3	71	#define __INLINE inline /!< inline keyword for IAR Compiler. Only available in High optimization mode! /
Sergunb	0:9dcf85d9b2f3	72	#define __STATIC_INLINE static inline
Sergunb	0:9dcf85d9b2f3	73
Sergunb	0:9dcf85d9b2f3	74	#elif defined ( __TMS470__ )
Sergunb	0:9dcf85d9b2f3	75	#define __ASM __asm /!< asm keyword for TI CCS Compiler /
Sergunb	0:9dcf85d9b2f3	76	#define __STATIC_INLINE static inline
Sergunb	0:9dcf85d9b2f3	77
Sergunb	0:9dcf85d9b2f3	78	#elif defined ( __GNUC__ )
Sergunb	0:9dcf85d9b2f3	79	#define __ASM __asm /!< asm keyword for GNU Compiler /
Sergunb	0:9dcf85d9b2f3	80	#define __INLINE inline /!< inline keyword for GNU Compiler /
Sergunb	0:9dcf85d9b2f3	81	#define __STATIC_INLINE static inline
Sergunb	0:9dcf85d9b2f3	82
Sergunb	0:9dcf85d9b2f3	83	#elif defined ( __TASKING__ )
Sergunb	0:9dcf85d9b2f3	84	#define __ASM __asm /!< asm keyword for TASKING Compiler /
Sergunb	0:9dcf85d9b2f3	85	#define __INLINE inline /!< inline keyword for TASKING Compiler /
Sergunb	0:9dcf85d9b2f3	86	#define __STATIC_INLINE static inline
Sergunb	0:9dcf85d9b2f3	87
Sergunb	0:9dcf85d9b2f3	88	#endif
Sergunb	0:9dcf85d9b2f3	89
Sergunb	0:9dcf85d9b2f3	90	/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
Sergunb	0:9dcf85d9b2f3	91	*/
Sergunb	0:9dcf85d9b2f3	92	#define __FPU_USED 0
Sergunb	0:9dcf85d9b2f3	93
Sergunb	0:9dcf85d9b2f3	94	#if defined ( __CC_ARM )
Sergunb	0:9dcf85d9b2f3	95	#if defined __TARGET_FPU_VFP
Sergunb	0:9dcf85d9b2f3	96	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Sergunb	0:9dcf85d9b2f3	97	#endif
Sergunb	0:9dcf85d9b2f3	98
Sergunb	0:9dcf85d9b2f3	99	#elif defined ( __ICCARM__ )
Sergunb	0:9dcf85d9b2f3	100	#if defined __ARMVFP__
Sergunb	0:9dcf85d9b2f3	101	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Sergunb	0:9dcf85d9b2f3	102	#endif
Sergunb	0:9dcf85d9b2f3	103
Sergunb	0:9dcf85d9b2f3	104	#elif defined ( __TMS470__ )
Sergunb	0:9dcf85d9b2f3	105	#if defined __TI__VFP_SUPPORT____
Sergunb	0:9dcf85d9b2f3	106	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Sergunb	0:9dcf85d9b2f3	107	#endif
Sergunb	0:9dcf85d9b2f3	108
Sergunb	0:9dcf85d9b2f3	109	#elif defined ( __GNUC__ )
Sergunb	0:9dcf85d9b2f3	110	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
Sergunb	0:9dcf85d9b2f3	111	#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Sergunb	0:9dcf85d9b2f3	112	#endif
Sergunb	0:9dcf85d9b2f3	113
Sergunb	0:9dcf85d9b2f3	114	#elif defined ( __TASKING__ )
Sergunb	0:9dcf85d9b2f3	115	#if defined __FPU_VFP__
Sergunb	0:9dcf85d9b2f3	116	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Sergunb	0:9dcf85d9b2f3	117	#endif
Sergunb	0:9dcf85d9b2f3	118	#endif
Sergunb	0:9dcf85d9b2f3	119
Sergunb	0:9dcf85d9b2f3	120	#include <stdint.h> /* standard types definitions */
Sergunb	0:9dcf85d9b2f3	121	#include <core_cmInstr.h> /* Core Instruction Access */
Sergunb	0:9dcf85d9b2f3	122	#include <core_cmFunc.h> /* Core Function Access */
Sergunb	0:9dcf85d9b2f3	123
Sergunb	0:9dcf85d9b2f3	124	#endif /* __CORE_CM3_H_GENERIC */
Sergunb	0:9dcf85d9b2f3	125
Sergunb	0:9dcf85d9b2f3	126	#ifndef __CMSIS_GENERIC
Sergunb	0:9dcf85d9b2f3	127
Sergunb	0:9dcf85d9b2f3	128	#ifndef __CORE_CM3_H_DEPENDANT
Sergunb	0:9dcf85d9b2f3	129	#define __CORE_CM3_H_DEPENDANT
Sergunb	0:9dcf85d9b2f3	130
Sergunb	0:9dcf85d9b2f3	131	/* check device defines and use defaults */
Sergunb	0:9dcf85d9b2f3	132	#if defined __CHECK_DEVICE_DEFINES
Sergunb	0:9dcf85d9b2f3	133	#ifndef __CM3_REV
Sergunb	0:9dcf85d9b2f3	134	#define __CM3_REV 0x0200
Sergunb	0:9dcf85d9b2f3	135	#warning "__CM3_REV not defined in device header file; using default!"
Sergunb	0:9dcf85d9b2f3	136	#endif
Sergunb	0:9dcf85d9b2f3	137
Sergunb	0:9dcf85d9b2f3	138	#ifndef __MPU_PRESENT
Sergunb	0:9dcf85d9b2f3	139	#define __MPU_PRESENT 0
Sergunb	0:9dcf85d9b2f3	140	#warning "__MPU_PRESENT not defined in device header file; using default!"
Sergunb	0:9dcf85d9b2f3	141	#endif
Sergunb	0:9dcf85d9b2f3	142
Sergunb	0:9dcf85d9b2f3	143	#ifndef __NVIC_PRIO_BITS
Sergunb	0:9dcf85d9b2f3	144	#define __NVIC_PRIO_BITS 4
Sergunb	0:9dcf85d9b2f3	145	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
Sergunb	0:9dcf85d9b2f3	146	#endif
Sergunb	0:9dcf85d9b2f3	147
Sergunb	0:9dcf85d9b2f3	148	#ifndef __Vendor_SysTickConfig
Sergunb	0:9dcf85d9b2f3	149	#define __Vendor_SysTickConfig 0
Sergunb	0:9dcf85d9b2f3	150	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
Sergunb	0:9dcf85d9b2f3	151	#endif
Sergunb	0:9dcf85d9b2f3	152	#endif
Sergunb	0:9dcf85d9b2f3	153
Sergunb	0:9dcf85d9b2f3	154	/* IO definitions (access restrictions to peripheral registers) */
Sergunb	0:9dcf85d9b2f3	155	/**
Sergunb	0:9dcf85d9b2f3	156	\defgroup CMSIS_glob_defs CMSIS Global Defines
Sergunb	0:9dcf85d9b2f3	157
Sergunb	0:9dcf85d9b2f3	158	<strong>IO Type Qualifiers</strong> are used
Sergunb	0:9dcf85d9b2f3	159	\li to specify the access to peripheral variables.
Sergunb	0:9dcf85d9b2f3	160	\li for automatic generation of peripheral register debug information.
Sergunb	0:9dcf85d9b2f3	161	*/
Sergunb	0:9dcf85d9b2f3	162	#ifdef __cplusplus
Sergunb	0:9dcf85d9b2f3	163	#define __I volatile /!< Defines 'read only' permissions /
Sergunb	0:9dcf85d9b2f3	164	#else
Sergunb	0:9dcf85d9b2f3	165	#define __I volatile const /!< Defines 'read only' permissions /
Sergunb	0:9dcf85d9b2f3	166	#endif
Sergunb	0:9dcf85d9b2f3	167	#define __O volatile /!< Defines 'write only' permissions /
Sergunb	0:9dcf85d9b2f3	168	#define __IO volatile /!< Defines 'read / write' permissions /
Sergunb	0:9dcf85d9b2f3	169
Sergunb	0:9dcf85d9b2f3	170	/@} end of group Cortex_M3 /
Sergunb	0:9dcf85d9b2f3	171
Sergunb	0:9dcf85d9b2f3	172
Sergunb	0:9dcf85d9b2f3	173
Sergunb	0:9dcf85d9b2f3	174	/*******************************************************************************
Sergunb	0:9dcf85d9b2f3	175	* Register Abstraction
Sergunb	0:9dcf85d9b2f3	176	Core Register contain:
Sergunb	0:9dcf85d9b2f3	177	- Core Register
Sergunb	0:9dcf85d9b2f3	178	- Core NVIC Register
Sergunb	0:9dcf85d9b2f3	179	- Core SCB Register
Sergunb	0:9dcf85d9b2f3	180	- Core SysTick Register
Sergunb	0:9dcf85d9b2f3	181	- Core Debug Register
Sergunb	0:9dcf85d9b2f3	182	- Core MPU Register
Sergunb	0:9dcf85d9b2f3	183	******************************************************************************/
Sergunb	0:9dcf85d9b2f3	184	/** \defgroup CMSIS_core_register Defines and Type Definitions
Sergunb	0:9dcf85d9b2f3	185	\brief Type definitions and defines for Cortex-M processor based devices.
Sergunb	0:9dcf85d9b2f3	186	*/
Sergunb	0:9dcf85d9b2f3	187
Sergunb	0:9dcf85d9b2f3	188	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	189	\defgroup CMSIS_CORE Status and Control Registers
Sergunb	0:9dcf85d9b2f3	190	\brief Core Register type definitions.
Sergunb	0:9dcf85d9b2f3	191	@{
Sergunb	0:9dcf85d9b2f3	192	*/
Sergunb	0:9dcf85d9b2f3	193
Sergunb	0:9dcf85d9b2f3	194	/** \brief Union type to access the Application Program Status Register (APSR).
Sergunb	0:9dcf85d9b2f3	195	*/
Sergunb	0:9dcf85d9b2f3	196	typedef union
Sergunb	0:9dcf85d9b2f3	197	{
Sergunb	0:9dcf85d9b2f3	198	struct
Sergunb	0:9dcf85d9b2f3	199	{
Sergunb	0:9dcf85d9b2f3	200	#if (__CORTEX_M != 0x04)
Sergunb	0:9dcf85d9b2f3	201	uint32_t _reserved0:27; /!< bit: 0..26 Reserved /
Sergunb	0:9dcf85d9b2f3	202	#else
Sergunb	0:9dcf85d9b2f3	203	uint32_t _reserved0:16; /!< bit: 0..15 Reserved /
Sergunb	0:9dcf85d9b2f3	204	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Sergunb	0:9dcf85d9b2f3	205	uint32_t _reserved1:7; /!< bit: 20..26 Reserved /
Sergunb	0:9dcf85d9b2f3	206	#endif
Sergunb	0:9dcf85d9b2f3	207	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Sergunb	0:9dcf85d9b2f3	208	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Sergunb	0:9dcf85d9b2f3	209	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Sergunb	0:9dcf85d9b2f3	210	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Sergunb	0:9dcf85d9b2f3	211	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Sergunb	0:9dcf85d9b2f3	212	} b; /!< Structure used for bit access /
Sergunb	0:9dcf85d9b2f3	213	uint32_t w; /!< Type used for word access /
Sergunb	0:9dcf85d9b2f3	214	} APSR_Type;
Sergunb	0:9dcf85d9b2f3	215
Sergunb	0:9dcf85d9b2f3	216
Sergunb	0:9dcf85d9b2f3	217	/** \brief Union type to access the Interrupt Program Status Register (IPSR).
Sergunb	0:9dcf85d9b2f3	218	*/
Sergunb	0:9dcf85d9b2f3	219	typedef union
Sergunb	0:9dcf85d9b2f3	220	{
Sergunb	0:9dcf85d9b2f3	221	struct
Sergunb	0:9dcf85d9b2f3	222	{
Sergunb	0:9dcf85d9b2f3	223	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Sergunb	0:9dcf85d9b2f3	224	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
Sergunb	0:9dcf85d9b2f3	225	} b; /!< Structure used for bit access /
Sergunb	0:9dcf85d9b2f3	226	uint32_t w; /!< Type used for word access /
Sergunb	0:9dcf85d9b2f3	227	} IPSR_Type;
Sergunb	0:9dcf85d9b2f3	228
Sergunb	0:9dcf85d9b2f3	229
Sergunb	0:9dcf85d9b2f3	230	/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
Sergunb	0:9dcf85d9b2f3	231	*/
Sergunb	0:9dcf85d9b2f3	232	typedef union
Sergunb	0:9dcf85d9b2f3	233	{
Sergunb	0:9dcf85d9b2f3	234	struct
Sergunb	0:9dcf85d9b2f3	235	{
Sergunb	0:9dcf85d9b2f3	236	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
Sergunb	0:9dcf85d9b2f3	237	#if (__CORTEX_M != 0x04)
Sergunb	0:9dcf85d9b2f3	238	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
Sergunb	0:9dcf85d9b2f3	239	#else
Sergunb	0:9dcf85d9b2f3	240	uint32_t _reserved0:7; /!< bit: 9..15 Reserved /
Sergunb	0:9dcf85d9b2f3	241	uint32_t GE:4; /!< bit: 16..19 Greater than or Equal flags /
Sergunb	0:9dcf85d9b2f3	242	uint32_t _reserved1:4; /!< bit: 20..23 Reserved /
Sergunb	0:9dcf85d9b2f3	243	#endif
Sergunb	0:9dcf85d9b2f3	244	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
Sergunb	0:9dcf85d9b2f3	245	uint32_t IT:2; /!< bit: 25..26 saved IT state (read 0) /
Sergunb	0:9dcf85d9b2f3	246	uint32_t Q:1; /!< bit: 27 Saturation condition flag /
Sergunb	0:9dcf85d9b2f3	247	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
Sergunb	0:9dcf85d9b2f3	248	uint32_t C:1; /!< bit: 29 Carry condition code flag /
Sergunb	0:9dcf85d9b2f3	249	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
Sergunb	0:9dcf85d9b2f3	250	uint32_t N:1; /!< bit: 31 Negative condition code flag /
Sergunb	0:9dcf85d9b2f3	251	} b; /!< Structure used for bit access /
Sergunb	0:9dcf85d9b2f3	252	uint32_t w; /!< Type used for word access /
Sergunb	0:9dcf85d9b2f3	253	} xPSR_Type;
Sergunb	0:9dcf85d9b2f3	254
Sergunb	0:9dcf85d9b2f3	255
Sergunb	0:9dcf85d9b2f3	256	/** \brief Union type to access the Control Registers (CONTROL).
Sergunb	0:9dcf85d9b2f3	257	*/
Sergunb	0:9dcf85d9b2f3	258	typedef union
Sergunb	0:9dcf85d9b2f3	259	{
Sergunb	0:9dcf85d9b2f3	260	struct
Sergunb	0:9dcf85d9b2f3	261	{
Sergunb	0:9dcf85d9b2f3	262	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
Sergunb	0:9dcf85d9b2f3	263	uint32_t SPSEL:1; /!< bit: 1 Stack to be used /
Sergunb	0:9dcf85d9b2f3	264	uint32_t FPCA:1; /!< bit: 2 FP extension active flag /
Sergunb	0:9dcf85d9b2f3	265	uint32_t _reserved0:29; /!< bit: 3..31 Reserved /
Sergunb	0:9dcf85d9b2f3	266	} b; /!< Structure used for bit access /
Sergunb	0:9dcf85d9b2f3	267	uint32_t w; /!< Type used for word access /
Sergunb	0:9dcf85d9b2f3	268	} CONTROL_Type;
Sergunb	0:9dcf85d9b2f3	269
Sergunb	0:9dcf85d9b2f3	270	/@} end of group CMSIS_CORE /
Sergunb	0:9dcf85d9b2f3	271
Sergunb	0:9dcf85d9b2f3	272
Sergunb	0:9dcf85d9b2f3	273	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	274	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
Sergunb	0:9dcf85d9b2f3	275	\brief Type definitions for the NVIC Registers
Sergunb	0:9dcf85d9b2f3	276	@{
Sergunb	0:9dcf85d9b2f3	277	*/
Sergunb	0:9dcf85d9b2f3	278
Sergunb	0:9dcf85d9b2f3	279	/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Sergunb	0:9dcf85d9b2f3	280	*/
Sergunb	0:9dcf85d9b2f3	281	typedef struct
Sergunb	0:9dcf85d9b2f3	282	{
Sergunb	0:9dcf85d9b2f3	283	__IO uint32_t ISER[8]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
Sergunb	0:9dcf85d9b2f3	284	uint32_t RESERVED0[24];
Sergunb	0:9dcf85d9b2f3	285	__IO uint32_t ICER[8]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
Sergunb	0:9dcf85d9b2f3	286	uint32_t RSERVED1[24];
Sergunb	0:9dcf85d9b2f3	287	__IO uint32_t ISPR[8]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
Sergunb	0:9dcf85d9b2f3	288	uint32_t RESERVED2[24];
Sergunb	0:9dcf85d9b2f3	289	__IO uint32_t ICPR[8]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
Sergunb	0:9dcf85d9b2f3	290	uint32_t RESERVED3[24];
Sergunb	0:9dcf85d9b2f3	291	__IO uint32_t IABR[8]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
Sergunb	0:9dcf85d9b2f3	292	uint32_t RESERVED4[56];
Sergunb	0:9dcf85d9b2f3	293	__IO uint8_t IP[240]; /!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) /
Sergunb	0:9dcf85d9b2f3	294	uint32_t RESERVED5[644];
Sergunb	0:9dcf85d9b2f3	295	__O uint32_t STIR; /!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register /
Sergunb	0:9dcf85d9b2f3	296	} NVIC_Type;
Sergunb	0:9dcf85d9b2f3	297
Sergunb	0:9dcf85d9b2f3	298	/* Software Triggered Interrupt Register Definitions */
Sergunb	0:9dcf85d9b2f3	299	#define NVIC_STIR_INTID_Pos 0 /!< STIR: INTLINESNUM Position /
Sergunb	0:9dcf85d9b2f3	300	#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /!< STIR: INTLINESNUM Mask /
Sergunb	0:9dcf85d9b2f3	301
Sergunb	0:9dcf85d9b2f3	302	/@} end of group CMSIS_NVIC /
Sergunb	0:9dcf85d9b2f3	303
Sergunb	0:9dcf85d9b2f3	304
Sergunb	0:9dcf85d9b2f3	305	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	306	\defgroup CMSIS_SCB System Control Block (SCB)
Sergunb	0:9dcf85d9b2f3	307	\brief Type definitions for the System Control Block Registers
Sergunb	0:9dcf85d9b2f3	308	@{
Sergunb	0:9dcf85d9b2f3	309	*/
Sergunb	0:9dcf85d9b2f3	310
Sergunb	0:9dcf85d9b2f3	311	/** \brief Structure type to access the System Control Block (SCB).
Sergunb	0:9dcf85d9b2f3	312	*/
Sergunb	0:9dcf85d9b2f3	313	typedef struct
Sergunb	0:9dcf85d9b2f3	314	{
Sergunb	0:9dcf85d9b2f3	315	__I uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
Sergunb	0:9dcf85d9b2f3	316	__IO uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
Sergunb	0:9dcf85d9b2f3	317	__IO uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
Sergunb	0:9dcf85d9b2f3	318	__IO uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
Sergunb	0:9dcf85d9b2f3	319	__IO uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
Sergunb	0:9dcf85d9b2f3	320	__IO uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
Sergunb	0:9dcf85d9b2f3	321	__IO uint8_t SHP[12]; /!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) /
Sergunb	0:9dcf85d9b2f3	322	__IO uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
Sergunb	0:9dcf85d9b2f3	323	__IO uint32_t CFSR; /!< Offset: 0x028 (R/W) Configurable Fault Status Register /
Sergunb	0:9dcf85d9b2f3	324	__IO uint32_t HFSR; /!< Offset: 0x02C (R/W) HardFault Status Register /
Sergunb	0:9dcf85d9b2f3	325	__IO uint32_t DFSR; /!< Offset: 0x030 (R/W) Debug Fault Status Register /
Sergunb	0:9dcf85d9b2f3	326	__IO uint32_t MMFAR; /!< Offset: 0x034 (R/W) MemManage Fault Address Register /
Sergunb	0:9dcf85d9b2f3	327	__IO uint32_t BFAR; /!< Offset: 0x038 (R/W) BusFault Address Register /
Sergunb	0:9dcf85d9b2f3	328	__IO uint32_t AFSR; /!< Offset: 0x03C (R/W) Auxiliary Fault Status Register /
Sergunb	0:9dcf85d9b2f3	329	__I uint32_t PFR[2]; /!< Offset: 0x040 (R/ ) Processor Feature Register /
Sergunb	0:9dcf85d9b2f3	330	__I uint32_t DFR; /!< Offset: 0x048 (R/ ) Debug Feature Register /
Sergunb	0:9dcf85d9b2f3	331	__I uint32_t ADR; /!< Offset: 0x04C (R/ ) Auxiliary Feature Register /
Sergunb	0:9dcf85d9b2f3	332	__I uint32_t MMFR[4]; /!< Offset: 0x050 (R/ ) Memory Model Feature Register /
Sergunb	0:9dcf85d9b2f3	333	__I uint32_t ISAR[5]; /!< Offset: 0x060 (R/ ) Instruction Set Attributes Register /
Sergunb	0:9dcf85d9b2f3	334	uint32_t RESERVED0[5];
Sergunb	0:9dcf85d9b2f3	335	__IO uint32_t CPACR; /!< Offset: 0x088 (R/W) Coprocessor Access Control Register /
Sergunb	0:9dcf85d9b2f3	336	} SCB_Type;
Sergunb	0:9dcf85d9b2f3	337
Sergunb	0:9dcf85d9b2f3	338	/* SCB CPUID Register Definitions */
Sergunb	0:9dcf85d9b2f3	339	#define SCB_CPUID_IMPLEMENTER_Pos 24 /!< SCB CPUID: IMPLEMENTER Position /
Sergunb	0:9dcf85d9b2f3	340	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
Sergunb	0:9dcf85d9b2f3	341
Sergunb	0:9dcf85d9b2f3	342	#define SCB_CPUID_VARIANT_Pos 20 /!< SCB CPUID: VARIANT Position /
Sergunb	0:9dcf85d9b2f3	343	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
Sergunb	0:9dcf85d9b2f3	344
Sergunb	0:9dcf85d9b2f3	345	#define SCB_CPUID_ARCHITECTURE_Pos 16 /!< SCB CPUID: ARCHITECTURE Position /
Sergunb	0:9dcf85d9b2f3	346	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
Sergunb	0:9dcf85d9b2f3	347
Sergunb	0:9dcf85d9b2f3	348	#define SCB_CPUID_PARTNO_Pos 4 /!< SCB CPUID: PARTNO Position /
Sergunb	0:9dcf85d9b2f3	349	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
Sergunb	0:9dcf85d9b2f3	350
Sergunb	0:9dcf85d9b2f3	351	#define SCB_CPUID_REVISION_Pos 0 /!< SCB CPUID: REVISION Position /
Sergunb	0:9dcf85d9b2f3	352	#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /!< SCB CPUID: REVISION Mask /
Sergunb	0:9dcf85d9b2f3	353
Sergunb	0:9dcf85d9b2f3	354	/* SCB Interrupt Control State Register Definitions */
Sergunb	0:9dcf85d9b2f3	355	#define SCB_ICSR_NMIPENDSET_Pos 31 /!< SCB ICSR: NMIPENDSET Position /
Sergunb	0:9dcf85d9b2f3	356	#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /!< SCB ICSR: NMIPENDSET Mask /
Sergunb	0:9dcf85d9b2f3	357
Sergunb	0:9dcf85d9b2f3	358	#define SCB_ICSR_PENDSVSET_Pos 28 /!< SCB ICSR: PENDSVSET Position /
Sergunb	0:9dcf85d9b2f3	359	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
Sergunb	0:9dcf85d9b2f3	360
Sergunb	0:9dcf85d9b2f3	361	#define SCB_ICSR_PENDSVCLR_Pos 27 /!< SCB ICSR: PENDSVCLR Position /
Sergunb	0:9dcf85d9b2f3	362	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
Sergunb	0:9dcf85d9b2f3	363
Sergunb	0:9dcf85d9b2f3	364	#define SCB_ICSR_PENDSTSET_Pos 26 /!< SCB ICSR: PENDSTSET Position /
Sergunb	0:9dcf85d9b2f3	365	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
Sergunb	0:9dcf85d9b2f3	366
Sergunb	0:9dcf85d9b2f3	367	#define SCB_ICSR_PENDSTCLR_Pos 25 /!< SCB ICSR: PENDSTCLR Position /
Sergunb	0:9dcf85d9b2f3	368	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
Sergunb	0:9dcf85d9b2f3	369
Sergunb	0:9dcf85d9b2f3	370	#define SCB_ICSR_ISRPREEMPT_Pos 23 /!< SCB ICSR: ISRPREEMPT Position /
Sergunb	0:9dcf85d9b2f3	371	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
Sergunb	0:9dcf85d9b2f3	372
Sergunb	0:9dcf85d9b2f3	373	#define SCB_ICSR_ISRPENDING_Pos 22 /!< SCB ICSR: ISRPENDING Position /
Sergunb	0:9dcf85d9b2f3	374	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
Sergunb	0:9dcf85d9b2f3	375
Sergunb	0:9dcf85d9b2f3	376	#define SCB_ICSR_VECTPENDING_Pos 12 /!< SCB ICSR: VECTPENDING Position /
Sergunb	0:9dcf85d9b2f3	377	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
Sergunb	0:9dcf85d9b2f3	378
Sergunb	0:9dcf85d9b2f3	379	#define SCB_ICSR_RETTOBASE_Pos 11 /!< SCB ICSR: RETTOBASE Position /
Sergunb	0:9dcf85d9b2f3	380	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
Sergunb	0:9dcf85d9b2f3	381
Sergunb	0:9dcf85d9b2f3	382	#define SCB_ICSR_VECTACTIVE_Pos 0 /!< SCB ICSR: VECTACTIVE Position /
Sergunb	0:9dcf85d9b2f3	383	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /!< SCB ICSR: VECTACTIVE Mask /
Sergunb	0:9dcf85d9b2f3	384
Sergunb	0:9dcf85d9b2f3	385	/* SCB Vector Table Offset Register Definitions */
Sergunb	0:9dcf85d9b2f3	386	#if (__CM3_REV < 0x0201) /* core r2p1 */
Sergunb	0:9dcf85d9b2f3	387	#define SCB_VTOR_TBLBASE_Pos 29 /!< SCB VTOR: TBLBASE Position /
Sergunb	0:9dcf85d9b2f3	388	#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /!< SCB VTOR: TBLBASE Mask /
Sergunb	0:9dcf85d9b2f3	389
Sergunb	0:9dcf85d9b2f3	390	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Sergunb	0:9dcf85d9b2f3	391	#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Sergunb	0:9dcf85d9b2f3	392	#else
Sergunb	0:9dcf85d9b2f3	393	#define SCB_VTOR_TBLOFF_Pos 7 /!< SCB VTOR: TBLOFF Position /
Sergunb	0:9dcf85d9b2f3	394	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
Sergunb	0:9dcf85d9b2f3	395	#endif
Sergunb	0:9dcf85d9b2f3	396
Sergunb	0:9dcf85d9b2f3	397	/* SCB Application Interrupt and Reset Control Register Definitions */
Sergunb	0:9dcf85d9b2f3	398	#define SCB_AIRCR_VECTKEY_Pos 16 /!< SCB AIRCR: VECTKEY Position /
Sergunb	0:9dcf85d9b2f3	399	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
Sergunb	0:9dcf85d9b2f3	400
Sergunb	0:9dcf85d9b2f3	401	#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /!< SCB AIRCR: VECTKEYSTAT Position /
Sergunb	0:9dcf85d9b2f3	402	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
Sergunb	0:9dcf85d9b2f3	403
Sergunb	0:9dcf85d9b2f3	404	#define SCB_AIRCR_ENDIANESS_Pos 15 /!< SCB AIRCR: ENDIANESS Position /
Sergunb	0:9dcf85d9b2f3	405	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
Sergunb	0:9dcf85d9b2f3	406
Sergunb	0:9dcf85d9b2f3	407	#define SCB_AIRCR_PRIGROUP_Pos 8 /!< SCB AIRCR: PRIGROUP Position /
Sergunb	0:9dcf85d9b2f3	408	#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /!< SCB AIRCR: PRIGROUP Mask /
Sergunb	0:9dcf85d9b2f3	409
Sergunb	0:9dcf85d9b2f3	410	#define SCB_AIRCR_SYSRESETREQ_Pos 2 /!< SCB AIRCR: SYSRESETREQ Position /
Sergunb	0:9dcf85d9b2f3	411	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
Sergunb	0:9dcf85d9b2f3	412
Sergunb	0:9dcf85d9b2f3	413	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /!< SCB AIRCR: VECTCLRACTIVE Position /
Sergunb	0:9dcf85d9b2f3	414	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
Sergunb	0:9dcf85d9b2f3	415
Sergunb	0:9dcf85d9b2f3	416	#define SCB_AIRCR_VECTRESET_Pos 0 /!< SCB AIRCR: VECTRESET Position /
Sergunb	0:9dcf85d9b2f3	417	#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /!< SCB AIRCR: VECTRESET Mask /
Sergunb	0:9dcf85d9b2f3	418
Sergunb	0:9dcf85d9b2f3	419	/* SCB System Control Register Definitions */
Sergunb	0:9dcf85d9b2f3	420	#define SCB_SCR_SEVONPEND_Pos 4 /!< SCB SCR: SEVONPEND Position /
Sergunb	0:9dcf85d9b2f3	421	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
Sergunb	0:9dcf85d9b2f3	422
Sergunb	0:9dcf85d9b2f3	423	#define SCB_SCR_SLEEPDEEP_Pos 2 /!< SCB SCR: SLEEPDEEP Position /
Sergunb	0:9dcf85d9b2f3	424	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
Sergunb	0:9dcf85d9b2f3	425
Sergunb	0:9dcf85d9b2f3	426	#define SCB_SCR_SLEEPONEXIT_Pos 1 /!< SCB SCR: SLEEPONEXIT Position /
Sergunb	0:9dcf85d9b2f3	427	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
Sergunb	0:9dcf85d9b2f3	428
Sergunb	0:9dcf85d9b2f3	429	/* SCB Configuration Control Register Definitions */
Sergunb	0:9dcf85d9b2f3	430	#define SCB_CCR_STKALIGN_Pos 9 /!< SCB CCR: STKALIGN Position /
Sergunb	0:9dcf85d9b2f3	431	#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /!< SCB CCR: STKALIGN Mask /
Sergunb	0:9dcf85d9b2f3	432
Sergunb	0:9dcf85d9b2f3	433	#define SCB_CCR_BFHFNMIGN_Pos 8 /!< SCB CCR: BFHFNMIGN Position /
Sergunb	0:9dcf85d9b2f3	434	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
Sergunb	0:9dcf85d9b2f3	435
Sergunb	0:9dcf85d9b2f3	436	#define SCB_CCR_DIV_0_TRP_Pos 4 /!< SCB CCR: DIV_0_TRP Position /
Sergunb	0:9dcf85d9b2f3	437	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
Sergunb	0:9dcf85d9b2f3	438
Sergunb	0:9dcf85d9b2f3	439	#define SCB_CCR_UNALIGN_TRP_Pos 3 /!< SCB CCR: UNALIGN_TRP Position /
Sergunb	0:9dcf85d9b2f3	440	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
Sergunb	0:9dcf85d9b2f3	441
Sergunb	0:9dcf85d9b2f3	442	#define SCB_CCR_USERSETMPEND_Pos 1 /!< SCB CCR: USERSETMPEND Position /
Sergunb	0:9dcf85d9b2f3	443	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
Sergunb	0:9dcf85d9b2f3	444
Sergunb	0:9dcf85d9b2f3	445	#define SCB_CCR_NONBASETHRDENA_Pos 0 /!< SCB CCR: NONBASETHRDENA Position /
Sergunb	0:9dcf85d9b2f3	446	#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /!< SCB CCR: NONBASETHRDENA Mask /
Sergunb	0:9dcf85d9b2f3	447
Sergunb	0:9dcf85d9b2f3	448	/* SCB System Handler Control and State Register Definitions */
Sergunb	0:9dcf85d9b2f3	449	#define SCB_SHCSR_USGFAULTENA_Pos 18 /!< SCB SHCSR: USGFAULTENA Position /
Sergunb	0:9dcf85d9b2f3	450	#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /!< SCB SHCSR: USGFAULTENA Mask /
Sergunb	0:9dcf85d9b2f3	451
Sergunb	0:9dcf85d9b2f3	452	#define SCB_SHCSR_BUSFAULTENA_Pos 17 /!< SCB SHCSR: BUSFAULTENA Position /
Sergunb	0:9dcf85d9b2f3	453	#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /!< SCB SHCSR: BUSFAULTENA Mask /
Sergunb	0:9dcf85d9b2f3	454
Sergunb	0:9dcf85d9b2f3	455	#define SCB_SHCSR_MEMFAULTENA_Pos 16 /!< SCB SHCSR: MEMFAULTENA Position /
Sergunb	0:9dcf85d9b2f3	456	#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /!< SCB SHCSR: MEMFAULTENA Mask /
Sergunb	0:9dcf85d9b2f3	457
Sergunb	0:9dcf85d9b2f3	458	#define SCB_SHCSR_SVCALLPENDED_Pos 15 /!< SCB SHCSR: SVCALLPENDED Position /
Sergunb	0:9dcf85d9b2f3	459	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
Sergunb	0:9dcf85d9b2f3	460
Sergunb	0:9dcf85d9b2f3	461	#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /!< SCB SHCSR: BUSFAULTPENDED Position /
Sergunb	0:9dcf85d9b2f3	462	#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /!< SCB SHCSR: BUSFAULTPENDED Mask /
Sergunb	0:9dcf85d9b2f3	463
Sergunb	0:9dcf85d9b2f3	464	#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /!< SCB SHCSR: MEMFAULTPENDED Position /
Sergunb	0:9dcf85d9b2f3	465	#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /!< SCB SHCSR: MEMFAULTPENDED Mask /
Sergunb	0:9dcf85d9b2f3	466
Sergunb	0:9dcf85d9b2f3	467	#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /!< SCB SHCSR: USGFAULTPENDED Position /
Sergunb	0:9dcf85d9b2f3	468	#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /!< SCB SHCSR: USGFAULTPENDED Mask /
Sergunb	0:9dcf85d9b2f3	469
Sergunb	0:9dcf85d9b2f3	470	#define SCB_SHCSR_SYSTICKACT_Pos 11 /!< SCB SHCSR: SYSTICKACT Position /
Sergunb	0:9dcf85d9b2f3	471	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
Sergunb	0:9dcf85d9b2f3	472
Sergunb	0:9dcf85d9b2f3	473	#define SCB_SHCSR_PENDSVACT_Pos 10 /!< SCB SHCSR: PENDSVACT Position /
Sergunb	0:9dcf85d9b2f3	474	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
Sergunb	0:9dcf85d9b2f3	475
Sergunb	0:9dcf85d9b2f3	476	#define SCB_SHCSR_MONITORACT_Pos 8 /!< SCB SHCSR: MONITORACT Position /
Sergunb	0:9dcf85d9b2f3	477	#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /!< SCB SHCSR: MONITORACT Mask /
Sergunb	0:9dcf85d9b2f3	478
Sergunb	0:9dcf85d9b2f3	479	#define SCB_SHCSR_SVCALLACT_Pos 7 /!< SCB SHCSR: SVCALLACT Position /
Sergunb	0:9dcf85d9b2f3	480	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
Sergunb	0:9dcf85d9b2f3	481
Sergunb	0:9dcf85d9b2f3	482	#define SCB_SHCSR_USGFAULTACT_Pos 3 /!< SCB SHCSR: USGFAULTACT Position /
Sergunb	0:9dcf85d9b2f3	483	#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /!< SCB SHCSR: USGFAULTACT Mask /
Sergunb	0:9dcf85d9b2f3	484
Sergunb	0:9dcf85d9b2f3	485	#define SCB_SHCSR_BUSFAULTACT_Pos 1 /!< SCB SHCSR: BUSFAULTACT Position /
Sergunb	0:9dcf85d9b2f3	486	#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /!< SCB SHCSR: BUSFAULTACT Mask /
Sergunb	0:9dcf85d9b2f3	487
Sergunb	0:9dcf85d9b2f3	488	#define SCB_SHCSR_MEMFAULTACT_Pos 0 /!< SCB SHCSR: MEMFAULTACT Position /
Sergunb	0:9dcf85d9b2f3	489	#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /!< SCB SHCSR: MEMFAULTACT Mask /
Sergunb	0:9dcf85d9b2f3	490
Sergunb	0:9dcf85d9b2f3	491	/* SCB Configurable Fault Status Registers Definitions */
Sergunb	0:9dcf85d9b2f3	492	#define SCB_CFSR_USGFAULTSR_Pos 16 /!< SCB CFSR: Usage Fault Status Register Position /
Sergunb	0:9dcf85d9b2f3	493	#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /!< SCB CFSR: Usage Fault Status Register Mask /
Sergunb	0:9dcf85d9b2f3	494
Sergunb	0:9dcf85d9b2f3	495	#define SCB_CFSR_BUSFAULTSR_Pos 8 /!< SCB CFSR: Bus Fault Status Register Position /
Sergunb	0:9dcf85d9b2f3	496	#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /!< SCB CFSR: Bus Fault Status Register Mask /
Sergunb	0:9dcf85d9b2f3	497
Sergunb	0:9dcf85d9b2f3	498	#define SCB_CFSR_MEMFAULTSR_Pos 0 /!< SCB CFSR: Memory Manage Fault Status Register Position /
Sergunb	0:9dcf85d9b2f3	499	#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /!< SCB CFSR: Memory Manage Fault Status Register Mask /
Sergunb	0:9dcf85d9b2f3	500
Sergunb	0:9dcf85d9b2f3	501	/* SCB Hard Fault Status Registers Definitions */
Sergunb	0:9dcf85d9b2f3	502	#define SCB_HFSR_DEBUGEVT_Pos 31 /!< SCB HFSR: DEBUGEVT Position /
Sergunb	0:9dcf85d9b2f3	503	#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /!< SCB HFSR: DEBUGEVT Mask /
Sergunb	0:9dcf85d9b2f3	504
Sergunb	0:9dcf85d9b2f3	505	#define SCB_HFSR_FORCED_Pos 30 /!< SCB HFSR: FORCED Position /
Sergunb	0:9dcf85d9b2f3	506	#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /!< SCB HFSR: FORCED Mask /
Sergunb	0:9dcf85d9b2f3	507
Sergunb	0:9dcf85d9b2f3	508	#define SCB_HFSR_VECTTBL_Pos 1 /!< SCB HFSR: VECTTBL Position /
Sergunb	0:9dcf85d9b2f3	509	#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /!< SCB HFSR: VECTTBL Mask /
Sergunb	0:9dcf85d9b2f3	510
Sergunb	0:9dcf85d9b2f3	511	/* SCB Debug Fault Status Register Definitions */
Sergunb	0:9dcf85d9b2f3	512	#define SCB_DFSR_EXTERNAL_Pos 4 /!< SCB DFSR: EXTERNAL Position /
Sergunb	0:9dcf85d9b2f3	513	#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /!< SCB DFSR: EXTERNAL Mask /
Sergunb	0:9dcf85d9b2f3	514
Sergunb	0:9dcf85d9b2f3	515	#define SCB_DFSR_VCATCH_Pos 3 /!< SCB DFSR: VCATCH Position /
Sergunb	0:9dcf85d9b2f3	516	#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /!< SCB DFSR: VCATCH Mask /
Sergunb	0:9dcf85d9b2f3	517
Sergunb	0:9dcf85d9b2f3	518	#define SCB_DFSR_DWTTRAP_Pos 2 /!< SCB DFSR: DWTTRAP Position /
Sergunb	0:9dcf85d9b2f3	519	#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /!< SCB DFSR: DWTTRAP Mask /
Sergunb	0:9dcf85d9b2f3	520
Sergunb	0:9dcf85d9b2f3	521	#define SCB_DFSR_BKPT_Pos 1 /!< SCB DFSR: BKPT Position /
Sergunb	0:9dcf85d9b2f3	522	#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /!< SCB DFSR: BKPT Mask /
Sergunb	0:9dcf85d9b2f3	523
Sergunb	0:9dcf85d9b2f3	524	#define SCB_DFSR_HALTED_Pos 0 /!< SCB DFSR: HALTED Position /
Sergunb	0:9dcf85d9b2f3	525	#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /!< SCB DFSR: HALTED Mask /
Sergunb	0:9dcf85d9b2f3	526
Sergunb	0:9dcf85d9b2f3	527	/@} end of group CMSIS_SCB /
Sergunb	0:9dcf85d9b2f3	528
Sergunb	0:9dcf85d9b2f3	529
Sergunb	0:9dcf85d9b2f3	530	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	531	\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
Sergunb	0:9dcf85d9b2f3	532	\brief Type definitions for the System Control and ID Register not in the SCB
Sergunb	0:9dcf85d9b2f3	533	@{
Sergunb	0:9dcf85d9b2f3	534	*/
Sergunb	0:9dcf85d9b2f3	535
Sergunb	0:9dcf85d9b2f3	536	/** \brief Structure type to access the System Control and ID Register not in the SCB.
Sergunb	0:9dcf85d9b2f3	537	*/
Sergunb	0:9dcf85d9b2f3	538	typedef struct
Sergunb	0:9dcf85d9b2f3	539	{
Sergunb	0:9dcf85d9b2f3	540	uint32_t RESERVED0[1];
Sergunb	0:9dcf85d9b2f3	541	__I uint32_t ICTR; /!< Offset: 0x004 (R/ ) Interrupt Controller Type Register /
Sergunb	0:9dcf85d9b2f3	542	#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
Sergunb	0:9dcf85d9b2f3	543	__IO uint32_t ACTLR; /!< Offset: 0x008 (R/W) Auxiliary Control Register /
Sergunb	0:9dcf85d9b2f3	544	#else
Sergunb	0:9dcf85d9b2f3	545	uint32_t RESERVED1[1];
Sergunb	0:9dcf85d9b2f3	546	#endif
Sergunb	0:9dcf85d9b2f3	547	} SCnSCB_Type;
Sergunb	0:9dcf85d9b2f3	548
Sergunb	0:9dcf85d9b2f3	549	/* Interrupt Controller Type Register Definitions */
Sergunb	0:9dcf85d9b2f3	550	#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /!< ICTR: INTLINESNUM Position /
Sergunb	0:9dcf85d9b2f3	551	#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /!< ICTR: INTLINESNUM Mask /
Sergunb	0:9dcf85d9b2f3	552
Sergunb	0:9dcf85d9b2f3	553	/* Auxiliary Control Register Definitions */
Sergunb	0:9dcf85d9b2f3	554
Sergunb	0:9dcf85d9b2f3	555	#define SCnSCB_ACTLR_DISFOLD_Pos 2 /!< ACTLR: DISFOLD Position /
Sergunb	0:9dcf85d9b2f3	556	#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /!< ACTLR: DISFOLD Mask /
Sergunb	0:9dcf85d9b2f3	557
Sergunb	0:9dcf85d9b2f3	558	#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /!< ACTLR: DISDEFWBUF Position /
Sergunb	0:9dcf85d9b2f3	559	#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /!< ACTLR: DISDEFWBUF Mask /
Sergunb	0:9dcf85d9b2f3	560
Sergunb	0:9dcf85d9b2f3	561	#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /!< ACTLR: DISMCYCINT Position /
Sergunb	0:9dcf85d9b2f3	562	#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /!< ACTLR: DISMCYCINT Mask /
Sergunb	0:9dcf85d9b2f3	563
Sergunb	0:9dcf85d9b2f3	564	/@} end of group CMSIS_SCnotSCB /
Sergunb	0:9dcf85d9b2f3	565
Sergunb	0:9dcf85d9b2f3	566
Sergunb	0:9dcf85d9b2f3	567	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	568	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
Sergunb	0:9dcf85d9b2f3	569	\brief Type definitions for the System Timer Registers.
Sergunb	0:9dcf85d9b2f3	570	@{
Sergunb	0:9dcf85d9b2f3	571	*/
Sergunb	0:9dcf85d9b2f3	572
Sergunb	0:9dcf85d9b2f3	573	/** \brief Structure type to access the System Timer (SysTick).
Sergunb	0:9dcf85d9b2f3	574	*/
Sergunb	0:9dcf85d9b2f3	575	typedef struct
Sergunb	0:9dcf85d9b2f3	576	{
Sergunb	0:9dcf85d9b2f3	577	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
Sergunb	0:9dcf85d9b2f3	578	__IO uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
Sergunb	0:9dcf85d9b2f3	579	__IO uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
Sergunb	0:9dcf85d9b2f3	580	__I uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
Sergunb	0:9dcf85d9b2f3	581	} SysTick_Type;
Sergunb	0:9dcf85d9b2f3	582
Sergunb	0:9dcf85d9b2f3	583	/* SysTick Control / Status Register Definitions */
Sergunb	0:9dcf85d9b2f3	584	#define SysTick_CTRL_COUNTFLAG_Pos 16 /!< SysTick CTRL: COUNTFLAG Position /
Sergunb	0:9dcf85d9b2f3	585	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
Sergunb	0:9dcf85d9b2f3	586
Sergunb	0:9dcf85d9b2f3	587	#define SysTick_CTRL_CLKSOURCE_Pos 2 /!< SysTick CTRL: CLKSOURCE Position /
Sergunb	0:9dcf85d9b2f3	588	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
Sergunb	0:9dcf85d9b2f3	589
Sergunb	0:9dcf85d9b2f3	590	#define SysTick_CTRL_TICKINT_Pos 1 /!< SysTick CTRL: TICKINT Position /
Sergunb	0:9dcf85d9b2f3	591	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
Sergunb	0:9dcf85d9b2f3	592
Sergunb	0:9dcf85d9b2f3	593	#define SysTick_CTRL_ENABLE_Pos 0 /!< SysTick CTRL: ENABLE Position /
Sergunb	0:9dcf85d9b2f3	594	#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /!< SysTick CTRL: ENABLE Mask /
Sergunb	0:9dcf85d9b2f3	595
Sergunb	0:9dcf85d9b2f3	596	/* SysTick Reload Register Definitions */
Sergunb	0:9dcf85d9b2f3	597	#define SysTick_LOAD_RELOAD_Pos 0 /!< SysTick LOAD: RELOAD Position /
Sergunb	0:9dcf85d9b2f3	598	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /!< SysTick LOAD: RELOAD Mask /
Sergunb	0:9dcf85d9b2f3	599
Sergunb	0:9dcf85d9b2f3	600	/* SysTick Current Register Definitions */
Sergunb	0:9dcf85d9b2f3	601	#define SysTick_VAL_CURRENT_Pos 0 /!< SysTick VAL: CURRENT Position /
Sergunb	0:9dcf85d9b2f3	602	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick VAL: CURRENT Mask /
Sergunb	0:9dcf85d9b2f3	603
Sergunb	0:9dcf85d9b2f3	604	/* SysTick Calibration Register Definitions */
Sergunb	0:9dcf85d9b2f3	605	#define SysTick_CALIB_NOREF_Pos 31 /!< SysTick CALIB: NOREF Position /
Sergunb	0:9dcf85d9b2f3	606	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
Sergunb	0:9dcf85d9b2f3	607
Sergunb	0:9dcf85d9b2f3	608	#define SysTick_CALIB_SKEW_Pos 30 /!< SysTick CALIB: SKEW Position /
Sergunb	0:9dcf85d9b2f3	609	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
Sergunb	0:9dcf85d9b2f3	610
Sergunb	0:9dcf85d9b2f3	611	#define SysTick_CALIB_TENMS_Pos 0 /!< SysTick CALIB: TENMS Position /
Sergunb	0:9dcf85d9b2f3	612	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /!< SysTick CALIB: TENMS Mask /
Sergunb	0:9dcf85d9b2f3	613
Sergunb	0:9dcf85d9b2f3	614	/@} end of group CMSIS_SysTick /
Sergunb	0:9dcf85d9b2f3	615
Sergunb	0:9dcf85d9b2f3	616
Sergunb	0:9dcf85d9b2f3	617	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	618	\defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
Sergunb	0:9dcf85d9b2f3	619	\brief Type definitions for the Instrumentation Trace Macrocell (ITM)
Sergunb	0:9dcf85d9b2f3	620	@{
Sergunb	0:9dcf85d9b2f3	621	*/
Sergunb	0:9dcf85d9b2f3	622
Sergunb	0:9dcf85d9b2f3	623	/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Sergunb	0:9dcf85d9b2f3	624	*/
Sergunb	0:9dcf85d9b2f3	625	typedef struct
Sergunb	0:9dcf85d9b2f3	626	{
Sergunb	0:9dcf85d9b2f3	627	__O union
Sergunb	0:9dcf85d9b2f3	628	{
Sergunb	0:9dcf85d9b2f3	629	__O uint8_t u8; /!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit /
Sergunb	0:9dcf85d9b2f3	630	__O uint16_t u16; /!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit /
Sergunb	0:9dcf85d9b2f3	631	__O uint32_t u32; /!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit /
Sergunb	0:9dcf85d9b2f3	632	} PORT [32]; /!< Offset: 0x000 ( /W) ITM Stimulus Port Registers /
Sergunb	0:9dcf85d9b2f3	633	uint32_t RESERVED0[864];
Sergunb	0:9dcf85d9b2f3	634	__IO uint32_t TER; /!< Offset: 0xE00 (R/W) ITM Trace Enable Register /
Sergunb	0:9dcf85d9b2f3	635	uint32_t RESERVED1[15];
Sergunb	0:9dcf85d9b2f3	636	__IO uint32_t TPR; /!< Offset: 0xE40 (R/W) ITM Trace Privilege Register /
Sergunb	0:9dcf85d9b2f3	637	uint32_t RESERVED2[15];
Sergunb	0:9dcf85d9b2f3	638	__IO uint32_t TCR; /!< Offset: 0xE80 (R/W) ITM Trace Control Register /
Sergunb	0:9dcf85d9b2f3	639	uint32_t RESERVED3[29];
Sergunb	0:9dcf85d9b2f3	640	__O uint32_t IWR; /!< Offset: 0xEF8 ( /W) ITM Integration Write Register /
Sergunb	0:9dcf85d9b2f3	641	__I uint32_t IRR; /!< Offset: 0xEFC (R/ ) ITM Integration Read Register /
Sergunb	0:9dcf85d9b2f3	642	__IO uint32_t IMCR; /!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register /
Sergunb	0:9dcf85d9b2f3	643	uint32_t RESERVED4[43];
Sergunb	0:9dcf85d9b2f3	644	__O uint32_t LAR; /!< Offset: 0xFB0 ( /W) ITM Lock Access Register /
Sergunb	0:9dcf85d9b2f3	645	__I uint32_t LSR; /!< Offset: 0xFB4 (R/ ) ITM Lock Status Register /
Sergunb	0:9dcf85d9b2f3	646	uint32_t RESERVED5[6];
Sergunb	0:9dcf85d9b2f3	647	__I uint32_t PID4; /!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 /
Sergunb	0:9dcf85d9b2f3	648	__I uint32_t PID5; /!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 /
Sergunb	0:9dcf85d9b2f3	649	__I uint32_t PID6; /!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 /
Sergunb	0:9dcf85d9b2f3	650	__I uint32_t PID7; /!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 /
Sergunb	0:9dcf85d9b2f3	651	__I uint32_t PID0; /!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 /
Sergunb	0:9dcf85d9b2f3	652	__I uint32_t PID1; /!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 /
Sergunb	0:9dcf85d9b2f3	653	__I uint32_t PID2; /!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 /
Sergunb	0:9dcf85d9b2f3	654	__I uint32_t PID3; /!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 /
Sergunb	0:9dcf85d9b2f3	655	__I uint32_t CID0; /!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 /
Sergunb	0:9dcf85d9b2f3	656	__I uint32_t CID1; /!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 /
Sergunb	0:9dcf85d9b2f3	657	__I uint32_t CID2; /!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 /
Sergunb	0:9dcf85d9b2f3	658	__I uint32_t CID3; /!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 /
Sergunb	0:9dcf85d9b2f3	659	} ITM_Type;
Sergunb	0:9dcf85d9b2f3	660
Sergunb	0:9dcf85d9b2f3	661	/* ITM Trace Privilege Register Definitions */
Sergunb	0:9dcf85d9b2f3	662	#define ITM_TPR_PRIVMASK_Pos 0 /!< ITM TPR: PRIVMASK Position /
Sergunb	0:9dcf85d9b2f3	663	#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /!< ITM TPR: PRIVMASK Mask /
Sergunb	0:9dcf85d9b2f3	664
Sergunb	0:9dcf85d9b2f3	665	/* ITM Trace Control Register Definitions */
Sergunb	0:9dcf85d9b2f3	666	#define ITM_TCR_BUSY_Pos 23 /!< ITM TCR: BUSY Position /
Sergunb	0:9dcf85d9b2f3	667	#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /!< ITM TCR: BUSY Mask /
Sergunb	0:9dcf85d9b2f3	668
Sergunb	0:9dcf85d9b2f3	669	#define ITM_TCR_TraceBusID_Pos 16 /!< ITM TCR: ATBID Position /
Sergunb	0:9dcf85d9b2f3	670	#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /!< ITM TCR: ATBID Mask /
Sergunb	0:9dcf85d9b2f3	671
Sergunb	0:9dcf85d9b2f3	672	#define ITM_TCR_GTSFREQ_Pos 10 /!< ITM TCR: Global timestamp frequency Position /
Sergunb	0:9dcf85d9b2f3	673	#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /!< ITM TCR: Global timestamp frequency Mask /
Sergunb	0:9dcf85d9b2f3	674
Sergunb	0:9dcf85d9b2f3	675	#define ITM_TCR_TSPrescale_Pos 8 /!< ITM TCR: TSPrescale Position /
Sergunb	0:9dcf85d9b2f3	676	#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /!< ITM TCR: TSPrescale Mask /
Sergunb	0:9dcf85d9b2f3	677
Sergunb	0:9dcf85d9b2f3	678	#define ITM_TCR_SWOENA_Pos 4 /!< ITM TCR: SWOENA Position /
Sergunb	0:9dcf85d9b2f3	679	#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /!< ITM TCR: SWOENA Mask /
Sergunb	0:9dcf85d9b2f3	680
Sergunb	0:9dcf85d9b2f3	681	#define ITM_TCR_DWTENA_Pos 3 /!< ITM TCR: DWTENA Position /
Sergunb	0:9dcf85d9b2f3	682	#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /!< ITM TCR: DWTENA Mask /
Sergunb	0:9dcf85d9b2f3	683
Sergunb	0:9dcf85d9b2f3	684	#define ITM_TCR_SYNCENA_Pos 2 /!< ITM TCR: SYNCENA Position /
Sergunb	0:9dcf85d9b2f3	685	#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /!< ITM TCR: SYNCENA Mask /
Sergunb	0:9dcf85d9b2f3	686
Sergunb	0:9dcf85d9b2f3	687	#define ITM_TCR_TSENA_Pos 1 /!< ITM TCR: TSENA Position /
Sergunb	0:9dcf85d9b2f3	688	#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /!< ITM TCR: TSENA Mask /
Sergunb	0:9dcf85d9b2f3	689
Sergunb	0:9dcf85d9b2f3	690	#define ITM_TCR_ITMENA_Pos 0 /!< ITM TCR: ITM Enable bit Position /
Sergunb	0:9dcf85d9b2f3	691	#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /!< ITM TCR: ITM Enable bit Mask /
Sergunb	0:9dcf85d9b2f3	692
Sergunb	0:9dcf85d9b2f3	693	/* ITM Integration Write Register Definitions */
Sergunb	0:9dcf85d9b2f3	694	#define ITM_IWR_ATVALIDM_Pos 0 /!< ITM IWR: ATVALIDM Position /
Sergunb	0:9dcf85d9b2f3	695	#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /!< ITM IWR: ATVALIDM Mask /
Sergunb	0:9dcf85d9b2f3	696
Sergunb	0:9dcf85d9b2f3	697	/* ITM Integration Read Register Definitions */
Sergunb	0:9dcf85d9b2f3	698	#define ITM_IRR_ATREADYM_Pos 0 /!< ITM IRR: ATREADYM Position /
Sergunb	0:9dcf85d9b2f3	699	#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /!< ITM IRR: ATREADYM Mask /
Sergunb	0:9dcf85d9b2f3	700
Sergunb	0:9dcf85d9b2f3	701	/* ITM Integration Mode Control Register Definitions */
Sergunb	0:9dcf85d9b2f3	702	#define ITM_IMCR_INTEGRATION_Pos 0 /!< ITM IMCR: INTEGRATION Position /
Sergunb	0:9dcf85d9b2f3	703	#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /!< ITM IMCR: INTEGRATION Mask /
Sergunb	0:9dcf85d9b2f3	704
Sergunb	0:9dcf85d9b2f3	705	/* ITM Lock Status Register Definitions */
Sergunb	0:9dcf85d9b2f3	706	#define ITM_LSR_ByteAcc_Pos 2 /!< ITM LSR: ByteAcc Position /
Sergunb	0:9dcf85d9b2f3	707	#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /!< ITM LSR: ByteAcc Mask /
Sergunb	0:9dcf85d9b2f3	708
Sergunb	0:9dcf85d9b2f3	709	#define ITM_LSR_Access_Pos 1 /!< ITM LSR: Access Position /
Sergunb	0:9dcf85d9b2f3	710	#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /!< ITM LSR: Access Mask /
Sergunb	0:9dcf85d9b2f3	711
Sergunb	0:9dcf85d9b2f3	712	#define ITM_LSR_Present_Pos 0 /!< ITM LSR: Present Position /
Sergunb	0:9dcf85d9b2f3	713	#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /!< ITM LSR: Present Mask /
Sergunb	0:9dcf85d9b2f3	714
Sergunb	0:9dcf85d9b2f3	715	/@}/ /* end of group CMSIS_ITM */
Sergunb	0:9dcf85d9b2f3	716
Sergunb	0:9dcf85d9b2f3	717
Sergunb	0:9dcf85d9b2f3	718	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	719	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
Sergunb	0:9dcf85d9b2f3	720	\brief Type definitions for the Data Watchpoint and Trace (DWT)
Sergunb	0:9dcf85d9b2f3	721	@{
Sergunb	0:9dcf85d9b2f3	722	*/
Sergunb	0:9dcf85d9b2f3	723
Sergunb	0:9dcf85d9b2f3	724	/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
Sergunb	0:9dcf85d9b2f3	725	*/
Sergunb	0:9dcf85d9b2f3	726	typedef struct
Sergunb	0:9dcf85d9b2f3	727	{
Sergunb	0:9dcf85d9b2f3	728	__IO uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
Sergunb	0:9dcf85d9b2f3	729	__IO uint32_t CYCCNT; /!< Offset: 0x004 (R/W) Cycle Count Register /
Sergunb	0:9dcf85d9b2f3	730	__IO uint32_t CPICNT; /!< Offset: 0x008 (R/W) CPI Count Register /
Sergunb	0:9dcf85d9b2f3	731	__IO uint32_t EXCCNT; /!< Offset: 0x00C (R/W) Exception Overhead Count Register /
Sergunb	0:9dcf85d9b2f3	732	__IO uint32_t SLEEPCNT; /!< Offset: 0x010 (R/W) Sleep Count Register /
Sergunb	0:9dcf85d9b2f3	733	__IO uint32_t LSUCNT; /!< Offset: 0x014 (R/W) LSU Count Register /
Sergunb	0:9dcf85d9b2f3	734	__IO uint32_t FOLDCNT; /!< Offset: 0x018 (R/W) Folded-instruction Count Register /
Sergunb	0:9dcf85d9b2f3	735	__I uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
Sergunb	0:9dcf85d9b2f3	736	__IO uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
Sergunb	0:9dcf85d9b2f3	737	__IO uint32_t MASK0; /!< Offset: 0x024 (R/W) Mask Register 0 /
Sergunb	0:9dcf85d9b2f3	738	__IO uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
Sergunb	0:9dcf85d9b2f3	739	uint32_t RESERVED0[1];
Sergunb	0:9dcf85d9b2f3	740	__IO uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
Sergunb	0:9dcf85d9b2f3	741	__IO uint32_t MASK1; /!< Offset: 0x034 (R/W) Mask Register 1 /
Sergunb	0:9dcf85d9b2f3	742	__IO uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
Sergunb	0:9dcf85d9b2f3	743	uint32_t RESERVED1[1];
Sergunb	0:9dcf85d9b2f3	744	__IO uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
Sergunb	0:9dcf85d9b2f3	745	__IO uint32_t MASK2; /!< Offset: 0x044 (R/W) Mask Register 2 /
Sergunb	0:9dcf85d9b2f3	746	__IO uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
Sergunb	0:9dcf85d9b2f3	747	uint32_t RESERVED2[1];
Sergunb	0:9dcf85d9b2f3	748	__IO uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
Sergunb	0:9dcf85d9b2f3	749	__IO uint32_t MASK3; /!< Offset: 0x054 (R/W) Mask Register 3 /
Sergunb	0:9dcf85d9b2f3	750	__IO uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
Sergunb	0:9dcf85d9b2f3	751	} DWT_Type;
Sergunb	0:9dcf85d9b2f3	752
Sergunb	0:9dcf85d9b2f3	753	/* DWT Control Register Definitions */
Sergunb	0:9dcf85d9b2f3	754	#define DWT_CTRL_NUMCOMP_Pos 28 /!< DWT CTRL: NUMCOMP Position /
Sergunb	0:9dcf85d9b2f3	755	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
Sergunb	0:9dcf85d9b2f3	756
Sergunb	0:9dcf85d9b2f3	757	#define DWT_CTRL_NOTRCPKT_Pos 27 /!< DWT CTRL: NOTRCPKT Position /
Sergunb	0:9dcf85d9b2f3	758	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
Sergunb	0:9dcf85d9b2f3	759
Sergunb	0:9dcf85d9b2f3	760	#define DWT_CTRL_NOEXTTRIG_Pos 26 /!< DWT CTRL: NOEXTTRIG Position /
Sergunb	0:9dcf85d9b2f3	761	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
Sergunb	0:9dcf85d9b2f3	762
Sergunb	0:9dcf85d9b2f3	763	#define DWT_CTRL_NOCYCCNT_Pos 25 /!< DWT CTRL: NOCYCCNT Position /
Sergunb	0:9dcf85d9b2f3	764	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
Sergunb	0:9dcf85d9b2f3	765
Sergunb	0:9dcf85d9b2f3	766	#define DWT_CTRL_NOPRFCNT_Pos 24 /!< DWT CTRL: NOPRFCNT Position /
Sergunb	0:9dcf85d9b2f3	767	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
Sergunb	0:9dcf85d9b2f3	768
Sergunb	0:9dcf85d9b2f3	769	#define DWT_CTRL_CYCEVTENA_Pos 22 /!< DWT CTRL: CYCEVTENA Position /
Sergunb	0:9dcf85d9b2f3	770	#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /!< DWT CTRL: CYCEVTENA Mask /
Sergunb	0:9dcf85d9b2f3	771
Sergunb	0:9dcf85d9b2f3	772	#define DWT_CTRL_FOLDEVTENA_Pos 21 /!< DWT CTRL: FOLDEVTENA Position /
Sergunb	0:9dcf85d9b2f3	773	#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /!< DWT CTRL: FOLDEVTENA Mask /
Sergunb	0:9dcf85d9b2f3	774
Sergunb	0:9dcf85d9b2f3	775	#define DWT_CTRL_LSUEVTENA_Pos 20 /!< DWT CTRL: LSUEVTENA Position /
Sergunb	0:9dcf85d9b2f3	776	#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /!< DWT CTRL: LSUEVTENA Mask /
Sergunb	0:9dcf85d9b2f3	777
Sergunb	0:9dcf85d9b2f3	778	#define DWT_CTRL_SLEEPEVTENA_Pos 19 /!< DWT CTRL: SLEEPEVTENA Position /
Sergunb	0:9dcf85d9b2f3	779	#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /!< DWT CTRL: SLEEPEVTENA Mask /
Sergunb	0:9dcf85d9b2f3	780
Sergunb	0:9dcf85d9b2f3	781	#define DWT_CTRL_EXCEVTENA_Pos 18 /!< DWT CTRL: EXCEVTENA Position /
Sergunb	0:9dcf85d9b2f3	782	#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /!< DWT CTRL: EXCEVTENA Mask /
Sergunb	0:9dcf85d9b2f3	783
Sergunb	0:9dcf85d9b2f3	784	#define DWT_CTRL_CPIEVTENA_Pos 17 /!< DWT CTRL: CPIEVTENA Position /
Sergunb	0:9dcf85d9b2f3	785	#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /!< DWT CTRL: CPIEVTENA Mask /
Sergunb	0:9dcf85d9b2f3	786
Sergunb	0:9dcf85d9b2f3	787	#define DWT_CTRL_EXCTRCENA_Pos 16 /!< DWT CTRL: EXCTRCENA Position /
Sergunb	0:9dcf85d9b2f3	788	#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /!< DWT CTRL: EXCTRCENA Mask /
Sergunb	0:9dcf85d9b2f3	789
Sergunb	0:9dcf85d9b2f3	790	#define DWT_CTRL_PCSAMPLENA_Pos 12 /!< DWT CTRL: PCSAMPLENA Position /
Sergunb	0:9dcf85d9b2f3	791	#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /!< DWT CTRL: PCSAMPLENA Mask /
Sergunb	0:9dcf85d9b2f3	792
Sergunb	0:9dcf85d9b2f3	793	#define DWT_CTRL_SYNCTAP_Pos 10 /!< DWT CTRL: SYNCTAP Position /
Sergunb	0:9dcf85d9b2f3	794	#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /!< DWT CTRL: SYNCTAP Mask /
Sergunb	0:9dcf85d9b2f3	795
Sergunb	0:9dcf85d9b2f3	796	#define DWT_CTRL_CYCTAP_Pos 9 /!< DWT CTRL: CYCTAP Position /
Sergunb	0:9dcf85d9b2f3	797	#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /!< DWT CTRL: CYCTAP Mask /
Sergunb	0:9dcf85d9b2f3	798
Sergunb	0:9dcf85d9b2f3	799	#define DWT_CTRL_POSTINIT_Pos 5 /!< DWT CTRL: POSTINIT Position /
Sergunb	0:9dcf85d9b2f3	800	#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /!< DWT CTRL: POSTINIT Mask /
Sergunb	0:9dcf85d9b2f3	801
Sergunb	0:9dcf85d9b2f3	802	#define DWT_CTRL_POSTPRESET_Pos 1 /!< DWT CTRL: POSTPRESET Position /
Sergunb	0:9dcf85d9b2f3	803	#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /!< DWT CTRL: POSTPRESET Mask /
Sergunb	0:9dcf85d9b2f3	804
Sergunb	0:9dcf85d9b2f3	805	#define DWT_CTRL_CYCCNTENA_Pos 0 /!< DWT CTRL: CYCCNTENA Position /
Sergunb	0:9dcf85d9b2f3	806	#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /!< DWT CTRL: CYCCNTENA Mask /
Sergunb	0:9dcf85d9b2f3	807
Sergunb	0:9dcf85d9b2f3	808	/* DWT CPI Count Register Definitions */
Sergunb	0:9dcf85d9b2f3	809	#define DWT_CPICNT_CPICNT_Pos 0 /!< DWT CPICNT: CPICNT Position /
Sergunb	0:9dcf85d9b2f3	810	#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /!< DWT CPICNT: CPICNT Mask /
Sergunb	0:9dcf85d9b2f3	811
Sergunb	0:9dcf85d9b2f3	812	/* DWT Exception Overhead Count Register Definitions */
Sergunb	0:9dcf85d9b2f3	813	#define DWT_EXCCNT_EXCCNT_Pos 0 /!< DWT EXCCNT: EXCCNT Position /
Sergunb	0:9dcf85d9b2f3	814	#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /!< DWT EXCCNT: EXCCNT Mask /
Sergunb	0:9dcf85d9b2f3	815
Sergunb	0:9dcf85d9b2f3	816	/* DWT Sleep Count Register Definitions */
Sergunb	0:9dcf85d9b2f3	817	#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /!< DWT SLEEPCNT: SLEEPCNT Position /
Sergunb	0:9dcf85d9b2f3	818	#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /!< DWT SLEEPCNT: SLEEPCNT Mask /
Sergunb	0:9dcf85d9b2f3	819
Sergunb	0:9dcf85d9b2f3	820	/* DWT LSU Count Register Definitions */
Sergunb	0:9dcf85d9b2f3	821	#define DWT_LSUCNT_LSUCNT_Pos 0 /!< DWT LSUCNT: LSUCNT Position /
Sergunb	0:9dcf85d9b2f3	822	#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /!< DWT LSUCNT: LSUCNT Mask /
Sergunb	0:9dcf85d9b2f3	823
Sergunb	0:9dcf85d9b2f3	824	/* DWT Folded-instruction Count Register Definitions */
Sergunb	0:9dcf85d9b2f3	825	#define DWT_FOLDCNT_FOLDCNT_Pos 0 /!< DWT FOLDCNT: FOLDCNT Position /
Sergunb	0:9dcf85d9b2f3	826	#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /!< DWT FOLDCNT: FOLDCNT Mask /
Sergunb	0:9dcf85d9b2f3	827
Sergunb	0:9dcf85d9b2f3	828	/* DWT Comparator Mask Register Definitions */
Sergunb	0:9dcf85d9b2f3	829	#define DWT_MASK_MASK_Pos 0 /!< DWT MASK: MASK Position /
Sergunb	0:9dcf85d9b2f3	830	#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /!< DWT MASK: MASK Mask /
Sergunb	0:9dcf85d9b2f3	831
Sergunb	0:9dcf85d9b2f3	832	/* DWT Comparator Function Register Definitions */
Sergunb	0:9dcf85d9b2f3	833	#define DWT_FUNCTION_MATCHED_Pos 24 /!< DWT FUNCTION: MATCHED Position /
Sergunb	0:9dcf85d9b2f3	834	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
Sergunb	0:9dcf85d9b2f3	835
Sergunb	0:9dcf85d9b2f3	836	#define DWT_FUNCTION_DATAVADDR1_Pos 16 /!< DWT FUNCTION: DATAVADDR1 Position /
Sergunb	0:9dcf85d9b2f3	837	#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /!< DWT FUNCTION: DATAVADDR1 Mask /
Sergunb	0:9dcf85d9b2f3	838
Sergunb	0:9dcf85d9b2f3	839	#define DWT_FUNCTION_DATAVADDR0_Pos 12 /!< DWT FUNCTION: DATAVADDR0 Position /
Sergunb	0:9dcf85d9b2f3	840	#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /!< DWT FUNCTION: DATAVADDR0 Mask /
Sergunb	0:9dcf85d9b2f3	841
Sergunb	0:9dcf85d9b2f3	842	#define DWT_FUNCTION_DATAVSIZE_Pos 10 /!< DWT FUNCTION: DATAVSIZE Position /
Sergunb	0:9dcf85d9b2f3	843	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
Sergunb	0:9dcf85d9b2f3	844
Sergunb	0:9dcf85d9b2f3	845	#define DWT_FUNCTION_LNK1ENA_Pos 9 /!< DWT FUNCTION: LNK1ENA Position /
Sergunb	0:9dcf85d9b2f3	846	#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /!< DWT FUNCTION: LNK1ENA Mask /
Sergunb	0:9dcf85d9b2f3	847
Sergunb	0:9dcf85d9b2f3	848	#define DWT_FUNCTION_DATAVMATCH_Pos 8 /!< DWT FUNCTION: DATAVMATCH Position /
Sergunb	0:9dcf85d9b2f3	849	#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /!< DWT FUNCTION: DATAVMATCH Mask /
Sergunb	0:9dcf85d9b2f3	850
Sergunb	0:9dcf85d9b2f3	851	#define DWT_FUNCTION_CYCMATCH_Pos 7 /!< DWT FUNCTION: CYCMATCH Position /
Sergunb	0:9dcf85d9b2f3	852	#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /!< DWT FUNCTION: CYCMATCH Mask /
Sergunb	0:9dcf85d9b2f3	853
Sergunb	0:9dcf85d9b2f3	854	#define DWT_FUNCTION_EMITRANGE_Pos 5 /!< DWT FUNCTION: EMITRANGE Position /
Sergunb	0:9dcf85d9b2f3	855	#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /!< DWT FUNCTION: EMITRANGE Mask /
Sergunb	0:9dcf85d9b2f3	856
Sergunb	0:9dcf85d9b2f3	857	#define DWT_FUNCTION_FUNCTION_Pos 0 /!< DWT FUNCTION: FUNCTION Position /
Sergunb	0:9dcf85d9b2f3	858	#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /!< DWT FUNCTION: FUNCTION Mask /
Sergunb	0:9dcf85d9b2f3	859
Sergunb	0:9dcf85d9b2f3	860	/@}/ /* end of group CMSIS_DWT */
Sergunb	0:9dcf85d9b2f3	861
Sergunb	0:9dcf85d9b2f3	862
Sergunb	0:9dcf85d9b2f3	863	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	864	\defgroup CMSIS_TPI Trace Port Interface (TPI)
Sergunb	0:9dcf85d9b2f3	865	\brief Type definitions for the Trace Port Interface (TPI)
Sergunb	0:9dcf85d9b2f3	866	@{
Sergunb	0:9dcf85d9b2f3	867	*/
Sergunb	0:9dcf85d9b2f3	868
Sergunb	0:9dcf85d9b2f3	869	/** \brief Structure type to access the Trace Port Interface Register (TPI).
Sergunb	0:9dcf85d9b2f3	870	*/
Sergunb	0:9dcf85d9b2f3	871	typedef struct
Sergunb	0:9dcf85d9b2f3	872	{
Sergunb	0:9dcf85d9b2f3	873	__IO uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
Sergunb	0:9dcf85d9b2f3	874	__IO uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
Sergunb	0:9dcf85d9b2f3	875	uint32_t RESERVED0[2];
Sergunb	0:9dcf85d9b2f3	876	__IO uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
Sergunb	0:9dcf85d9b2f3	877	uint32_t RESERVED1[55];
Sergunb	0:9dcf85d9b2f3	878	__IO uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
Sergunb	0:9dcf85d9b2f3	879	uint32_t RESERVED2[131];
Sergunb	0:9dcf85d9b2f3	880	__I uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
Sergunb	0:9dcf85d9b2f3	881	__IO uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
Sergunb	0:9dcf85d9b2f3	882	__I uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
Sergunb	0:9dcf85d9b2f3	883	uint32_t RESERVED3[759];
Sergunb	0:9dcf85d9b2f3	884	__I uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
Sergunb	0:9dcf85d9b2f3	885	__I uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
Sergunb	0:9dcf85d9b2f3	886	__I uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
Sergunb	0:9dcf85d9b2f3	887	uint32_t RESERVED4[1];
Sergunb	0:9dcf85d9b2f3	888	__I uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
Sergunb	0:9dcf85d9b2f3	889	__I uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
Sergunb	0:9dcf85d9b2f3	890	__IO uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
Sergunb	0:9dcf85d9b2f3	891	uint32_t RESERVED5[39];
Sergunb	0:9dcf85d9b2f3	892	__IO uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
Sergunb	0:9dcf85d9b2f3	893	__IO uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
Sergunb	0:9dcf85d9b2f3	894	uint32_t RESERVED7[8];
Sergunb	0:9dcf85d9b2f3	895	__I uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
Sergunb	0:9dcf85d9b2f3	896	__I uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
Sergunb	0:9dcf85d9b2f3	897	} TPI_Type;
Sergunb	0:9dcf85d9b2f3	898
Sergunb	0:9dcf85d9b2f3	899	/* TPI Asynchronous Clock Prescaler Register Definitions */
Sergunb	0:9dcf85d9b2f3	900	#define TPI_ACPR_PRESCALER_Pos 0 /!< TPI ACPR: PRESCALER Position /
Sergunb	0:9dcf85d9b2f3	901	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /!< TPI ACPR: PRESCALER Mask /
Sergunb	0:9dcf85d9b2f3	902
Sergunb	0:9dcf85d9b2f3	903	/* TPI Selected Pin Protocol Register Definitions */
Sergunb	0:9dcf85d9b2f3	904	#define TPI_SPPR_TXMODE_Pos 0 /!< TPI SPPR: TXMODE Position /
Sergunb	0:9dcf85d9b2f3	905	#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /!< TPI SPPR: TXMODE Mask /
Sergunb	0:9dcf85d9b2f3	906
Sergunb	0:9dcf85d9b2f3	907	/* TPI Formatter and Flush Status Register Definitions */
Sergunb	0:9dcf85d9b2f3	908	#define TPI_FFSR_FtNonStop_Pos 3 /!< TPI FFSR: FtNonStop Position /
Sergunb	0:9dcf85d9b2f3	909	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
Sergunb	0:9dcf85d9b2f3	910
Sergunb	0:9dcf85d9b2f3	911	#define TPI_FFSR_TCPresent_Pos 2 /!< TPI FFSR: TCPresent Position /
Sergunb	0:9dcf85d9b2f3	912	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
Sergunb	0:9dcf85d9b2f3	913
Sergunb	0:9dcf85d9b2f3	914	#define TPI_FFSR_FtStopped_Pos 1 /!< TPI FFSR: FtStopped Position /
Sergunb	0:9dcf85d9b2f3	915	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
Sergunb	0:9dcf85d9b2f3	916
Sergunb	0:9dcf85d9b2f3	917	#define TPI_FFSR_FlInProg_Pos 0 /!< TPI FFSR: FlInProg Position /
Sergunb	0:9dcf85d9b2f3	918	#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /!< TPI FFSR: FlInProg Mask /
Sergunb	0:9dcf85d9b2f3	919
Sergunb	0:9dcf85d9b2f3	920	/* TPI Formatter and Flush Control Register Definitions */
Sergunb	0:9dcf85d9b2f3	921	#define TPI_FFCR_TrigIn_Pos 8 /!< TPI FFCR: TrigIn Position /
Sergunb	0:9dcf85d9b2f3	922	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
Sergunb	0:9dcf85d9b2f3	923
Sergunb	0:9dcf85d9b2f3	924	#define TPI_FFCR_EnFCont_Pos 1 /!< TPI FFCR: EnFCont Position /
Sergunb	0:9dcf85d9b2f3	925	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
Sergunb	0:9dcf85d9b2f3	926
Sergunb	0:9dcf85d9b2f3	927	/* TPI TRIGGER Register Definitions */
Sergunb	0:9dcf85d9b2f3	928	#define TPI_TRIGGER_TRIGGER_Pos 0 /!< TPI TRIGGER: TRIGGER Position /
Sergunb	0:9dcf85d9b2f3	929	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /!< TPI TRIGGER: TRIGGER Mask /
Sergunb	0:9dcf85d9b2f3	930
Sergunb	0:9dcf85d9b2f3	931	/* TPI Integration ETM Data Register Definitions (FIFO0) */
Sergunb	0:9dcf85d9b2f3	932	#define TPI_FIFO0_ITM_ATVALID_Pos 29 /!< TPI FIFO0: ITM_ATVALID Position /
Sergunb	0:9dcf85d9b2f3	933	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
Sergunb	0:9dcf85d9b2f3	934
Sergunb	0:9dcf85d9b2f3	935	#define TPI_FIFO0_ITM_bytecount_Pos 27 /!< TPI FIFO0: ITM_bytecount Position /
Sergunb	0:9dcf85d9b2f3	936	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
Sergunb	0:9dcf85d9b2f3	937
Sergunb	0:9dcf85d9b2f3	938	#define TPI_FIFO0_ETM_ATVALID_Pos 26 /!< TPI FIFO0: ETM_ATVALID Position /
Sergunb	0:9dcf85d9b2f3	939	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
Sergunb	0:9dcf85d9b2f3	940
Sergunb	0:9dcf85d9b2f3	941	#define TPI_FIFO0_ETM_bytecount_Pos 24 /!< TPI FIFO0: ETM_bytecount Position /
Sergunb	0:9dcf85d9b2f3	942	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
Sergunb	0:9dcf85d9b2f3	943
Sergunb	0:9dcf85d9b2f3	944	#define TPI_FIFO0_ETM2_Pos 16 /!< TPI FIFO0: ETM2 Position /
Sergunb	0:9dcf85d9b2f3	945	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
Sergunb	0:9dcf85d9b2f3	946
Sergunb	0:9dcf85d9b2f3	947	#define TPI_FIFO0_ETM1_Pos 8 /!< TPI FIFO0: ETM1 Position /
Sergunb	0:9dcf85d9b2f3	948	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
Sergunb	0:9dcf85d9b2f3	949
Sergunb	0:9dcf85d9b2f3	950	#define TPI_FIFO0_ETM0_Pos 0 /!< TPI FIFO0: ETM0 Position /
Sergunb	0:9dcf85d9b2f3	951	#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /!< TPI FIFO0: ETM0 Mask /
Sergunb	0:9dcf85d9b2f3	952
Sergunb	0:9dcf85d9b2f3	953	/* TPI ITATBCTR2 Register Definitions */
Sergunb	0:9dcf85d9b2f3	954	#define TPI_ITATBCTR2_ATREADY_Pos 0 /!< TPI ITATBCTR2: ATREADY Position /
Sergunb	0:9dcf85d9b2f3	955	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /!< TPI ITATBCTR2: ATREADY Mask /
Sergunb	0:9dcf85d9b2f3	956
Sergunb	0:9dcf85d9b2f3	957	/* TPI Integration ITM Data Register Definitions (FIFO1) */
Sergunb	0:9dcf85d9b2f3	958	#define TPI_FIFO1_ITM_ATVALID_Pos 29 /!< TPI FIFO1: ITM_ATVALID Position /
Sergunb	0:9dcf85d9b2f3	959	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
Sergunb	0:9dcf85d9b2f3	960
Sergunb	0:9dcf85d9b2f3	961	#define TPI_FIFO1_ITM_bytecount_Pos 27 /!< TPI FIFO1: ITM_bytecount Position /
Sergunb	0:9dcf85d9b2f3	962	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
Sergunb	0:9dcf85d9b2f3	963
Sergunb	0:9dcf85d9b2f3	964	#define TPI_FIFO1_ETM_ATVALID_Pos 26 /!< TPI FIFO1: ETM_ATVALID Position /
Sergunb	0:9dcf85d9b2f3	965	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
Sergunb	0:9dcf85d9b2f3	966
Sergunb	0:9dcf85d9b2f3	967	#define TPI_FIFO1_ETM_bytecount_Pos 24 /!< TPI FIFO1: ETM_bytecount Position /
Sergunb	0:9dcf85d9b2f3	968	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
Sergunb	0:9dcf85d9b2f3	969
Sergunb	0:9dcf85d9b2f3	970	#define TPI_FIFO1_ITM2_Pos 16 /!< TPI FIFO1: ITM2 Position /
Sergunb	0:9dcf85d9b2f3	971	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
Sergunb	0:9dcf85d9b2f3	972
Sergunb	0:9dcf85d9b2f3	973	#define TPI_FIFO1_ITM1_Pos 8 /!< TPI FIFO1: ITM1 Position /
Sergunb	0:9dcf85d9b2f3	974	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
Sergunb	0:9dcf85d9b2f3	975
Sergunb	0:9dcf85d9b2f3	976	#define TPI_FIFO1_ITM0_Pos 0 /!< TPI FIFO1: ITM0 Position /
Sergunb	0:9dcf85d9b2f3	977	#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /!< TPI FIFO1: ITM0 Mask /
Sergunb	0:9dcf85d9b2f3	978
Sergunb	0:9dcf85d9b2f3	979	/* TPI ITATBCTR0 Register Definitions */
Sergunb	0:9dcf85d9b2f3	980	#define TPI_ITATBCTR0_ATREADY_Pos 0 /!< TPI ITATBCTR0: ATREADY Position /
Sergunb	0:9dcf85d9b2f3	981	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /!< TPI ITATBCTR0: ATREADY Mask /
Sergunb	0:9dcf85d9b2f3	982
Sergunb	0:9dcf85d9b2f3	983	/* TPI Integration Mode Control Register Definitions */
Sergunb	0:9dcf85d9b2f3	984	#define TPI_ITCTRL_Mode_Pos 0 /!< TPI ITCTRL: Mode Position /
Sergunb	0:9dcf85d9b2f3	985	#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /!< TPI ITCTRL: Mode Mask /
Sergunb	0:9dcf85d9b2f3	986
Sergunb	0:9dcf85d9b2f3	987	/* TPI DEVID Register Definitions */
Sergunb	0:9dcf85d9b2f3	988	#define TPI_DEVID_NRZVALID_Pos 11 /!< TPI DEVID: NRZVALID Position /
Sergunb	0:9dcf85d9b2f3	989	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
Sergunb	0:9dcf85d9b2f3	990
Sergunb	0:9dcf85d9b2f3	991	#define TPI_DEVID_MANCVALID_Pos 10 /!< TPI DEVID: MANCVALID Position /
Sergunb	0:9dcf85d9b2f3	992	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
Sergunb	0:9dcf85d9b2f3	993
Sergunb	0:9dcf85d9b2f3	994	#define TPI_DEVID_PTINVALID_Pos 9 /!< TPI DEVID: PTINVALID Position /
Sergunb	0:9dcf85d9b2f3	995	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
Sergunb	0:9dcf85d9b2f3	996
Sergunb	0:9dcf85d9b2f3	997	#define TPI_DEVID_MinBufSz_Pos 6 /!< TPI DEVID: MinBufSz Position /
Sergunb	0:9dcf85d9b2f3	998	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
Sergunb	0:9dcf85d9b2f3	999
Sergunb	0:9dcf85d9b2f3	1000	#define TPI_DEVID_AsynClkIn_Pos 5 /!< TPI DEVID: AsynClkIn Position /
Sergunb	0:9dcf85d9b2f3	1001	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
Sergunb	0:9dcf85d9b2f3	1002
Sergunb	0:9dcf85d9b2f3	1003	#define TPI_DEVID_NrTraceInput_Pos 0 /!< TPI DEVID: NrTraceInput Position /
Sergunb	0:9dcf85d9b2f3	1004	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /!< TPI DEVID: NrTraceInput Mask /
Sergunb	0:9dcf85d9b2f3	1005
Sergunb	0:9dcf85d9b2f3	1006	/* TPI DEVTYPE Register Definitions */
Sergunb	0:9dcf85d9b2f3	1007	#define TPI_DEVTYPE_SubType_Pos 0 /!< TPI DEVTYPE: SubType Position /
Sergunb	0:9dcf85d9b2f3	1008	#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /!< TPI DEVTYPE: SubType Mask /
Sergunb	0:9dcf85d9b2f3	1009
Sergunb	0:9dcf85d9b2f3	1010	#define TPI_DEVTYPE_MajorType_Pos 4 /!< TPI DEVTYPE: MajorType Position /
Sergunb	0:9dcf85d9b2f3	1011	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
Sergunb	0:9dcf85d9b2f3	1012
Sergunb	0:9dcf85d9b2f3	1013	/@}/ /* end of group CMSIS_TPI */
Sergunb	0:9dcf85d9b2f3	1014
Sergunb	0:9dcf85d9b2f3	1015
Sergunb	0:9dcf85d9b2f3	1016	#if (__MPU_PRESENT == 1)
Sergunb	0:9dcf85d9b2f3	1017	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	1018	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
Sergunb	0:9dcf85d9b2f3	1019	\brief Type definitions for the Memory Protection Unit (MPU)
Sergunb	0:9dcf85d9b2f3	1020	@{
Sergunb	0:9dcf85d9b2f3	1021	*/
Sergunb	0:9dcf85d9b2f3	1022
Sergunb	0:9dcf85d9b2f3	1023	/** \brief Structure type to access the Memory Protection Unit (MPU).
Sergunb	0:9dcf85d9b2f3	1024	*/
Sergunb	0:9dcf85d9b2f3	1025	typedef struct
Sergunb	0:9dcf85d9b2f3	1026	{
Sergunb	0:9dcf85d9b2f3	1027	__I uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
Sergunb	0:9dcf85d9b2f3	1028	__IO uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
Sergunb	0:9dcf85d9b2f3	1029	__IO uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region RNRber Register /
Sergunb	0:9dcf85d9b2f3	1030	__IO uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
Sergunb	0:9dcf85d9b2f3	1031	__IO uint32_t RASR; /!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register /
Sergunb	0:9dcf85d9b2f3	1032	__IO uint32_t RBAR_A1; /!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register /
Sergunb	0:9dcf85d9b2f3	1033	__IO uint32_t RASR_A1; /!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register /
Sergunb	0:9dcf85d9b2f3	1034	__IO uint32_t RBAR_A2; /!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register /
Sergunb	0:9dcf85d9b2f3	1035	__IO uint32_t RASR_A2; /!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register /
Sergunb	0:9dcf85d9b2f3	1036	__IO uint32_t RBAR_A3; /!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register /
Sergunb	0:9dcf85d9b2f3	1037	__IO uint32_t RASR_A3; /!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register /
Sergunb	0:9dcf85d9b2f3	1038	} MPU_Type;
Sergunb	0:9dcf85d9b2f3	1039
Sergunb	0:9dcf85d9b2f3	1040	/* MPU Type Register */
Sergunb	0:9dcf85d9b2f3	1041	#define MPU_TYPE_IREGION_Pos 16 /!< MPU TYPE: IREGION Position /
Sergunb	0:9dcf85d9b2f3	1042	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
Sergunb	0:9dcf85d9b2f3	1043
Sergunb	0:9dcf85d9b2f3	1044	#define MPU_TYPE_DREGION_Pos 8 /!< MPU TYPE: DREGION Position /
Sergunb	0:9dcf85d9b2f3	1045	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
Sergunb	0:9dcf85d9b2f3	1046
Sergunb	0:9dcf85d9b2f3	1047	#define MPU_TYPE_SEPARATE_Pos 0 /!< MPU TYPE: SEPARATE Position /
Sergunb	0:9dcf85d9b2f3	1048	#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /!< MPU TYPE: SEPARATE Mask /
Sergunb	0:9dcf85d9b2f3	1049
Sergunb	0:9dcf85d9b2f3	1050	/* MPU Control Register */
Sergunb	0:9dcf85d9b2f3	1051	#define MPU_CTRL_PRIVDEFENA_Pos 2 /!< MPU CTRL: PRIVDEFENA Position /
Sergunb	0:9dcf85d9b2f3	1052	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
Sergunb	0:9dcf85d9b2f3	1053
Sergunb	0:9dcf85d9b2f3	1054	#define MPU_CTRL_HFNMIENA_Pos 1 /!< MPU CTRL: HFNMIENA Position /
Sergunb	0:9dcf85d9b2f3	1055	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
Sergunb	0:9dcf85d9b2f3	1056
Sergunb	0:9dcf85d9b2f3	1057	#define MPU_CTRL_ENABLE_Pos 0 /!< MPU CTRL: ENABLE Position /
Sergunb	0:9dcf85d9b2f3	1058	#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /!< MPU CTRL: ENABLE Mask /
Sergunb	0:9dcf85d9b2f3	1059
Sergunb	0:9dcf85d9b2f3	1060	/* MPU Region Number Register */
Sergunb	0:9dcf85d9b2f3	1061	#define MPU_RNR_REGION_Pos 0 /!< MPU RNR: REGION Position /
Sergunb	0:9dcf85d9b2f3	1062	#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /!< MPU RNR: REGION Mask /
Sergunb	0:9dcf85d9b2f3	1063
Sergunb	0:9dcf85d9b2f3	1064	/* MPU Region Base Address Register */
Sergunb	0:9dcf85d9b2f3	1065	#define MPU_RBAR_ADDR_Pos 5 /!< MPU RBAR: ADDR Position /
Sergunb	0:9dcf85d9b2f3	1066	#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /!< MPU RBAR: ADDR Mask /
Sergunb	0:9dcf85d9b2f3	1067
Sergunb	0:9dcf85d9b2f3	1068	#define MPU_RBAR_VALID_Pos 4 /!< MPU RBAR: VALID Position /
Sergunb	0:9dcf85d9b2f3	1069	#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /!< MPU RBAR: VALID Mask /
Sergunb	0:9dcf85d9b2f3	1070
Sergunb	0:9dcf85d9b2f3	1071	#define MPU_RBAR_REGION_Pos 0 /!< MPU RBAR: REGION Position /
Sergunb	0:9dcf85d9b2f3	1072	#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /!< MPU RBAR: REGION Mask /
Sergunb	0:9dcf85d9b2f3	1073
Sergunb	0:9dcf85d9b2f3	1074	/* MPU Region Attribute and Size Register */
Sergunb	0:9dcf85d9b2f3	1075	#define MPU_RASR_ATTRS_Pos 16 /!< MPU RASR: MPU Region Attribute field Position /
Sergunb	0:9dcf85d9b2f3	1076	#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /!< MPU RASR: MPU Region Attribute field Mask /
Sergunb	0:9dcf85d9b2f3	1077
Sergunb	0:9dcf85d9b2f3	1078	#define MPU_RASR_XN_Pos 28 /!< MPU RASR: ATTRS.XN Position /
Sergunb	0:9dcf85d9b2f3	1079	#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /!< MPU RASR: ATTRS.XN Mask /
Sergunb	0:9dcf85d9b2f3	1080
Sergunb	0:9dcf85d9b2f3	1081	#define MPU_RASR_AP_Pos 24 /!< MPU RASR: ATTRS.AP Position /
Sergunb	0:9dcf85d9b2f3	1082	#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /!< MPU RASR: ATTRS.AP Mask /
Sergunb	0:9dcf85d9b2f3	1083
Sergunb	0:9dcf85d9b2f3	1084	#define MPU_RASR_TEX_Pos 19 /!< MPU RASR: ATTRS.TEX Position /
Sergunb	0:9dcf85d9b2f3	1085	#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /!< MPU RASR: ATTRS.TEX Mask /
Sergunb	0:9dcf85d9b2f3	1086
Sergunb	0:9dcf85d9b2f3	1087	#define MPU_RASR_S_Pos 18 /!< MPU RASR: ATTRS.S Position /
Sergunb	0:9dcf85d9b2f3	1088	#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /!< MPU RASR: ATTRS.S Mask /
Sergunb	0:9dcf85d9b2f3	1089
Sergunb	0:9dcf85d9b2f3	1090	#define MPU_RASR_C_Pos 17 /!< MPU RASR: ATTRS.C Position /
Sergunb	0:9dcf85d9b2f3	1091	#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /!< MPU RASR: ATTRS.C Mask /
Sergunb	0:9dcf85d9b2f3	1092
Sergunb	0:9dcf85d9b2f3	1093	#define MPU_RASR_B_Pos 16 /!< MPU RASR: ATTRS.B Position /
Sergunb	0:9dcf85d9b2f3	1094	#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /!< MPU RASR: ATTRS.B Mask /
Sergunb	0:9dcf85d9b2f3	1095
Sergunb	0:9dcf85d9b2f3	1096	#define MPU_RASR_SRD_Pos 8 /!< MPU RASR: Sub-Region Disable Position /
Sergunb	0:9dcf85d9b2f3	1097	#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /!< MPU RASR: Sub-Region Disable Mask /
Sergunb	0:9dcf85d9b2f3	1098
Sergunb	0:9dcf85d9b2f3	1099	#define MPU_RASR_SIZE_Pos 1 /!< MPU RASR: Region Size Field Position /
Sergunb	0:9dcf85d9b2f3	1100	#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /!< MPU RASR: Region Size Field Mask /
Sergunb	0:9dcf85d9b2f3	1101
Sergunb	0:9dcf85d9b2f3	1102	#define MPU_RASR_ENABLE_Pos 0 /!< MPU RASR: Region enable bit Position /
Sergunb	0:9dcf85d9b2f3	1103	#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /!< MPU RASR: Region enable bit Disable Mask /
Sergunb	0:9dcf85d9b2f3	1104
Sergunb	0:9dcf85d9b2f3	1105	/@} end of group CMSIS_MPU /
Sergunb	0:9dcf85d9b2f3	1106	#endif
Sergunb	0:9dcf85d9b2f3	1107
Sergunb	0:9dcf85d9b2f3	1108
Sergunb	0:9dcf85d9b2f3	1109	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	1110	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
Sergunb	0:9dcf85d9b2f3	1111	\brief Type definitions for the Core Debug Registers
Sergunb	0:9dcf85d9b2f3	1112	@{
Sergunb	0:9dcf85d9b2f3	1113	*/
Sergunb	0:9dcf85d9b2f3	1114
Sergunb	0:9dcf85d9b2f3	1115	/** \brief Structure type to access the Core Debug Register (CoreDebug).
Sergunb	0:9dcf85d9b2f3	1116	*/
Sergunb	0:9dcf85d9b2f3	1117	typedef struct
Sergunb	0:9dcf85d9b2f3	1118	{
Sergunb	0:9dcf85d9b2f3	1119	__IO uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
Sergunb	0:9dcf85d9b2f3	1120	__O uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
Sergunb	0:9dcf85d9b2f3	1121	__IO uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
Sergunb	0:9dcf85d9b2f3	1122	__IO uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
Sergunb	0:9dcf85d9b2f3	1123	} CoreDebug_Type;
Sergunb	0:9dcf85d9b2f3	1124
Sergunb	0:9dcf85d9b2f3	1125	/* Debug Halting Control and Status Register */
Sergunb	0:9dcf85d9b2f3	1126	#define CoreDebug_DHCSR_DBGKEY_Pos 16 /!< CoreDebug DHCSR: DBGKEY Position /
Sergunb	0:9dcf85d9b2f3	1127	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
Sergunb	0:9dcf85d9b2f3	1128
Sergunb	0:9dcf85d9b2f3	1129	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /!< CoreDebug DHCSR: S_RESET_ST Position /
Sergunb	0:9dcf85d9b2f3	1130	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
Sergunb	0:9dcf85d9b2f3	1131
Sergunb	0:9dcf85d9b2f3	1132	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /!< CoreDebug DHCSR: S_RETIRE_ST Position /
Sergunb	0:9dcf85d9b2f3	1133	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
Sergunb	0:9dcf85d9b2f3	1134
Sergunb	0:9dcf85d9b2f3	1135	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /!< CoreDebug DHCSR: S_LOCKUP Position /
Sergunb	0:9dcf85d9b2f3	1136	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
Sergunb	0:9dcf85d9b2f3	1137
Sergunb	0:9dcf85d9b2f3	1138	#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /!< CoreDebug DHCSR: S_SLEEP Position /
Sergunb	0:9dcf85d9b2f3	1139	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
Sergunb	0:9dcf85d9b2f3	1140
Sergunb	0:9dcf85d9b2f3	1141	#define CoreDebug_DHCSR_S_HALT_Pos 17 /!< CoreDebug DHCSR: S_HALT Position /
Sergunb	0:9dcf85d9b2f3	1142	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
Sergunb	0:9dcf85d9b2f3	1143
Sergunb	0:9dcf85d9b2f3	1144	#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /!< CoreDebug DHCSR: S_REGRDY Position /
Sergunb	0:9dcf85d9b2f3	1145	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
Sergunb	0:9dcf85d9b2f3	1146
Sergunb	0:9dcf85d9b2f3	1147	#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /!< CoreDebug DHCSR: C_SNAPSTALL Position /
Sergunb	0:9dcf85d9b2f3	1148	#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /!< CoreDebug DHCSR: C_SNAPSTALL Mask /
Sergunb	0:9dcf85d9b2f3	1149
Sergunb	0:9dcf85d9b2f3	1150	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /!< CoreDebug DHCSR: C_MASKINTS Position /
Sergunb	0:9dcf85d9b2f3	1151	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
Sergunb	0:9dcf85d9b2f3	1152
Sergunb	0:9dcf85d9b2f3	1153	#define CoreDebug_DHCSR_C_STEP_Pos 2 /!< CoreDebug DHCSR: C_STEP Position /
Sergunb	0:9dcf85d9b2f3	1154	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
Sergunb	0:9dcf85d9b2f3	1155
Sergunb	0:9dcf85d9b2f3	1156	#define CoreDebug_DHCSR_C_HALT_Pos 1 /!< CoreDebug DHCSR: C_HALT Position /
Sergunb	0:9dcf85d9b2f3	1157	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
Sergunb	0:9dcf85d9b2f3	1158
Sergunb	0:9dcf85d9b2f3	1159	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /!< CoreDebug DHCSR: C_DEBUGEN Position /
Sergunb	0:9dcf85d9b2f3	1160	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
Sergunb	0:9dcf85d9b2f3	1161
Sergunb	0:9dcf85d9b2f3	1162	/* Debug Core Register Selector Register */
Sergunb	0:9dcf85d9b2f3	1163	#define CoreDebug_DCRSR_REGWnR_Pos 16 /!< CoreDebug DCRSR: REGWnR Position /
Sergunb	0:9dcf85d9b2f3	1164	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
Sergunb	0:9dcf85d9b2f3	1165
Sergunb	0:9dcf85d9b2f3	1166	#define CoreDebug_DCRSR_REGSEL_Pos 0 /!< CoreDebug DCRSR: REGSEL Position /
Sergunb	0:9dcf85d9b2f3	1167	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /!< CoreDebug DCRSR: REGSEL Mask /
Sergunb	0:9dcf85d9b2f3	1168
Sergunb	0:9dcf85d9b2f3	1169	/* Debug Exception and Monitor Control Register */
Sergunb	0:9dcf85d9b2f3	1170	#define CoreDebug_DEMCR_TRCENA_Pos 24 /!< CoreDebug DEMCR: TRCENA Position /
Sergunb	0:9dcf85d9b2f3	1171	#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /!< CoreDebug DEMCR: TRCENA Mask /
Sergunb	0:9dcf85d9b2f3	1172
Sergunb	0:9dcf85d9b2f3	1173	#define CoreDebug_DEMCR_MON_REQ_Pos 19 /!< CoreDebug DEMCR: MON_REQ Position /
Sergunb	0:9dcf85d9b2f3	1174	#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /!< CoreDebug DEMCR: MON_REQ Mask /
Sergunb	0:9dcf85d9b2f3	1175
Sergunb	0:9dcf85d9b2f3	1176	#define CoreDebug_DEMCR_MON_STEP_Pos 18 /!< CoreDebug DEMCR: MON_STEP Position /
Sergunb	0:9dcf85d9b2f3	1177	#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /!< CoreDebug DEMCR: MON_STEP Mask /
Sergunb	0:9dcf85d9b2f3	1178
Sergunb	0:9dcf85d9b2f3	1179	#define CoreDebug_DEMCR_MON_PEND_Pos 17 /!< CoreDebug DEMCR: MON_PEND Position /
Sergunb	0:9dcf85d9b2f3	1180	#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /!< CoreDebug DEMCR: MON_PEND Mask /
Sergunb	0:9dcf85d9b2f3	1181
Sergunb	0:9dcf85d9b2f3	1182	#define CoreDebug_DEMCR_MON_EN_Pos 16 /!< CoreDebug DEMCR: MON_EN Position /
Sergunb	0:9dcf85d9b2f3	1183	#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /!< CoreDebug DEMCR: MON_EN Mask /
Sergunb	0:9dcf85d9b2f3	1184
Sergunb	0:9dcf85d9b2f3	1185	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /!< CoreDebug DEMCR: VC_HARDERR Position /
Sergunb	0:9dcf85d9b2f3	1186	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
Sergunb	0:9dcf85d9b2f3	1187
Sergunb	0:9dcf85d9b2f3	1188	#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /!< CoreDebug DEMCR: VC_INTERR Position /
Sergunb	0:9dcf85d9b2f3	1189	#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /!< CoreDebug DEMCR: VC_INTERR Mask /
Sergunb	0:9dcf85d9b2f3	1190
Sergunb	0:9dcf85d9b2f3	1191	#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /!< CoreDebug DEMCR: VC_BUSERR Position /
Sergunb	0:9dcf85d9b2f3	1192	#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /!< CoreDebug DEMCR: VC_BUSERR Mask /
Sergunb	0:9dcf85d9b2f3	1193
Sergunb	0:9dcf85d9b2f3	1194	#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /!< CoreDebug DEMCR: VC_STATERR Position /
Sergunb	0:9dcf85d9b2f3	1195	#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /!< CoreDebug DEMCR: VC_STATERR Mask /
Sergunb	0:9dcf85d9b2f3	1196
Sergunb	0:9dcf85d9b2f3	1197	#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /!< CoreDebug DEMCR: VC_CHKERR Position /
Sergunb	0:9dcf85d9b2f3	1198	#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /!< CoreDebug DEMCR: VC_CHKERR Mask /
Sergunb	0:9dcf85d9b2f3	1199
Sergunb	0:9dcf85d9b2f3	1200	#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /!< CoreDebug DEMCR: VC_NOCPERR Position /
Sergunb	0:9dcf85d9b2f3	1201	#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /!< CoreDebug DEMCR: VC_NOCPERR Mask /
Sergunb	0:9dcf85d9b2f3	1202
Sergunb	0:9dcf85d9b2f3	1203	#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /!< CoreDebug DEMCR: VC_MMERR Position /
Sergunb	0:9dcf85d9b2f3	1204	#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /!< CoreDebug DEMCR: VC_MMERR Mask /
Sergunb	0:9dcf85d9b2f3	1205
Sergunb	0:9dcf85d9b2f3	1206	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /!< CoreDebug DEMCR: VC_CORERESET Position /
Sergunb	0:9dcf85d9b2f3	1207	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /!< CoreDebug DEMCR: VC_CORERESET Mask /
Sergunb	0:9dcf85d9b2f3	1208
Sergunb	0:9dcf85d9b2f3	1209	/@} end of group CMSIS_CoreDebug /
Sergunb	0:9dcf85d9b2f3	1210
Sergunb	0:9dcf85d9b2f3	1211
Sergunb	0:9dcf85d9b2f3	1212	/** \ingroup CMSIS_core_register
Sergunb	0:9dcf85d9b2f3	1213	\defgroup CMSIS_core_base Core Definitions
Sergunb	0:9dcf85d9b2f3	1214	\brief Definitions for base addresses, unions, and structures.
Sergunb	0:9dcf85d9b2f3	1215	@{
Sergunb	0:9dcf85d9b2f3	1216	*/
Sergunb	0:9dcf85d9b2f3	1217
Sergunb	0:9dcf85d9b2f3	1218	/* Memory mapping of Cortex-M3 Hardware */
Sergunb	0:9dcf85d9b2f3	1219	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
Sergunb	0:9dcf85d9b2f3	1220	#define ITM_BASE (0xE0000000UL) /!< ITM Base Address /
Sergunb	0:9dcf85d9b2f3	1221	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
Sergunb	0:9dcf85d9b2f3	1222	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
Sergunb	0:9dcf85d9b2f3	1223	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
Sergunb	0:9dcf85d9b2f3	1224	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
Sergunb	0:9dcf85d9b2f3	1225	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
Sergunb	0:9dcf85d9b2f3	1226	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
Sergunb	0:9dcf85d9b2f3	1227
Sergunb	0:9dcf85d9b2f3	1228	#define SCnSCB ((SCnSCB_Type ) SCS_BASE ) /!< System control Register not in SCB */
Sergunb	0:9dcf85d9b2f3	1229	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
Sergunb	0:9dcf85d9b2f3	1230	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
Sergunb	0:9dcf85d9b2f3	1231	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
Sergunb	0:9dcf85d9b2f3	1232	#define ITM ((ITM_Type ) ITM_BASE ) /!< ITM configuration struct */
Sergunb	0:9dcf85d9b2f3	1233	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
Sergunb	0:9dcf85d9b2f3	1234	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
Sergunb	0:9dcf85d9b2f3	1235	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE) /!< Core Debug configuration struct */
Sergunb	0:9dcf85d9b2f3	1236
Sergunb	0:9dcf85d9b2f3	1237	#if (__MPU_PRESENT == 1)
Sergunb	0:9dcf85d9b2f3	1238	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
Sergunb	0:9dcf85d9b2f3	1239	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
Sergunb	0:9dcf85d9b2f3	1240	#endif
Sergunb	0:9dcf85d9b2f3	1241
Sergunb	0:9dcf85d9b2f3	1242	/@} /
Sergunb	0:9dcf85d9b2f3	1243
Sergunb	0:9dcf85d9b2f3	1244
Sergunb	0:9dcf85d9b2f3	1245
Sergunb	0:9dcf85d9b2f3	1246	/*******************************************************************************
Sergunb	0:9dcf85d9b2f3	1247	* Hardware Abstraction Layer
Sergunb	0:9dcf85d9b2f3	1248	Core Function Interface contains:
Sergunb	0:9dcf85d9b2f3	1249	- Core NVIC Functions
Sergunb	0:9dcf85d9b2f3	1250	- Core SysTick Functions
Sergunb	0:9dcf85d9b2f3	1251	- Core Debug Functions
Sergunb	0:9dcf85d9b2f3	1252	- Core Register Access Functions
Sergunb	0:9dcf85d9b2f3	1253	******************************************************************************/
Sergunb	0:9dcf85d9b2f3	1254	/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
Sergunb	0:9dcf85d9b2f3	1255	*/
Sergunb	0:9dcf85d9b2f3	1256
Sergunb	0:9dcf85d9b2f3	1257
Sergunb	0:9dcf85d9b2f3	1258
Sergunb	0:9dcf85d9b2f3	1259	/* ########################## NVIC functions #################################### */
Sergunb	0:9dcf85d9b2f3	1260	/** \ingroup CMSIS_Core_FunctionInterface
Sergunb	0:9dcf85d9b2f3	1261	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
Sergunb	0:9dcf85d9b2f3	1262	\brief Functions that manage interrupts and exceptions via the NVIC.
Sergunb	0:9dcf85d9b2f3	1263	@{
Sergunb	0:9dcf85d9b2f3	1264	*/
Sergunb	0:9dcf85d9b2f3	1265
Sergunb	0:9dcf85d9b2f3	1266	/** \brief Set Priority Grouping
Sergunb	0:9dcf85d9b2f3	1267
Sergunb	0:9dcf85d9b2f3	1268	The function sets the priority grouping field using the required unlock sequence.
Sergunb	0:9dcf85d9b2f3	1269	The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Sergunb	0:9dcf85d9b2f3	1270	Only values from 0..7 are used.
Sergunb	0:9dcf85d9b2f3	1271	In case of a conflict between priority grouping and available
Sergunb	0:9dcf85d9b2f3	1272	priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
Sergunb	0:9dcf85d9b2f3	1273
Sergunb	0:9dcf85d9b2f3	1274	\param [in] PriorityGroup Priority grouping field.
Sergunb	0:9dcf85d9b2f3	1275	*/
Sergunb	0:9dcf85d9b2f3	1276	__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
Sergunb	0:9dcf85d9b2f3	1277	{
Sergunb	0:9dcf85d9b2f3	1278	uint32_t reg_value;
Sergunb	0:9dcf85d9b2f3	1279	uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
Sergunb	0:9dcf85d9b2f3	1280
Sergunb	0:9dcf85d9b2f3	1281	reg_value = SCB->AIRCR; /* read old register configuration */
Sergunb	0:9dcf85d9b2f3	1282	reg_value &= ~(SCB_AIRCR_VECTKEY_Msk \| SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
Sergunb	0:9dcf85d9b2f3	1283	reg_value = (reg_value \|
Sergunb	0:9dcf85d9b2f3	1284	((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
Sergunb	0:9dcf85d9b2f3	1285	(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
Sergunb	0:9dcf85d9b2f3	1286	SCB->AIRCR = reg_value;
Sergunb	0:9dcf85d9b2f3	1287	}
Sergunb	0:9dcf85d9b2f3	1288
Sergunb	0:9dcf85d9b2f3	1289
Sergunb	0:9dcf85d9b2f3	1290	/** \brief Get Priority Grouping
Sergunb	0:9dcf85d9b2f3	1291
Sergunb	0:9dcf85d9b2f3	1292	The function reads the priority grouping field from the NVIC Interrupt Controller.
Sergunb	0:9dcf85d9b2f3	1293
Sergunb	0:9dcf85d9b2f3	1294	\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
Sergunb	0:9dcf85d9b2f3	1295	*/
Sergunb	0:9dcf85d9b2f3	1296	__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
Sergunb	0:9dcf85d9b2f3	1297	{
Sergunb	0:9dcf85d9b2f3	1298	return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
Sergunb	0:9dcf85d9b2f3	1299	}
Sergunb	0:9dcf85d9b2f3	1300
Sergunb	0:9dcf85d9b2f3	1301
Sergunb	0:9dcf85d9b2f3	1302	/** \brief Enable External Interrupt
Sergunb	0:9dcf85d9b2f3	1303
Sergunb	0:9dcf85d9b2f3	1304	The function enables a device-specific interrupt in the NVIC interrupt controller.
Sergunb	0:9dcf85d9b2f3	1305
Sergunb	0:9dcf85d9b2f3	1306	\param [in] IRQn External interrupt number. Value cannot be negative.
Sergunb	0:9dcf85d9b2f3	1307	*/
Sergunb	0:9dcf85d9b2f3	1308	__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
Sergunb	0:9dcf85d9b2f3	1309	{
Sergunb	0:9dcf85d9b2f3	1310	NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
Sergunb	0:9dcf85d9b2f3	1311	}
Sergunb	0:9dcf85d9b2f3	1312
Sergunb	0:9dcf85d9b2f3	1313
Sergunb	0:9dcf85d9b2f3	1314	/** \brief Disable External Interrupt
Sergunb	0:9dcf85d9b2f3	1315
Sergunb	0:9dcf85d9b2f3	1316	The function disables a device-specific interrupt in the NVIC interrupt controller.
Sergunb	0:9dcf85d9b2f3	1317
Sergunb	0:9dcf85d9b2f3	1318	\param [in] IRQn External interrupt number. Value cannot be negative.
Sergunb	0:9dcf85d9b2f3	1319	*/
Sergunb	0:9dcf85d9b2f3	1320	__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
Sergunb	0:9dcf85d9b2f3	1321	{
Sergunb	0:9dcf85d9b2f3	1322	NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
Sergunb	0:9dcf85d9b2f3	1323	}
Sergunb	0:9dcf85d9b2f3	1324
Sergunb	0:9dcf85d9b2f3	1325
Sergunb	0:9dcf85d9b2f3	1326	/** \brief Get Pending Interrupt
Sergunb	0:9dcf85d9b2f3	1327
Sergunb	0:9dcf85d9b2f3	1328	The function reads the pending register in the NVIC and returns the pending bit
Sergunb	0:9dcf85d9b2f3	1329	for the specified interrupt.
Sergunb	0:9dcf85d9b2f3	1330
Sergunb	0:9dcf85d9b2f3	1331	\param [in] IRQn Interrupt number.
Sergunb	0:9dcf85d9b2f3	1332
Sergunb	0:9dcf85d9b2f3	1333	\return 0 Interrupt status is not pending.
Sergunb	0:9dcf85d9b2f3	1334	\return 1 Interrupt status is pending.
Sergunb	0:9dcf85d9b2f3	1335	*/
Sergunb	0:9dcf85d9b2f3	1336	__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
Sergunb	0:9dcf85d9b2f3	1337	{
Sergunb	0:9dcf85d9b2f3	1338	return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
Sergunb	0:9dcf85d9b2f3	1339	}
Sergunb	0:9dcf85d9b2f3	1340
Sergunb	0:9dcf85d9b2f3	1341
Sergunb	0:9dcf85d9b2f3	1342	/** \brief Set Pending Interrupt
Sergunb	0:9dcf85d9b2f3	1343
Sergunb	0:9dcf85d9b2f3	1344	The function sets the pending bit of an external interrupt.
Sergunb	0:9dcf85d9b2f3	1345
Sergunb	0:9dcf85d9b2f3	1346	\param [in] IRQn Interrupt number. Value cannot be negative.
Sergunb	0:9dcf85d9b2f3	1347	*/
Sergunb	0:9dcf85d9b2f3	1348	__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
Sergunb	0:9dcf85d9b2f3	1349	{
Sergunb	0:9dcf85d9b2f3	1350	NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
Sergunb	0:9dcf85d9b2f3	1351	}
Sergunb	0:9dcf85d9b2f3	1352
Sergunb	0:9dcf85d9b2f3	1353
Sergunb	0:9dcf85d9b2f3	1354	/** \brief Clear Pending Interrupt
Sergunb	0:9dcf85d9b2f3	1355
Sergunb	0:9dcf85d9b2f3	1356	The function clears the pending bit of an external interrupt.
Sergunb	0:9dcf85d9b2f3	1357
Sergunb	0:9dcf85d9b2f3	1358	\param [in] IRQn External interrupt number. Value cannot be negative.
Sergunb	0:9dcf85d9b2f3	1359	*/
Sergunb	0:9dcf85d9b2f3	1360	__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
Sergunb	0:9dcf85d9b2f3	1361	{
Sergunb	0:9dcf85d9b2f3	1362	NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
Sergunb	0:9dcf85d9b2f3	1363	}
Sergunb	0:9dcf85d9b2f3	1364
Sergunb	0:9dcf85d9b2f3	1365
Sergunb	0:9dcf85d9b2f3	1366	/** \brief Get Active Interrupt
Sergunb	0:9dcf85d9b2f3	1367
Sergunb	0:9dcf85d9b2f3	1368	The function reads the active register in NVIC and returns the active bit.
Sergunb	0:9dcf85d9b2f3	1369
Sergunb	0:9dcf85d9b2f3	1370	\param [in] IRQn Interrupt number.
Sergunb	0:9dcf85d9b2f3	1371
Sergunb	0:9dcf85d9b2f3	1372	\return 0 Interrupt status is not active.
Sergunb	0:9dcf85d9b2f3	1373	\return 1 Interrupt status is active.
Sergunb	0:9dcf85d9b2f3	1374	*/
Sergunb	0:9dcf85d9b2f3	1375	__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
Sergunb	0:9dcf85d9b2f3	1376	{
Sergunb	0:9dcf85d9b2f3	1377	return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
Sergunb	0:9dcf85d9b2f3	1378	}
Sergunb	0:9dcf85d9b2f3	1379
Sergunb	0:9dcf85d9b2f3	1380
Sergunb	0:9dcf85d9b2f3	1381	/** \brief Set Interrupt Priority
Sergunb	0:9dcf85d9b2f3	1382
Sergunb	0:9dcf85d9b2f3	1383	The function sets the priority of an interrupt.
Sergunb	0:9dcf85d9b2f3	1384
Sergunb	0:9dcf85d9b2f3	1385	\note The priority cannot be set for every core interrupt.
Sergunb	0:9dcf85d9b2f3	1386
Sergunb	0:9dcf85d9b2f3	1387	\param [in] IRQn Interrupt number.
Sergunb	0:9dcf85d9b2f3	1388	\param [in] priority Priority to set.
Sergunb	0:9dcf85d9b2f3	1389	*/
Sergunb	0:9dcf85d9b2f3	1390	__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
Sergunb	0:9dcf85d9b2f3	1391	{
Sergunb	0:9dcf85d9b2f3	1392	if(IRQn < 0) {
Sergunb	0:9dcf85d9b2f3	1393	SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
Sergunb	0:9dcf85d9b2f3	1394	else {
Sergunb	0:9dcf85d9b2f3	1395	NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
Sergunb	0:9dcf85d9b2f3	1396	}
Sergunb	0:9dcf85d9b2f3	1397
Sergunb	0:9dcf85d9b2f3	1398
Sergunb	0:9dcf85d9b2f3	1399	/** \brief Get Interrupt Priority
Sergunb	0:9dcf85d9b2f3	1400
Sergunb	0:9dcf85d9b2f3	1401	The function reads the priority of an interrupt. The interrupt
Sergunb	0:9dcf85d9b2f3	1402	number can be positive to specify an external (device specific)
Sergunb	0:9dcf85d9b2f3	1403	interrupt, or negative to specify an internal (core) interrupt.
Sergunb	0:9dcf85d9b2f3	1404
Sergunb	0:9dcf85d9b2f3	1405
Sergunb	0:9dcf85d9b2f3	1406	\param [in] IRQn Interrupt number.
Sergunb	0:9dcf85d9b2f3	1407	\return Interrupt Priority. Value is aligned automatically to the implemented
Sergunb	0:9dcf85d9b2f3	1408	priority bits of the microcontroller.
Sergunb	0:9dcf85d9b2f3	1409	*/
Sergunb	0:9dcf85d9b2f3	1410	__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
Sergunb	0:9dcf85d9b2f3	1411	{
Sergunb	0:9dcf85d9b2f3	1412
Sergunb	0:9dcf85d9b2f3	1413	if(IRQn < 0) {
Sergunb	0:9dcf85d9b2f3	1414	return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
Sergunb	0:9dcf85d9b2f3	1415	else {
Sergunb	0:9dcf85d9b2f3	1416	return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
Sergunb	0:9dcf85d9b2f3	1417	}
Sergunb	0:9dcf85d9b2f3	1418
Sergunb	0:9dcf85d9b2f3	1419
Sergunb	0:9dcf85d9b2f3	1420	/** \brief Encode Priority
Sergunb	0:9dcf85d9b2f3	1421
Sergunb	0:9dcf85d9b2f3	1422	The function encodes the priority for an interrupt with the given priority group,
Sergunb	0:9dcf85d9b2f3	1423	preemptive priority value, and subpriority value.
Sergunb	0:9dcf85d9b2f3	1424	In case of a conflict between priority grouping and available
Sergunb	0:9dcf85d9b2f3	1425	priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
Sergunb	0:9dcf85d9b2f3	1426
Sergunb	0:9dcf85d9b2f3	1427	\param [in] PriorityGroup Used priority group.
Sergunb	0:9dcf85d9b2f3	1428	\param [in] PreemptPriority Preemptive priority value (starting from 0).
Sergunb	0:9dcf85d9b2f3	1429	\param [in] SubPriority Subpriority value (starting from 0).
Sergunb	0:9dcf85d9b2f3	1430	\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
Sergunb	0:9dcf85d9b2f3	1431	*/
Sergunb	0:9dcf85d9b2f3	1432	__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
Sergunb	0:9dcf85d9b2f3	1433	{
Sergunb	0:9dcf85d9b2f3	1434	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Sergunb	0:9dcf85d9b2f3	1435	uint32_t PreemptPriorityBits;
Sergunb	0:9dcf85d9b2f3	1436	uint32_t SubPriorityBits;
Sergunb	0:9dcf85d9b2f3	1437
Sergunb	0:9dcf85d9b2f3	1438	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Sergunb	0:9dcf85d9b2f3	1439	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Sergunb	0:9dcf85d9b2f3	1440
Sergunb	0:9dcf85d9b2f3	1441	return (
Sergunb	0:9dcf85d9b2f3	1442	((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) \|
Sergunb	0:9dcf85d9b2f3	1443	((SubPriority & ((1 << (SubPriorityBits )) - 1)))
Sergunb	0:9dcf85d9b2f3	1444	);
Sergunb	0:9dcf85d9b2f3	1445	}
Sergunb	0:9dcf85d9b2f3	1446
Sergunb	0:9dcf85d9b2f3	1447
Sergunb	0:9dcf85d9b2f3	1448	/** \brief Decode Priority
Sergunb	0:9dcf85d9b2f3	1449
Sergunb	0:9dcf85d9b2f3	1450	The function decodes an interrupt priority value with a given priority group to
Sergunb	0:9dcf85d9b2f3	1451	preemptive priority value and subpriority value.
Sergunb	0:9dcf85d9b2f3	1452	In case of a conflict between priority grouping and available
Sergunb	0:9dcf85d9b2f3	1453	priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
Sergunb	0:9dcf85d9b2f3	1454
Sergunb	0:9dcf85d9b2f3	1455	\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
Sergunb	0:9dcf85d9b2f3	1456	\param [in] PriorityGroup Used priority group.
Sergunb	0:9dcf85d9b2f3	1457	\param [out] pPreemptPriority Preemptive priority value (starting from 0).
Sergunb	0:9dcf85d9b2f3	1458	\param [out] pSubPriority Subpriority value (starting from 0).
Sergunb	0:9dcf85d9b2f3	1459	*/
Sergunb	0:9dcf85d9b2f3	1460	__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
Sergunb	0:9dcf85d9b2f3	1461	{
Sergunb	0:9dcf85d9b2f3	1462	uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
Sergunb	0:9dcf85d9b2f3	1463	uint32_t PreemptPriorityBits;
Sergunb	0:9dcf85d9b2f3	1464	uint32_t SubPriorityBits;
Sergunb	0:9dcf85d9b2f3	1465
Sergunb	0:9dcf85d9b2f3	1466	PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
Sergunb	0:9dcf85d9b2f3	1467	SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
Sergunb	0:9dcf85d9b2f3	1468
Sergunb	0:9dcf85d9b2f3	1469	*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
Sergunb	0:9dcf85d9b2f3	1470	*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
Sergunb	0:9dcf85d9b2f3	1471	}
Sergunb	0:9dcf85d9b2f3	1472
Sergunb	0:9dcf85d9b2f3	1473
Sergunb	0:9dcf85d9b2f3	1474	/** \brief System Reset
Sergunb	0:9dcf85d9b2f3	1475
Sergunb	0:9dcf85d9b2f3	1476	The function initiates a system reset request to reset the MCU.
Sergunb	0:9dcf85d9b2f3	1477	*/
Sergunb	0:9dcf85d9b2f3	1478	__STATIC_INLINE void NVIC_SystemReset(void)
Sergunb	0:9dcf85d9b2f3	1479	{
Sergunb	0:9dcf85d9b2f3	1480	__DSB(); /* Ensure all outstanding memory accesses included
Sergunb	0:9dcf85d9b2f3	1481	buffered write are completed before reset */
Sergunb	0:9dcf85d9b2f3	1482	SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) \|
Sergunb	0:9dcf85d9b2f3	1483	(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) \|
Sergunb	0:9dcf85d9b2f3	1484	SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
Sergunb	0:9dcf85d9b2f3	1485	__DSB(); /* Ensure completion of memory access */
Sergunb	0:9dcf85d9b2f3	1486	while(1); /* wait until reset */
Sergunb	0:9dcf85d9b2f3	1487	}
Sergunb	0:9dcf85d9b2f3	1488
Sergunb	0:9dcf85d9b2f3	1489	/@} end of CMSIS_Core_NVICFunctions /
Sergunb	0:9dcf85d9b2f3	1490
Sergunb	0:9dcf85d9b2f3	1491
Sergunb	0:9dcf85d9b2f3	1492
Sergunb	0:9dcf85d9b2f3	1493	/* ################################## SysTick function ############################################ */
Sergunb	0:9dcf85d9b2f3	1494	/** \ingroup CMSIS_Core_FunctionInterface
Sergunb	0:9dcf85d9b2f3	1495	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
Sergunb	0:9dcf85d9b2f3	1496	\brief Functions that configure the System.
Sergunb	0:9dcf85d9b2f3	1497	@{
Sergunb	0:9dcf85d9b2f3	1498	*/
Sergunb	0:9dcf85d9b2f3	1499
Sergunb	0:9dcf85d9b2f3	1500	#if (__Vendor_SysTickConfig == 0)
Sergunb	0:9dcf85d9b2f3	1501
Sergunb	0:9dcf85d9b2f3	1502	/** \brief System Tick Configuration
Sergunb	0:9dcf85d9b2f3	1503
Sergunb	0:9dcf85d9b2f3	1504	The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
Sergunb	0:9dcf85d9b2f3	1505	Counter is in free running mode to generate periodic interrupts.
Sergunb	0:9dcf85d9b2f3	1506
Sergunb	0:9dcf85d9b2f3	1507	\param [in] ticks Number of ticks between two interrupts.
Sergunb	0:9dcf85d9b2f3	1508
Sergunb	0:9dcf85d9b2f3	1509	\return 0 Function succeeded.
Sergunb	0:9dcf85d9b2f3	1510	\return 1 Function failed.
Sergunb	0:9dcf85d9b2f3	1511
Sergunb	0:9dcf85d9b2f3	1512	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
Sergunb	0:9dcf85d9b2f3	1513	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
Sergunb	0:9dcf85d9b2f3	1514	must contain a vendor-specific implementation of this function.
Sergunb	0:9dcf85d9b2f3	1515
Sergunb	0:9dcf85d9b2f3	1516	*/
Sergunb	0:9dcf85d9b2f3	1517	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
Sergunb	0:9dcf85d9b2f3	1518	{
Sergunb	0:9dcf85d9b2f3	1519	if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
Sergunb	0:9dcf85d9b2f3	1520
Sergunb	0:9dcf85d9b2f3	1521	SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
Sergunb	0:9dcf85d9b2f3	1522	NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
Sergunb	0:9dcf85d9b2f3	1523	SysTick->VAL = 0; /* Load the SysTick Counter Value */
Sergunb	0:9dcf85d9b2f3	1524	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
Sergunb	0:9dcf85d9b2f3	1525	SysTick_CTRL_TICKINT_Msk \|
Sergunb	0:9dcf85d9b2f3	1526	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Sergunb	0:9dcf85d9b2f3	1527	return (0); /* Function successful */
Sergunb	0:9dcf85d9b2f3	1528	}
Sergunb	0:9dcf85d9b2f3	1529
Sergunb	0:9dcf85d9b2f3	1530	#endif
Sergunb	0:9dcf85d9b2f3	1531
Sergunb	0:9dcf85d9b2f3	1532	/@} end of CMSIS_Core_SysTickFunctions /
Sergunb	0:9dcf85d9b2f3	1533
Sergunb	0:9dcf85d9b2f3	1534
Sergunb	0:9dcf85d9b2f3	1535
Sergunb	0:9dcf85d9b2f3	1536	/* ##################################### Debug In/Output function ########################################### */
Sergunb	0:9dcf85d9b2f3	1537	/** \ingroup CMSIS_Core_FunctionInterface
Sergunb	0:9dcf85d9b2f3	1538	\defgroup CMSIS_core_DebugFunctions ITM Functions
Sergunb	0:9dcf85d9b2f3	1539	\brief Functions that access the ITM debug interface.
Sergunb	0:9dcf85d9b2f3	1540	@{
Sergunb	0:9dcf85d9b2f3	1541	*/
Sergunb	0:9dcf85d9b2f3	1542
Sergunb	0:9dcf85d9b2f3	1543	extern volatile int32_t ITM_RxBuffer; /!< External variable to receive characters. /
Sergunb	0:9dcf85d9b2f3	1544	#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /!< Value identifying \ref ITM_RxBuffer is ready for next character. /
Sergunb	0:9dcf85d9b2f3	1545
Sergunb	0:9dcf85d9b2f3	1546
Sergunb	0:9dcf85d9b2f3	1547	/** \brief ITM Send Character
Sergunb	0:9dcf85d9b2f3	1548
Sergunb	0:9dcf85d9b2f3	1549	The function transmits a character via the ITM channel 0, and
Sergunb	0:9dcf85d9b2f3	1550	\li Just returns when no debugger is connected that has booked the output.
Sergunb	0:9dcf85d9b2f3	1551	\li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
Sergunb	0:9dcf85d9b2f3	1552
Sergunb	0:9dcf85d9b2f3	1553	\param [in] ch Character to transmit.
Sergunb	0:9dcf85d9b2f3	1554
Sergunb	0:9dcf85d9b2f3	1555	\returns Character to transmit.
Sergunb	0:9dcf85d9b2f3	1556	*/
Sergunb	0:9dcf85d9b2f3	1557	__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
Sergunb	0:9dcf85d9b2f3	1558	{
Sergunb	0:9dcf85d9b2f3	1559	if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
Sergunb	0:9dcf85d9b2f3	1560	(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
Sergunb	0:9dcf85d9b2f3	1561	{
Sergunb	0:9dcf85d9b2f3	1562	while (ITM->PORT[0].u32 == 0);
Sergunb	0:9dcf85d9b2f3	1563	ITM->PORT[0].u8 = (uint8_t) ch;
Sergunb	0:9dcf85d9b2f3	1564	}
Sergunb	0:9dcf85d9b2f3	1565	return (ch);
Sergunb	0:9dcf85d9b2f3	1566	}
Sergunb	0:9dcf85d9b2f3	1567
Sergunb	0:9dcf85d9b2f3	1568
Sergunb	0:9dcf85d9b2f3	1569	/** \brief ITM Receive Character
Sergunb	0:9dcf85d9b2f3	1570
Sergunb	0:9dcf85d9b2f3	1571	The function inputs a character via the external variable \ref ITM_RxBuffer.
Sergunb	0:9dcf85d9b2f3	1572
Sergunb	0:9dcf85d9b2f3	1573	\return Received character.
Sergunb	0:9dcf85d9b2f3	1574	\return -1 No character pending.
Sergunb	0:9dcf85d9b2f3	1575	*/
Sergunb	0:9dcf85d9b2f3	1576	__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
Sergunb	0:9dcf85d9b2f3	1577	int32_t ch = -1; /* no character available */
Sergunb	0:9dcf85d9b2f3	1578
Sergunb	0:9dcf85d9b2f3	1579	if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
Sergunb	0:9dcf85d9b2f3	1580	ch = ITM_RxBuffer;
Sergunb	0:9dcf85d9b2f3	1581	ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
Sergunb	0:9dcf85d9b2f3	1582	}
Sergunb	0:9dcf85d9b2f3	1583
Sergunb	0:9dcf85d9b2f3	1584	return (ch);
Sergunb	0:9dcf85d9b2f3	1585	}
Sergunb	0:9dcf85d9b2f3	1586
Sergunb	0:9dcf85d9b2f3	1587
Sergunb	0:9dcf85d9b2f3	1588	/** \brief ITM Check Character
Sergunb	0:9dcf85d9b2f3	1589
Sergunb	0:9dcf85d9b2f3	1590	The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
Sergunb	0:9dcf85d9b2f3	1591
Sergunb	0:9dcf85d9b2f3	1592	\return 0 No character available.
Sergunb	0:9dcf85d9b2f3	1593	\return 1 Character available.
Sergunb	0:9dcf85d9b2f3	1594	*/
Sergunb	0:9dcf85d9b2f3	1595	__STATIC_INLINE int32_t ITM_CheckChar (void) {
Sergunb	0:9dcf85d9b2f3	1596
Sergunb	0:9dcf85d9b2f3	1597	if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
Sergunb	0:9dcf85d9b2f3	1598	return (0); /* no character available */
Sergunb	0:9dcf85d9b2f3	1599	} else {
Sergunb	0:9dcf85d9b2f3	1600	return (1); /* character available */
Sergunb	0:9dcf85d9b2f3	1601	}
Sergunb	0:9dcf85d9b2f3	1602	}
Sergunb	0:9dcf85d9b2f3	1603
Sergunb	0:9dcf85d9b2f3	1604	/@} end of CMSIS_core_DebugFunctions /
Sergunb	0:9dcf85d9b2f3	1605
Sergunb	0:9dcf85d9b2f3	1606	#endif /* __CORE_CM3_H_DEPENDANT */
Sergunb	0:9dcf85d9b2f3	1607
Sergunb	0:9dcf85d9b2f3	1608	#endif /* __CMSIS_GENERIC */
Sergunb	0:9dcf85d9b2f3	1609
Sergunb	0:9dcf85d9b2f3	1610	#ifdef __cplusplus
Sergunb	0:9dcf85d9b2f3	1611	}
Sergunb	0:9dcf85d9b2f3	1612	#endif

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Type:	Program
Created:	04 Sep 2017
Imports:	13
Forks:	0
Commits:	1
Dependents:	0
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Followers:	1

cmsis/core_cm3.h@0:9dcf85d9b2f3, 2017-09-04 (annotated)

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