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stm32f10x_tim.c
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f10x_tim.c 00004 * @author MCD Application Team 00005 * @version V3.5.0 00006 * @date 11-March-2011 00007 * @brief This file provides all the TIM firmware functions. 00008 ****************************************************************************** 00009 * @attention 00010 * 00011 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00012 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00013 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00014 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00015 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00016 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00017 * 00018 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00019 ****************************************************************************** 00020 */ 00021 00022 /* Includes ------------------------------------------------------------------*/ 00023 #include "stm32f10x_tim.h" 00024 #include "stm32f10x_rcc.h" 00025 00026 /** @addtogroup STM32F10x_StdPeriph_Driver 00027 * @{ 00028 */ 00029 00030 /** @defgroup TIM 00031 * @brief TIM driver modules 00032 * @{ 00033 */ 00034 00035 /** @defgroup TIM_Private_TypesDefinitions 00036 * @{ 00037 */ 00038 00039 /** 00040 * @} 00041 */ 00042 00043 /** @defgroup TIM_Private_Defines 00044 * @{ 00045 */ 00046 00047 /* ---------------------- TIM registers bit mask ------------------------ */ 00048 #define SMCR_ETR_Mask ((uint16_t)0x00FF) 00049 #define CCMR_Offset ((uint16_t)0x0018) 00050 #define CCER_CCE_Set ((uint16_t)0x0001) 00051 #define CCER_CCNE_Set ((uint16_t)0x0004) 00052 00053 /** 00054 * @} 00055 */ 00056 00057 /** @defgroup TIM_Private_Macros 00058 * @{ 00059 */ 00060 00061 /** 00062 * @} 00063 */ 00064 00065 /** @defgroup TIM_Private_Variables 00066 * @{ 00067 */ 00068 00069 /** 00070 * @} 00071 */ 00072 00073 /** @defgroup TIM_Private_FunctionPrototypes 00074 * @{ 00075 */ 00076 00077 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00078 uint16_t TIM_ICFilter); 00079 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00080 uint16_t TIM_ICFilter); 00081 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00082 uint16_t TIM_ICFilter); 00083 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 00084 uint16_t TIM_ICFilter); 00085 /** 00086 * @} 00087 */ 00088 00089 /** @defgroup TIM_Private_Macros 00090 * @{ 00091 */ 00092 00093 /** 00094 * @} 00095 */ 00096 00097 /** @defgroup TIM_Private_Variables 00098 * @{ 00099 */ 00100 00101 /** 00102 * @} 00103 */ 00104 00105 /** @defgroup TIM_Private_FunctionPrototypes 00106 * @{ 00107 */ 00108 00109 /** 00110 * @} 00111 */ 00112 00113 /** @defgroup TIM_Private_Functions 00114 * @{ 00115 */ 00116 00117 /** 00118 * @brief Deinitializes the TIMx peripheral registers to their default reset values. 00119 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 00120 * @retval None 00121 */ 00122 void TIM_DeInit(TIM_TypeDef* TIMx) 00123 { 00124 /* Check the parameters */ 00125 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00126 00127 if (TIMx == TIM1) 00128 { 00129 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); 00130 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); 00131 } 00132 else if (TIMx == TIM2) 00133 { 00134 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); 00135 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); 00136 } 00137 else if (TIMx == TIM3) 00138 { 00139 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); 00140 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); 00141 } 00142 else if (TIMx == TIM4) 00143 { 00144 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); 00145 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); 00146 } 00147 else if (TIMx == TIM5) 00148 { 00149 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); 00150 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); 00151 } 00152 else if (TIMx == TIM6) 00153 { 00154 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); 00155 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); 00156 } 00157 else if (TIMx == TIM7) 00158 { 00159 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); 00160 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); 00161 } 00162 else if (TIMx == TIM8) 00163 { 00164 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); 00165 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); 00166 } 00167 else if (TIMx == TIM9) 00168 { 00169 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); 00170 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); 00171 } 00172 else if (TIMx == TIM10) 00173 { 00174 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); 00175 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); 00176 } 00177 else if (TIMx == TIM11) 00178 { 00179 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE); 00180 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE); 00181 } 00182 else if (TIMx == TIM12) 00183 { 00184 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE); 00185 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE); 00186 } 00187 else if (TIMx == TIM13) 00188 { 00189 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE); 00190 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE); 00191 } 00192 else if (TIMx == TIM14) 00193 { 00194 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE); 00195 RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); 00196 } 00197 else if (TIMx == TIM15) 00198 { 00199 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE); 00200 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE); 00201 } 00202 else if (TIMx == TIM16) 00203 { 00204 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE); 00205 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE); 00206 } 00207 else 00208 { 00209 if (TIMx == TIM17) 00210 { 00211 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE); 00212 RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE); 00213 } 00214 } 00215 } 00216 00217 /** 00218 * @brief Initializes the TIMx Time Base Unit peripheral according to 00219 * the specified parameters in the TIM_TimeBaseInitStruct. 00220 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 00221 * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef 00222 * structure that contains the configuration information for the 00223 * specified TIM peripheral. 00224 * @retval None 00225 */ 00226 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) 00227 { 00228 uint16_t tmpcr1 = 0; 00229 00230 /* Check the parameters */ 00231 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00232 assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode)); 00233 assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision)); 00234 00235 tmpcr1 = TIMx->CR1; 00236 00237 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)|| 00238 (TIMx == TIM4) || (TIMx == TIM5)) 00239 { 00240 /* Select the Counter Mode */ 00241 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); 00242 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; 00243 } 00244 00245 if((TIMx != TIM6) && (TIMx != TIM7)) 00246 { 00247 /* Set the clock division */ 00248 tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD)); 00249 tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; 00250 } 00251 00252 TIMx->CR1 = tmpcr1; 00253 00254 /* Set the Autoreload value */ 00255 TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ; 00256 00257 /* Set the Prescaler value */ 00258 TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; 00259 00260 if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17)) 00261 { 00262 /* Set the Repetition Counter value */ 00263 TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; 00264 } 00265 00266 /* Generate an update event to reload the Prescaler and the Repetition counter 00267 values immediately */ 00268 TIMx->EGR = TIM_PSCReloadMode_Immediate; 00269 } 00270 00271 /** 00272 * @brief Initializes the TIMx Channel1 according to the specified 00273 * parameters in the TIM_OCInitStruct. 00274 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 00275 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure 00276 * that contains the configuration information for the specified TIM peripheral. 00277 * @retval None 00278 */ 00279 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 00280 { 00281 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00282 00283 /* Check the parameters */ 00284 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 00285 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 00286 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00287 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00288 /* Disable the Channel 1: Reset the CC1E Bit */ 00289 TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E); 00290 /* Get the TIMx CCER register value */ 00291 tmpccer = TIMx->CCER; 00292 /* Get the TIMx CR2 register value */ 00293 tmpcr2 = TIMx->CR2; 00294 00295 /* Get the TIMx CCMR1 register value */ 00296 tmpccmrx = TIMx->CCMR1; 00297 00298 /* Reset the Output Compare Mode Bits */ 00299 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M)); 00300 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S)); 00301 00302 /* Select the Output Compare Mode */ 00303 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; 00304 00305 /* Reset the Output Polarity level */ 00306 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P)); 00307 /* Set the Output Compare Polarity */ 00308 tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; 00309 00310 /* Set the Output State */ 00311 tmpccer |= TIM_OCInitStruct->TIM_OutputState; 00312 00313 if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| 00314 (TIMx == TIM16)|| (TIMx == TIM17)) 00315 { 00316 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); 00317 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); 00318 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); 00319 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 00320 00321 /* Reset the Output N Polarity level */ 00322 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP)); 00323 /* Set the Output N Polarity */ 00324 tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; 00325 00326 /* Reset the Output N State */ 00327 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE)); 00328 /* Set the Output N State */ 00329 tmpccer |= TIM_OCInitStruct->TIM_OutputNState; 00330 00331 /* Reset the Output Compare and Output Compare N IDLE State */ 00332 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1)); 00333 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N)); 00334 00335 /* Set the Output Idle state */ 00336 tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; 00337 /* Set the Output N Idle state */ 00338 tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; 00339 } 00340 /* Write to TIMx CR2 */ 00341 TIMx->CR2 = tmpcr2; 00342 00343 /* Write to TIMx CCMR1 */ 00344 TIMx->CCMR1 = tmpccmrx; 00345 00346 /* Set the Capture Compare Register value */ 00347 TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse; 00348 00349 /* Write to TIMx CCER */ 00350 TIMx->CCER = tmpccer; 00351 } 00352 00353 /** 00354 * @brief Initializes the TIMx Channel2 according to the specified 00355 * parameters in the TIM_OCInitStruct. 00356 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 00357 * the TIM peripheral. 00358 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure 00359 * that contains the configuration information for the specified TIM peripheral. 00360 * @retval None 00361 */ 00362 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 00363 { 00364 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00365 00366 /* Check the parameters */ 00367 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 00368 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 00369 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00370 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00371 /* Disable the Channel 2: Reset the CC2E Bit */ 00372 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E)); 00373 00374 /* Get the TIMx CCER register value */ 00375 tmpccer = TIMx->CCER; 00376 /* Get the TIMx CR2 register value */ 00377 tmpcr2 = TIMx->CR2; 00378 00379 /* Get the TIMx CCMR1 register value */ 00380 tmpccmrx = TIMx->CCMR1; 00381 00382 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 00383 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M)); 00384 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)); 00385 00386 /* Select the Output Compare Mode */ 00387 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); 00388 00389 /* Reset the Output Polarity level */ 00390 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P)); 00391 /* Set the Output Compare Polarity */ 00392 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); 00393 00394 /* Set the Output State */ 00395 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); 00396 00397 if((TIMx == TIM1) || (TIMx == TIM8)) 00398 { 00399 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); 00400 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); 00401 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); 00402 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 00403 00404 /* Reset the Output N Polarity level */ 00405 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP)); 00406 /* Set the Output N Polarity */ 00407 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); 00408 00409 /* Reset the Output N State */ 00410 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE)); 00411 /* Set the Output N State */ 00412 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); 00413 00414 /* Reset the Output Compare and Output Compare N IDLE State */ 00415 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2)); 00416 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N)); 00417 00418 /* Set the Output Idle state */ 00419 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); 00420 /* Set the Output N Idle state */ 00421 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); 00422 } 00423 /* Write to TIMx CR2 */ 00424 TIMx->CR2 = tmpcr2; 00425 00426 /* Write to TIMx CCMR1 */ 00427 TIMx->CCMR1 = tmpccmrx; 00428 00429 /* Set the Capture Compare Register value */ 00430 TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse; 00431 00432 /* Write to TIMx CCER */ 00433 TIMx->CCER = tmpccer; 00434 } 00435 00436 /** 00437 * @brief Initializes the TIMx Channel3 according to the specified 00438 * parameters in the TIM_OCInitStruct. 00439 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 00440 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure 00441 * that contains the configuration information for the specified TIM peripheral. 00442 * @retval None 00443 */ 00444 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 00445 { 00446 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00447 00448 /* Check the parameters */ 00449 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 00450 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 00451 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00452 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00453 /* Disable the Channel 2: Reset the CC2E Bit */ 00454 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E)); 00455 00456 /* Get the TIMx CCER register value */ 00457 tmpccer = TIMx->CCER; 00458 /* Get the TIMx CR2 register value */ 00459 tmpcr2 = TIMx->CR2; 00460 00461 /* Get the TIMx CCMR2 register value */ 00462 tmpccmrx = TIMx->CCMR2; 00463 00464 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 00465 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M)); 00466 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S)); 00467 /* Select the Output Compare Mode */ 00468 tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; 00469 00470 /* Reset the Output Polarity level */ 00471 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P)); 00472 /* Set the Output Compare Polarity */ 00473 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); 00474 00475 /* Set the Output State */ 00476 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); 00477 00478 if((TIMx == TIM1) || (TIMx == TIM8)) 00479 { 00480 assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState)); 00481 assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity)); 00482 assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState)); 00483 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 00484 00485 /* Reset the Output N Polarity level */ 00486 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP)); 00487 /* Set the Output N Polarity */ 00488 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); 00489 /* Reset the Output N State */ 00490 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE)); 00491 00492 /* Set the Output N State */ 00493 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); 00494 /* Reset the Output Compare and Output Compare N IDLE State */ 00495 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3)); 00496 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N)); 00497 /* Set the Output Idle state */ 00498 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); 00499 /* Set the Output N Idle state */ 00500 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); 00501 } 00502 /* Write to TIMx CR2 */ 00503 TIMx->CR2 = tmpcr2; 00504 00505 /* Write to TIMx CCMR2 */ 00506 TIMx->CCMR2 = tmpccmrx; 00507 00508 /* Set the Capture Compare Register value */ 00509 TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse; 00510 00511 /* Write to TIMx CCER */ 00512 TIMx->CCER = tmpccer; 00513 } 00514 00515 /** 00516 * @brief Initializes the TIMx Channel4 according to the specified 00517 * parameters in the TIM_OCInitStruct. 00518 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 00519 * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure 00520 * that contains the configuration information for the specified TIM peripheral. 00521 * @retval None 00522 */ 00523 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct) 00524 { 00525 uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; 00526 00527 /* Check the parameters */ 00528 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 00529 assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode)); 00530 assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState)); 00531 assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity)); 00532 /* Disable the Channel 2: Reset the CC4E Bit */ 00533 TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E)); 00534 00535 /* Get the TIMx CCER register value */ 00536 tmpccer = TIMx->CCER; 00537 /* Get the TIMx CR2 register value */ 00538 tmpcr2 = TIMx->CR2; 00539 00540 /* Get the TIMx CCMR2 register value */ 00541 tmpccmrx = TIMx->CCMR2; 00542 00543 /* Reset the Output Compare mode and Capture/Compare selection Bits */ 00544 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M)); 00545 tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S)); 00546 00547 /* Select the Output Compare Mode */ 00548 tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); 00549 00550 /* Reset the Output Polarity level */ 00551 tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P)); 00552 /* Set the Output Compare Polarity */ 00553 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); 00554 00555 /* Set the Output State */ 00556 tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); 00557 00558 if((TIMx == TIM1) || (TIMx == TIM8)) 00559 { 00560 assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState)); 00561 /* Reset the Output Compare IDLE State */ 00562 tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4)); 00563 /* Set the Output Idle state */ 00564 tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); 00565 } 00566 /* Write to TIMx CR2 */ 00567 TIMx->CR2 = tmpcr2; 00568 00569 /* Write to TIMx CCMR2 */ 00570 TIMx->CCMR2 = tmpccmrx; 00571 00572 /* Set the Capture Compare Register value */ 00573 TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse; 00574 00575 /* Write to TIMx CCER */ 00576 TIMx->CCER = tmpccer; 00577 } 00578 00579 /** 00580 * @brief Initializes the TIM peripheral according to the specified 00581 * parameters in the TIM_ICInitStruct. 00582 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 00583 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure 00584 * that contains the configuration information for the specified TIM peripheral. 00585 * @retval None 00586 */ 00587 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) 00588 { 00589 /* Check the parameters */ 00590 assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel)); 00591 assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection)); 00592 assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler)); 00593 assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter)); 00594 00595 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 00596 (TIMx == TIM4) ||(TIMx == TIM5)) 00597 { 00598 assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity)); 00599 } 00600 else 00601 { 00602 assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity)); 00603 } 00604 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) 00605 { 00606 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 00607 /* TI1 Configuration */ 00608 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 00609 TIM_ICInitStruct->TIM_ICSelection, 00610 TIM_ICInitStruct->TIM_ICFilter); 00611 /* Set the Input Capture Prescaler value */ 00612 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 00613 } 00614 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) 00615 { 00616 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 00617 /* TI2 Configuration */ 00618 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 00619 TIM_ICInitStruct->TIM_ICSelection, 00620 TIM_ICInitStruct->TIM_ICFilter); 00621 /* Set the Input Capture Prescaler value */ 00622 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 00623 } 00624 else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) 00625 { 00626 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 00627 /* TI3 Configuration */ 00628 TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 00629 TIM_ICInitStruct->TIM_ICSelection, 00630 TIM_ICInitStruct->TIM_ICFilter); 00631 /* Set the Input Capture Prescaler value */ 00632 TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 00633 } 00634 else 00635 { 00636 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 00637 /* TI4 Configuration */ 00638 TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, 00639 TIM_ICInitStruct->TIM_ICSelection, 00640 TIM_ICInitStruct->TIM_ICFilter); 00641 /* Set the Input Capture Prescaler value */ 00642 TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 00643 } 00644 } 00645 00646 /** 00647 * @brief Configures the TIM peripheral according to the specified 00648 * parameters in the TIM_ICInitStruct to measure an external PWM signal. 00649 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 00650 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure 00651 * that contains the configuration information for the specified TIM peripheral. 00652 * @retval None 00653 */ 00654 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct) 00655 { 00656 uint16_t icoppositepolarity = TIM_ICPolarity_Rising; 00657 uint16_t icoppositeselection = TIM_ICSelection_DirectTI; 00658 /* Check the parameters */ 00659 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 00660 /* Select the Opposite Input Polarity */ 00661 if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) 00662 { 00663 icoppositepolarity = TIM_ICPolarity_Falling; 00664 } 00665 else 00666 { 00667 icoppositepolarity = TIM_ICPolarity_Rising; 00668 } 00669 /* Select the Opposite Input */ 00670 if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) 00671 { 00672 icoppositeselection = TIM_ICSelection_IndirectTI; 00673 } 00674 else 00675 { 00676 icoppositeselection = TIM_ICSelection_DirectTI; 00677 } 00678 if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) 00679 { 00680 /* TI1 Configuration */ 00681 TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, 00682 TIM_ICInitStruct->TIM_ICFilter); 00683 /* Set the Input Capture Prescaler value */ 00684 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 00685 /* TI2 Configuration */ 00686 TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); 00687 /* Set the Input Capture Prescaler value */ 00688 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 00689 } 00690 else 00691 { 00692 /* TI2 Configuration */ 00693 TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, 00694 TIM_ICInitStruct->TIM_ICFilter); 00695 /* Set the Input Capture Prescaler value */ 00696 TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 00697 /* TI1 Configuration */ 00698 TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); 00699 /* Set the Input Capture Prescaler value */ 00700 TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); 00701 } 00702 } 00703 00704 /** 00705 * @brief Configures the: Break feature, dead time, Lock level, the OSSI, 00706 * the OSSR State and the AOE(automatic output enable). 00707 * @param TIMx: where x can be 1 or 8 to select the TIM 00708 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that 00709 * contains the BDTR Register configuration information for the TIM peripheral. 00710 * @retval None 00711 */ 00712 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) 00713 { 00714 /* Check the parameters */ 00715 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 00716 assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState)); 00717 assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState)); 00718 assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel)); 00719 assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break)); 00720 assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity)); 00721 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput)); 00722 /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, 00723 the OSSI State, the dead time value and the Automatic Output Enable Bit */ 00724 TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | 00725 TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | 00726 TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | 00727 TIM_BDTRInitStruct->TIM_AutomaticOutput; 00728 } 00729 00730 /** 00731 * @brief Fills each TIM_TimeBaseInitStruct member with its default value. 00732 * @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef 00733 * structure which will be initialized. 00734 * @retval None 00735 */ 00736 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct) 00737 { 00738 /* Set the default configuration */ 00739 TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; 00740 TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; 00741 TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; 00742 TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; 00743 TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; 00744 } 00745 00746 /** 00747 * @brief Fills each TIM_OCInitStruct member with its default value. 00748 * @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will 00749 * be initialized. 00750 * @retval None 00751 */ 00752 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct) 00753 { 00754 /* Set the default configuration */ 00755 TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; 00756 TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; 00757 TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; 00758 TIM_OCInitStruct->TIM_Pulse = 0x0000; 00759 TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; 00760 TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; 00761 TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; 00762 TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; 00763 } 00764 00765 /** 00766 * @brief Fills each TIM_ICInitStruct member with its default value. 00767 * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will 00768 * be initialized. 00769 * @retval None 00770 */ 00771 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct) 00772 { 00773 /* Set the default configuration */ 00774 TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; 00775 TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; 00776 TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; 00777 TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; 00778 TIM_ICInitStruct->TIM_ICFilter = 0x00; 00779 } 00780 00781 /** 00782 * @brief Fills each TIM_BDTRInitStruct member with its default value. 00783 * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which 00784 * will be initialized. 00785 * @retval None 00786 */ 00787 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct) 00788 { 00789 /* Set the default configuration */ 00790 TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; 00791 TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; 00792 TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; 00793 TIM_BDTRInitStruct->TIM_DeadTime = 0x00; 00794 TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; 00795 TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; 00796 TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; 00797 } 00798 00799 /** 00800 * @brief Enables or disables the specified TIM peripheral. 00801 * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. 00802 * @param NewState: new state of the TIMx peripheral. 00803 * This parameter can be: ENABLE or DISABLE. 00804 * @retval None 00805 */ 00806 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState) 00807 { 00808 /* Check the parameters */ 00809 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00810 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00811 00812 if (NewState != DISABLE) 00813 { 00814 /* Enable the TIM Counter */ 00815 TIMx->CR1 |= TIM_CR1_CEN; 00816 } 00817 else 00818 { 00819 /* Disable the TIM Counter */ 00820 TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN)); 00821 } 00822 } 00823 00824 /** 00825 * @brief Enables or disables the TIM peripheral Main Outputs. 00826 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral. 00827 * @param NewState: new state of the TIM peripheral Main Outputs. 00828 * This parameter can be: ENABLE or DISABLE. 00829 * @retval None 00830 */ 00831 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState) 00832 { 00833 /* Check the parameters */ 00834 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 00835 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00836 if (NewState != DISABLE) 00837 { 00838 /* Enable the TIM Main Output */ 00839 TIMx->BDTR |= TIM_BDTR_MOE; 00840 } 00841 else 00842 { 00843 /* Disable the TIM Main Output */ 00844 TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE)); 00845 } 00846 } 00847 00848 /** 00849 * @brief Enables or disables the specified TIM interrupts. 00850 * @param TIMx: where x can be 1 to 17 to select the TIMx peripheral. 00851 * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled. 00852 * This parameter can be any combination of the following values: 00853 * @arg TIM_IT_Update: TIM update Interrupt source 00854 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source 00855 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source 00856 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source 00857 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source 00858 * @arg TIM_IT_COM: TIM Commutation Interrupt source 00859 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source 00860 * @arg TIM_IT_Break: TIM Break Interrupt source 00861 * @note 00862 * - TIM6 and TIM7 can only generate an update interrupt. 00863 * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, 00864 * TIM_IT_CC2 or TIM_IT_Trigger. 00865 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. 00866 * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 00867 * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. 00868 * @param NewState: new state of the TIM interrupts. 00869 * This parameter can be: ENABLE or DISABLE. 00870 * @retval None 00871 */ 00872 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState) 00873 { 00874 /* Check the parameters */ 00875 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00876 assert_param(IS_TIM_IT(TIM_IT)); 00877 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00878 00879 if (NewState != DISABLE) 00880 { 00881 /* Enable the Interrupt sources */ 00882 TIMx->DIER |= TIM_IT; 00883 } 00884 else 00885 { 00886 /* Disable the Interrupt sources */ 00887 TIMx->DIER &= (uint16_t)~TIM_IT; 00888 } 00889 } 00890 00891 /** 00892 * @brief Configures the TIMx event to be generate by software. 00893 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 00894 * @param TIM_EventSource: specifies the event source. 00895 * This parameter can be one or more of the following values: 00896 * @arg TIM_EventSource_Update: Timer update Event source 00897 * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source 00898 * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source 00899 * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source 00900 * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source 00901 * @arg TIM_EventSource_COM: Timer COM event source 00902 * @arg TIM_EventSource_Trigger: Timer Trigger Event source 00903 * @arg TIM_EventSource_Break: Timer Break event source 00904 * @note 00905 * - TIM6 and TIM7 can only generate an update event. 00906 * - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8. 00907 * @retval None 00908 */ 00909 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource) 00910 { 00911 /* Check the parameters */ 00912 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 00913 assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource)); 00914 00915 /* Set the event sources */ 00916 TIMx->EGR = TIM_EventSource; 00917 } 00918 00919 /** 00920 * @brief Configures the TIMx's DMA interface. 00921 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 00922 * the TIM peripheral. 00923 * @param TIM_DMABase: DMA Base address. 00924 * This parameter can be one of the following values: 00925 * @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR, 00926 * TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR, 00927 * TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER, 00928 * TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR, 00929 * TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2, 00930 * TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR, 00931 * TIM_DMABase_DCR. 00932 * @param TIM_DMABurstLength: DMA Burst length. 00933 * This parameter can be one value between: 00934 * TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers. 00935 * @retval None 00936 */ 00937 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) 00938 { 00939 /* Check the parameters */ 00940 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 00941 assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 00942 assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength)); 00943 /* Set the DMA Base and the DMA Burst Length */ 00944 TIMx->DCR = TIM_DMABase | TIM_DMABurstLength; 00945 } 00946 00947 /** 00948 * @brief Enables or disables the TIMx's DMA Requests. 00949 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17 00950 * to select the TIM peripheral. 00951 * @param TIM_DMASource: specifies the DMA Request sources. 00952 * This parameter can be any combination of the following values: 00953 * @arg TIM_DMA_Update: TIM update Interrupt source 00954 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source 00955 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source 00956 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source 00957 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source 00958 * @arg TIM_DMA_COM: TIM Commutation DMA source 00959 * @arg TIM_DMA_Trigger: TIM Trigger DMA source 00960 * @param NewState: new state of the DMA Request sources. 00961 * This parameter can be: ENABLE or DISABLE. 00962 * @retval None 00963 */ 00964 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState) 00965 { 00966 /* Check the parameters */ 00967 assert_param(IS_TIM_LIST9_PERIPH(TIMx)); 00968 assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource)); 00969 assert_param(IS_FUNCTIONAL_STATE(NewState)); 00970 00971 if (NewState != DISABLE) 00972 { 00973 /* Enable the DMA sources */ 00974 TIMx->DIER |= TIM_DMASource; 00975 } 00976 else 00977 { 00978 /* Disable the DMA sources */ 00979 TIMx->DIER &= (uint16_t)~TIM_DMASource; 00980 } 00981 } 00982 00983 /** 00984 * @brief Configures the TIMx internal Clock 00985 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 00986 * to select the TIM peripheral. 00987 * @retval None 00988 */ 00989 void TIM_InternalClockConfig(TIM_TypeDef* TIMx) 00990 { 00991 /* Check the parameters */ 00992 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 00993 /* Disable slave mode to clock the prescaler directly with the internal clock */ 00994 TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); 00995 } 00996 00997 /** 00998 * @brief Configures the TIMx Internal Trigger as External Clock 00999 * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. 01000 * @param TIM_ITRSource: Trigger source. 01001 * This parameter can be one of the following values: 01002 * @param TIM_TS_ITR0: Internal Trigger 0 01003 * @param TIM_TS_ITR1: Internal Trigger 1 01004 * @param TIM_TS_ITR2: Internal Trigger 2 01005 * @param TIM_TS_ITR3: Internal Trigger 3 01006 * @retval None 01007 */ 01008 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) 01009 { 01010 /* Check the parameters */ 01011 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 01012 assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource)); 01013 /* Select the Internal Trigger */ 01014 TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); 01015 /* Select the External clock mode1 */ 01016 TIMx->SMCR |= TIM_SlaveMode_External1; 01017 } 01018 01019 /** 01020 * @brief Configures the TIMx Trigger as External Clock 01021 * @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral. 01022 * @param TIM_TIxExternalCLKSource: Trigger source. 01023 * This parameter can be one of the following values: 01024 * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector 01025 * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1 01026 * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2 01027 * @param TIM_ICPolarity: specifies the TIx Polarity. 01028 * This parameter can be one of the following values: 01029 * @arg TIM_ICPolarity_Rising 01030 * @arg TIM_ICPolarity_Falling 01031 * @param ICFilter : specifies the filter value. 01032 * This parameter must be a value between 0x0 and 0xF. 01033 * @retval None 01034 */ 01035 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, 01036 uint16_t TIM_ICPolarity, uint16_t ICFilter) 01037 { 01038 /* Check the parameters */ 01039 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 01040 assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource)); 01041 assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity)); 01042 assert_param(IS_TIM_IC_FILTER(ICFilter)); 01043 /* Configure the Timer Input Clock Source */ 01044 if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) 01045 { 01046 TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); 01047 } 01048 else 01049 { 01050 TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); 01051 } 01052 /* Select the Trigger source */ 01053 TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); 01054 /* Select the External clock mode1 */ 01055 TIMx->SMCR |= TIM_SlaveMode_External1; 01056 } 01057 01058 /** 01059 * @brief Configures the External clock Mode1 01060 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01061 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 01062 * This parameter can be one of the following values: 01063 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. 01064 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. 01065 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. 01066 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. 01067 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 01068 * This parameter can be one of the following values: 01069 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. 01070 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. 01071 * @param ExtTRGFilter: External Trigger Filter. 01072 * This parameter must be a value between 0x00 and 0x0F 01073 * @retval None 01074 */ 01075 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 01076 uint16_t ExtTRGFilter) 01077 { 01078 uint16_t tmpsmcr = 0; 01079 /* Check the parameters */ 01080 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01081 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); 01082 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); 01083 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); 01084 /* Configure the ETR Clock source */ 01085 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); 01086 01087 /* Get the TIMx SMCR register value */ 01088 tmpsmcr = TIMx->SMCR; 01089 /* Reset the SMS Bits */ 01090 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); 01091 /* Select the External clock mode1 */ 01092 tmpsmcr |= TIM_SlaveMode_External1; 01093 /* Select the Trigger selection : ETRF */ 01094 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); 01095 tmpsmcr |= TIM_TS_ETRF; 01096 /* Write to TIMx SMCR */ 01097 TIMx->SMCR = tmpsmcr; 01098 } 01099 01100 /** 01101 * @brief Configures the External clock Mode2 01102 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01103 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 01104 * This parameter can be one of the following values: 01105 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. 01106 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. 01107 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. 01108 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. 01109 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 01110 * This parameter can be one of the following values: 01111 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. 01112 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. 01113 * @param ExtTRGFilter: External Trigger Filter. 01114 * This parameter must be a value between 0x00 and 0x0F 01115 * @retval None 01116 */ 01117 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 01118 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) 01119 { 01120 /* Check the parameters */ 01121 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01122 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); 01123 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); 01124 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); 01125 /* Configure the ETR Clock source */ 01126 TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); 01127 /* Enable the External clock mode2 */ 01128 TIMx->SMCR |= TIM_SMCR_ECE; 01129 } 01130 01131 /** 01132 * @brief Configures the TIMx External Trigger (ETR). 01133 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01134 * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. 01135 * This parameter can be one of the following values: 01136 * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF. 01137 * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2. 01138 * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4. 01139 * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8. 01140 * @param TIM_ExtTRGPolarity: The external Trigger Polarity. 01141 * This parameter can be one of the following values: 01142 * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active. 01143 * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active. 01144 * @param ExtTRGFilter: External Trigger Filter. 01145 * This parameter must be a value between 0x00 and 0x0F 01146 * @retval None 01147 */ 01148 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, 01149 uint16_t ExtTRGFilter) 01150 { 01151 uint16_t tmpsmcr = 0; 01152 /* Check the parameters */ 01153 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01154 assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler)); 01155 assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity)); 01156 assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter)); 01157 tmpsmcr = TIMx->SMCR; 01158 /* Reset the ETR Bits */ 01159 tmpsmcr &= SMCR_ETR_Mask; 01160 /* Set the Prescaler, the Filter value and the Polarity */ 01161 tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); 01162 /* Write to TIMx SMCR */ 01163 TIMx->SMCR = tmpsmcr; 01164 } 01165 01166 /** 01167 * @brief Configures the TIMx Prescaler. 01168 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 01169 * @param Prescaler: specifies the Prescaler Register value 01170 * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode 01171 * This parameter can be one of the following values: 01172 * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event. 01173 * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately. 01174 * @retval None 01175 */ 01176 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) 01177 { 01178 /* Check the parameters */ 01179 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 01180 assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode)); 01181 /* Set the Prescaler value */ 01182 TIMx->PSC = Prescaler; 01183 /* Set or reset the UG Bit */ 01184 TIMx->EGR = TIM_PSCReloadMode; 01185 } 01186 01187 /** 01188 * @brief Specifies the TIMx Counter Mode to be used. 01189 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01190 * @param TIM_CounterMode: specifies the Counter Mode to be used 01191 * This parameter can be one of the following values: 01192 * @arg TIM_CounterMode_Up: TIM Up Counting Mode 01193 * @arg TIM_CounterMode_Down: TIM Down Counting Mode 01194 * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1 01195 * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2 01196 * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3 01197 * @retval None 01198 */ 01199 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode) 01200 { 01201 uint16_t tmpcr1 = 0; 01202 /* Check the parameters */ 01203 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01204 assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode)); 01205 tmpcr1 = TIMx->CR1; 01206 /* Reset the CMS and DIR Bits */ 01207 tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS))); 01208 /* Set the Counter Mode */ 01209 tmpcr1 |= TIM_CounterMode; 01210 /* Write to TIMx CR1 register */ 01211 TIMx->CR1 = tmpcr1; 01212 } 01213 01214 /** 01215 * @brief Selects the Input Trigger source 01216 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 01217 * @param TIM_InputTriggerSource: The Input Trigger source. 01218 * This parameter can be one of the following values: 01219 * @arg TIM_TS_ITR0: Internal Trigger 0 01220 * @arg TIM_TS_ITR1: Internal Trigger 1 01221 * @arg TIM_TS_ITR2: Internal Trigger 2 01222 * @arg TIM_TS_ITR3: Internal Trigger 3 01223 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector 01224 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 01225 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 01226 * @arg TIM_TS_ETRF: External Trigger input 01227 * @retval None 01228 */ 01229 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource) 01230 { 01231 uint16_t tmpsmcr = 0; 01232 /* Check the parameters */ 01233 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 01234 assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource)); 01235 /* Get the TIMx SMCR register value */ 01236 tmpsmcr = TIMx->SMCR; 01237 /* Reset the TS Bits */ 01238 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS)); 01239 /* Set the Input Trigger source */ 01240 tmpsmcr |= TIM_InputTriggerSource; 01241 /* Write to TIMx SMCR */ 01242 TIMx->SMCR = tmpsmcr; 01243 } 01244 01245 /** 01246 * @brief Configures the TIMx Encoder Interface. 01247 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01248 * @param TIM_EncoderMode: specifies the TIMx Encoder Mode. 01249 * This parameter can be one of the following values: 01250 * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level. 01251 * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level. 01252 * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending 01253 * on the level of the other input. 01254 * @param TIM_IC1Polarity: specifies the IC1 Polarity 01255 * This parameter can be one of the following values: 01256 * @arg TIM_ICPolarity_Falling: IC Falling edge. 01257 * @arg TIM_ICPolarity_Rising: IC Rising edge. 01258 * @param TIM_IC2Polarity: specifies the IC2 Polarity 01259 * This parameter can be one of the following values: 01260 * @arg TIM_ICPolarity_Falling: IC Falling edge. 01261 * @arg TIM_ICPolarity_Rising: IC Rising edge. 01262 * @retval None 01263 */ 01264 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, 01265 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) 01266 { 01267 uint16_t tmpsmcr = 0; 01268 uint16_t tmpccmr1 = 0; 01269 uint16_t tmpccer = 0; 01270 01271 /* Check the parameters */ 01272 assert_param(IS_TIM_LIST5_PERIPH(TIMx)); 01273 assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode)); 01274 assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity)); 01275 assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity)); 01276 01277 /* Get the TIMx SMCR register value */ 01278 tmpsmcr = TIMx->SMCR; 01279 01280 /* Get the TIMx CCMR1 register value */ 01281 tmpccmr1 = TIMx->CCMR1; 01282 01283 /* Get the TIMx CCER register value */ 01284 tmpccer = TIMx->CCER; 01285 01286 /* Set the encoder Mode */ 01287 tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS)); 01288 tmpsmcr |= TIM_EncoderMode; 01289 01290 /* Select the Capture Compare 1 and the Capture Compare 2 as input */ 01291 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S))); 01292 tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0; 01293 01294 /* Set the TI1 and the TI2 Polarities */ 01295 tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P))); 01296 tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); 01297 01298 /* Write to TIMx SMCR */ 01299 TIMx->SMCR = tmpsmcr; 01300 /* Write to TIMx CCMR1 */ 01301 TIMx->CCMR1 = tmpccmr1; 01302 /* Write to TIMx CCER */ 01303 TIMx->CCER = tmpccer; 01304 } 01305 01306 /** 01307 * @brief Forces the TIMx output 1 waveform to active or inactive level. 01308 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 01309 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01310 * This parameter can be one of the following values: 01311 * @arg TIM_ForcedAction_Active: Force active level on OC1REF 01312 * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF. 01313 * @retval None 01314 */ 01315 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01316 { 01317 uint16_t tmpccmr1 = 0; 01318 /* Check the parameters */ 01319 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 01320 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01321 tmpccmr1 = TIMx->CCMR1; 01322 /* Reset the OC1M Bits */ 01323 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M); 01324 /* Configure The Forced output Mode */ 01325 tmpccmr1 |= TIM_ForcedAction; 01326 /* Write to TIMx CCMR1 register */ 01327 TIMx->CCMR1 = tmpccmr1; 01328 } 01329 01330 /** 01331 * @brief Forces the TIMx output 2 waveform to active or inactive level. 01332 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 01333 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01334 * This parameter can be one of the following values: 01335 * @arg TIM_ForcedAction_Active: Force active level on OC2REF 01336 * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF. 01337 * @retval None 01338 */ 01339 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01340 { 01341 uint16_t tmpccmr1 = 0; 01342 /* Check the parameters */ 01343 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 01344 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01345 tmpccmr1 = TIMx->CCMR1; 01346 /* Reset the OC2M Bits */ 01347 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M); 01348 /* Configure The Forced output Mode */ 01349 tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); 01350 /* Write to TIMx CCMR1 register */ 01351 TIMx->CCMR1 = tmpccmr1; 01352 } 01353 01354 /** 01355 * @brief Forces the TIMx output 3 waveform to active or inactive level. 01356 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01357 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01358 * This parameter can be one of the following values: 01359 * @arg TIM_ForcedAction_Active: Force active level on OC3REF 01360 * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF. 01361 * @retval None 01362 */ 01363 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01364 { 01365 uint16_t tmpccmr2 = 0; 01366 /* Check the parameters */ 01367 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01368 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01369 tmpccmr2 = TIMx->CCMR2; 01370 /* Reset the OC1M Bits */ 01371 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M); 01372 /* Configure The Forced output Mode */ 01373 tmpccmr2 |= TIM_ForcedAction; 01374 /* Write to TIMx CCMR2 register */ 01375 TIMx->CCMR2 = tmpccmr2; 01376 } 01377 01378 /** 01379 * @brief Forces the TIMx output 4 waveform to active or inactive level. 01380 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01381 * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform. 01382 * This parameter can be one of the following values: 01383 * @arg TIM_ForcedAction_Active: Force active level on OC4REF 01384 * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF. 01385 * @retval None 01386 */ 01387 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction) 01388 { 01389 uint16_t tmpccmr2 = 0; 01390 /* Check the parameters */ 01391 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01392 assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction)); 01393 tmpccmr2 = TIMx->CCMR2; 01394 /* Reset the OC2M Bits */ 01395 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M); 01396 /* Configure The Forced output Mode */ 01397 tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); 01398 /* Write to TIMx CCMR2 register */ 01399 TIMx->CCMR2 = tmpccmr2; 01400 } 01401 01402 /** 01403 * @brief Enables or disables TIMx peripheral Preload register on ARR. 01404 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 01405 * @param NewState: new state of the TIMx peripheral Preload register 01406 * This parameter can be: ENABLE or DISABLE. 01407 * @retval None 01408 */ 01409 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState) 01410 { 01411 /* Check the parameters */ 01412 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 01413 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01414 if (NewState != DISABLE) 01415 { 01416 /* Set the ARR Preload Bit */ 01417 TIMx->CR1 |= TIM_CR1_ARPE; 01418 } 01419 else 01420 { 01421 /* Reset the ARR Preload Bit */ 01422 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE); 01423 } 01424 } 01425 01426 /** 01427 * @brief Selects the TIM peripheral Commutation event. 01428 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral 01429 * @param NewState: new state of the Commutation event. 01430 * This parameter can be: ENABLE or DISABLE. 01431 * @retval None 01432 */ 01433 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState) 01434 { 01435 /* Check the parameters */ 01436 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 01437 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01438 if (NewState != DISABLE) 01439 { 01440 /* Set the COM Bit */ 01441 TIMx->CR2 |= TIM_CR2_CCUS; 01442 } 01443 else 01444 { 01445 /* Reset the COM Bit */ 01446 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS); 01447 } 01448 } 01449 01450 /** 01451 * @brief Selects the TIMx peripheral Capture Compare DMA source. 01452 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select 01453 * the TIM peripheral. 01454 * @param NewState: new state of the Capture Compare DMA source 01455 * This parameter can be: ENABLE or DISABLE. 01456 * @retval None 01457 */ 01458 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState) 01459 { 01460 /* Check the parameters */ 01461 assert_param(IS_TIM_LIST4_PERIPH(TIMx)); 01462 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01463 if (NewState != DISABLE) 01464 { 01465 /* Set the CCDS Bit */ 01466 TIMx->CR2 |= TIM_CR2_CCDS; 01467 } 01468 else 01469 { 01470 /* Reset the CCDS Bit */ 01471 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS); 01472 } 01473 } 01474 01475 /** 01476 * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit. 01477 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15 01478 * to select the TIMx peripheral 01479 * @param NewState: new state of the Capture Compare Preload Control bit 01480 * This parameter can be: ENABLE or DISABLE. 01481 * @retval None 01482 */ 01483 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState) 01484 { 01485 /* Check the parameters */ 01486 assert_param(IS_TIM_LIST5_PERIPH(TIMx)); 01487 assert_param(IS_FUNCTIONAL_STATE(NewState)); 01488 if (NewState != DISABLE) 01489 { 01490 /* Set the CCPC Bit */ 01491 TIMx->CR2 |= TIM_CR2_CCPC; 01492 } 01493 else 01494 { 01495 /* Reset the CCPC Bit */ 01496 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC); 01497 } 01498 } 01499 01500 /** 01501 * @brief Enables or disables the TIMx peripheral Preload register on CCR1. 01502 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 01503 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01504 * This parameter can be one of the following values: 01505 * @arg TIM_OCPreload_Enable 01506 * @arg TIM_OCPreload_Disable 01507 * @retval None 01508 */ 01509 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01510 { 01511 uint16_t tmpccmr1 = 0; 01512 /* Check the parameters */ 01513 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 01514 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01515 tmpccmr1 = TIMx->CCMR1; 01516 /* Reset the OC1PE Bit */ 01517 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE); 01518 /* Enable or Disable the Output Compare Preload feature */ 01519 tmpccmr1 |= TIM_OCPreload; 01520 /* Write to TIMx CCMR1 register */ 01521 TIMx->CCMR1 = tmpccmr1; 01522 } 01523 01524 /** 01525 * @brief Enables or disables the TIMx peripheral Preload register on CCR2. 01526 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 01527 * the TIM peripheral. 01528 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01529 * This parameter can be one of the following values: 01530 * @arg TIM_OCPreload_Enable 01531 * @arg TIM_OCPreload_Disable 01532 * @retval None 01533 */ 01534 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01535 { 01536 uint16_t tmpccmr1 = 0; 01537 /* Check the parameters */ 01538 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 01539 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01540 tmpccmr1 = TIMx->CCMR1; 01541 /* Reset the OC2PE Bit */ 01542 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE); 01543 /* Enable or Disable the Output Compare Preload feature */ 01544 tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); 01545 /* Write to TIMx CCMR1 register */ 01546 TIMx->CCMR1 = tmpccmr1; 01547 } 01548 01549 /** 01550 * @brief Enables or disables the TIMx peripheral Preload register on CCR3. 01551 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01552 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01553 * This parameter can be one of the following values: 01554 * @arg TIM_OCPreload_Enable 01555 * @arg TIM_OCPreload_Disable 01556 * @retval None 01557 */ 01558 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01559 { 01560 uint16_t tmpccmr2 = 0; 01561 /* Check the parameters */ 01562 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01563 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01564 tmpccmr2 = TIMx->CCMR2; 01565 /* Reset the OC3PE Bit */ 01566 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE); 01567 /* Enable or Disable the Output Compare Preload feature */ 01568 tmpccmr2 |= TIM_OCPreload; 01569 /* Write to TIMx CCMR2 register */ 01570 TIMx->CCMR2 = tmpccmr2; 01571 } 01572 01573 /** 01574 * @brief Enables or disables the TIMx peripheral Preload register on CCR4. 01575 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01576 * @param TIM_OCPreload: new state of the TIMx peripheral Preload register 01577 * This parameter can be one of the following values: 01578 * @arg TIM_OCPreload_Enable 01579 * @arg TIM_OCPreload_Disable 01580 * @retval None 01581 */ 01582 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload) 01583 { 01584 uint16_t tmpccmr2 = 0; 01585 /* Check the parameters */ 01586 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01587 assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload)); 01588 tmpccmr2 = TIMx->CCMR2; 01589 /* Reset the OC4PE Bit */ 01590 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE); 01591 /* Enable or Disable the Output Compare Preload feature */ 01592 tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); 01593 /* Write to TIMx CCMR2 register */ 01594 TIMx->CCMR2 = tmpccmr2; 01595 } 01596 01597 /** 01598 * @brief Configures the TIMx Output Compare 1 Fast feature. 01599 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 01600 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01601 * This parameter can be one of the following values: 01602 * @arg TIM_OCFast_Enable: TIM output compare fast enable 01603 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01604 * @retval None 01605 */ 01606 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) 01607 { 01608 uint16_t tmpccmr1 = 0; 01609 /* Check the parameters */ 01610 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 01611 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); 01612 /* Get the TIMx CCMR1 register value */ 01613 tmpccmr1 = TIMx->CCMR1; 01614 /* Reset the OC1FE Bit */ 01615 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE); 01616 /* Enable or Disable the Output Compare Fast Bit */ 01617 tmpccmr1 |= TIM_OCFast; 01618 /* Write to TIMx CCMR1 */ 01619 TIMx->CCMR1 = tmpccmr1; 01620 } 01621 01622 /** 01623 * @brief Configures the TIMx Output Compare 2 Fast feature. 01624 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select 01625 * the TIM peripheral. 01626 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01627 * This parameter can be one of the following values: 01628 * @arg TIM_OCFast_Enable: TIM output compare fast enable 01629 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01630 * @retval None 01631 */ 01632 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) 01633 { 01634 uint16_t tmpccmr1 = 0; 01635 /* Check the parameters */ 01636 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 01637 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); 01638 /* Get the TIMx CCMR1 register value */ 01639 tmpccmr1 = TIMx->CCMR1; 01640 /* Reset the OC2FE Bit */ 01641 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE); 01642 /* Enable or Disable the Output Compare Fast Bit */ 01643 tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); 01644 /* Write to TIMx CCMR1 */ 01645 TIMx->CCMR1 = tmpccmr1; 01646 } 01647 01648 /** 01649 * @brief Configures the TIMx Output Compare 3 Fast feature. 01650 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01651 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01652 * This parameter can be one of the following values: 01653 * @arg TIM_OCFast_Enable: TIM output compare fast enable 01654 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01655 * @retval None 01656 */ 01657 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) 01658 { 01659 uint16_t tmpccmr2 = 0; 01660 /* Check the parameters */ 01661 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01662 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); 01663 /* Get the TIMx CCMR2 register value */ 01664 tmpccmr2 = TIMx->CCMR2; 01665 /* Reset the OC3FE Bit */ 01666 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE); 01667 /* Enable or Disable the Output Compare Fast Bit */ 01668 tmpccmr2 |= TIM_OCFast; 01669 /* Write to TIMx CCMR2 */ 01670 TIMx->CCMR2 = tmpccmr2; 01671 } 01672 01673 /** 01674 * @brief Configures the TIMx Output Compare 4 Fast feature. 01675 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01676 * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit. 01677 * This parameter can be one of the following values: 01678 * @arg TIM_OCFast_Enable: TIM output compare fast enable 01679 * @arg TIM_OCFast_Disable: TIM output compare fast disable 01680 * @retval None 01681 */ 01682 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast) 01683 { 01684 uint16_t tmpccmr2 = 0; 01685 /* Check the parameters */ 01686 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01687 assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast)); 01688 /* Get the TIMx CCMR2 register value */ 01689 tmpccmr2 = TIMx->CCMR2; 01690 /* Reset the OC4FE Bit */ 01691 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE); 01692 /* Enable or Disable the Output Compare Fast Bit */ 01693 tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); 01694 /* Write to TIMx CCMR2 */ 01695 TIMx->CCMR2 = tmpccmr2; 01696 } 01697 01698 /** 01699 * @brief Clears or safeguards the OCREF1 signal on an external event 01700 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01701 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01702 * This parameter can be one of the following values: 01703 * @arg TIM_OCClear_Enable: TIM Output clear enable 01704 * @arg TIM_OCClear_Disable: TIM Output clear disable 01705 * @retval None 01706 */ 01707 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01708 { 01709 uint16_t tmpccmr1 = 0; 01710 /* Check the parameters */ 01711 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01712 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01713 01714 tmpccmr1 = TIMx->CCMR1; 01715 01716 /* Reset the OC1CE Bit */ 01717 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE); 01718 /* Enable or Disable the Output Compare Clear Bit */ 01719 tmpccmr1 |= TIM_OCClear; 01720 /* Write to TIMx CCMR1 register */ 01721 TIMx->CCMR1 = tmpccmr1; 01722 } 01723 01724 /** 01725 * @brief Clears or safeguards the OCREF2 signal on an external event 01726 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01727 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01728 * This parameter can be one of the following values: 01729 * @arg TIM_OCClear_Enable: TIM Output clear enable 01730 * @arg TIM_OCClear_Disable: TIM Output clear disable 01731 * @retval None 01732 */ 01733 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01734 { 01735 uint16_t tmpccmr1 = 0; 01736 /* Check the parameters */ 01737 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01738 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01739 tmpccmr1 = TIMx->CCMR1; 01740 /* Reset the OC2CE Bit */ 01741 tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE); 01742 /* Enable or Disable the Output Compare Clear Bit */ 01743 tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); 01744 /* Write to TIMx CCMR1 register */ 01745 TIMx->CCMR1 = tmpccmr1; 01746 } 01747 01748 /** 01749 * @brief Clears or safeguards the OCREF3 signal on an external event 01750 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01751 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01752 * This parameter can be one of the following values: 01753 * @arg TIM_OCClear_Enable: TIM Output clear enable 01754 * @arg TIM_OCClear_Disable: TIM Output clear disable 01755 * @retval None 01756 */ 01757 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01758 { 01759 uint16_t tmpccmr2 = 0; 01760 /* Check the parameters */ 01761 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01762 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01763 tmpccmr2 = TIMx->CCMR2; 01764 /* Reset the OC3CE Bit */ 01765 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE); 01766 /* Enable or Disable the Output Compare Clear Bit */ 01767 tmpccmr2 |= TIM_OCClear; 01768 /* Write to TIMx CCMR2 register */ 01769 TIMx->CCMR2 = tmpccmr2; 01770 } 01771 01772 /** 01773 * @brief Clears or safeguards the OCREF4 signal on an external event 01774 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01775 * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit. 01776 * This parameter can be one of the following values: 01777 * @arg TIM_OCClear_Enable: TIM Output clear enable 01778 * @arg TIM_OCClear_Disable: TIM Output clear disable 01779 * @retval None 01780 */ 01781 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear) 01782 { 01783 uint16_t tmpccmr2 = 0; 01784 /* Check the parameters */ 01785 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01786 assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear)); 01787 tmpccmr2 = TIMx->CCMR2; 01788 /* Reset the OC4CE Bit */ 01789 tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE); 01790 /* Enable or Disable the Output Compare Clear Bit */ 01791 tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); 01792 /* Write to TIMx CCMR2 register */ 01793 TIMx->CCMR2 = tmpccmr2; 01794 } 01795 01796 /** 01797 * @brief Configures the TIMx channel 1 polarity. 01798 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 01799 * @param TIM_OCPolarity: specifies the OC1 Polarity 01800 * This parameter can be one of the following values: 01801 * @arg TIM_OCPolarity_High: Output Compare active high 01802 * @arg TIM_OCPolarity_Low: Output Compare active low 01803 * @retval None 01804 */ 01805 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 01806 { 01807 uint16_t tmpccer = 0; 01808 /* Check the parameters */ 01809 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 01810 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 01811 tmpccer = TIMx->CCER; 01812 /* Set or Reset the CC1P Bit */ 01813 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P); 01814 tmpccer |= TIM_OCPolarity; 01815 /* Write to TIMx CCER register */ 01816 TIMx->CCER = tmpccer; 01817 } 01818 01819 /** 01820 * @brief Configures the TIMx Channel 1N polarity. 01821 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. 01822 * @param TIM_OCNPolarity: specifies the OC1N Polarity 01823 * This parameter can be one of the following values: 01824 * @arg TIM_OCNPolarity_High: Output Compare active high 01825 * @arg TIM_OCNPolarity_Low: Output Compare active low 01826 * @retval None 01827 */ 01828 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) 01829 { 01830 uint16_t tmpccer = 0; 01831 /* Check the parameters */ 01832 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 01833 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); 01834 01835 tmpccer = TIMx->CCER; 01836 /* Set or Reset the CC1NP Bit */ 01837 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP); 01838 tmpccer |= TIM_OCNPolarity; 01839 /* Write to TIMx CCER register */ 01840 TIMx->CCER = tmpccer; 01841 } 01842 01843 /** 01844 * @brief Configures the TIMx channel 2 polarity. 01845 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 01846 * @param TIM_OCPolarity: specifies the OC2 Polarity 01847 * This parameter can be one of the following values: 01848 * @arg TIM_OCPolarity_High: Output Compare active high 01849 * @arg TIM_OCPolarity_Low: Output Compare active low 01850 * @retval None 01851 */ 01852 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 01853 { 01854 uint16_t tmpccer = 0; 01855 /* Check the parameters */ 01856 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 01857 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 01858 tmpccer = TIMx->CCER; 01859 /* Set or Reset the CC2P Bit */ 01860 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P); 01861 tmpccer |= (uint16_t)(TIM_OCPolarity << 4); 01862 /* Write to TIMx CCER register */ 01863 TIMx->CCER = tmpccer; 01864 } 01865 01866 /** 01867 * @brief Configures the TIMx Channel 2N polarity. 01868 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01869 * @param TIM_OCNPolarity: specifies the OC2N Polarity 01870 * This parameter can be one of the following values: 01871 * @arg TIM_OCNPolarity_High: Output Compare active high 01872 * @arg TIM_OCNPolarity_Low: Output Compare active low 01873 * @retval None 01874 */ 01875 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) 01876 { 01877 uint16_t tmpccer = 0; 01878 /* Check the parameters */ 01879 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 01880 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); 01881 01882 tmpccer = TIMx->CCER; 01883 /* Set or Reset the CC2NP Bit */ 01884 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP); 01885 tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); 01886 /* Write to TIMx CCER register */ 01887 TIMx->CCER = tmpccer; 01888 } 01889 01890 /** 01891 * @brief Configures the TIMx channel 3 polarity. 01892 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01893 * @param TIM_OCPolarity: specifies the OC3 Polarity 01894 * This parameter can be one of the following values: 01895 * @arg TIM_OCPolarity_High: Output Compare active high 01896 * @arg TIM_OCPolarity_Low: Output Compare active low 01897 * @retval None 01898 */ 01899 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 01900 { 01901 uint16_t tmpccer = 0; 01902 /* Check the parameters */ 01903 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01904 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 01905 tmpccer = TIMx->CCER; 01906 /* Set or Reset the CC3P Bit */ 01907 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P); 01908 tmpccer |= (uint16_t)(TIM_OCPolarity << 8); 01909 /* Write to TIMx CCER register */ 01910 TIMx->CCER = tmpccer; 01911 } 01912 01913 /** 01914 * @brief Configures the TIMx Channel 3N polarity. 01915 * @param TIMx: where x can be 1 or 8 to select the TIM peripheral. 01916 * @param TIM_OCNPolarity: specifies the OC3N Polarity 01917 * This parameter can be one of the following values: 01918 * @arg TIM_OCNPolarity_High: Output Compare active high 01919 * @arg TIM_OCNPolarity_Low: Output Compare active low 01920 * @retval None 01921 */ 01922 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity) 01923 { 01924 uint16_t tmpccer = 0; 01925 01926 /* Check the parameters */ 01927 assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 01928 assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity)); 01929 01930 tmpccer = TIMx->CCER; 01931 /* Set or Reset the CC3NP Bit */ 01932 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP); 01933 tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); 01934 /* Write to TIMx CCER register */ 01935 TIMx->CCER = tmpccer; 01936 } 01937 01938 /** 01939 * @brief Configures the TIMx channel 4 polarity. 01940 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 01941 * @param TIM_OCPolarity: specifies the OC4 Polarity 01942 * This parameter can be one of the following values: 01943 * @arg TIM_OCPolarity_High: Output Compare active high 01944 * @arg TIM_OCPolarity_Low: Output Compare active low 01945 * @retval None 01946 */ 01947 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity) 01948 { 01949 uint16_t tmpccer = 0; 01950 /* Check the parameters */ 01951 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 01952 assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity)); 01953 tmpccer = TIMx->CCER; 01954 /* Set or Reset the CC4P Bit */ 01955 tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P); 01956 tmpccer |= (uint16_t)(TIM_OCPolarity << 12); 01957 /* Write to TIMx CCER register */ 01958 TIMx->CCER = tmpccer; 01959 } 01960 01961 /** 01962 * @brief Enables or disables the TIM Capture Compare Channel x. 01963 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 01964 * @param TIM_Channel: specifies the TIM Channel 01965 * This parameter can be one of the following values: 01966 * @arg TIM_Channel_1: TIM Channel 1 01967 * @arg TIM_Channel_2: TIM Channel 2 01968 * @arg TIM_Channel_3: TIM Channel 3 01969 * @arg TIM_Channel_4: TIM Channel 4 01970 * @param TIM_CCx: specifies the TIM Channel CCxE bit new state. 01971 * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 01972 * @retval None 01973 */ 01974 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) 01975 { 01976 uint16_t tmp = 0; 01977 01978 /* Check the parameters */ 01979 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 01980 assert_param(IS_TIM_CHANNEL(TIM_Channel)); 01981 assert_param(IS_TIM_CCX(TIM_CCx)); 01982 01983 tmp = CCER_CCE_Set << TIM_Channel; 01984 01985 /* Reset the CCxE Bit */ 01986 TIMx->CCER &= (uint16_t)~ tmp; 01987 01988 /* Set or reset the CCxE Bit */ 01989 TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); 01990 } 01991 01992 /** 01993 * @brief Enables or disables the TIM Capture Compare Channel xN. 01994 * @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral. 01995 * @param TIM_Channel: specifies the TIM Channel 01996 * This parameter can be one of the following values: 01997 * @arg TIM_Channel_1: TIM Channel 1 01998 * @arg TIM_Channel_2: TIM Channel 2 01999 * @arg TIM_Channel_3: TIM Channel 3 02000 * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state. 02001 * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 02002 * @retval None 02003 */ 02004 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) 02005 { 02006 uint16_t tmp = 0; 02007 02008 /* Check the parameters */ 02009 assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 02010 assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel)); 02011 assert_param(IS_TIM_CCXN(TIM_CCxN)); 02012 02013 tmp = CCER_CCNE_Set << TIM_Channel; 02014 02015 /* Reset the CCxNE Bit */ 02016 TIMx->CCER &= (uint16_t) ~tmp; 02017 02018 /* Set or reset the CCxNE Bit */ 02019 TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); 02020 } 02021 02022 /** 02023 * @brief Selects the TIM Output Compare Mode. 02024 * @note This function disables the selected channel before changing the Output 02025 * Compare Mode. 02026 * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions. 02027 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 02028 * @param TIM_Channel: specifies the TIM Channel 02029 * This parameter can be one of the following values: 02030 * @arg TIM_Channel_1: TIM Channel 1 02031 * @arg TIM_Channel_2: TIM Channel 2 02032 * @arg TIM_Channel_3: TIM Channel 3 02033 * @arg TIM_Channel_4: TIM Channel 4 02034 * @param TIM_OCMode: specifies the TIM Output Compare Mode. 02035 * This parameter can be one of the following values: 02036 * @arg TIM_OCMode_Timing 02037 * @arg TIM_OCMode_Active 02038 * @arg TIM_OCMode_Toggle 02039 * @arg TIM_OCMode_PWM1 02040 * @arg TIM_OCMode_PWM2 02041 * @arg TIM_ForcedAction_Active 02042 * @arg TIM_ForcedAction_InActive 02043 * @retval None 02044 */ 02045 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) 02046 { 02047 uint32_t tmp = 0; 02048 uint16_t tmp1 = 0; 02049 02050 /* Check the parameters */ 02051 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 02052 assert_param(IS_TIM_CHANNEL(TIM_Channel)); 02053 assert_param(IS_TIM_OCM(TIM_OCMode)); 02054 02055 tmp = (uint32_t) TIMx; 02056 tmp += CCMR_Offset; 02057 02058 tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; 02059 02060 /* Disable the Channel: Reset the CCxE Bit */ 02061 TIMx->CCER &= (uint16_t) ~tmp1; 02062 02063 if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3)) 02064 { 02065 tmp += (TIM_Channel>>1); 02066 02067 /* Reset the OCxM bits in the CCMRx register */ 02068 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M); 02069 02070 /* Configure the OCxM bits in the CCMRx register */ 02071 *(__IO uint32_t *) tmp |= TIM_OCMode; 02072 } 02073 else 02074 { 02075 tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1; 02076 02077 /* Reset the OCxM bits in the CCMRx register */ 02078 *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M); 02079 02080 /* Configure the OCxM bits in the CCMRx register */ 02081 *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8); 02082 } 02083 } 02084 02085 /** 02086 * @brief Enables or Disables the TIMx Update event. 02087 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02088 * @param NewState: new state of the TIMx UDIS bit 02089 * This parameter can be: ENABLE or DISABLE. 02090 * @retval None 02091 */ 02092 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState) 02093 { 02094 /* Check the parameters */ 02095 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02096 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02097 if (NewState != DISABLE) 02098 { 02099 /* Set the Update Disable Bit */ 02100 TIMx->CR1 |= TIM_CR1_UDIS; 02101 } 02102 else 02103 { 02104 /* Reset the Update Disable Bit */ 02105 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS); 02106 } 02107 } 02108 02109 /** 02110 * @brief Configures the TIMx Update Request Interrupt source. 02111 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02112 * @param TIM_UpdateSource: specifies the Update source. 02113 * This parameter can be one of the following values: 02114 * @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow 02115 or the setting of UG bit, or an update generation 02116 through the slave mode controller. 02117 * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow. 02118 * @retval None 02119 */ 02120 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource) 02121 { 02122 /* Check the parameters */ 02123 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02124 assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource)); 02125 if (TIM_UpdateSource != TIM_UpdateSource_Global) 02126 { 02127 /* Set the URS Bit */ 02128 TIMx->CR1 |= TIM_CR1_URS; 02129 } 02130 else 02131 { 02132 /* Reset the URS Bit */ 02133 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS); 02134 } 02135 } 02136 02137 /** 02138 * @brief Enables or disables the TIMx's Hall sensor interface. 02139 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02140 * @param NewState: new state of the TIMx Hall sensor interface. 02141 * This parameter can be: ENABLE or DISABLE. 02142 * @retval None 02143 */ 02144 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState) 02145 { 02146 /* Check the parameters */ 02147 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02148 assert_param(IS_FUNCTIONAL_STATE(NewState)); 02149 if (NewState != DISABLE) 02150 { 02151 /* Set the TI1S Bit */ 02152 TIMx->CR2 |= TIM_CR2_TI1S; 02153 } 02154 else 02155 { 02156 /* Reset the TI1S Bit */ 02157 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S); 02158 } 02159 } 02160 02161 /** 02162 * @brief Selects the TIMx's One Pulse Mode. 02163 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02164 * @param TIM_OPMode: specifies the OPM Mode to be used. 02165 * This parameter can be one of the following values: 02166 * @arg TIM_OPMode_Single 02167 * @arg TIM_OPMode_Repetitive 02168 * @retval None 02169 */ 02170 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode) 02171 { 02172 /* Check the parameters */ 02173 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02174 assert_param(IS_TIM_OPM_MODE(TIM_OPMode)); 02175 /* Reset the OPM Bit */ 02176 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM); 02177 /* Configure the OPM Mode */ 02178 TIMx->CR1 |= TIM_OPMode; 02179 } 02180 02181 /** 02182 * @brief Selects the TIMx Trigger Output Mode. 02183 * @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral. 02184 * @param TIM_TRGOSource: specifies the Trigger Output source. 02185 * This paramter can be one of the following values: 02186 * 02187 * - For all TIMx 02188 * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO). 02189 * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO). 02190 * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO). 02191 * 02192 * - For all TIMx except TIM6 and TIM7 02193 * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag 02194 * is to be set, as soon as a capture or compare match occurs (TRGO). 02195 * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO). 02196 * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO). 02197 * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO). 02198 * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO). 02199 * 02200 * @retval None 02201 */ 02202 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource) 02203 { 02204 /* Check the parameters */ 02205 assert_param(IS_TIM_LIST7_PERIPH(TIMx)); 02206 assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource)); 02207 /* Reset the MMS Bits */ 02208 TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS); 02209 /* Select the TRGO source */ 02210 TIMx->CR2 |= TIM_TRGOSource; 02211 } 02212 02213 /** 02214 * @brief Selects the TIMx Slave Mode. 02215 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 02216 * @param TIM_SlaveMode: specifies the Timer Slave Mode. 02217 * This parameter can be one of the following values: 02218 * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes 02219 * the counter and triggers an update of the registers. 02220 * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high. 02221 * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI. 02222 * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter. 02223 * @retval None 02224 */ 02225 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode) 02226 { 02227 /* Check the parameters */ 02228 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02229 assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode)); 02230 /* Reset the SMS Bits */ 02231 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS); 02232 /* Select the Slave Mode */ 02233 TIMx->SMCR |= TIM_SlaveMode; 02234 } 02235 02236 /** 02237 * @brief Sets or Resets the TIMx Master/Slave Mode. 02238 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 02239 * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode. 02240 * This parameter can be one of the following values: 02241 * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer 02242 * and its slaves (through TRGO). 02243 * @arg TIM_MasterSlaveMode_Disable: No action 02244 * @retval None 02245 */ 02246 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode) 02247 { 02248 /* Check the parameters */ 02249 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02250 assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode)); 02251 /* Reset the MSM Bit */ 02252 TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM); 02253 02254 /* Set or Reset the MSM Bit */ 02255 TIMx->SMCR |= TIM_MasterSlaveMode; 02256 } 02257 02258 /** 02259 * @brief Sets the TIMx Counter Register value 02260 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02261 * @param Counter: specifies the Counter register new value. 02262 * @retval None 02263 */ 02264 void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter) 02265 { 02266 /* Check the parameters */ 02267 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02268 /* Set the Counter Register value */ 02269 TIMx->CNT = Counter; 02270 } 02271 02272 /** 02273 * @brief Sets the TIMx Autoreload Register value 02274 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02275 * @param Autoreload: specifies the Autoreload register new value. 02276 * @retval None 02277 */ 02278 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload) 02279 { 02280 /* Check the parameters */ 02281 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02282 /* Set the Autoreload Register value */ 02283 TIMx->ARR = Autoreload; 02284 } 02285 02286 /** 02287 * @brief Sets the TIMx Capture Compare1 Register value 02288 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 02289 * @param Compare1: specifies the Capture Compare1 register new value. 02290 * @retval None 02291 */ 02292 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1) 02293 { 02294 /* Check the parameters */ 02295 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 02296 /* Set the Capture Compare1 Register value */ 02297 TIMx->CCR1 = Compare1; 02298 } 02299 02300 /** 02301 * @brief Sets the TIMx Capture Compare2 Register value 02302 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 02303 * @param Compare2: specifies the Capture Compare2 register new value. 02304 * @retval None 02305 */ 02306 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2) 02307 { 02308 /* Check the parameters */ 02309 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02310 /* Set the Capture Compare2 Register value */ 02311 TIMx->CCR2 = Compare2; 02312 } 02313 02314 /** 02315 * @brief Sets the TIMx Capture Compare3 Register value 02316 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02317 * @param Compare3: specifies the Capture Compare3 register new value. 02318 * @retval None 02319 */ 02320 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3) 02321 { 02322 /* Check the parameters */ 02323 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02324 /* Set the Capture Compare3 Register value */ 02325 TIMx->CCR3 = Compare3; 02326 } 02327 02328 /** 02329 * @brief Sets the TIMx Capture Compare4 Register value 02330 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02331 * @param Compare4: specifies the Capture Compare4 register new value. 02332 * @retval None 02333 */ 02334 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4) 02335 { 02336 /* Check the parameters */ 02337 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02338 /* Set the Capture Compare4 Register value */ 02339 TIMx->CCR4 = Compare4; 02340 } 02341 02342 /** 02343 * @brief Sets the TIMx Input Capture 1 prescaler. 02344 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 02345 * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value. 02346 * This parameter can be one of the following values: 02347 * @arg TIM_ICPSC_DIV1: no prescaler 02348 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 02349 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 02350 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 02351 * @retval None 02352 */ 02353 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) 02354 { 02355 /* Check the parameters */ 02356 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 02357 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); 02358 /* Reset the IC1PSC Bits */ 02359 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC); 02360 /* Set the IC1PSC value */ 02361 TIMx->CCMR1 |= TIM_ICPSC; 02362 } 02363 02364 /** 02365 * @brief Sets the TIMx Input Capture 2 prescaler. 02366 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 02367 * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value. 02368 * This parameter can be one of the following values: 02369 * @arg TIM_ICPSC_DIV1: no prescaler 02370 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 02371 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 02372 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 02373 * @retval None 02374 */ 02375 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) 02376 { 02377 /* Check the parameters */ 02378 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02379 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); 02380 /* Reset the IC2PSC Bits */ 02381 TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC); 02382 /* Set the IC2PSC value */ 02383 TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8); 02384 } 02385 02386 /** 02387 * @brief Sets the TIMx Input Capture 3 prescaler. 02388 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02389 * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value. 02390 * This parameter can be one of the following values: 02391 * @arg TIM_ICPSC_DIV1: no prescaler 02392 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 02393 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 02394 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 02395 * @retval None 02396 */ 02397 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) 02398 { 02399 /* Check the parameters */ 02400 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02401 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); 02402 /* Reset the IC3PSC Bits */ 02403 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC); 02404 /* Set the IC3PSC value */ 02405 TIMx->CCMR2 |= TIM_ICPSC; 02406 } 02407 02408 /** 02409 * @brief Sets the TIMx Input Capture 4 prescaler. 02410 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02411 * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value. 02412 * This parameter can be one of the following values: 02413 * @arg TIM_ICPSC_DIV1: no prescaler 02414 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events 02415 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events 02416 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events 02417 * @retval None 02418 */ 02419 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC) 02420 { 02421 /* Check the parameters */ 02422 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02423 assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC)); 02424 /* Reset the IC4PSC Bits */ 02425 TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC); 02426 /* Set the IC4PSC value */ 02427 TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8); 02428 } 02429 02430 /** 02431 * @brief Sets the TIMx Clock Division value. 02432 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select 02433 * the TIM peripheral. 02434 * @param TIM_CKD: specifies the clock division value. 02435 * This parameter can be one of the following value: 02436 * @arg TIM_CKD_DIV1: TDTS = Tck_tim 02437 * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim 02438 * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim 02439 * @retval None 02440 */ 02441 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD) 02442 { 02443 /* Check the parameters */ 02444 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 02445 assert_param(IS_TIM_CKD_DIV(TIM_CKD)); 02446 /* Reset the CKD Bits */ 02447 TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD); 02448 /* Set the CKD value */ 02449 TIMx->CR1 |= TIM_CKD; 02450 } 02451 02452 /** 02453 * @brief Gets the TIMx Input Capture 1 value. 02454 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 02455 * @retval Capture Compare 1 Register value. 02456 */ 02457 uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx) 02458 { 02459 /* Check the parameters */ 02460 assert_param(IS_TIM_LIST8_PERIPH(TIMx)); 02461 /* Get the Capture 1 Register value */ 02462 return TIMx->CCR1; 02463 } 02464 02465 /** 02466 * @brief Gets the TIMx Input Capture 2 value. 02467 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 02468 * @retval Capture Compare 2 Register value. 02469 */ 02470 uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx) 02471 { 02472 /* Check the parameters */ 02473 assert_param(IS_TIM_LIST6_PERIPH(TIMx)); 02474 /* Get the Capture 2 Register value */ 02475 return TIMx->CCR2; 02476 } 02477 02478 /** 02479 * @brief Gets the TIMx Input Capture 3 value. 02480 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02481 * @retval Capture Compare 3 Register value. 02482 */ 02483 uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx) 02484 { 02485 /* Check the parameters */ 02486 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02487 /* Get the Capture 3 Register value */ 02488 return TIMx->CCR3; 02489 } 02490 02491 /** 02492 * @brief Gets the TIMx Input Capture 4 value. 02493 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02494 * @retval Capture Compare 4 Register value. 02495 */ 02496 uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx) 02497 { 02498 /* Check the parameters */ 02499 assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 02500 /* Get the Capture 4 Register value */ 02501 return TIMx->CCR4; 02502 } 02503 02504 /** 02505 * @brief Gets the TIMx Counter value. 02506 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02507 * @retval Counter Register value. 02508 */ 02509 uint16_t TIM_GetCounter(TIM_TypeDef* TIMx) 02510 { 02511 /* Check the parameters */ 02512 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02513 /* Get the Counter Register value */ 02514 return TIMx->CNT; 02515 } 02516 02517 /** 02518 * @brief Gets the TIMx Prescaler value. 02519 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02520 * @retval Prescaler Register value. 02521 */ 02522 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx) 02523 { 02524 /* Check the parameters */ 02525 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02526 /* Get the Prescaler Register value */ 02527 return TIMx->PSC; 02528 } 02529 02530 /** 02531 * @brief Checks whether the specified TIM flag is set or not. 02532 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02533 * @param TIM_FLAG: specifies the flag to check. 02534 * This parameter can be one of the following values: 02535 * @arg TIM_FLAG_Update: TIM update Flag 02536 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag 02537 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag 02538 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag 02539 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag 02540 * @arg TIM_FLAG_COM: TIM Commutation Flag 02541 * @arg TIM_FLAG_Trigger: TIM Trigger Flag 02542 * @arg TIM_FLAG_Break: TIM Break Flag 02543 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag 02544 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag 02545 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag 02546 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag 02547 * @note 02548 * - TIM6 and TIM7 can have only one update flag. 02549 * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, 02550 * TIM_FLAG_CC2 or TIM_FLAG_Trigger. 02551 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. 02552 * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 02553 * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. 02554 * @retval The new state of TIM_FLAG (SET or RESET). 02555 */ 02556 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) 02557 { 02558 ITStatus bitstatus = RESET; 02559 /* Check the parameters */ 02560 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02561 assert_param(IS_TIM_GET_FLAG(TIM_FLAG)); 02562 02563 if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET) 02564 { 02565 bitstatus = SET; 02566 } 02567 else 02568 { 02569 bitstatus = RESET; 02570 } 02571 return bitstatus; 02572 } 02573 02574 /** 02575 * @brief Clears the TIMx's pending flags. 02576 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02577 * @param TIM_FLAG: specifies the flag bit to clear. 02578 * This parameter can be any combination of the following values: 02579 * @arg TIM_FLAG_Update: TIM update Flag 02580 * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag 02581 * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag 02582 * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag 02583 * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag 02584 * @arg TIM_FLAG_COM: TIM Commutation Flag 02585 * @arg TIM_FLAG_Trigger: TIM Trigger Flag 02586 * @arg TIM_FLAG_Break: TIM Break Flag 02587 * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag 02588 * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag 02589 * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag 02590 * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag 02591 * @note 02592 * - TIM6 and TIM7 can have only one update flag. 02593 * - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, 02594 * TIM_FLAG_CC2 or TIM_FLAG_Trigger. 02595 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1. 02596 * - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15. 02597 * - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. 02598 * @retval None 02599 */ 02600 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG) 02601 { 02602 /* Check the parameters */ 02603 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02604 assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG)); 02605 02606 /* Clear the flags */ 02607 TIMx->SR = (uint16_t)~TIM_FLAG; 02608 } 02609 02610 /** 02611 * @brief Checks whether the TIM interrupt has occurred or not. 02612 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02613 * @param TIM_IT: specifies the TIM interrupt source to check. 02614 * This parameter can be one of the following values: 02615 * @arg TIM_IT_Update: TIM update Interrupt source 02616 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source 02617 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source 02618 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source 02619 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source 02620 * @arg TIM_IT_COM: TIM Commutation Interrupt source 02621 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source 02622 * @arg TIM_IT_Break: TIM Break Interrupt source 02623 * @note 02624 * - TIM6 and TIM7 can generate only an update interrupt. 02625 * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, 02626 * TIM_IT_CC2 or TIM_IT_Trigger. 02627 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. 02628 * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 02629 * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. 02630 * @retval The new state of the TIM_IT(SET or RESET). 02631 */ 02632 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT) 02633 { 02634 ITStatus bitstatus = RESET; 02635 uint16_t itstatus = 0x0, itenable = 0x0; 02636 /* Check the parameters */ 02637 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02638 assert_param(IS_TIM_GET_IT(TIM_IT)); 02639 02640 itstatus = TIMx->SR & TIM_IT; 02641 02642 itenable = TIMx->DIER & TIM_IT; 02643 if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) 02644 { 02645 bitstatus = SET; 02646 } 02647 else 02648 { 02649 bitstatus = RESET; 02650 } 02651 return bitstatus; 02652 } 02653 02654 /** 02655 * @brief Clears the TIMx's interrupt pending bits. 02656 * @param TIMx: where x can be 1 to 17 to select the TIM peripheral. 02657 * @param TIM_IT: specifies the pending bit to clear. 02658 * This parameter can be any combination of the following values: 02659 * @arg TIM_IT_Update: TIM1 update Interrupt source 02660 * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source 02661 * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source 02662 * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source 02663 * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source 02664 * @arg TIM_IT_COM: TIM Commutation Interrupt source 02665 * @arg TIM_IT_Trigger: TIM Trigger Interrupt source 02666 * @arg TIM_IT_Break: TIM Break Interrupt source 02667 * @note 02668 * - TIM6 and TIM7 can generate only an update interrupt. 02669 * - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1, 02670 * TIM_IT_CC2 or TIM_IT_Trigger. 02671 * - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1. 02672 * - TIM_IT_Break is used only with TIM1, TIM8 and TIM15. 02673 * - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17. 02674 * @retval None 02675 */ 02676 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT) 02677 { 02678 /* Check the parameters */ 02679 assert_param(IS_TIM_ALL_PERIPH(TIMx)); 02680 assert_param(IS_TIM_IT(TIM_IT)); 02681 /* Clear the IT pending Bit */ 02682 TIMx->SR = (uint16_t)~TIM_IT; 02683 } 02684 02685 /** 02686 * @brief Configure the TI1 as Input. 02687 * @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral. 02688 * @param TIM_ICPolarity : The Input Polarity. 02689 * This parameter can be one of the following values: 02690 * @arg TIM_ICPolarity_Rising 02691 * @arg TIM_ICPolarity_Falling 02692 * @param TIM_ICSelection: specifies the input to be used. 02693 * This parameter can be one of the following values: 02694 * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. 02695 * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. 02696 * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. 02697 * @param TIM_ICFilter: Specifies the Input Capture Filter. 02698 * This parameter must be a value between 0x00 and 0x0F. 02699 * @retval None 02700 */ 02701 static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 02702 uint16_t TIM_ICFilter) 02703 { 02704 uint16_t tmpccmr1 = 0, tmpccer = 0; 02705 /* Disable the Channel 1: Reset the CC1E Bit */ 02706 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E); 02707 tmpccmr1 = TIMx->CCMR1; 02708 tmpccer = TIMx->CCER; 02709 /* Select the Input and set the filter */ 02710 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F))); 02711 tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); 02712 02713 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 02714 (TIMx == TIM4) ||(TIMx == TIM5)) 02715 { 02716 /* Select the Polarity and set the CC1E Bit */ 02717 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P)); 02718 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); 02719 } 02720 else 02721 { 02722 /* Select the Polarity and set the CC1E Bit */ 02723 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)); 02724 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E); 02725 } 02726 02727 /* Write to TIMx CCMR1 and CCER registers */ 02728 TIMx->CCMR1 = tmpccmr1; 02729 TIMx->CCER = tmpccer; 02730 } 02731 02732 /** 02733 * @brief Configure the TI2 as Input. 02734 * @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral. 02735 * @param TIM_ICPolarity : The Input Polarity. 02736 * This parameter can be one of the following values: 02737 * @arg TIM_ICPolarity_Rising 02738 * @arg TIM_ICPolarity_Falling 02739 * @param TIM_ICSelection: specifies the input to be used. 02740 * This parameter can be one of the following values: 02741 * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. 02742 * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. 02743 * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. 02744 * @param TIM_ICFilter: Specifies the Input Capture Filter. 02745 * This parameter must be a value between 0x00 and 0x0F. 02746 * @retval None 02747 */ 02748 static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 02749 uint16_t TIM_ICFilter) 02750 { 02751 uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; 02752 /* Disable the Channel 2: Reset the CC2E Bit */ 02753 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E); 02754 tmpccmr1 = TIMx->CCMR1; 02755 tmpccer = TIMx->CCER; 02756 tmp = (uint16_t)(TIM_ICPolarity << 4); 02757 /* Select the Input and set the filter */ 02758 tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F))); 02759 tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); 02760 tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); 02761 02762 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 02763 (TIMx == TIM4) ||(TIMx == TIM5)) 02764 { 02765 /* Select the Polarity and set the CC2E Bit */ 02766 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P)); 02767 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E); 02768 } 02769 else 02770 { 02771 /* Select the Polarity and set the CC2E Bit */ 02772 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP)); 02773 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E); 02774 } 02775 02776 /* Write to TIMx CCMR1 and CCER registers */ 02777 TIMx->CCMR1 = tmpccmr1 ; 02778 TIMx->CCER = tmpccer; 02779 } 02780 02781 /** 02782 * @brief Configure the TI3 as Input. 02783 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02784 * @param TIM_ICPolarity : The Input Polarity. 02785 * This parameter can be one of the following values: 02786 * @arg TIM_ICPolarity_Rising 02787 * @arg TIM_ICPolarity_Falling 02788 * @param TIM_ICSelection: specifies the input to be used. 02789 * This parameter can be one of the following values: 02790 * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. 02791 * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. 02792 * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. 02793 * @param TIM_ICFilter: Specifies the Input Capture Filter. 02794 * This parameter must be a value between 0x00 and 0x0F. 02795 * @retval None 02796 */ 02797 static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 02798 uint16_t TIM_ICFilter) 02799 { 02800 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 02801 /* Disable the Channel 3: Reset the CC3E Bit */ 02802 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E); 02803 tmpccmr2 = TIMx->CCMR2; 02804 tmpccer = TIMx->CCER; 02805 tmp = (uint16_t)(TIM_ICPolarity << 8); 02806 /* Select the Input and set the filter */ 02807 tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F))); 02808 tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); 02809 02810 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 02811 (TIMx == TIM4) ||(TIMx == TIM5)) 02812 { 02813 /* Select the Polarity and set the CC3E Bit */ 02814 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P)); 02815 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E); 02816 } 02817 else 02818 { 02819 /* Select the Polarity and set the CC3E Bit */ 02820 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP)); 02821 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E); 02822 } 02823 02824 /* Write to TIMx CCMR2 and CCER registers */ 02825 TIMx->CCMR2 = tmpccmr2; 02826 TIMx->CCER = tmpccer; 02827 } 02828 02829 /** 02830 * @brief Configure the TI4 as Input. 02831 * @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral. 02832 * @param TIM_ICPolarity : The Input Polarity. 02833 * This parameter can be one of the following values: 02834 * @arg TIM_ICPolarity_Rising 02835 * @arg TIM_ICPolarity_Falling 02836 * @param TIM_ICSelection: specifies the input to be used. 02837 * This parameter can be one of the following values: 02838 * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. 02839 * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. 02840 * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. 02841 * @param TIM_ICFilter: Specifies the Input Capture Filter. 02842 * This parameter must be a value between 0x00 and 0x0F. 02843 * @retval None 02844 */ 02845 static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, 02846 uint16_t TIM_ICFilter) 02847 { 02848 uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; 02849 02850 /* Disable the Channel 4: Reset the CC4E Bit */ 02851 TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E); 02852 tmpccmr2 = TIMx->CCMR2; 02853 tmpccer = TIMx->CCER; 02854 tmp = (uint16_t)(TIM_ICPolarity << 12); 02855 /* Select the Input and set the filter */ 02856 tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F))); 02857 tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); 02858 tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); 02859 02860 if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) || 02861 (TIMx == TIM4) ||(TIMx == TIM5)) 02862 { 02863 /* Select the Polarity and set the CC4E Bit */ 02864 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P)); 02865 tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E); 02866 } 02867 else 02868 { 02869 /* Select the Polarity and set the CC4E Bit */ 02870 tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP)); 02871 tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E); 02872 } 02873 /* Write to TIMx CCMR2 and CCER registers */ 02874 TIMx->CCMR2 = tmpccmr2; 02875 TIMx->CCER = tmpccer; 02876 } 02877 02878 /** 02879 * @} 02880 */ 02881 02882 /** 02883 * @} 02884 */ 02885 02886 /** 02887 * @} 02888 */ 02889 02890 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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