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stm32f10x_rcc.h
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f10x_rcc.h 00004 * @author MCD Application Team 00005 * @version V3.5.0 00006 * @date 11-March-2011 00007 * @brief This file contains all the functions prototypes for the RCC firmware 00008 * library. 00009 ****************************************************************************** 00010 * @attention 00011 * 00012 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS 00013 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE 00014 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY 00015 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING 00016 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE 00017 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. 00018 * 00019 * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2> 00020 ****************************************************************************** 00021 */ 00022 00023 /* Define to prevent recursive inclusion -------------------------------------*/ 00024 #ifndef __STM32F10x_RCC_H 00025 #define __STM32F10x_RCC_H 00026 00027 #ifdef __cplusplus 00028 extern "C" { 00029 #endif 00030 00031 /* Includes ------------------------------------------------------------------*/ 00032 #include "stm32f10x.h" 00033 00034 /** @addtogroup STM32F10x_StdPeriph_Driver 00035 * @{ 00036 */ 00037 00038 /** @addtogroup RCC 00039 * @{ 00040 */ 00041 00042 /** @defgroup RCC_Exported_Types 00043 * @{ 00044 */ 00045 00046 typedef struct 00047 { 00048 uint32_t SYSCLK_Frequency; /*!< returns SYSCLK clock frequency expressed in Hz */ 00049 uint32_t HCLK_Frequency; /*!< returns HCLK clock frequency expressed in Hz */ 00050 uint32_t PCLK1_Frequency; /*!< returns PCLK1 clock frequency expressed in Hz */ 00051 uint32_t PCLK2_Frequency; /*!< returns PCLK2 clock frequency expressed in Hz */ 00052 uint32_t ADCCLK_Frequency; /*!< returns ADCCLK clock frequency expressed in Hz */ 00053 }RCC_ClocksTypeDef; 00054 00055 /** 00056 * @} 00057 */ 00058 00059 /** @defgroup RCC_Exported_Constants 00060 * @{ 00061 */ 00062 00063 /** @defgroup HSE_configuration 00064 * @{ 00065 */ 00066 00067 #define RCC_HSE_OFF ((uint32_t)0x00000000) 00068 #define RCC_HSE_ON ((uint32_t)0x00010000) 00069 #define RCC_HSE_Bypass ((uint32_t)0x00040000) 00070 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \ 00071 ((HSE) == RCC_HSE_Bypass)) 00072 00073 /** 00074 * @} 00075 */ 00076 00077 /** @defgroup PLL_entry_clock_source 00078 * @{ 00079 */ 00080 00081 #define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) 00082 00083 #if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_CL) 00084 #define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) 00085 #define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) 00086 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 00087 ((SOURCE) == RCC_PLLSource_HSE_Div1) || \ 00088 ((SOURCE) == RCC_PLLSource_HSE_Div2)) 00089 #else 00090 #define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) 00091 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \ 00092 ((SOURCE) == RCC_PLLSource_PREDIV1)) 00093 #endif /* STM32F10X_CL */ 00094 00095 /** 00096 * @} 00097 */ 00098 00099 /** @defgroup PLL_multiplication_factor 00100 * @{ 00101 */ 00102 #ifndef STM32F10X_CL 00103 #define RCC_PLLMul_2 ((uint32_t)0x00000000) 00104 #define RCC_PLLMul_3 ((uint32_t)0x00040000) 00105 #define RCC_PLLMul_4 ((uint32_t)0x00080000) 00106 #define RCC_PLLMul_5 ((uint32_t)0x000C0000) 00107 #define RCC_PLLMul_6 ((uint32_t)0x00100000) 00108 #define RCC_PLLMul_7 ((uint32_t)0x00140000) 00109 #define RCC_PLLMul_8 ((uint32_t)0x00180000) 00110 #define RCC_PLLMul_9 ((uint32_t)0x001C0000) 00111 #define RCC_PLLMul_10 ((uint32_t)0x00200000) 00112 #define RCC_PLLMul_11 ((uint32_t)0x00240000) 00113 #define RCC_PLLMul_12 ((uint32_t)0x00280000) 00114 #define RCC_PLLMul_13 ((uint32_t)0x002C0000) 00115 #define RCC_PLLMul_14 ((uint32_t)0x00300000) 00116 #define RCC_PLLMul_15 ((uint32_t)0x00340000) 00117 #define RCC_PLLMul_16 ((uint32_t)0x00380000) 00118 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \ 00119 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 00120 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 00121 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 00122 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \ 00123 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \ 00124 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \ 00125 ((MUL) == RCC_PLLMul_16)) 00126 00127 #else 00128 #define RCC_PLLMul_4 ((uint32_t)0x00080000) 00129 #define RCC_PLLMul_5 ((uint32_t)0x000C0000) 00130 #define RCC_PLLMul_6 ((uint32_t)0x00100000) 00131 #define RCC_PLLMul_7 ((uint32_t)0x00140000) 00132 #define RCC_PLLMul_8 ((uint32_t)0x00180000) 00133 #define RCC_PLLMul_9 ((uint32_t)0x001C0000) 00134 #define RCC_PLLMul_6_5 ((uint32_t)0x00340000) 00135 00136 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \ 00137 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \ 00138 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \ 00139 ((MUL) == RCC_PLLMul_6_5)) 00140 #endif /* STM32F10X_CL */ 00141 /** 00142 * @} 00143 */ 00144 00145 /** @defgroup PREDIV1_division_factor 00146 * @{ 00147 */ 00148 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 00149 #define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) 00150 #define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) 00151 #define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) 00152 #define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) 00153 #define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) 00154 #define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) 00155 #define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) 00156 #define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) 00157 #define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) 00158 #define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) 00159 #define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) 00160 #define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) 00161 #define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) 00162 #define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) 00163 #define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) 00164 #define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) 00165 00166 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \ 00167 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \ 00168 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \ 00169 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \ 00170 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \ 00171 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \ 00172 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \ 00173 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16)) 00174 #endif 00175 /** 00176 * @} 00177 */ 00178 00179 00180 /** @defgroup PREDIV1_clock_source 00181 * @{ 00182 */ 00183 #ifdef STM32F10X_CL 00184 /* PREDIV1 clock source (for STM32 connectivity line devices) */ 00185 #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) 00186 #define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) 00187 00188 #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE) || \ 00189 ((SOURCE) == RCC_PREDIV1_Source_PLL2)) 00190 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) 00191 /* PREDIV1 clock source (for STM32 Value line devices) */ 00192 #define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) 00193 00194 #define IS_RCC_PREDIV1_SOURCE(SOURCE) (((SOURCE) == RCC_PREDIV1_Source_HSE)) 00195 #endif 00196 /** 00197 * @} 00198 */ 00199 00200 #ifdef STM32F10X_CL 00201 /** @defgroup PREDIV2_division_factor 00202 * @{ 00203 */ 00204 00205 #define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) 00206 #define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) 00207 #define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) 00208 #define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) 00209 #define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) 00210 #define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) 00211 #define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) 00212 #define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) 00213 #define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) 00214 #define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) 00215 #define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) 00216 #define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) 00217 #define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) 00218 #define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) 00219 #define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) 00220 #define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) 00221 00222 #define IS_RCC_PREDIV2(PREDIV2) (((PREDIV2) == RCC_PREDIV2_Div1) || ((PREDIV2) == RCC_PREDIV2_Div2) || \ 00223 ((PREDIV2) == RCC_PREDIV2_Div3) || ((PREDIV2) == RCC_PREDIV2_Div4) || \ 00224 ((PREDIV2) == RCC_PREDIV2_Div5) || ((PREDIV2) == RCC_PREDIV2_Div6) || \ 00225 ((PREDIV2) == RCC_PREDIV2_Div7) || ((PREDIV2) == RCC_PREDIV2_Div8) || \ 00226 ((PREDIV2) == RCC_PREDIV2_Div9) || ((PREDIV2) == RCC_PREDIV2_Div10) || \ 00227 ((PREDIV2) == RCC_PREDIV2_Div11) || ((PREDIV2) == RCC_PREDIV2_Div12) || \ 00228 ((PREDIV2) == RCC_PREDIV2_Div13) || ((PREDIV2) == RCC_PREDIV2_Div14) || \ 00229 ((PREDIV2) == RCC_PREDIV2_Div15) || ((PREDIV2) == RCC_PREDIV2_Div16)) 00230 /** 00231 * @} 00232 */ 00233 00234 00235 /** @defgroup PLL2_multiplication_factor 00236 * @{ 00237 */ 00238 00239 #define RCC_PLL2Mul_8 ((uint32_t)0x00000600) 00240 #define RCC_PLL2Mul_9 ((uint32_t)0x00000700) 00241 #define RCC_PLL2Mul_10 ((uint32_t)0x00000800) 00242 #define RCC_PLL2Mul_11 ((uint32_t)0x00000900) 00243 #define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) 00244 #define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) 00245 #define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) 00246 #define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) 00247 #define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) 00248 00249 #define IS_RCC_PLL2_MUL(MUL) (((MUL) == RCC_PLL2Mul_8) || ((MUL) == RCC_PLL2Mul_9) || \ 00250 ((MUL) == RCC_PLL2Mul_10) || ((MUL) == RCC_PLL2Mul_11) || \ 00251 ((MUL) == RCC_PLL2Mul_12) || ((MUL) == RCC_PLL2Mul_13) || \ 00252 ((MUL) == RCC_PLL2Mul_14) || ((MUL) == RCC_PLL2Mul_16) || \ 00253 ((MUL) == RCC_PLL2Mul_20)) 00254 /** 00255 * @} 00256 */ 00257 00258 00259 /** @defgroup PLL3_multiplication_factor 00260 * @{ 00261 */ 00262 00263 #define RCC_PLL3Mul_8 ((uint32_t)0x00006000) 00264 #define RCC_PLL3Mul_9 ((uint32_t)0x00007000) 00265 #define RCC_PLL3Mul_10 ((uint32_t)0x00008000) 00266 #define RCC_PLL3Mul_11 ((uint32_t)0x00009000) 00267 #define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) 00268 #define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) 00269 #define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) 00270 #define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) 00271 #define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) 00272 00273 #define IS_RCC_PLL3_MUL(MUL) (((MUL) == RCC_PLL3Mul_8) || ((MUL) == RCC_PLL3Mul_9) || \ 00274 ((MUL) == RCC_PLL3Mul_10) || ((MUL) == RCC_PLL3Mul_11) || \ 00275 ((MUL) == RCC_PLL3Mul_12) || ((MUL) == RCC_PLL3Mul_13) || \ 00276 ((MUL) == RCC_PLL3Mul_14) || ((MUL) == RCC_PLL3Mul_16) || \ 00277 ((MUL) == RCC_PLL3Mul_20)) 00278 /** 00279 * @} 00280 */ 00281 00282 #endif /* STM32F10X_CL */ 00283 00284 00285 /** @defgroup System_clock_source 00286 * @{ 00287 */ 00288 00289 #define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) 00290 #define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) 00291 #define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) 00292 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \ 00293 ((SOURCE) == RCC_SYSCLKSource_HSE) || \ 00294 ((SOURCE) == RCC_SYSCLKSource_PLLCLK)) 00295 /** 00296 * @} 00297 */ 00298 00299 /** @defgroup AHB_clock_source 00300 * @{ 00301 */ 00302 00303 #define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) 00304 #define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) 00305 #define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) 00306 #define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) 00307 #define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) 00308 #define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) 00309 #define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) 00310 #define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) 00311 #define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) 00312 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \ 00313 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \ 00314 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \ 00315 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \ 00316 ((HCLK) == RCC_SYSCLK_Div512)) 00317 /** 00318 * @} 00319 */ 00320 00321 /** @defgroup APB1_APB2_clock_source 00322 * @{ 00323 */ 00324 00325 #define RCC_HCLK_Div1 ((uint32_t)0x00000000) 00326 #define RCC_HCLK_Div2 ((uint32_t)0x00000400) 00327 #define RCC_HCLK_Div4 ((uint32_t)0x00000500) 00328 #define RCC_HCLK_Div8 ((uint32_t)0x00000600) 00329 #define RCC_HCLK_Div16 ((uint32_t)0x00000700) 00330 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \ 00331 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \ 00332 ((PCLK) == RCC_HCLK_Div16)) 00333 /** 00334 * @} 00335 */ 00336 00337 /** @defgroup RCC_Interrupt_source 00338 * @{ 00339 */ 00340 00341 #define RCC_IT_LSIRDY ((uint8_t)0x01) 00342 #define RCC_IT_LSERDY ((uint8_t)0x02) 00343 #define RCC_IT_HSIRDY ((uint8_t)0x04) 00344 #define RCC_IT_HSERDY ((uint8_t)0x08) 00345 #define RCC_IT_PLLRDY ((uint8_t)0x10) 00346 #define RCC_IT_CSS ((uint8_t)0x80) 00347 00348 #ifndef STM32F10X_CL 00349 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xE0) == 0x00) && ((IT) != 0x00)) 00350 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 00351 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 00352 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS)) 00353 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x60) == 0x00) && ((IT) != 0x00)) 00354 #else 00355 #define RCC_IT_PLL2RDY ((uint8_t)0x20) 00356 #define RCC_IT_PLL3RDY ((uint8_t)0x40) 00357 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00)) 00358 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \ 00359 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \ 00360 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \ 00361 ((IT) == RCC_IT_PLL2RDY) || ((IT) == RCC_IT_PLL3RDY)) 00362 #define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00) 00363 #endif /* STM32F10X_CL */ 00364 00365 00366 /** 00367 * @} 00368 */ 00369 00370 #ifndef STM32F10X_CL 00371 /** @defgroup USB_Device_clock_source 00372 * @{ 00373 */ 00374 00375 #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) 00376 #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) 00377 00378 #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \ 00379 ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1)) 00380 /** 00381 * @} 00382 */ 00383 #else 00384 /** @defgroup USB_OTG_FS_clock_source 00385 * @{ 00386 */ 00387 #define RCC_OTGFSCLKSource_PLLVCO_Div3 ((uint8_t)0x00) 00388 #define RCC_OTGFSCLKSource_PLLVCO_Div2 ((uint8_t)0x01) 00389 00390 #define IS_RCC_OTGFSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div3) || \ 00391 ((SOURCE) == RCC_OTGFSCLKSource_PLLVCO_Div2)) 00392 /** 00393 * @} 00394 */ 00395 #endif /* STM32F10X_CL */ 00396 00397 00398 #ifdef STM32F10X_CL 00399 /** @defgroup I2S2_clock_source 00400 * @{ 00401 */ 00402 #define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) 00403 #define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) 00404 00405 #define IS_RCC_I2S2CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_SYSCLK) || \ 00406 ((SOURCE) == RCC_I2S2CLKSource_PLL3_VCO)) 00407 /** 00408 * @} 00409 */ 00410 00411 /** @defgroup I2S3_clock_source 00412 * @{ 00413 */ 00414 #define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) 00415 #define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) 00416 00417 #define IS_RCC_I2S3CLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S3CLKSource_SYSCLK) || \ 00418 ((SOURCE) == RCC_I2S3CLKSource_PLL3_VCO)) 00419 /** 00420 * @} 00421 */ 00422 #endif /* STM32F10X_CL */ 00423 00424 00425 /** @defgroup ADC_clock_source 00426 * @{ 00427 */ 00428 00429 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000) 00430 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000) 00431 #define RCC_PCLK2_Div6 ((uint32_t)0x00008000) 00432 #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) 00433 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \ 00434 ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8)) 00435 /** 00436 * @} 00437 */ 00438 00439 /** @defgroup LSE_configuration 00440 * @{ 00441 */ 00442 00443 #define RCC_LSE_OFF ((uint8_t)0x00) 00444 #define RCC_LSE_ON ((uint8_t)0x01) 00445 #define RCC_LSE_Bypass ((uint8_t)0x04) 00446 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \ 00447 ((LSE) == RCC_LSE_Bypass)) 00448 /** 00449 * @} 00450 */ 00451 00452 /** @defgroup RTC_clock_source 00453 * @{ 00454 */ 00455 00456 #define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) 00457 #define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) 00458 #define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) 00459 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \ 00460 ((SOURCE) == RCC_RTCCLKSource_LSI) || \ 00461 ((SOURCE) == RCC_RTCCLKSource_HSE_Div128)) 00462 /** 00463 * @} 00464 */ 00465 00466 /** @defgroup AHB_peripheral 00467 * @{ 00468 */ 00469 00470 #define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) 00471 #define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) 00472 #define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) 00473 #define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) 00474 #define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) 00475 00476 #ifndef STM32F10X_CL 00477 #define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) 00478 #define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) 00479 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFAA8) == 0x00) && ((PERIPH) != 0x00)) 00480 #else 00481 #define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000) 00482 #define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) 00483 #define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) 00484 #define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) 00485 00486 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFFFE2FA8) == 0x00) && ((PERIPH) != 0x00)) 00487 #define IS_RCC_AHB_PERIPH_RESET(PERIPH) ((((PERIPH) & 0xFFFFAFFF) == 0x00) && ((PERIPH) != 0x00)) 00488 #endif /* STM32F10X_CL */ 00489 /** 00490 * @} 00491 */ 00492 00493 /** @defgroup APB2_peripheral 00494 * @{ 00495 */ 00496 00497 #define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) 00498 #define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) 00499 #define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) 00500 #define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) 00501 #define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) 00502 #define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) 00503 #define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) 00504 #define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) 00505 #define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) 00506 #define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) 00507 #define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) 00508 #define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) 00509 #define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) 00510 #define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) 00511 #define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) 00512 #define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) 00513 #define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) 00514 #define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) 00515 #define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) 00516 #define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) 00517 #define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) 00518 00519 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFC00002) == 0x00) && ((PERIPH) != 0x00)) 00520 /** 00521 * @} 00522 */ 00523 00524 /** @defgroup APB1_peripheral 00525 * @{ 00526 */ 00527 00528 #define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) 00529 #define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) 00530 #define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) 00531 #define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) 00532 #define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) 00533 #define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) 00534 #define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) 00535 #define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) 00536 #define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) 00537 #define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) 00538 #define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) 00539 #define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) 00540 #define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) 00541 #define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) 00542 #define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) 00543 #define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) 00544 #define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) 00545 #define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) 00546 #define RCC_APB1Periph_USB ((uint32_t)0x00800000) 00547 #define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) 00548 #define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) 00549 #define RCC_APB1Periph_BKP ((uint32_t)0x08000000) 00550 #define RCC_APB1Periph_PWR ((uint32_t)0x10000000) 00551 #define RCC_APB1Periph_DAC ((uint32_t)0x20000000) 00552 #define RCC_APB1Periph_CEC ((uint32_t)0x40000000) 00553 00554 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x81013600) == 0x00) && ((PERIPH) != 0x00)) 00555 00556 /** 00557 * @} 00558 */ 00559 00560 /** @defgroup Clock_source_to_output_on_MCO_pin 00561 * @{ 00562 */ 00563 00564 #define RCC_MCO_NoClock ((uint8_t)0x00) 00565 #define RCC_MCO_SYSCLK ((uint8_t)0x04) 00566 #define RCC_MCO_HSI ((uint8_t)0x05) 00567 #define RCC_MCO_HSE ((uint8_t)0x06) 00568 #define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) 00569 00570 #ifndef STM32F10X_CL 00571 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 00572 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 00573 ((MCO) == RCC_MCO_PLLCLK_Div2)) 00574 #else 00575 #define RCC_MCO_PLL2CLK ((uint8_t)0x08) 00576 #define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) 00577 #define RCC_MCO_XT1 ((uint8_t)0x0A) 00578 #define RCC_MCO_PLL3CLK ((uint8_t)0x0B) 00579 00580 #define IS_RCC_MCO(MCO) (((MCO) == RCC_MCO_NoClock) || ((MCO) == RCC_MCO_HSI) || \ 00581 ((MCO) == RCC_MCO_SYSCLK) || ((MCO) == RCC_MCO_HSE) || \ 00582 ((MCO) == RCC_MCO_PLLCLK_Div2) || ((MCO) == RCC_MCO_PLL2CLK) || \ 00583 ((MCO) == RCC_MCO_PLL3CLK_Div2) || ((MCO) == RCC_MCO_XT1) || \ 00584 ((MCO) == RCC_MCO_PLL3CLK)) 00585 #endif /* STM32F10X_CL */ 00586 00587 /** 00588 * @} 00589 */ 00590 00591 /** @defgroup RCC_Flag 00592 * @{ 00593 */ 00594 00595 #define RCC_FLAG_HSIRDY ((uint8_t)0x21) 00596 #define RCC_FLAG_HSERDY ((uint8_t)0x31) 00597 #define RCC_FLAG_PLLRDY ((uint8_t)0x39) 00598 #define RCC_FLAG_LSERDY ((uint8_t)0x41) 00599 #define RCC_FLAG_LSIRDY ((uint8_t)0x61) 00600 #define RCC_FLAG_PINRST ((uint8_t)0x7A) 00601 #define RCC_FLAG_PORRST ((uint8_t)0x7B) 00602 #define RCC_FLAG_SFTRST ((uint8_t)0x7C) 00603 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D) 00604 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E) 00605 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F) 00606 00607 #ifndef STM32F10X_CL 00608 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 00609 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 00610 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 00611 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 00612 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ 00613 ((FLAG) == RCC_FLAG_LPWRRST)) 00614 #else 00615 #define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) 00616 #define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) 00617 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \ 00618 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \ 00619 ((FLAG) == RCC_FLAG_PLL2RDY) || ((FLAG) == RCC_FLAG_PLL3RDY) || \ 00620 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_PINRST) || \ 00621 ((FLAG) == RCC_FLAG_PORRST) || ((FLAG) == RCC_FLAG_SFTRST) || \ 00622 ((FLAG) == RCC_FLAG_IWDGRST)|| ((FLAG) == RCC_FLAG_WWDGRST)|| \ 00623 ((FLAG) == RCC_FLAG_LPWRRST)) 00624 #endif /* STM32F10X_CL */ 00625 00626 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F) 00627 /** 00628 * @} 00629 */ 00630 00631 /** 00632 * @} 00633 */ 00634 00635 /** @defgroup RCC_Exported_Macros 00636 * @{ 00637 */ 00638 00639 /** 00640 * @} 00641 */ 00642 00643 /** @defgroup RCC_Exported_Functions 00644 * @{ 00645 */ 00646 00647 void RCC_DeInit(void); 00648 void RCC_HSEConfig(uint32_t RCC_HSE); 00649 ErrorStatus RCC_WaitForHSEStartUp(void); 00650 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); 00651 void RCC_HSICmd(FunctionalState NewState); 00652 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); 00653 void RCC_PLLCmd(FunctionalState NewState); 00654 00655 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL) 00656 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); 00657 #endif 00658 00659 #ifdef STM32F10X_CL 00660 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); 00661 void RCC_PLL2Config(uint32_t RCC_PLL2Mul); 00662 void RCC_PLL2Cmd(FunctionalState NewState); 00663 void RCC_PLL3Config(uint32_t RCC_PLL3Mul); 00664 void RCC_PLL3Cmd(FunctionalState NewState); 00665 #endif /* STM32F10X_CL */ 00666 00667 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); 00668 uint8_t RCC_GetSYSCLKSource(void); 00669 void RCC_HCLKConfig(uint32_t RCC_SYSCLK); 00670 void RCC_PCLK1Config(uint32_t RCC_HCLK); 00671 void RCC_PCLK2Config(uint32_t RCC_HCLK); 00672 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); 00673 00674 #ifndef STM32F10X_CL 00675 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); 00676 #else 00677 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource); 00678 #endif /* STM32F10X_CL */ 00679 00680 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); 00681 00682 #ifdef STM32F10X_CL 00683 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); 00684 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); 00685 #endif /* STM32F10X_CL */ 00686 00687 void RCC_LSEConfig(uint8_t RCC_LSE); 00688 void RCC_LSICmd(FunctionalState NewState); 00689 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); 00690 void RCC_RTCCLKCmd(FunctionalState NewState); 00691 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); 00692 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 00693 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 00694 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 00695 00696 #ifdef STM32F10X_CL 00697 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); 00698 #endif /* STM32F10X_CL */ 00699 00700 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); 00701 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); 00702 void RCC_BackupResetCmd(FunctionalState NewState); 00703 void RCC_ClockSecuritySystemCmd(FunctionalState NewState); 00704 void RCC_MCOConfig(uint8_t RCC_MCO); 00705 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); 00706 void RCC_ClearFlag(void); 00707 ITStatus RCC_GetITStatus(uint8_t RCC_IT); 00708 void RCC_ClearITPendingBit(uint8_t RCC_IT); 00709 00710 #ifdef __cplusplus 00711 } 00712 #endif 00713 00714 #endif /* __STM32F10x_RCC_H */ 00715 /** 00716 * @} 00717 */ 00718 00719 /** 00720 * @} 00721 */ 00722 00723 /** 00724 * @} 00725 */ 00726 00727 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
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