Sergey Pastor / grbl1

stm_lib/src/stm32f10x_rcc.c@0:8f0d870509fe, 2017-09-04 (annotated)

Committer:
Sergunb
Date:
Mon Sep 04 12:04:13 2017 +0000
Revision:
0:8f0d870509fe
Initial commit

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Sergunb 0:8f0d870509fe 1 /**
Sergunb 0:8f0d870509fe 2 ******************************************************************************
Sergunb 0:8f0d870509fe 3 * @file stm32f10x_rcc.c
Sergunb 0:8f0d870509fe 4 * @author MCD Application Team
Sergunb 0:8f0d870509fe 5 * @version V3.5.0
Sergunb 0:8f0d870509fe 6 * @date 11-March-2011
Sergunb 0:8f0d870509fe 7 * @brief This file provides all the RCC firmware functions.
Sergunb 0:8f0d870509fe 8 ******************************************************************************
Sergunb 0:8f0d870509fe 9 * @attention
Sergunb 0:8f0d870509fe 10 *
Sergunb 0:8f0d870509fe 11 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
Sergunb 0:8f0d870509fe 12 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
Sergunb 0:8f0d870509fe 13 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
Sergunb 0:8f0d870509fe 14 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
Sergunb 0:8f0d870509fe 15 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
Sergunb 0:8f0d870509fe 16 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
Sergunb 0:8f0d870509fe 17 *
Sergunb 0:8f0d870509fe 18 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
Sergunb 0:8f0d870509fe 19 ******************************************************************************
Sergunb 0:8f0d870509fe 20 */
Sergunb 0:8f0d870509fe 21
Sergunb 0:8f0d870509fe 22 /* Includes ------------------------------------------------------------------*/
Sergunb 0:8f0d870509fe 23 #include "stm32f10x_rcc.h"
Sergunb 0:8f0d870509fe 24
Sergunb 0:8f0d870509fe 25 /** @addtogroup STM32F10x_StdPeriph_Driver
Sergunb 0:8f0d870509fe 26 * @{
Sergunb 0:8f0d870509fe 27 */
Sergunb 0:8f0d870509fe 28
Sergunb 0:8f0d870509fe 29 /** @defgroup RCC
Sergunb 0:8f0d870509fe 30 * @brief RCC driver modules
Sergunb 0:8f0d870509fe 31 * @{
Sergunb 0:8f0d870509fe 32 */
Sergunb 0:8f0d870509fe 33
Sergunb 0:8f0d870509fe 34 /** @defgroup RCC_Private_TypesDefinitions
Sergunb 0:8f0d870509fe 35 * @{
Sergunb 0:8f0d870509fe 36 */
Sergunb 0:8f0d870509fe 37
Sergunb 0:8f0d870509fe 38 /**
Sergunb 0:8f0d870509fe 39 * @}
Sergunb 0:8f0d870509fe 40 */
Sergunb 0:8f0d870509fe 41
Sergunb 0:8f0d870509fe 42 /** @defgroup RCC_Private_Defines
Sergunb 0:8f0d870509fe 43 * @{
Sergunb 0:8f0d870509fe 44 */
Sergunb 0:8f0d870509fe 45
Sergunb 0:8f0d870509fe 46 /* ------------ RCC registers bit address in the alias region ----------- */
Sergunb 0:8f0d870509fe 47 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Sergunb 0:8f0d870509fe 48
Sergunb 0:8f0d870509fe 49 /* --- CR Register ---*/
Sergunb 0:8f0d870509fe 50
Sergunb 0:8f0d870509fe 51 /* Alias word address of HSION bit */
Sergunb 0:8f0d870509fe 52 #define CR_OFFSET (RCC_OFFSET + 0x00)
Sergunb 0:8f0d870509fe 53 #define HSION_BitNumber 0x00
Sergunb 0:8f0d870509fe 54 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
Sergunb 0:8f0d870509fe 55
Sergunb 0:8f0d870509fe 56 /* Alias word address of PLLON bit */
Sergunb 0:8f0d870509fe 57 #define PLLON_BitNumber 0x18
Sergunb 0:8f0d870509fe 58 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
Sergunb 0:8f0d870509fe 59
Sergunb 0:8f0d870509fe 60 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 61 /* Alias word address of PLL2ON bit */
Sergunb 0:8f0d870509fe 62 #define PLL2ON_BitNumber 0x1A
Sergunb 0:8f0d870509fe 63 #define CR_PLL2ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL2ON_BitNumber * 4))
Sergunb 0:8f0d870509fe 64
Sergunb 0:8f0d870509fe 65 /* Alias word address of PLL3ON bit */
Sergunb 0:8f0d870509fe 66 #define PLL3ON_BitNumber 0x1C
Sergunb 0:8f0d870509fe 67 #define CR_PLL3ON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLL3ON_BitNumber * 4))
Sergunb 0:8f0d870509fe 68 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 69
Sergunb 0:8f0d870509fe 70 /* Alias word address of CSSON bit */
Sergunb 0:8f0d870509fe 71 #define CSSON_BitNumber 0x13
Sergunb 0:8f0d870509fe 72 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
Sergunb 0:8f0d870509fe 73
Sergunb 0:8f0d870509fe 74 /* --- CFGR Register ---*/
Sergunb 0:8f0d870509fe 75
Sergunb 0:8f0d870509fe 76 /* Alias word address of USBPRE bit */
Sergunb 0:8f0d870509fe 77 #define CFGR_OFFSET (RCC_OFFSET + 0x04)
Sergunb 0:8f0d870509fe 78
Sergunb 0:8f0d870509fe 79 #ifndef STM32F10X_CL
Sergunb 0:8f0d870509fe 80 #define USBPRE_BitNumber 0x16
Sergunb 0:8f0d870509fe 81 #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4))
Sergunb 0:8f0d870509fe 82 #else
Sergunb 0:8f0d870509fe 83 #define OTGFSPRE_BitNumber 0x16
Sergunb 0:8f0d870509fe 84 #define CFGR_OTGFSPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (OTGFSPRE_BitNumber * 4))
Sergunb 0:8f0d870509fe 85 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 86
Sergunb 0:8f0d870509fe 87 /* --- BDCR Register ---*/
Sergunb 0:8f0d870509fe 88
Sergunb 0:8f0d870509fe 89 /* Alias word address of RTCEN bit */
Sergunb 0:8f0d870509fe 90 #define BDCR_OFFSET (RCC_OFFSET + 0x20)
Sergunb 0:8f0d870509fe 91 #define RTCEN_BitNumber 0x0F
Sergunb 0:8f0d870509fe 92 #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
Sergunb 0:8f0d870509fe 93
Sergunb 0:8f0d870509fe 94 /* Alias word address of BDRST bit */
Sergunb 0:8f0d870509fe 95 #define BDRST_BitNumber 0x10
Sergunb 0:8f0d870509fe 96 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
Sergunb 0:8f0d870509fe 97
Sergunb 0:8f0d870509fe 98 /* --- CSR Register ---*/
Sergunb 0:8f0d870509fe 99
Sergunb 0:8f0d870509fe 100 /* Alias word address of LSION bit */
Sergunb 0:8f0d870509fe 101 #define CSR_OFFSET (RCC_OFFSET + 0x24)
Sergunb 0:8f0d870509fe 102 #define LSION_BitNumber 0x00
Sergunb 0:8f0d870509fe 103 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
Sergunb 0:8f0d870509fe 104
Sergunb 0:8f0d870509fe 105 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 106 /* --- CFGR2 Register ---*/
Sergunb 0:8f0d870509fe 107
Sergunb 0:8f0d870509fe 108 /* Alias word address of I2S2SRC bit */
Sergunb 0:8f0d870509fe 109 #define CFGR2_OFFSET (RCC_OFFSET + 0x2C)
Sergunb 0:8f0d870509fe 110 #define I2S2SRC_BitNumber 0x11
Sergunb 0:8f0d870509fe 111 #define CFGR2_I2S2SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S2SRC_BitNumber * 4))
Sergunb 0:8f0d870509fe 112
Sergunb 0:8f0d870509fe 113 /* Alias word address of I2S3SRC bit */
Sergunb 0:8f0d870509fe 114 #define I2S3SRC_BitNumber 0x12
Sergunb 0:8f0d870509fe 115 #define CFGR2_I2S3SRC_BB (PERIPH_BB_BASE + (CFGR2_OFFSET * 32) + (I2S3SRC_BitNumber * 4))
Sergunb 0:8f0d870509fe 116 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 117
Sergunb 0:8f0d870509fe 118 /* ---------------------- RCC registers bit mask ------------------------ */
Sergunb 0:8f0d870509fe 119
Sergunb 0:8f0d870509fe 120 /* CR register bit mask */
Sergunb 0:8f0d870509fe 121 #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
Sergunb 0:8f0d870509fe 122 #define CR_HSEBYP_Set ((uint32_t)0x00040000)
Sergunb 0:8f0d870509fe 123 #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
Sergunb 0:8f0d870509fe 124 #define CR_HSEON_Set ((uint32_t)0x00010000)
Sergunb 0:8f0d870509fe 125 #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
Sergunb 0:8f0d870509fe 126
Sergunb 0:8f0d870509fe 127 /* CFGR register bit mask */
Sergunb 0:8f0d870509fe 128 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
Sergunb 0:8f0d870509fe 129 #define CFGR_PLL_Mask ((uint32_t)0xFFC2FFFF)
Sergunb 0:8f0d870509fe 130 #else
Sergunb 0:8f0d870509fe 131 #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF)
Sergunb 0:8f0d870509fe 132 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 133
Sergunb 0:8f0d870509fe 134 #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000)
Sergunb 0:8f0d870509fe 135 #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000)
Sergunb 0:8f0d870509fe 136 #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000)
Sergunb 0:8f0d870509fe 137 #define CFGR_SWS_Mask ((uint32_t)0x0000000C)
Sergunb 0:8f0d870509fe 138 #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC)
Sergunb 0:8f0d870509fe 139 #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
Sergunb 0:8f0d870509fe 140 #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0)
Sergunb 0:8f0d870509fe 141 #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
Sergunb 0:8f0d870509fe 142 #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700)
Sergunb 0:8f0d870509fe 143 #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
Sergunb 0:8f0d870509fe 144 #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800)
Sergunb 0:8f0d870509fe 145 #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
Sergunb 0:8f0d870509fe 146 #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
Sergunb 0:8f0d870509fe 147
Sergunb 0:8f0d870509fe 148 /* CSR register bit mask */
Sergunb 0:8f0d870509fe 149 #define CSR_RMVF_Set ((uint32_t)0x01000000)
Sergunb 0:8f0d870509fe 150
Sergunb 0:8f0d870509fe 151 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
Sergunb 0:8f0d870509fe 152 /* CFGR2 register bit mask */
Sergunb 0:8f0d870509fe 153 #define CFGR2_PREDIV1SRC ((uint32_t)0x00010000)
Sergunb 0:8f0d870509fe 154 #define CFGR2_PREDIV1 ((uint32_t)0x0000000F)
Sergunb 0:8f0d870509fe 155 #endif
Sergunb 0:8f0d870509fe 156 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 157 #define CFGR2_PREDIV2 ((uint32_t)0x000000F0)
Sergunb 0:8f0d870509fe 158 #define CFGR2_PLL2MUL ((uint32_t)0x00000F00)
Sergunb 0:8f0d870509fe 159 #define CFGR2_PLL3MUL ((uint32_t)0x0000F000)
Sergunb 0:8f0d870509fe 160 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 161
Sergunb 0:8f0d870509fe 162 /* RCC Flag Mask */
Sergunb 0:8f0d870509fe 163 #define FLAG_Mask ((uint8_t)0x1F)
Sergunb 0:8f0d870509fe 164
Sergunb 0:8f0d870509fe 165 /* CIR register byte 2 (Bits[15:8]) base address */
Sergunb 0:8f0d870509fe 166 #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009)
Sergunb 0:8f0d870509fe 167
Sergunb 0:8f0d870509fe 168 /* CIR register byte 3 (Bits[23:16]) base address */
Sergunb 0:8f0d870509fe 169 #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
Sergunb 0:8f0d870509fe 170
Sergunb 0:8f0d870509fe 171 /* CFGR register byte 4 (Bits[31:24]) base address */
Sergunb 0:8f0d870509fe 172 #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007)
Sergunb 0:8f0d870509fe 173
Sergunb 0:8f0d870509fe 174 /* BDCR register base address */
Sergunb 0:8f0d870509fe 175 #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET)
Sergunb 0:8f0d870509fe 176
Sergunb 0:8f0d870509fe 177 /**
Sergunb 0:8f0d870509fe 178 * @}
Sergunb 0:8f0d870509fe 179 */
Sergunb 0:8f0d870509fe 180
Sergunb 0:8f0d870509fe 181 /** @defgroup RCC_Private_Macros
Sergunb 0:8f0d870509fe 182 * @{
Sergunb 0:8f0d870509fe 183 */
Sergunb 0:8f0d870509fe 184
Sergunb 0:8f0d870509fe 185 /**
Sergunb 0:8f0d870509fe 186 * @}
Sergunb 0:8f0d870509fe 187 */
Sergunb 0:8f0d870509fe 188
Sergunb 0:8f0d870509fe 189 /** @defgroup RCC_Private_Variables
Sergunb 0:8f0d870509fe 190 * @{
Sergunb 0:8f0d870509fe 191 */
Sergunb 0:8f0d870509fe 192
Sergunb 0:8f0d870509fe 193 static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
Sergunb 0:8f0d870509fe 194 static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
Sergunb 0:8f0d870509fe 195
Sergunb 0:8f0d870509fe 196 /**
Sergunb 0:8f0d870509fe 197 * @}
Sergunb 0:8f0d870509fe 198 */
Sergunb 0:8f0d870509fe 199
Sergunb 0:8f0d870509fe 200 /** @defgroup RCC_Private_FunctionPrototypes
Sergunb 0:8f0d870509fe 201 * @{
Sergunb 0:8f0d870509fe 202 */
Sergunb 0:8f0d870509fe 203
Sergunb 0:8f0d870509fe 204 /**
Sergunb 0:8f0d870509fe 205 * @}
Sergunb 0:8f0d870509fe 206 */
Sergunb 0:8f0d870509fe 207
Sergunb 0:8f0d870509fe 208 /** @defgroup RCC_Private_Functions
Sergunb 0:8f0d870509fe 209 * @{
Sergunb 0:8f0d870509fe 210 */
Sergunb 0:8f0d870509fe 211
Sergunb 0:8f0d870509fe 212 /**
Sergunb 0:8f0d870509fe 213 * @brief Resets the RCC clock configuration to the default reset state.
Sergunb 0:8f0d870509fe 214 * @param None
Sergunb 0:8f0d870509fe 215 * @retval None
Sergunb 0:8f0d870509fe 216 */
Sergunb 0:8f0d870509fe 217 void RCC_DeInit(void)
Sergunb 0:8f0d870509fe 218 {
Sergunb 0:8f0d870509fe 219 /* Set HSION bit */
Sergunb 0:8f0d870509fe 220 RCC->CR |= (uint32_t)0x00000001;
Sergunb 0:8f0d870509fe 221
Sergunb 0:8f0d870509fe 222 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
Sergunb 0:8f0d870509fe 223 #ifndef STM32F10X_CL
Sergunb 0:8f0d870509fe 224 RCC->CFGR &= (uint32_t)0xF8FF0000;
Sergunb 0:8f0d870509fe 225 #else
Sergunb 0:8f0d870509fe 226 RCC->CFGR &= (uint32_t)0xF0FF0000;
Sergunb 0:8f0d870509fe 227 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 228
Sergunb 0:8f0d870509fe 229 /* Reset HSEON, CSSON and PLLON bits */
Sergunb 0:8f0d870509fe 230 RCC->CR &= (uint32_t)0xFEF6FFFF;
Sergunb 0:8f0d870509fe 231
Sergunb 0:8f0d870509fe 232 /* Reset HSEBYP bit */
Sergunb 0:8f0d870509fe 233 RCC->CR &= (uint32_t)0xFFFBFFFF;
Sergunb 0:8f0d870509fe 234
Sergunb 0:8f0d870509fe 235 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
Sergunb 0:8f0d870509fe 236 RCC->CFGR &= (uint32_t)0xFF80FFFF;
Sergunb 0:8f0d870509fe 237
Sergunb 0:8f0d870509fe 238 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 239 /* Reset PLL2ON and PLL3ON bits */
Sergunb 0:8f0d870509fe 240 RCC->CR &= (uint32_t)0xEBFFFFFF;
Sergunb 0:8f0d870509fe 241
Sergunb 0:8f0d870509fe 242 /* Disable all interrupts and clear pending bits */
Sergunb 0:8f0d870509fe 243 RCC->CIR = 0x00FF0000;
Sergunb 0:8f0d870509fe 244
Sergunb 0:8f0d870509fe 245 /* Reset CFGR2 register */
Sergunb 0:8f0d870509fe 246 RCC->CFGR2 = 0x00000000;
Sergunb 0:8f0d870509fe 247 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 248 /* Disable all interrupts and clear pending bits */
Sergunb 0:8f0d870509fe 249 RCC->CIR = 0x009F0000;
Sergunb 0:8f0d870509fe 250
Sergunb 0:8f0d870509fe 251 /* Reset CFGR2 register */
Sergunb 0:8f0d870509fe 252 RCC->CFGR2 = 0x00000000;
Sergunb 0:8f0d870509fe 253 #else
Sergunb 0:8f0d870509fe 254 /* Disable all interrupts and clear pending bits */
Sergunb 0:8f0d870509fe 255 RCC->CIR = 0x009F0000;
Sergunb 0:8f0d870509fe 256 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 257
Sergunb 0:8f0d870509fe 258 }
Sergunb 0:8f0d870509fe 259
Sergunb 0:8f0d870509fe 260 /**
Sergunb 0:8f0d870509fe 261 * @brief Configures the External High Speed oscillator (HSE).
Sergunb 0:8f0d870509fe 262 * @note HSE can not be stopped if it is used directly or through the PLL as system clock.
Sergunb 0:8f0d870509fe 263 * @param RCC_HSE: specifies the new state of the HSE.
Sergunb 0:8f0d870509fe 264 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 265 * @arg RCC_HSE_OFF: HSE oscillator OFF
Sergunb 0:8f0d870509fe 266 * @arg RCC_HSE_ON: HSE oscillator ON
Sergunb 0:8f0d870509fe 267 * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
Sergunb 0:8f0d870509fe 268 * @retval None
Sergunb 0:8f0d870509fe 269 */
Sergunb 0:8f0d870509fe 270 void RCC_HSEConfig(uint32_t RCC_HSE)
Sergunb 0:8f0d870509fe 271 {
Sergunb 0:8f0d870509fe 272 /* Check the parameters */
Sergunb 0:8f0d870509fe 273 assert_param(IS_RCC_HSE(RCC_HSE));
Sergunb 0:8f0d870509fe 274 /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
Sergunb 0:8f0d870509fe 275 /* Reset HSEON bit */
Sergunb 0:8f0d870509fe 276 RCC->CR &= CR_HSEON_Reset;
Sergunb 0:8f0d870509fe 277 /* Reset HSEBYP bit */
Sergunb 0:8f0d870509fe 278 RCC->CR &= CR_HSEBYP_Reset;
Sergunb 0:8f0d870509fe 279 /* Configure HSE (RCC_HSE_OFF is already covered by the code section above) */
Sergunb 0:8f0d870509fe 280 switch(RCC_HSE)
Sergunb 0:8f0d870509fe 281 {
Sergunb 0:8f0d870509fe 282 case RCC_HSE_ON:
Sergunb 0:8f0d870509fe 283 /* Set HSEON bit */
Sergunb 0:8f0d870509fe 284 RCC->CR |= CR_HSEON_Set;
Sergunb 0:8f0d870509fe 285 break;
Sergunb 0:8f0d870509fe 286
Sergunb 0:8f0d870509fe 287 case RCC_HSE_Bypass:
Sergunb 0:8f0d870509fe 288 /* Set HSEBYP and HSEON bits */
Sergunb 0:8f0d870509fe 289 RCC->CR |= CR_HSEBYP_Set | CR_HSEON_Set;
Sergunb 0:8f0d870509fe 290 break;
Sergunb 0:8f0d870509fe 291
Sergunb 0:8f0d870509fe 292 default:
Sergunb 0:8f0d870509fe 293 break;
Sergunb 0:8f0d870509fe 294 }
Sergunb 0:8f0d870509fe 295 }
Sergunb 0:8f0d870509fe 296
Sergunb 0:8f0d870509fe 297 /**
Sergunb 0:8f0d870509fe 298 * @brief Waits for HSE start-up.
Sergunb 0:8f0d870509fe 299 * @param None
Sergunb 0:8f0d870509fe 300 * @retval An ErrorStatus enumuration value:
Sergunb 0:8f0d870509fe 301 * - SUCCESS: HSE oscillator is stable and ready to use
Sergunb 0:8f0d870509fe 302 * - ERROR: HSE oscillator not yet ready
Sergunb 0:8f0d870509fe 303 */
Sergunb 0:8f0d870509fe 304 ErrorStatus RCC_WaitForHSEStartUp(void)
Sergunb 0:8f0d870509fe 305 {
Sergunb 0:8f0d870509fe 306 __IO uint32_t StartUpCounter = 0;
Sergunb 0:8f0d870509fe 307 ErrorStatus status = ERROR;
Sergunb 0:8f0d870509fe 308 FlagStatus HSEStatus = RESET;
Sergunb 0:8f0d870509fe 309
Sergunb 0:8f0d870509fe 310 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:8f0d870509fe 311 do
Sergunb 0:8f0d870509fe 312 {
Sergunb 0:8f0d870509fe 313 HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
Sergunb 0:8f0d870509fe 314 StartUpCounter++;
Sergunb 0:8f0d870509fe 315 } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
Sergunb 0:8f0d870509fe 316
Sergunb 0:8f0d870509fe 317 if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
Sergunb 0:8f0d870509fe 318 {
Sergunb 0:8f0d870509fe 319 status = SUCCESS;
Sergunb 0:8f0d870509fe 320 }
Sergunb 0:8f0d870509fe 321 else
Sergunb 0:8f0d870509fe 322 {
Sergunb 0:8f0d870509fe 323 status = ERROR;
Sergunb 0:8f0d870509fe 324 }
Sergunb 0:8f0d870509fe 325 return (status);
Sergunb 0:8f0d870509fe 326 }
Sergunb 0:8f0d870509fe 327
Sergunb 0:8f0d870509fe 328 /**
Sergunb 0:8f0d870509fe 329 * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
Sergunb 0:8f0d870509fe 330 * @param HSICalibrationValue: specifies the calibration trimming value.
Sergunb 0:8f0d870509fe 331 * This parameter must be a number between 0 and 0x1F.
Sergunb 0:8f0d870509fe 332 * @retval None
Sergunb 0:8f0d870509fe 333 */
Sergunb 0:8f0d870509fe 334 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
Sergunb 0:8f0d870509fe 335 {
Sergunb 0:8f0d870509fe 336 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 337 /* Check the parameters */
Sergunb 0:8f0d870509fe 338 assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
Sergunb 0:8f0d870509fe 339 tmpreg = RCC->CR;
Sergunb 0:8f0d870509fe 340 /* Clear HSITRIM[4:0] bits */
Sergunb 0:8f0d870509fe 341 tmpreg &= CR_HSITRIM_Mask;
Sergunb 0:8f0d870509fe 342 /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
Sergunb 0:8f0d870509fe 343 tmpreg |= (uint32_t)HSICalibrationValue << 3;
Sergunb 0:8f0d870509fe 344 /* Store the new value */
Sergunb 0:8f0d870509fe 345 RCC->CR = tmpreg;
Sergunb 0:8f0d870509fe 346 }
Sergunb 0:8f0d870509fe 347
Sergunb 0:8f0d870509fe 348 /**
Sergunb 0:8f0d870509fe 349 * @brief Enables or disables the Internal High Speed oscillator (HSI).
Sergunb 0:8f0d870509fe 350 * @note HSI can not be stopped if it is used directly or through the PLL as system clock.
Sergunb 0:8f0d870509fe 351 * @param NewState: new state of the HSI. This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 352 * @retval None
Sergunb 0:8f0d870509fe 353 */
Sergunb 0:8f0d870509fe 354 void RCC_HSICmd(FunctionalState NewState)
Sergunb 0:8f0d870509fe 355 {
Sergunb 0:8f0d870509fe 356 /* Check the parameters */
Sergunb 0:8f0d870509fe 357 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 358 *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
Sergunb 0:8f0d870509fe 359 }
Sergunb 0:8f0d870509fe 360
Sergunb 0:8f0d870509fe 361 /**
Sergunb 0:8f0d870509fe 362 * @brief Configures the PLL clock source and multiplication factor.
Sergunb 0:8f0d870509fe 363 * @note This function must be used only when the PLL is disabled.
Sergunb 0:8f0d870509fe 364 * @param RCC_PLLSource: specifies the PLL entry clock source.
Sergunb 0:8f0d870509fe 365 * For @b STM32_Connectivity_line_devices or @b STM32_Value_line_devices,
Sergunb 0:8f0d870509fe 366 * this parameter can be one of the following values:
Sergunb 0:8f0d870509fe 367 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
Sergunb 0:8f0d870509fe 368 * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
Sergunb 0:8f0d870509fe 369 * For @b other_STM32_devices, this parameter can be one of the following values:
Sergunb 0:8f0d870509fe 370 * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock divided by 2 selected as PLL clock entry
Sergunb 0:8f0d870509fe 371 * @arg RCC_PLLSource_HSE_Div1: HSE oscillator clock selected as PLL clock entry
Sergunb 0:8f0d870509fe 372 * @arg RCC_PLLSource_HSE_Div2: HSE oscillator clock divided by 2 selected as PLL clock entry
Sergunb 0:8f0d870509fe 373 * @param RCC_PLLMul: specifies the PLL multiplication factor.
Sergunb 0:8f0d870509fe 374 * For @b STM32_Connectivity_line_devices, this parameter can be RCC_PLLMul_x where x:{[4,9], 6_5}
Sergunb 0:8f0d870509fe 375 * For @b other_STM32_devices, this parameter can be RCC_PLLMul_x where x:[2,16]
Sergunb 0:8f0d870509fe 376 * @retval None
Sergunb 0:8f0d870509fe 377 */
Sergunb 0:8f0d870509fe 378 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
Sergunb 0:8f0d870509fe 379 {
Sergunb 0:8f0d870509fe 380 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 381
Sergunb 0:8f0d870509fe 382 /* Check the parameters */
Sergunb 0:8f0d870509fe 383 assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
Sergunb 0:8f0d870509fe 384 assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
Sergunb 0:8f0d870509fe 385
Sergunb 0:8f0d870509fe 386 tmpreg = RCC->CFGR;
Sergunb 0:8f0d870509fe 387 /* Clear PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
Sergunb 0:8f0d870509fe 388 tmpreg &= CFGR_PLL_Mask;
Sergunb 0:8f0d870509fe 389 /* Set the PLL configuration bits */
Sergunb 0:8f0d870509fe 390 tmpreg |= RCC_PLLSource | RCC_PLLMul;
Sergunb 0:8f0d870509fe 391 /* Store the new value */
Sergunb 0:8f0d870509fe 392 RCC->CFGR = tmpreg;
Sergunb 0:8f0d870509fe 393 }
Sergunb 0:8f0d870509fe 394
Sergunb 0:8f0d870509fe 395 /**
Sergunb 0:8f0d870509fe 396 * @brief Enables or disables the PLL.
Sergunb 0:8f0d870509fe 397 * @note The PLL can not be disabled if it is used as system clock.
Sergunb 0:8f0d870509fe 398 * @param NewState: new state of the PLL. This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 399 * @retval None
Sergunb 0:8f0d870509fe 400 */
Sergunb 0:8f0d870509fe 401 void RCC_PLLCmd(FunctionalState NewState)
Sergunb 0:8f0d870509fe 402 {
Sergunb 0:8f0d870509fe 403 /* Check the parameters */
Sergunb 0:8f0d870509fe 404 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 405
Sergunb 0:8f0d870509fe 406 *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
Sergunb 0:8f0d870509fe 407 }
Sergunb 0:8f0d870509fe 408
Sergunb 0:8f0d870509fe 409 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) || defined (STM32F10X_CL)
Sergunb 0:8f0d870509fe 410 /**
Sergunb 0:8f0d870509fe 411 * @brief Configures the PREDIV1 division factor.
Sergunb 0:8f0d870509fe 412 * @note
Sergunb 0:8f0d870509fe 413 * - This function must be used only when the PLL is disabled.
Sergunb 0:8f0d870509fe 414 * - This function applies only to STM32 Connectivity line and Value line
Sergunb 0:8f0d870509fe 415 * devices.
Sergunb 0:8f0d870509fe 416 * @param RCC_PREDIV1_Source: specifies the PREDIV1 clock source.
Sergunb 0:8f0d870509fe 417 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 418 * @arg RCC_PREDIV1_Source_HSE: HSE selected as PREDIV1 clock
Sergunb 0:8f0d870509fe 419 * @arg RCC_PREDIV1_Source_PLL2: PLL2 selected as PREDIV1 clock
Sergunb 0:8f0d870509fe 420 * @note
Sergunb 0:8f0d870509fe 421 * For @b STM32_Value_line_devices this parameter is always RCC_PREDIV1_Source_HSE
Sergunb 0:8f0d870509fe 422 * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
Sergunb 0:8f0d870509fe 423 * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
Sergunb 0:8f0d870509fe 424 * @retval None
Sergunb 0:8f0d870509fe 425 */
Sergunb 0:8f0d870509fe 426 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div)
Sergunb 0:8f0d870509fe 427 {
Sergunb 0:8f0d870509fe 428 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 429
Sergunb 0:8f0d870509fe 430 /* Check the parameters */
Sergunb 0:8f0d870509fe 431 assert_param(IS_RCC_PREDIV1_SOURCE(RCC_PREDIV1_Source));
Sergunb 0:8f0d870509fe 432 assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
Sergunb 0:8f0d870509fe 433
Sergunb 0:8f0d870509fe 434 tmpreg = RCC->CFGR2;
Sergunb 0:8f0d870509fe 435 /* Clear PREDIV1[3:0] and PREDIV1SRC bits */
Sergunb 0:8f0d870509fe 436 tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC);
Sergunb 0:8f0d870509fe 437 /* Set the PREDIV1 clock source and division factor */
Sergunb 0:8f0d870509fe 438 tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div ;
Sergunb 0:8f0d870509fe 439 /* Store the new value */
Sergunb 0:8f0d870509fe 440 RCC->CFGR2 = tmpreg;
Sergunb 0:8f0d870509fe 441 }
Sergunb 0:8f0d870509fe 442 #endif
Sergunb 0:8f0d870509fe 443
Sergunb 0:8f0d870509fe 444 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 445 /**
Sergunb 0:8f0d870509fe 446 * @brief Configures the PREDIV2 division factor.
Sergunb 0:8f0d870509fe 447 * @note
Sergunb 0:8f0d870509fe 448 * - This function must be used only when both PLL2 and PLL3 are disabled.
Sergunb 0:8f0d870509fe 449 * - This function applies only to STM32 Connectivity line devices.
Sergunb 0:8f0d870509fe 450 * @param RCC_PREDIV2_Div: specifies the PREDIV2 clock division factor.
Sergunb 0:8f0d870509fe 451 * This parameter can be RCC_PREDIV2_Divx where x:[1,16]
Sergunb 0:8f0d870509fe 452 * @retval None
Sergunb 0:8f0d870509fe 453 */
Sergunb 0:8f0d870509fe 454 void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div)
Sergunb 0:8f0d870509fe 455 {
Sergunb 0:8f0d870509fe 456 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 457
Sergunb 0:8f0d870509fe 458 /* Check the parameters */
Sergunb 0:8f0d870509fe 459 assert_param(IS_RCC_PREDIV2(RCC_PREDIV2_Div));
Sergunb 0:8f0d870509fe 460
Sergunb 0:8f0d870509fe 461 tmpreg = RCC->CFGR2;
Sergunb 0:8f0d870509fe 462 /* Clear PREDIV2[3:0] bits */
Sergunb 0:8f0d870509fe 463 tmpreg &= ~CFGR2_PREDIV2;
Sergunb 0:8f0d870509fe 464 /* Set the PREDIV2 division factor */
Sergunb 0:8f0d870509fe 465 tmpreg |= RCC_PREDIV2_Div;
Sergunb 0:8f0d870509fe 466 /* Store the new value */
Sergunb 0:8f0d870509fe 467 RCC->CFGR2 = tmpreg;
Sergunb 0:8f0d870509fe 468 }
Sergunb 0:8f0d870509fe 469
Sergunb 0:8f0d870509fe 470 /**
Sergunb 0:8f0d870509fe 471 * @brief Configures the PLL2 multiplication factor.
Sergunb 0:8f0d870509fe 472 * @note
Sergunb 0:8f0d870509fe 473 * - This function must be used only when the PLL2 is disabled.
Sergunb 0:8f0d870509fe 474 * - This function applies only to STM32 Connectivity line devices.
Sergunb 0:8f0d870509fe 475 * @param RCC_PLL2Mul: specifies the PLL2 multiplication factor.
Sergunb 0:8f0d870509fe 476 * This parameter can be RCC_PLL2Mul_x where x:{[8,14], 16, 20}
Sergunb 0:8f0d870509fe 477 * @retval None
Sergunb 0:8f0d870509fe 478 */
Sergunb 0:8f0d870509fe 479 void RCC_PLL2Config(uint32_t RCC_PLL2Mul)
Sergunb 0:8f0d870509fe 480 {
Sergunb 0:8f0d870509fe 481 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 482
Sergunb 0:8f0d870509fe 483 /* Check the parameters */
Sergunb 0:8f0d870509fe 484 assert_param(IS_RCC_PLL2_MUL(RCC_PLL2Mul));
Sergunb 0:8f0d870509fe 485
Sergunb 0:8f0d870509fe 486 tmpreg = RCC->CFGR2;
Sergunb 0:8f0d870509fe 487 /* Clear PLL2Mul[3:0] bits */
Sergunb 0:8f0d870509fe 488 tmpreg &= ~CFGR2_PLL2MUL;
Sergunb 0:8f0d870509fe 489 /* Set the PLL2 configuration bits */
Sergunb 0:8f0d870509fe 490 tmpreg |= RCC_PLL2Mul;
Sergunb 0:8f0d870509fe 491 /* Store the new value */
Sergunb 0:8f0d870509fe 492 RCC->CFGR2 = tmpreg;
Sergunb 0:8f0d870509fe 493 }
Sergunb 0:8f0d870509fe 494
Sergunb 0:8f0d870509fe 495
Sergunb 0:8f0d870509fe 496 /**
Sergunb 0:8f0d870509fe 497 * @brief Enables or disables the PLL2.
Sergunb 0:8f0d870509fe 498 * @note
Sergunb 0:8f0d870509fe 499 * - The PLL2 can not be disabled if it is used indirectly as system clock
Sergunb 0:8f0d870509fe 500 * (i.e. it is used as PLL clock entry that is used as System clock).
Sergunb 0:8f0d870509fe 501 * - This function applies only to STM32 Connectivity line devices.
Sergunb 0:8f0d870509fe 502 * @param NewState: new state of the PLL2. This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 503 * @retval None
Sergunb 0:8f0d870509fe 504 */
Sergunb 0:8f0d870509fe 505 void RCC_PLL2Cmd(FunctionalState NewState)
Sergunb 0:8f0d870509fe 506 {
Sergunb 0:8f0d870509fe 507 /* Check the parameters */
Sergunb 0:8f0d870509fe 508 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 509
Sergunb 0:8f0d870509fe 510 *(__IO uint32_t *) CR_PLL2ON_BB = (uint32_t)NewState;
Sergunb 0:8f0d870509fe 511 }
Sergunb 0:8f0d870509fe 512
Sergunb 0:8f0d870509fe 513
Sergunb 0:8f0d870509fe 514 /**
Sergunb 0:8f0d870509fe 515 * @brief Configures the PLL3 multiplication factor.
Sergunb 0:8f0d870509fe 516 * @note
Sergunb 0:8f0d870509fe 517 * - This function must be used only when the PLL3 is disabled.
Sergunb 0:8f0d870509fe 518 * - This function applies only to STM32 Connectivity line devices.
Sergunb 0:8f0d870509fe 519 * @param RCC_PLL3Mul: specifies the PLL3 multiplication factor.
Sergunb 0:8f0d870509fe 520 * This parameter can be RCC_PLL3Mul_x where x:{[8,14], 16, 20}
Sergunb 0:8f0d870509fe 521 * @retval None
Sergunb 0:8f0d870509fe 522 */
Sergunb 0:8f0d870509fe 523 void RCC_PLL3Config(uint32_t RCC_PLL3Mul)
Sergunb 0:8f0d870509fe 524 {
Sergunb 0:8f0d870509fe 525 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 526
Sergunb 0:8f0d870509fe 527 /* Check the parameters */
Sergunb 0:8f0d870509fe 528 assert_param(IS_RCC_PLL3_MUL(RCC_PLL3Mul));
Sergunb 0:8f0d870509fe 529
Sergunb 0:8f0d870509fe 530 tmpreg = RCC->CFGR2;
Sergunb 0:8f0d870509fe 531 /* Clear PLL3Mul[3:0] bits */
Sergunb 0:8f0d870509fe 532 tmpreg &= ~CFGR2_PLL3MUL;
Sergunb 0:8f0d870509fe 533 /* Set the PLL3 configuration bits */
Sergunb 0:8f0d870509fe 534 tmpreg |= RCC_PLL3Mul;
Sergunb 0:8f0d870509fe 535 /* Store the new value */
Sergunb 0:8f0d870509fe 536 RCC->CFGR2 = tmpreg;
Sergunb 0:8f0d870509fe 537 }
Sergunb 0:8f0d870509fe 538
Sergunb 0:8f0d870509fe 539
Sergunb 0:8f0d870509fe 540 /**
Sergunb 0:8f0d870509fe 541 * @brief Enables or disables the PLL3.
Sergunb 0:8f0d870509fe 542 * @note This function applies only to STM32 Connectivity line devices.
Sergunb 0:8f0d870509fe 543 * @param NewState: new state of the PLL3. This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 544 * @retval None
Sergunb 0:8f0d870509fe 545 */
Sergunb 0:8f0d870509fe 546 void RCC_PLL3Cmd(FunctionalState NewState)
Sergunb 0:8f0d870509fe 547 {
Sergunb 0:8f0d870509fe 548 /* Check the parameters */
Sergunb 0:8f0d870509fe 549
Sergunb 0:8f0d870509fe 550 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 551 *(__IO uint32_t *) CR_PLL3ON_BB = (uint32_t)NewState;
Sergunb 0:8f0d870509fe 552 }
Sergunb 0:8f0d870509fe 553 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 554
Sergunb 0:8f0d870509fe 555 /**
Sergunb 0:8f0d870509fe 556 * @brief Configures the system clock (SYSCLK).
Sergunb 0:8f0d870509fe 557 * @param RCC_SYSCLKSource: specifies the clock source used as system clock.
Sergunb 0:8f0d870509fe 558 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 559 * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock
Sergunb 0:8f0d870509fe 560 * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock
Sergunb 0:8f0d870509fe 561 * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
Sergunb 0:8f0d870509fe 562 * @retval None
Sergunb 0:8f0d870509fe 563 */
Sergunb 0:8f0d870509fe 564 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
Sergunb 0:8f0d870509fe 565 {
Sergunb 0:8f0d870509fe 566 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 567 /* Check the parameters */
Sergunb 0:8f0d870509fe 568 assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
Sergunb 0:8f0d870509fe 569 tmpreg = RCC->CFGR;
Sergunb 0:8f0d870509fe 570 /* Clear SW[1:0] bits */
Sergunb 0:8f0d870509fe 571 tmpreg &= CFGR_SW_Mask;
Sergunb 0:8f0d870509fe 572 /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
Sergunb 0:8f0d870509fe 573 tmpreg |= RCC_SYSCLKSource;
Sergunb 0:8f0d870509fe 574 /* Store the new value */
Sergunb 0:8f0d870509fe 575 RCC->CFGR = tmpreg;
Sergunb 0:8f0d870509fe 576 }
Sergunb 0:8f0d870509fe 577
Sergunb 0:8f0d870509fe 578 /**
Sergunb 0:8f0d870509fe 579 * @brief Returns the clock source used as system clock.
Sergunb 0:8f0d870509fe 580 * @param None
Sergunb 0:8f0d870509fe 581 * @retval The clock source used as system clock. The returned value can
Sergunb 0:8f0d870509fe 582 * be one of the following:
Sergunb 0:8f0d870509fe 583 * - 0x00: HSI used as system clock
Sergunb 0:8f0d870509fe 584 * - 0x04: HSE used as system clock
Sergunb 0:8f0d870509fe 585 * - 0x08: PLL used as system clock
Sergunb 0:8f0d870509fe 586 */
Sergunb 0:8f0d870509fe 587 uint8_t RCC_GetSYSCLKSource(void)
Sergunb 0:8f0d870509fe 588 {
Sergunb 0:8f0d870509fe 589 return ((uint8_t)(RCC->CFGR & CFGR_SWS_Mask));
Sergunb 0:8f0d870509fe 590 }
Sergunb 0:8f0d870509fe 591
Sergunb 0:8f0d870509fe 592 /**
Sergunb 0:8f0d870509fe 593 * @brief Configures the AHB clock (HCLK).
Sergunb 0:8f0d870509fe 594 * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
Sergunb 0:8f0d870509fe 595 * the system clock (SYSCLK).
Sergunb 0:8f0d870509fe 596 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 597 * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
Sergunb 0:8f0d870509fe 598 * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
Sergunb 0:8f0d870509fe 599 * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
Sergunb 0:8f0d870509fe 600 * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
Sergunb 0:8f0d870509fe 601 * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
Sergunb 0:8f0d870509fe 602 * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
Sergunb 0:8f0d870509fe 603 * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
Sergunb 0:8f0d870509fe 604 * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
Sergunb 0:8f0d870509fe 605 * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Sergunb 0:8f0d870509fe 606 * @retval None
Sergunb 0:8f0d870509fe 607 */
Sergunb 0:8f0d870509fe 608 void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
Sergunb 0:8f0d870509fe 609 {
Sergunb 0:8f0d870509fe 610 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 611 /* Check the parameters */
Sergunb 0:8f0d870509fe 612 assert_param(IS_RCC_HCLK(RCC_SYSCLK));
Sergunb 0:8f0d870509fe 613 tmpreg = RCC->CFGR;
Sergunb 0:8f0d870509fe 614 /* Clear HPRE[3:0] bits */
Sergunb 0:8f0d870509fe 615 tmpreg &= CFGR_HPRE_Reset_Mask;
Sergunb 0:8f0d870509fe 616 /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
Sergunb 0:8f0d870509fe 617 tmpreg |= RCC_SYSCLK;
Sergunb 0:8f0d870509fe 618 /* Store the new value */
Sergunb 0:8f0d870509fe 619 RCC->CFGR = tmpreg;
Sergunb 0:8f0d870509fe 620 }
Sergunb 0:8f0d870509fe 621
Sergunb 0:8f0d870509fe 622 /**
Sergunb 0:8f0d870509fe 623 * @brief Configures the Low Speed APB clock (PCLK1).
Sergunb 0:8f0d870509fe 624 * @param RCC_HCLK: defines the APB1 clock divider. This clock is derived from
Sergunb 0:8f0d870509fe 625 * the AHB clock (HCLK).
Sergunb 0:8f0d870509fe 626 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 627 * @arg RCC_HCLK_Div1: APB1 clock = HCLK
Sergunb 0:8f0d870509fe 628 * @arg RCC_HCLK_Div2: APB1 clock = HCLK/2
Sergunb 0:8f0d870509fe 629 * @arg RCC_HCLK_Div4: APB1 clock = HCLK/4
Sergunb 0:8f0d870509fe 630 * @arg RCC_HCLK_Div8: APB1 clock = HCLK/8
Sergunb 0:8f0d870509fe 631 * @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
Sergunb 0:8f0d870509fe 632 * @retval None
Sergunb 0:8f0d870509fe 633 */
Sergunb 0:8f0d870509fe 634 void RCC_PCLK1Config(uint32_t RCC_HCLK)
Sergunb 0:8f0d870509fe 635 {
Sergunb 0:8f0d870509fe 636 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 637 /* Check the parameters */
Sergunb 0:8f0d870509fe 638 assert_param(IS_RCC_PCLK(RCC_HCLK));
Sergunb 0:8f0d870509fe 639 tmpreg = RCC->CFGR;
Sergunb 0:8f0d870509fe 640 /* Clear PPRE1[2:0] bits */
Sergunb 0:8f0d870509fe 641 tmpreg &= CFGR_PPRE1_Reset_Mask;
Sergunb 0:8f0d870509fe 642 /* Set PPRE1[2:0] bits according to RCC_HCLK value */
Sergunb 0:8f0d870509fe 643 tmpreg |= RCC_HCLK;
Sergunb 0:8f0d870509fe 644 /* Store the new value */
Sergunb 0:8f0d870509fe 645 RCC->CFGR = tmpreg;
Sergunb 0:8f0d870509fe 646 }
Sergunb 0:8f0d870509fe 647
Sergunb 0:8f0d870509fe 648 /**
Sergunb 0:8f0d870509fe 649 * @brief Configures the High Speed APB clock (PCLK2).
Sergunb 0:8f0d870509fe 650 * @param RCC_HCLK: defines the APB2 clock divider. This clock is derived from
Sergunb 0:8f0d870509fe 651 * the AHB clock (HCLK).
Sergunb 0:8f0d870509fe 652 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 653 * @arg RCC_HCLK_Div1: APB2 clock = HCLK
Sergunb 0:8f0d870509fe 654 * @arg RCC_HCLK_Div2: APB2 clock = HCLK/2
Sergunb 0:8f0d870509fe 655 * @arg RCC_HCLK_Div4: APB2 clock = HCLK/4
Sergunb 0:8f0d870509fe 656 * @arg RCC_HCLK_Div8: APB2 clock = HCLK/8
Sergunb 0:8f0d870509fe 657 * @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
Sergunb 0:8f0d870509fe 658 * @retval None
Sergunb 0:8f0d870509fe 659 */
Sergunb 0:8f0d870509fe 660 void RCC_PCLK2Config(uint32_t RCC_HCLK)
Sergunb 0:8f0d870509fe 661 {
Sergunb 0:8f0d870509fe 662 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 663 /* Check the parameters */
Sergunb 0:8f0d870509fe 664 assert_param(IS_RCC_PCLK(RCC_HCLK));
Sergunb 0:8f0d870509fe 665 tmpreg = RCC->CFGR;
Sergunb 0:8f0d870509fe 666 /* Clear PPRE2[2:0] bits */
Sergunb 0:8f0d870509fe 667 tmpreg &= CFGR_PPRE2_Reset_Mask;
Sergunb 0:8f0d870509fe 668 /* Set PPRE2[2:0] bits according to RCC_HCLK value */
Sergunb 0:8f0d870509fe 669 tmpreg |= RCC_HCLK << 3;
Sergunb 0:8f0d870509fe 670 /* Store the new value */
Sergunb 0:8f0d870509fe 671 RCC->CFGR = tmpreg;
Sergunb 0:8f0d870509fe 672 }
Sergunb 0:8f0d870509fe 673
Sergunb 0:8f0d870509fe 674 /**
Sergunb 0:8f0d870509fe 675 * @brief Enables or disables the specified RCC interrupts.
Sergunb 0:8f0d870509fe 676 * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
Sergunb 0:8f0d870509fe 677 *
Sergunb 0:8f0d870509fe 678 * For @b STM32_Connectivity_line_devices, this parameter can be any combination
Sergunb 0:8f0d870509fe 679 * of the following values
Sergunb 0:8f0d870509fe 680 * @arg RCC_IT_LSIRDY: LSI ready interrupt
Sergunb 0:8f0d870509fe 681 * @arg RCC_IT_LSERDY: LSE ready interrupt
Sergunb 0:8f0d870509fe 682 * @arg RCC_IT_HSIRDY: HSI ready interrupt
Sergunb 0:8f0d870509fe 683 * @arg RCC_IT_HSERDY: HSE ready interrupt
Sergunb 0:8f0d870509fe 684 * @arg RCC_IT_PLLRDY: PLL ready interrupt
Sergunb 0:8f0d870509fe 685 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
Sergunb 0:8f0d870509fe 686 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
Sergunb 0:8f0d870509fe 687 *
Sergunb 0:8f0d870509fe 688 * For @b other_STM32_devices, this parameter can be any combination of the
Sergunb 0:8f0d870509fe 689 * following values
Sergunb 0:8f0d870509fe 690 * @arg RCC_IT_LSIRDY: LSI ready interrupt
Sergunb 0:8f0d870509fe 691 * @arg RCC_IT_LSERDY: LSE ready interrupt
Sergunb 0:8f0d870509fe 692 * @arg RCC_IT_HSIRDY: HSI ready interrupt
Sergunb 0:8f0d870509fe 693 * @arg RCC_IT_HSERDY: HSE ready interrupt
Sergunb 0:8f0d870509fe 694 * @arg RCC_IT_PLLRDY: PLL ready interrupt
Sergunb 0:8f0d870509fe 695 *
Sergunb 0:8f0d870509fe 696 * @param NewState: new state of the specified RCC interrupts.
Sergunb 0:8f0d870509fe 697 * This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 698 * @retval None
Sergunb 0:8f0d870509fe 699 */
Sergunb 0:8f0d870509fe 700 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
Sergunb 0:8f0d870509fe 701 {
Sergunb 0:8f0d870509fe 702 /* Check the parameters */
Sergunb 0:8f0d870509fe 703 assert_param(IS_RCC_IT(RCC_IT));
Sergunb 0:8f0d870509fe 704 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 705 if (NewState != DISABLE)
Sergunb 0:8f0d870509fe 706 {
Sergunb 0:8f0d870509fe 707 /* Perform Byte access to RCC_CIR bits to enable the selected interrupts */
Sergunb 0:8f0d870509fe 708 *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
Sergunb 0:8f0d870509fe 709 }
Sergunb 0:8f0d870509fe 710 else
Sergunb 0:8f0d870509fe 711 {
Sergunb 0:8f0d870509fe 712 /* Perform Byte access to RCC_CIR bits to disable the selected interrupts */
Sergunb 0:8f0d870509fe 713 *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
Sergunb 0:8f0d870509fe 714 }
Sergunb 0:8f0d870509fe 715 }
Sergunb 0:8f0d870509fe 716
Sergunb 0:8f0d870509fe 717 #ifndef STM32F10X_CL
Sergunb 0:8f0d870509fe 718 /**
Sergunb 0:8f0d870509fe 719 * @brief Configures the USB clock (USBCLK).
Sergunb 0:8f0d870509fe 720 * @param RCC_USBCLKSource: specifies the USB clock source. This clock is
Sergunb 0:8f0d870509fe 721 * derived from the PLL output.
Sergunb 0:8f0d870509fe 722 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 723 * @arg RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
Sergunb 0:8f0d870509fe 724 * clock source
Sergunb 0:8f0d870509fe 725 * @arg RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source
Sergunb 0:8f0d870509fe 726 * @retval None
Sergunb 0:8f0d870509fe 727 */
Sergunb 0:8f0d870509fe 728 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
Sergunb 0:8f0d870509fe 729 {
Sergunb 0:8f0d870509fe 730 /* Check the parameters */
Sergunb 0:8f0d870509fe 731 assert_param(IS_RCC_USBCLK_SOURCE(RCC_USBCLKSource));
Sergunb 0:8f0d870509fe 732
Sergunb 0:8f0d870509fe 733 *(__IO uint32_t *) CFGR_USBPRE_BB = RCC_USBCLKSource;
Sergunb 0:8f0d870509fe 734 }
Sergunb 0:8f0d870509fe 735 #else
Sergunb 0:8f0d870509fe 736 /**
Sergunb 0:8f0d870509fe 737 * @brief Configures the USB OTG FS clock (OTGFSCLK).
Sergunb 0:8f0d870509fe 738 * This function applies only to STM32 Connectivity line devices.
Sergunb 0:8f0d870509fe 739 * @param RCC_OTGFSCLKSource: specifies the USB OTG FS clock source.
Sergunb 0:8f0d870509fe 740 * This clock is derived from the PLL output.
Sergunb 0:8f0d870509fe 741 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 742 * @arg RCC_OTGFSCLKSource_PLLVCO_Div3: PLL VCO clock divided by 2 selected as USB OTG FS clock source
Sergunb 0:8f0d870509fe 743 * @arg RCC_OTGFSCLKSource_PLLVCO_Div2: PLL VCO clock divided by 2 selected as USB OTG FS clock source
Sergunb 0:8f0d870509fe 744 * @retval None
Sergunb 0:8f0d870509fe 745 */
Sergunb 0:8f0d870509fe 746 void RCC_OTGFSCLKConfig(uint32_t RCC_OTGFSCLKSource)
Sergunb 0:8f0d870509fe 747 {
Sergunb 0:8f0d870509fe 748 /* Check the parameters */
Sergunb 0:8f0d870509fe 749 assert_param(IS_RCC_OTGFSCLK_SOURCE(RCC_OTGFSCLKSource));
Sergunb 0:8f0d870509fe 750
Sergunb 0:8f0d870509fe 751 *(__IO uint32_t *) CFGR_OTGFSPRE_BB = RCC_OTGFSCLKSource;
Sergunb 0:8f0d870509fe 752 }
Sergunb 0:8f0d870509fe 753 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 754
Sergunb 0:8f0d870509fe 755 /**
Sergunb 0:8f0d870509fe 756 * @brief Configures the ADC clock (ADCCLK).
Sergunb 0:8f0d870509fe 757 * @param RCC_PCLK2: defines the ADC clock divider. This clock is derived from
Sergunb 0:8f0d870509fe 758 * the APB2 clock (PCLK2).
Sergunb 0:8f0d870509fe 759 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 760 * @arg RCC_PCLK2_Div2: ADC clock = PCLK2/2
Sergunb 0:8f0d870509fe 761 * @arg RCC_PCLK2_Div4: ADC clock = PCLK2/4
Sergunb 0:8f0d870509fe 762 * @arg RCC_PCLK2_Div6: ADC clock = PCLK2/6
Sergunb 0:8f0d870509fe 763 * @arg RCC_PCLK2_Div8: ADC clock = PCLK2/8
Sergunb 0:8f0d870509fe 764 * @retval None
Sergunb 0:8f0d870509fe 765 */
Sergunb 0:8f0d870509fe 766 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
Sergunb 0:8f0d870509fe 767 {
Sergunb 0:8f0d870509fe 768 uint32_t tmpreg = 0;
Sergunb 0:8f0d870509fe 769 /* Check the parameters */
Sergunb 0:8f0d870509fe 770 assert_param(IS_RCC_ADCCLK(RCC_PCLK2));
Sergunb 0:8f0d870509fe 771 tmpreg = RCC->CFGR;
Sergunb 0:8f0d870509fe 772 /* Clear ADCPRE[1:0] bits */
Sergunb 0:8f0d870509fe 773 tmpreg &= CFGR_ADCPRE_Reset_Mask;
Sergunb 0:8f0d870509fe 774 /* Set ADCPRE[1:0] bits according to RCC_PCLK2 value */
Sergunb 0:8f0d870509fe 775 tmpreg |= RCC_PCLK2;
Sergunb 0:8f0d870509fe 776 /* Store the new value */
Sergunb 0:8f0d870509fe 777 RCC->CFGR = tmpreg;
Sergunb 0:8f0d870509fe 778 }
Sergunb 0:8f0d870509fe 779
Sergunb 0:8f0d870509fe 780 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 781 /**
Sergunb 0:8f0d870509fe 782 * @brief Configures the I2S2 clock source(I2S2CLK).
Sergunb 0:8f0d870509fe 783 * @note
Sergunb 0:8f0d870509fe 784 * - This function must be called before enabling I2S2 APB clock.
Sergunb 0:8f0d870509fe 785 * - This function applies only to STM32 Connectivity line devices.
Sergunb 0:8f0d870509fe 786 * @param RCC_I2S2CLKSource: specifies the I2S2 clock source.
Sergunb 0:8f0d870509fe 787 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 788 * @arg RCC_I2S2CLKSource_SYSCLK: system clock selected as I2S2 clock entry
Sergunb 0:8f0d870509fe 789 * @arg RCC_I2S2CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S2 clock entry
Sergunb 0:8f0d870509fe 790 * @retval None
Sergunb 0:8f0d870509fe 791 */
Sergunb 0:8f0d870509fe 792 void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource)
Sergunb 0:8f0d870509fe 793 {
Sergunb 0:8f0d870509fe 794 /* Check the parameters */
Sergunb 0:8f0d870509fe 795 assert_param(IS_RCC_I2S2CLK_SOURCE(RCC_I2S2CLKSource));
Sergunb 0:8f0d870509fe 796
Sergunb 0:8f0d870509fe 797 *(__IO uint32_t *) CFGR2_I2S2SRC_BB = RCC_I2S2CLKSource;
Sergunb 0:8f0d870509fe 798 }
Sergunb 0:8f0d870509fe 799
Sergunb 0:8f0d870509fe 800 /**
Sergunb 0:8f0d870509fe 801 * @brief Configures the I2S3 clock source(I2S2CLK).
Sergunb 0:8f0d870509fe 802 * @note
Sergunb 0:8f0d870509fe 803 * - This function must be called before enabling I2S3 APB clock.
Sergunb 0:8f0d870509fe 804 * - This function applies only to STM32 Connectivity line devices.
Sergunb 0:8f0d870509fe 805 * @param RCC_I2S3CLKSource: specifies the I2S3 clock source.
Sergunb 0:8f0d870509fe 806 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 807 * @arg RCC_I2S3CLKSource_SYSCLK: system clock selected as I2S3 clock entry
Sergunb 0:8f0d870509fe 808 * @arg RCC_I2S3CLKSource_PLL3_VCO: PLL3 VCO clock selected as I2S3 clock entry
Sergunb 0:8f0d870509fe 809 * @retval None
Sergunb 0:8f0d870509fe 810 */
Sergunb 0:8f0d870509fe 811 void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource)
Sergunb 0:8f0d870509fe 812 {
Sergunb 0:8f0d870509fe 813 /* Check the parameters */
Sergunb 0:8f0d870509fe 814 assert_param(IS_RCC_I2S3CLK_SOURCE(RCC_I2S3CLKSource));
Sergunb 0:8f0d870509fe 815
Sergunb 0:8f0d870509fe 816 *(__IO uint32_t *) CFGR2_I2S3SRC_BB = RCC_I2S3CLKSource;
Sergunb 0:8f0d870509fe 817 }
Sergunb 0:8f0d870509fe 818 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 819
Sergunb 0:8f0d870509fe 820 /**
Sergunb 0:8f0d870509fe 821 * @brief Configures the External Low Speed oscillator (LSE).
Sergunb 0:8f0d870509fe 822 * @param RCC_LSE: specifies the new state of the LSE.
Sergunb 0:8f0d870509fe 823 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 824 * @arg RCC_LSE_OFF: LSE oscillator OFF
Sergunb 0:8f0d870509fe 825 * @arg RCC_LSE_ON: LSE oscillator ON
Sergunb 0:8f0d870509fe 826 * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Sergunb 0:8f0d870509fe 827 * @retval None
Sergunb 0:8f0d870509fe 828 */
Sergunb 0:8f0d870509fe 829 void RCC_LSEConfig(uint8_t RCC_LSE)
Sergunb 0:8f0d870509fe 830 {
Sergunb 0:8f0d870509fe 831 /* Check the parameters */
Sergunb 0:8f0d870509fe 832 assert_param(IS_RCC_LSE(RCC_LSE));
Sergunb 0:8f0d870509fe 833 /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
Sergunb 0:8f0d870509fe 834 /* Reset LSEON bit */
Sergunb 0:8f0d870509fe 835 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
Sergunb 0:8f0d870509fe 836 /* Reset LSEBYP bit */
Sergunb 0:8f0d870509fe 837 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
Sergunb 0:8f0d870509fe 838 /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
Sergunb 0:8f0d870509fe 839 switch(RCC_LSE)
Sergunb 0:8f0d870509fe 840 {
Sergunb 0:8f0d870509fe 841 case RCC_LSE_ON:
Sergunb 0:8f0d870509fe 842 /* Set LSEON bit */
Sergunb 0:8f0d870509fe 843 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
Sergunb 0:8f0d870509fe 844 break;
Sergunb 0:8f0d870509fe 845
Sergunb 0:8f0d870509fe 846 case RCC_LSE_Bypass:
Sergunb 0:8f0d870509fe 847 /* Set LSEBYP and LSEON bits */
Sergunb 0:8f0d870509fe 848 *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
Sergunb 0:8f0d870509fe 849 break;
Sergunb 0:8f0d870509fe 850
Sergunb 0:8f0d870509fe 851 default:
Sergunb 0:8f0d870509fe 852 break;
Sergunb 0:8f0d870509fe 853 }
Sergunb 0:8f0d870509fe 854 }
Sergunb 0:8f0d870509fe 855
Sergunb 0:8f0d870509fe 856 /**
Sergunb 0:8f0d870509fe 857 * @brief Enables or disables the Internal Low Speed oscillator (LSI).
Sergunb 0:8f0d870509fe 858 * @note LSI can not be disabled if the IWDG is running.
Sergunb 0:8f0d870509fe 859 * @param NewState: new state of the LSI. This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 860 * @retval None
Sergunb 0:8f0d870509fe 861 */
Sergunb 0:8f0d870509fe 862 void RCC_LSICmd(FunctionalState NewState)
Sergunb 0:8f0d870509fe 863 {
Sergunb 0:8f0d870509fe 864 /* Check the parameters */
Sergunb 0:8f0d870509fe 865 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 866 *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
Sergunb 0:8f0d870509fe 867 }
Sergunb 0:8f0d870509fe 868
Sergunb 0:8f0d870509fe 869 /**
Sergunb 0:8f0d870509fe 870 * @brief Configures the RTC clock (RTCCLK).
Sergunb 0:8f0d870509fe 871 * @note Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
Sergunb 0:8f0d870509fe 872 * @param RCC_RTCCLKSource: specifies the RTC clock source.
Sergunb 0:8f0d870509fe 873 * This parameter can be one of the following values:
Sergunb 0:8f0d870509fe 874 * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
Sergunb 0:8f0d870509fe 875 * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
Sergunb 0:8f0d870509fe 876 * @arg RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
Sergunb 0:8f0d870509fe 877 * @retval None
Sergunb 0:8f0d870509fe 878 */
Sergunb 0:8f0d870509fe 879 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
Sergunb 0:8f0d870509fe 880 {
Sergunb 0:8f0d870509fe 881 /* Check the parameters */
Sergunb 0:8f0d870509fe 882 assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
Sergunb 0:8f0d870509fe 883 /* Select the RTC clock source */
Sergunb 0:8f0d870509fe 884 RCC->BDCR |= RCC_RTCCLKSource;
Sergunb 0:8f0d870509fe 885 }
Sergunb 0:8f0d870509fe 886
Sergunb 0:8f0d870509fe 887 /**
Sergunb 0:8f0d870509fe 888 * @brief Enables or disables the RTC clock.
Sergunb 0:8f0d870509fe 889 * @note This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
Sergunb 0:8f0d870509fe 890 * @param NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 891 * @retval None
Sergunb 0:8f0d870509fe 892 */
Sergunb 0:8f0d870509fe 893 void RCC_RTCCLKCmd(FunctionalState NewState)
Sergunb 0:8f0d870509fe 894 {
Sergunb 0:8f0d870509fe 895 /* Check the parameters */
Sergunb 0:8f0d870509fe 896 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 897 *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
Sergunb 0:8f0d870509fe 898 }
Sergunb 0:8f0d870509fe 899
Sergunb 0:8f0d870509fe 900 /**
Sergunb 0:8f0d870509fe 901 * @brief Returns the frequencies of different on chip clocks.
Sergunb 0:8f0d870509fe 902 * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
Sergunb 0:8f0d870509fe 903 * the clocks frequencies.
Sergunb 0:8f0d870509fe 904 * @note The result of this function could be not correct when using
Sergunb 0:8f0d870509fe 905 * fractional value for HSE crystal.
Sergunb 0:8f0d870509fe 906 * @retval None
Sergunb 0:8f0d870509fe 907 */
Sergunb 0:8f0d870509fe 908 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
Sergunb 0:8f0d870509fe 909 {
Sergunb 0:8f0d870509fe 910 uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
Sergunb 0:8f0d870509fe 911
Sergunb 0:8f0d870509fe 912 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 913 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
Sergunb 0:8f0d870509fe 914 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 915
Sergunb 0:8f0d870509fe 916 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 917 uint32_t prediv1factor = 0;
Sergunb 0:8f0d870509fe 918 #endif
Sergunb 0:8f0d870509fe 919
Sergunb 0:8f0d870509fe 920 /* Get SYSCLK source -------------------------------------------------------*/
Sergunb 0:8f0d870509fe 921 tmp = RCC->CFGR & CFGR_SWS_Mask;
Sergunb 0:8f0d870509fe 922
Sergunb 0:8f0d870509fe 923 switch (tmp)
Sergunb 0:8f0d870509fe 924 {
Sergunb 0:8f0d870509fe 925 case 0x00: /* HSI used as system clock */
Sergunb 0:8f0d870509fe 926 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
Sergunb 0:8f0d870509fe 927 break;
Sergunb 0:8f0d870509fe 928 case 0x04: /* HSE used as system clock */
Sergunb 0:8f0d870509fe 929 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
Sergunb 0:8f0d870509fe 930 break;
Sergunb 0:8f0d870509fe 931 case 0x08: /* PLL used as system clock */
Sergunb 0:8f0d870509fe 932
Sergunb 0:8f0d870509fe 933 /* Get PLL clock source and multiplication factor ----------------------*/
Sergunb 0:8f0d870509fe 934 pllmull = RCC->CFGR & CFGR_PLLMull_Mask;
Sergunb 0:8f0d870509fe 935 pllsource = RCC->CFGR & CFGR_PLLSRC_Mask;
Sergunb 0:8f0d870509fe 936
Sergunb 0:8f0d870509fe 937 #ifndef STM32F10X_CL
Sergunb 0:8f0d870509fe 938 pllmull = ( pllmull >> 18) + 2;
Sergunb 0:8f0d870509fe 939
Sergunb 0:8f0d870509fe 940 if (pllsource == 0x00)
Sergunb 0:8f0d870509fe 941 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
Sergunb 0:8f0d870509fe 942 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
Sergunb 0:8f0d870509fe 943 }
Sergunb 0:8f0d870509fe 944 else
Sergunb 0:8f0d870509fe 945 {
Sergunb 0:8f0d870509fe 946 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 947 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
Sergunb 0:8f0d870509fe 948 /* HSE oscillator clock selected as PREDIV1 clock entry */
Sergunb 0:8f0d870509fe 949 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
Sergunb 0:8f0d870509fe 950 #else
Sergunb 0:8f0d870509fe 951 /* HSE selected as PLL clock entry */
Sergunb 0:8f0d870509fe 952 if ((RCC->CFGR & CFGR_PLLXTPRE_Mask) != (uint32_t)RESET)
Sergunb 0:8f0d870509fe 953 {/* HSE oscillator clock divided by 2 */
Sergunb 0:8f0d870509fe 954 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
Sergunb 0:8f0d870509fe 955 }
Sergunb 0:8f0d870509fe 956 else
Sergunb 0:8f0d870509fe 957 {
Sergunb 0:8f0d870509fe 958 RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
Sergunb 0:8f0d870509fe 959 }
Sergunb 0:8f0d870509fe 960 #endif
Sergunb 0:8f0d870509fe 961 }
Sergunb 0:8f0d870509fe 962 #else
Sergunb 0:8f0d870509fe 963 pllmull = pllmull >> 18;
Sergunb 0:8f0d870509fe 964
Sergunb 0:8f0d870509fe 965 if (pllmull != 0x0D)
Sergunb 0:8f0d870509fe 966 {
Sergunb 0:8f0d870509fe 967 pllmull += 2;
Sergunb 0:8f0d870509fe 968 }
Sergunb 0:8f0d870509fe 969 else
Sergunb 0:8f0d870509fe 970 { /* PLL multiplication factor = PLL input clock * 6.5 */
Sergunb 0:8f0d870509fe 971 pllmull = 13 / 2;
Sergunb 0:8f0d870509fe 972 }
Sergunb 0:8f0d870509fe 973
Sergunb 0:8f0d870509fe 974 if (pllsource == 0x00)
Sergunb 0:8f0d870509fe 975 {/* HSI oscillator clock divided by 2 selected as PLL clock entry */
Sergunb 0:8f0d870509fe 976 RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
Sergunb 0:8f0d870509fe 977 }
Sergunb 0:8f0d870509fe 978 else
Sergunb 0:8f0d870509fe 979 {/* PREDIV1 selected as PLL clock entry */
Sergunb 0:8f0d870509fe 980
Sergunb 0:8f0d870509fe 981 /* Get PREDIV1 clock source and division factor */
Sergunb 0:8f0d870509fe 982 prediv1source = RCC->CFGR2 & CFGR2_PREDIV1SRC;
Sergunb 0:8f0d870509fe 983 prediv1factor = (RCC->CFGR2 & CFGR2_PREDIV1) + 1;
Sergunb 0:8f0d870509fe 984
Sergunb 0:8f0d870509fe 985 if (prediv1source == 0)
Sergunb 0:8f0d870509fe 986 { /* HSE oscillator clock selected as PREDIV1 clock entry */
Sergunb 0:8f0d870509fe 987 RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE / prediv1factor) * pllmull;
Sergunb 0:8f0d870509fe 988 }
Sergunb 0:8f0d870509fe 989 else
Sergunb 0:8f0d870509fe 990 {/* PLL2 clock selected as PREDIV1 clock entry */
Sergunb 0:8f0d870509fe 991
Sergunb 0:8f0d870509fe 992 /* Get PREDIV2 division factor and PLL2 multiplication factor */
Sergunb 0:8f0d870509fe 993 prediv2factor = ((RCC->CFGR2 & CFGR2_PREDIV2) >> 4) + 1;
Sergunb 0:8f0d870509fe 994 pll2mull = ((RCC->CFGR2 & CFGR2_PLL2MUL) >> 8 ) + 2;
Sergunb 0:8f0d870509fe 995 RCC_Clocks->SYSCLK_Frequency = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
Sergunb 0:8f0d870509fe 996 }
Sergunb 0:8f0d870509fe 997 }
Sergunb 0:8f0d870509fe 998 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 999 break;
Sergunb 0:8f0d870509fe 1000
Sergunb 0:8f0d870509fe 1001 default:
Sergunb 0:8f0d870509fe 1002 RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
Sergunb 0:8f0d870509fe 1003 break;
Sergunb 0:8f0d870509fe 1004 }
Sergunb 0:8f0d870509fe 1005
Sergunb 0:8f0d870509fe 1006 /* Compute HCLK, PCLK1, PCLK2 and ADCCLK clocks frequencies ----------------*/
Sergunb 0:8f0d870509fe 1007 /* Get HCLK prescaler */
Sergunb 0:8f0d870509fe 1008 tmp = RCC->CFGR & CFGR_HPRE_Set_Mask;
Sergunb 0:8f0d870509fe 1009 tmp = tmp >> 4;
Sergunb 0:8f0d870509fe 1010 presc = APBAHBPrescTable[tmp];
Sergunb 0:8f0d870509fe 1011 /* HCLK clock frequency */
Sergunb 0:8f0d870509fe 1012 RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
Sergunb 0:8f0d870509fe 1013 /* Get PCLK1 prescaler */
Sergunb 0:8f0d870509fe 1014 tmp = RCC->CFGR & CFGR_PPRE1_Set_Mask;
Sergunb 0:8f0d870509fe 1015 tmp = tmp >> 8;
Sergunb 0:8f0d870509fe 1016 presc = APBAHBPrescTable[tmp];
Sergunb 0:8f0d870509fe 1017 /* PCLK1 clock frequency */
Sergunb 0:8f0d870509fe 1018 RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
Sergunb 0:8f0d870509fe 1019 /* Get PCLK2 prescaler */
Sergunb 0:8f0d870509fe 1020 tmp = RCC->CFGR & CFGR_PPRE2_Set_Mask;
Sergunb 0:8f0d870509fe 1021 tmp = tmp >> 11;
Sergunb 0:8f0d870509fe 1022 presc = APBAHBPrescTable[tmp];
Sergunb 0:8f0d870509fe 1023 /* PCLK2 clock frequency */
Sergunb 0:8f0d870509fe 1024 RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
Sergunb 0:8f0d870509fe 1025 /* Get ADCCLK prescaler */
Sergunb 0:8f0d870509fe 1026 tmp = RCC->CFGR & CFGR_ADCPRE_Set_Mask;
Sergunb 0:8f0d870509fe 1027 tmp = tmp >> 14;
Sergunb 0:8f0d870509fe 1028 presc = ADCPrescTable[tmp];
Sergunb 0:8f0d870509fe 1029 /* ADCCLK clock frequency */
Sergunb 0:8f0d870509fe 1030 RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
Sergunb 0:8f0d870509fe 1031 }
Sergunb 0:8f0d870509fe 1032
Sergunb 0:8f0d870509fe 1033 /**
Sergunb 0:8f0d870509fe 1034 * @brief Enables or disables the AHB peripheral clock.
Sergunb 0:8f0d870509fe 1035 * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
Sergunb 0:8f0d870509fe 1036 *
Sergunb 0:8f0d870509fe 1037 * For @b STM32_Connectivity_line_devices, this parameter can be any combination
Sergunb 0:8f0d870509fe 1038 * of the following values:
Sergunb 0:8f0d870509fe 1039 * @arg RCC_AHBPeriph_DMA1
Sergunb 0:8f0d870509fe 1040 * @arg RCC_AHBPeriph_DMA2
Sergunb 0:8f0d870509fe 1041 * @arg RCC_AHBPeriph_SRAM
Sergunb 0:8f0d870509fe 1042 * @arg RCC_AHBPeriph_FLITF
Sergunb 0:8f0d870509fe 1043 * @arg RCC_AHBPeriph_CRC
Sergunb 0:8f0d870509fe 1044 * @arg RCC_AHBPeriph_OTG_FS
Sergunb 0:8f0d870509fe 1045 * @arg RCC_AHBPeriph_ETH_MAC
Sergunb 0:8f0d870509fe 1046 * @arg RCC_AHBPeriph_ETH_MAC_Tx
Sergunb 0:8f0d870509fe 1047 * @arg RCC_AHBPeriph_ETH_MAC_Rx
Sergunb 0:8f0d870509fe 1048 *
Sergunb 0:8f0d870509fe 1049 * For @b other_STM32_devices, this parameter can be any combination of the
Sergunb 0:8f0d870509fe 1050 * following values:
Sergunb 0:8f0d870509fe 1051 * @arg RCC_AHBPeriph_DMA1
Sergunb 0:8f0d870509fe 1052 * @arg RCC_AHBPeriph_DMA2
Sergunb 0:8f0d870509fe 1053 * @arg RCC_AHBPeriph_SRAM
Sergunb 0:8f0d870509fe 1054 * @arg RCC_AHBPeriph_FLITF
Sergunb 0:8f0d870509fe 1055 * @arg RCC_AHBPeriph_CRC
Sergunb 0:8f0d870509fe 1056 * @arg RCC_AHBPeriph_FSMC
Sergunb 0:8f0d870509fe 1057 * @arg RCC_AHBPeriph_SDIO
Sergunb 0:8f0d870509fe 1058 *
Sergunb 0:8f0d870509fe 1059 * @note SRAM and FLITF clock can be disabled only during sleep mode.
Sergunb 0:8f0d870509fe 1060 * @param NewState: new state of the specified peripheral clock.
Sergunb 0:8f0d870509fe 1061 * This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 1062 * @retval None
Sergunb 0:8f0d870509fe 1063 */
Sergunb 0:8f0d870509fe 1064 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
Sergunb 0:8f0d870509fe 1065 {
Sergunb 0:8f0d870509fe 1066 /* Check the parameters */
Sergunb 0:8f0d870509fe 1067 assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
Sergunb 0:8f0d870509fe 1068 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 1069
Sergunb 0:8f0d870509fe 1070 if (NewState != DISABLE)
Sergunb 0:8f0d870509fe 1071 {
Sergunb 0:8f0d870509fe 1072 RCC->AHBENR |= RCC_AHBPeriph;
Sergunb 0:8f0d870509fe 1073 }
Sergunb 0:8f0d870509fe 1074 else
Sergunb 0:8f0d870509fe 1075 {
Sergunb 0:8f0d870509fe 1076 RCC->AHBENR &= ~RCC_AHBPeriph;
Sergunb 0:8f0d870509fe 1077 }
Sergunb 0:8f0d870509fe 1078 }
Sergunb 0:8f0d870509fe 1079
Sergunb 0:8f0d870509fe 1080 /**
Sergunb 0:8f0d870509fe 1081 * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
Sergunb 0:8f0d870509fe 1082 * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
Sergunb 0:8f0d870509fe 1083 * This parameter can be any combination of the following values:
Sergunb 0:8f0d870509fe 1084 * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
Sergunb 0:8f0d870509fe 1085 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
Sergunb 0:8f0d870509fe 1086 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
Sergunb 0:8f0d870509fe 1087 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
Sergunb 0:8f0d870509fe 1088 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
Sergunb 0:8f0d870509fe 1089 * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
Sergunb 0:8f0d870509fe 1090 * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
Sergunb 0:8f0d870509fe 1091 * @param NewState: new state of the specified peripheral clock.
Sergunb 0:8f0d870509fe 1092 * This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 1093 * @retval None
Sergunb 0:8f0d870509fe 1094 */
Sergunb 0:8f0d870509fe 1095 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Sergunb 0:8f0d870509fe 1096 {
Sergunb 0:8f0d870509fe 1097 /* Check the parameters */
Sergunb 0:8f0d870509fe 1098 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
Sergunb 0:8f0d870509fe 1099 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 1100 if (NewState != DISABLE)
Sergunb 0:8f0d870509fe 1101 {
Sergunb 0:8f0d870509fe 1102 RCC->APB2ENR |= RCC_APB2Periph;
Sergunb 0:8f0d870509fe 1103 }
Sergunb 0:8f0d870509fe 1104 else
Sergunb 0:8f0d870509fe 1105 {
Sergunb 0:8f0d870509fe 1106 RCC->APB2ENR &= ~RCC_APB2Periph;
Sergunb 0:8f0d870509fe 1107 }
Sergunb 0:8f0d870509fe 1108 }
Sergunb 0:8f0d870509fe 1109
Sergunb 0:8f0d870509fe 1110 /**
Sergunb 0:8f0d870509fe 1111 * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
Sergunb 0:8f0d870509fe 1112 * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
Sergunb 0:8f0d870509fe 1113 * This parameter can be any combination of the following values:
Sergunb 0:8f0d870509fe 1114 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
Sergunb 0:8f0d870509fe 1115 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
Sergunb 0:8f0d870509fe 1116 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
Sergunb 0:8f0d870509fe 1117 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
Sergunb 0:8f0d870509fe 1118 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
Sergunb 0:8f0d870509fe 1119 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
Sergunb 0:8f0d870509fe 1120 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
Sergunb 0:8f0d870509fe 1121 * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
Sergunb 0:8f0d870509fe 1122 * @param NewState: new state of the specified peripheral clock.
Sergunb 0:8f0d870509fe 1123 * This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 1124 * @retval None
Sergunb 0:8f0d870509fe 1125 */
Sergunb 0:8f0d870509fe 1126 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Sergunb 0:8f0d870509fe 1127 {
Sergunb 0:8f0d870509fe 1128 /* Check the parameters */
Sergunb 0:8f0d870509fe 1129 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
Sergunb 0:8f0d870509fe 1130 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 1131 if (NewState != DISABLE)
Sergunb 0:8f0d870509fe 1132 {
Sergunb 0:8f0d870509fe 1133 RCC->APB1ENR |= RCC_APB1Periph;
Sergunb 0:8f0d870509fe 1134 }
Sergunb 0:8f0d870509fe 1135 else
Sergunb 0:8f0d870509fe 1136 {
Sergunb 0:8f0d870509fe 1137 RCC->APB1ENR &= ~RCC_APB1Periph;
Sergunb 0:8f0d870509fe 1138 }
Sergunb 0:8f0d870509fe 1139 }
Sergunb 0:8f0d870509fe 1140
Sergunb 0:8f0d870509fe 1141 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 1142 /**
Sergunb 0:8f0d870509fe 1143 * @brief Forces or releases AHB peripheral reset.
Sergunb 0:8f0d870509fe 1144 * @note This function applies only to STM32 Connectivity line devices.
Sergunb 0:8f0d870509fe 1145 * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
Sergunb 0:8f0d870509fe 1146 * This parameter can be any combination of the following values:
Sergunb 0:8f0d870509fe 1147 * @arg RCC_AHBPeriph_OTG_FS
Sergunb 0:8f0d870509fe 1148 * @arg RCC_AHBPeriph_ETH_MAC
Sergunb 0:8f0d870509fe 1149 * @param NewState: new state of the specified peripheral reset.
Sergunb 0:8f0d870509fe 1150 * This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 1151 * @retval None
Sergunb 0:8f0d870509fe 1152 */
Sergunb 0:8f0d870509fe 1153 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
Sergunb 0:8f0d870509fe 1154 {
Sergunb 0:8f0d870509fe 1155 /* Check the parameters */
Sergunb 0:8f0d870509fe 1156 assert_param(IS_RCC_AHB_PERIPH_RESET(RCC_AHBPeriph));
Sergunb 0:8f0d870509fe 1157 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 1158
Sergunb 0:8f0d870509fe 1159 if (NewState != DISABLE)
Sergunb 0:8f0d870509fe 1160 {
Sergunb 0:8f0d870509fe 1161 RCC->AHBRSTR |= RCC_AHBPeriph;
Sergunb 0:8f0d870509fe 1162 }
Sergunb 0:8f0d870509fe 1163 else
Sergunb 0:8f0d870509fe 1164 {
Sergunb 0:8f0d870509fe 1165 RCC->AHBRSTR &= ~RCC_AHBPeriph;
Sergunb 0:8f0d870509fe 1166 }
Sergunb 0:8f0d870509fe 1167 }
Sergunb 0:8f0d870509fe 1168 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 1169
Sergunb 0:8f0d870509fe 1170 /**
Sergunb 0:8f0d870509fe 1171 * @brief Forces or releases High Speed APB (APB2) peripheral reset.
Sergunb 0:8f0d870509fe 1172 * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
Sergunb 0:8f0d870509fe 1173 * This parameter can be any combination of the following values:
Sergunb 0:8f0d870509fe 1174 * @arg RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB,
Sergunb 0:8f0d870509fe 1175 * RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE,
Sergunb 0:8f0d870509fe 1176 * RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1,
Sergunb 0:8f0d870509fe 1177 * RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1,
Sergunb 0:8f0d870509fe 1178 * RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3,
Sergunb 0:8f0d870509fe 1179 * RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17,
Sergunb 0:8f0d870509fe 1180 * RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
Sergunb 0:8f0d870509fe 1181 * @param NewState: new state of the specified peripheral reset.
Sergunb 0:8f0d870509fe 1182 * This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 1183 * @retval None
Sergunb 0:8f0d870509fe 1184 */
Sergunb 0:8f0d870509fe 1185 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
Sergunb 0:8f0d870509fe 1186 {
Sergunb 0:8f0d870509fe 1187 /* Check the parameters */
Sergunb 0:8f0d870509fe 1188 assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
Sergunb 0:8f0d870509fe 1189 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 1190 if (NewState != DISABLE)
Sergunb 0:8f0d870509fe 1191 {
Sergunb 0:8f0d870509fe 1192 RCC->APB2RSTR |= RCC_APB2Periph;
Sergunb 0:8f0d870509fe 1193 }
Sergunb 0:8f0d870509fe 1194 else
Sergunb 0:8f0d870509fe 1195 {
Sergunb 0:8f0d870509fe 1196 RCC->APB2RSTR &= ~RCC_APB2Periph;
Sergunb 0:8f0d870509fe 1197 }
Sergunb 0:8f0d870509fe 1198 }
Sergunb 0:8f0d870509fe 1199
Sergunb 0:8f0d870509fe 1200 /**
Sergunb 0:8f0d870509fe 1201 * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
Sergunb 0:8f0d870509fe 1202 * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
Sergunb 0:8f0d870509fe 1203 * This parameter can be any combination of the following values:
Sergunb 0:8f0d870509fe 1204 * @arg RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4,
Sergunb 0:8f0d870509fe 1205 * RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7,
Sergunb 0:8f0d870509fe 1206 * RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3,
Sergunb 0:8f0d870509fe 1207 * RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4,
Sergunb 0:8f0d870509fe 1208 * RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2,
Sergunb 0:8f0d870509fe 1209 * RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP,
Sergunb 0:8f0d870509fe 1210 * RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC,
Sergunb 0:8f0d870509fe 1211 * RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
Sergunb 0:8f0d870509fe 1212 * @param NewState: new state of the specified peripheral clock.
Sergunb 0:8f0d870509fe 1213 * This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 1214 * @retval None
Sergunb 0:8f0d870509fe 1215 */
Sergunb 0:8f0d870509fe 1216 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
Sergunb 0:8f0d870509fe 1217 {
Sergunb 0:8f0d870509fe 1218 /* Check the parameters */
Sergunb 0:8f0d870509fe 1219 assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
Sergunb 0:8f0d870509fe 1220 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 1221 if (NewState != DISABLE)
Sergunb 0:8f0d870509fe 1222 {
Sergunb 0:8f0d870509fe 1223 RCC->APB1RSTR |= RCC_APB1Periph;
Sergunb 0:8f0d870509fe 1224 }
Sergunb 0:8f0d870509fe 1225 else
Sergunb 0:8f0d870509fe 1226 {
Sergunb 0:8f0d870509fe 1227 RCC->APB1RSTR &= ~RCC_APB1Periph;
Sergunb 0:8f0d870509fe 1228 }
Sergunb 0:8f0d870509fe 1229 }
Sergunb 0:8f0d870509fe 1230
Sergunb 0:8f0d870509fe 1231 /**
Sergunb 0:8f0d870509fe 1232 * @brief Forces or releases the Backup domain reset.
Sergunb 0:8f0d870509fe 1233 * @param NewState: new state of the Backup domain reset.
Sergunb 0:8f0d870509fe 1234 * This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 1235 * @retval None
Sergunb 0:8f0d870509fe 1236 */
Sergunb 0:8f0d870509fe 1237 void RCC_BackupResetCmd(FunctionalState NewState)
Sergunb 0:8f0d870509fe 1238 {
Sergunb 0:8f0d870509fe 1239 /* Check the parameters */
Sergunb 0:8f0d870509fe 1240 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 1241 *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
Sergunb 0:8f0d870509fe 1242 }
Sergunb 0:8f0d870509fe 1243
Sergunb 0:8f0d870509fe 1244 /**
Sergunb 0:8f0d870509fe 1245 * @brief Enables or disables the Clock Security System.
Sergunb 0:8f0d870509fe 1246 * @param NewState: new state of the Clock Security System..
Sergunb 0:8f0d870509fe 1247 * This parameter can be: ENABLE or DISABLE.
Sergunb 0:8f0d870509fe 1248 * @retval None
Sergunb 0:8f0d870509fe 1249 */
Sergunb 0:8f0d870509fe 1250 void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
Sergunb 0:8f0d870509fe 1251 {
Sergunb 0:8f0d870509fe 1252 /* Check the parameters */
Sergunb 0:8f0d870509fe 1253 assert_param(IS_FUNCTIONAL_STATE(NewState));
Sergunb 0:8f0d870509fe 1254 *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
Sergunb 0:8f0d870509fe 1255 }
Sergunb 0:8f0d870509fe 1256
Sergunb 0:8f0d870509fe 1257 /**
Sergunb 0:8f0d870509fe 1258 * @brief Selects the clock source to output on MCO pin.
Sergunb 0:8f0d870509fe 1259 * @param RCC_MCO: specifies the clock source to output.
Sergunb 0:8f0d870509fe 1260 *
Sergunb 0:8f0d870509fe 1261 * For @b STM32_Connectivity_line_devices, this parameter can be one of the
Sergunb 0:8f0d870509fe 1262 * following values:
Sergunb 0:8f0d870509fe 1263 * @arg RCC_MCO_NoClock: No clock selected
Sergunb 0:8f0d870509fe 1264 * @arg RCC_MCO_SYSCLK: System clock selected
Sergunb 0:8f0d870509fe 1265 * @arg RCC_MCO_HSI: HSI oscillator clock selected
Sergunb 0:8f0d870509fe 1266 * @arg RCC_MCO_HSE: HSE oscillator clock selected
Sergunb 0:8f0d870509fe 1267 * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
Sergunb 0:8f0d870509fe 1268 * @arg RCC_MCO_PLL2CLK: PLL2 clock selected
Sergunb 0:8f0d870509fe 1269 * @arg RCC_MCO_PLL3CLK_Div2: PLL3 clock divided by 2 selected
Sergunb 0:8f0d870509fe 1270 * @arg RCC_MCO_XT1: External 3-25 MHz oscillator clock selected
Sergunb 0:8f0d870509fe 1271 * @arg RCC_MCO_PLL3CLK: PLL3 clock selected
Sergunb 0:8f0d870509fe 1272 *
Sergunb 0:8f0d870509fe 1273 * For @b other_STM32_devices, this parameter can be one of the following values:
Sergunb 0:8f0d870509fe 1274 * @arg RCC_MCO_NoClock: No clock selected
Sergunb 0:8f0d870509fe 1275 * @arg RCC_MCO_SYSCLK: System clock selected
Sergunb 0:8f0d870509fe 1276 * @arg RCC_MCO_HSI: HSI oscillator clock selected
Sergunb 0:8f0d870509fe 1277 * @arg RCC_MCO_HSE: HSE oscillator clock selected
Sergunb 0:8f0d870509fe 1278 * @arg RCC_MCO_PLLCLK_Div2: PLL clock divided by 2 selected
Sergunb 0:8f0d870509fe 1279 *
Sergunb 0:8f0d870509fe 1280 * @retval None
Sergunb 0:8f0d870509fe 1281 */
Sergunb 0:8f0d870509fe 1282 void RCC_MCOConfig(uint8_t RCC_MCO)
Sergunb 0:8f0d870509fe 1283 {
Sergunb 0:8f0d870509fe 1284 /* Check the parameters */
Sergunb 0:8f0d870509fe 1285 assert_param(IS_RCC_MCO(RCC_MCO));
Sergunb 0:8f0d870509fe 1286
Sergunb 0:8f0d870509fe 1287 /* Perform Byte access to MCO bits to select the MCO source */
Sergunb 0:8f0d870509fe 1288 *(__IO uint8_t *) CFGR_BYTE4_ADDRESS = RCC_MCO;
Sergunb 0:8f0d870509fe 1289 }
Sergunb 0:8f0d870509fe 1290
Sergunb 0:8f0d870509fe 1291 /**
Sergunb 0:8f0d870509fe 1292 * @brief Checks whether the specified RCC flag is set or not.
Sergunb 0:8f0d870509fe 1293 * @param RCC_FLAG: specifies the flag to check.
Sergunb 0:8f0d870509fe 1294 *
Sergunb 0:8f0d870509fe 1295 * For @b STM32_Connectivity_line_devices, this parameter can be one of the
Sergunb 0:8f0d870509fe 1296 * following values:
Sergunb 0:8f0d870509fe 1297 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Sergunb 0:8f0d870509fe 1298 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
Sergunb 0:8f0d870509fe 1299 * @arg RCC_FLAG_PLLRDY: PLL clock ready
Sergunb 0:8f0d870509fe 1300 * @arg RCC_FLAG_PLL2RDY: PLL2 clock ready
Sergunb 0:8f0d870509fe 1301 * @arg RCC_FLAG_PLL3RDY: PLL3 clock ready
Sergunb 0:8f0d870509fe 1302 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
Sergunb 0:8f0d870509fe 1303 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Sergunb 0:8f0d870509fe 1304 * @arg RCC_FLAG_PINRST: Pin reset
Sergunb 0:8f0d870509fe 1305 * @arg RCC_FLAG_PORRST: POR/PDR reset
Sergunb 0:8f0d870509fe 1306 * @arg RCC_FLAG_SFTRST: Software reset
Sergunb 0:8f0d870509fe 1307 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
Sergunb 0:8f0d870509fe 1308 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
Sergunb 0:8f0d870509fe 1309 * @arg RCC_FLAG_LPWRRST: Low Power reset
Sergunb 0:8f0d870509fe 1310 *
Sergunb 0:8f0d870509fe 1311 * For @b other_STM32_devices, this parameter can be one of the following values:
Sergunb 0:8f0d870509fe 1312 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Sergunb 0:8f0d870509fe 1313 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
Sergunb 0:8f0d870509fe 1314 * @arg RCC_FLAG_PLLRDY: PLL clock ready
Sergunb 0:8f0d870509fe 1315 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
Sergunb 0:8f0d870509fe 1316 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Sergunb 0:8f0d870509fe 1317 * @arg RCC_FLAG_PINRST: Pin reset
Sergunb 0:8f0d870509fe 1318 * @arg RCC_FLAG_PORRST: POR/PDR reset
Sergunb 0:8f0d870509fe 1319 * @arg RCC_FLAG_SFTRST: Software reset
Sergunb 0:8f0d870509fe 1320 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
Sergunb 0:8f0d870509fe 1321 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
Sergunb 0:8f0d870509fe 1322 * @arg RCC_FLAG_LPWRRST: Low Power reset
Sergunb 0:8f0d870509fe 1323 *
Sergunb 0:8f0d870509fe 1324 * @retval The new state of RCC_FLAG (SET or RESET).
Sergunb 0:8f0d870509fe 1325 */
Sergunb 0:8f0d870509fe 1326 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
Sergunb 0:8f0d870509fe 1327 {
Sergunb 0:8f0d870509fe 1328 uint32_t tmp = 0;
Sergunb 0:8f0d870509fe 1329 uint32_t statusreg = 0;
Sergunb 0:8f0d870509fe 1330 FlagStatus bitstatus = RESET;
Sergunb 0:8f0d870509fe 1331 /* Check the parameters */
Sergunb 0:8f0d870509fe 1332 assert_param(IS_RCC_FLAG(RCC_FLAG));
Sergunb 0:8f0d870509fe 1333
Sergunb 0:8f0d870509fe 1334 /* Get the RCC register index */
Sergunb 0:8f0d870509fe 1335 tmp = RCC_FLAG >> 5;
Sergunb 0:8f0d870509fe 1336 if (tmp == 1) /* The flag to check is in CR register */
Sergunb 0:8f0d870509fe 1337 {
Sergunb 0:8f0d870509fe 1338 statusreg = RCC->CR;
Sergunb 0:8f0d870509fe 1339 }
Sergunb 0:8f0d870509fe 1340 else if (tmp == 2) /* The flag to check is in BDCR register */
Sergunb 0:8f0d870509fe 1341 {
Sergunb 0:8f0d870509fe 1342 statusreg = RCC->BDCR;
Sergunb 0:8f0d870509fe 1343 }
Sergunb 0:8f0d870509fe 1344 else /* The flag to check is in CSR register */
Sergunb 0:8f0d870509fe 1345 {
Sergunb 0:8f0d870509fe 1346 statusreg = RCC->CSR;
Sergunb 0:8f0d870509fe 1347 }
Sergunb 0:8f0d870509fe 1348
Sergunb 0:8f0d870509fe 1349 /* Get the flag position */
Sergunb 0:8f0d870509fe 1350 tmp = RCC_FLAG & FLAG_Mask;
Sergunb 0:8f0d870509fe 1351 if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
Sergunb 0:8f0d870509fe 1352 {
Sergunb 0:8f0d870509fe 1353 bitstatus = SET;
Sergunb 0:8f0d870509fe 1354 }
Sergunb 0:8f0d870509fe 1355 else
Sergunb 0:8f0d870509fe 1356 {
Sergunb 0:8f0d870509fe 1357 bitstatus = RESET;
Sergunb 0:8f0d870509fe 1358 }
Sergunb 0:8f0d870509fe 1359
Sergunb 0:8f0d870509fe 1360 /* Return the flag status */
Sergunb 0:8f0d870509fe 1361 return bitstatus;
Sergunb 0:8f0d870509fe 1362 }
Sergunb 0:8f0d870509fe 1363
Sergunb 0:8f0d870509fe 1364 /**
Sergunb 0:8f0d870509fe 1365 * @brief Clears the RCC reset flags.
Sergunb 0:8f0d870509fe 1366 * @note The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Sergunb 0:8f0d870509fe 1367 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Sergunb 0:8f0d870509fe 1368 * @param None
Sergunb 0:8f0d870509fe 1369 * @retval None
Sergunb 0:8f0d870509fe 1370 */
Sergunb 0:8f0d870509fe 1371 void RCC_ClearFlag(void)
Sergunb 0:8f0d870509fe 1372 {
Sergunb 0:8f0d870509fe 1373 /* Set RMVF bit to clear the reset flags */
Sergunb 0:8f0d870509fe 1374 RCC->CSR |= CSR_RMVF_Set;
Sergunb 0:8f0d870509fe 1375 }
Sergunb 0:8f0d870509fe 1376
Sergunb 0:8f0d870509fe 1377 /**
Sergunb 0:8f0d870509fe 1378 * @brief Checks whether the specified RCC interrupt has occurred or not.
Sergunb 0:8f0d870509fe 1379 * @param RCC_IT: specifies the RCC interrupt source to check.
Sergunb 0:8f0d870509fe 1380 *
Sergunb 0:8f0d870509fe 1381 * For @b STM32_Connectivity_line_devices, this parameter can be one of the
Sergunb 0:8f0d870509fe 1382 * following values:
Sergunb 0:8f0d870509fe 1383 * @arg RCC_IT_LSIRDY: LSI ready interrupt
Sergunb 0:8f0d870509fe 1384 * @arg RCC_IT_LSERDY: LSE ready interrupt
Sergunb 0:8f0d870509fe 1385 * @arg RCC_IT_HSIRDY: HSI ready interrupt
Sergunb 0:8f0d870509fe 1386 * @arg RCC_IT_HSERDY: HSE ready interrupt
Sergunb 0:8f0d870509fe 1387 * @arg RCC_IT_PLLRDY: PLL ready interrupt
Sergunb 0:8f0d870509fe 1388 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
Sergunb 0:8f0d870509fe 1389 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
Sergunb 0:8f0d870509fe 1390 * @arg RCC_IT_CSS: Clock Security System interrupt
Sergunb 0:8f0d870509fe 1391 *
Sergunb 0:8f0d870509fe 1392 * For @b other_STM32_devices, this parameter can be one of the following values:
Sergunb 0:8f0d870509fe 1393 * @arg RCC_IT_LSIRDY: LSI ready interrupt
Sergunb 0:8f0d870509fe 1394 * @arg RCC_IT_LSERDY: LSE ready interrupt
Sergunb 0:8f0d870509fe 1395 * @arg RCC_IT_HSIRDY: HSI ready interrupt
Sergunb 0:8f0d870509fe 1396 * @arg RCC_IT_HSERDY: HSE ready interrupt
Sergunb 0:8f0d870509fe 1397 * @arg RCC_IT_PLLRDY: PLL ready interrupt
Sergunb 0:8f0d870509fe 1398 * @arg RCC_IT_CSS: Clock Security System interrupt
Sergunb 0:8f0d870509fe 1399 *
Sergunb 0:8f0d870509fe 1400 * @retval The new state of RCC_IT (SET or RESET).
Sergunb 0:8f0d870509fe 1401 */
Sergunb 0:8f0d870509fe 1402 ITStatus RCC_GetITStatus(uint8_t RCC_IT)
Sergunb 0:8f0d870509fe 1403 {
Sergunb 0:8f0d870509fe 1404 ITStatus bitstatus = RESET;
Sergunb 0:8f0d870509fe 1405 /* Check the parameters */
Sergunb 0:8f0d870509fe 1406 assert_param(IS_RCC_GET_IT(RCC_IT));
Sergunb 0:8f0d870509fe 1407
Sergunb 0:8f0d870509fe 1408 /* Check the status of the specified RCC interrupt */
Sergunb 0:8f0d870509fe 1409 if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
Sergunb 0:8f0d870509fe 1410 {
Sergunb 0:8f0d870509fe 1411 bitstatus = SET;
Sergunb 0:8f0d870509fe 1412 }
Sergunb 0:8f0d870509fe 1413 else
Sergunb 0:8f0d870509fe 1414 {
Sergunb 0:8f0d870509fe 1415 bitstatus = RESET;
Sergunb 0:8f0d870509fe 1416 }
Sergunb 0:8f0d870509fe 1417
Sergunb 0:8f0d870509fe 1418 /* Return the RCC_IT status */
Sergunb 0:8f0d870509fe 1419 return bitstatus;
Sergunb 0:8f0d870509fe 1420 }
Sergunb 0:8f0d870509fe 1421
Sergunb 0:8f0d870509fe 1422 /**
Sergunb 0:8f0d870509fe 1423 * @brief Clears the RCC's interrupt pending bits.
Sergunb 0:8f0d870509fe 1424 * @param RCC_IT: specifies the interrupt pending bit to clear.
Sergunb 0:8f0d870509fe 1425 *
Sergunb 0:8f0d870509fe 1426 * For @b STM32_Connectivity_line_devices, this parameter can be any combination
Sergunb 0:8f0d870509fe 1427 * of the following values:
Sergunb 0:8f0d870509fe 1428 * @arg RCC_IT_LSIRDY: LSI ready interrupt
Sergunb 0:8f0d870509fe 1429 * @arg RCC_IT_LSERDY: LSE ready interrupt
Sergunb 0:8f0d870509fe 1430 * @arg RCC_IT_HSIRDY: HSI ready interrupt
Sergunb 0:8f0d870509fe 1431 * @arg RCC_IT_HSERDY: HSE ready interrupt
Sergunb 0:8f0d870509fe 1432 * @arg RCC_IT_PLLRDY: PLL ready interrupt
Sergunb 0:8f0d870509fe 1433 * @arg RCC_IT_PLL2RDY: PLL2 ready interrupt
Sergunb 0:8f0d870509fe 1434 * @arg RCC_IT_PLL3RDY: PLL3 ready interrupt
Sergunb 0:8f0d870509fe 1435 * @arg RCC_IT_CSS: Clock Security System interrupt
Sergunb 0:8f0d870509fe 1436 *
Sergunb 0:8f0d870509fe 1437 * For @b other_STM32_devices, this parameter can be any combination of the
Sergunb 0:8f0d870509fe 1438 * following values:
Sergunb 0:8f0d870509fe 1439 * @arg RCC_IT_LSIRDY: LSI ready interrupt
Sergunb 0:8f0d870509fe 1440 * @arg RCC_IT_LSERDY: LSE ready interrupt
Sergunb 0:8f0d870509fe 1441 * @arg RCC_IT_HSIRDY: HSI ready interrupt
Sergunb 0:8f0d870509fe 1442 * @arg RCC_IT_HSERDY: HSE ready interrupt
Sergunb 0:8f0d870509fe 1443 * @arg RCC_IT_PLLRDY: PLL ready interrupt
Sergunb 0:8f0d870509fe 1444 *
Sergunb 0:8f0d870509fe 1445 * @arg RCC_IT_CSS: Clock Security System interrupt
Sergunb 0:8f0d870509fe 1446 * @retval None
Sergunb 0:8f0d870509fe 1447 */
Sergunb 0:8f0d870509fe 1448 void RCC_ClearITPendingBit(uint8_t RCC_IT)
Sergunb 0:8f0d870509fe 1449 {
Sergunb 0:8f0d870509fe 1450 /* Check the parameters */
Sergunb 0:8f0d870509fe 1451 assert_param(IS_RCC_CLEAR_IT(RCC_IT));
Sergunb 0:8f0d870509fe 1452
Sergunb 0:8f0d870509fe 1453 /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
Sergunb 0:8f0d870509fe 1454 pending bits */
Sergunb 0:8f0d870509fe 1455 *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
Sergunb 0:8f0d870509fe 1456 }
Sergunb 0:8f0d870509fe 1457
Sergunb 0:8f0d870509fe 1458 /**
Sergunb 0:8f0d870509fe 1459 * @}
Sergunb 0:8f0d870509fe 1460 */
Sergunb 0:8f0d870509fe 1461
Sergunb 0:8f0d870509fe 1462 /**
Sergunb 0:8f0d870509fe 1463 * @}
Sergunb 0:8f0d870509fe 1464 */
Sergunb 0:8f0d870509fe 1465
Sergunb 0:8f0d870509fe 1466 /**
Sergunb 0:8f0d870509fe 1467 * @}
Sergunb 0:8f0d870509fe 1468 */
Sergunb 0:8f0d870509fe 1469
Sergunb 0:8f0d870509fe 1470 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/