Sergey Pastor / grbl1

I'm trying to port GRBL 1.1 to the STM32F746 chip. Tell me the solution, thanks.

cmsis_boot/system_stm32f10x.c@0:8f0d870509fe, 2017-09-04 (annotated)

Committer:
Sergunb
Date:
Mon Sep 04 12:04:13 2017 +0000
Revision:
0:8f0d870509fe
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8f0d870509fe 1 /**
Sergunb 0:8f0d870509fe 2 ******************************************************************************
Sergunb 0:8f0d870509fe 3 * @file system_stm32f10x.c
Sergunb 0:8f0d870509fe 4 * @author MCD Application Team
Sergunb 0:8f0d870509fe 5 * @version V3.5.0
Sergunb 0:8f0d870509fe 6 * @date 11-March-2011
Sergunb 0:8f0d870509fe 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
Sergunb 0:8f0d870509fe 8 *
Sergunb 0:8f0d870509fe 9 * 1. This file provides two functions and one global variable to be called from
Sergunb 0:8f0d870509fe 10 * user application:
Sergunb 0:8f0d870509fe 11 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
Sergunb 0:8f0d870509fe 12 * factors, AHB/APBx prescalers and Flash settings).
Sergunb 0:8f0d870509fe 13 * This function is called at startup just after reset and
Sergunb 0:8f0d870509fe 14 * before branch to main program. This call is made inside
Sergunb 0:8f0d870509fe 15 * the "startup_stm32f10x_xx.s" file.
Sergunb 0:8f0d870509fe 16 *
Sergunb 0:8f0d870509fe 17 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
Sergunb 0:8f0d870509fe 18 * by the user application to setup the SysTick
Sergunb 0:8f0d870509fe 19 * timer or configure other parameters.
Sergunb 0:8f0d870509fe 20 *
Sergunb 0:8f0d870509fe 21 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
Sergunb 0:8f0d870509fe 22 * be called whenever the core clock is changed
Sergunb 0:8f0d870509fe 23 * during program execution.
Sergunb 0:8f0d870509fe 24 *
Sergunb 0:8f0d870509fe 25 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
Sergunb 0:8f0d870509fe 26 * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
Sergunb 0:8f0d870509fe 27 * configure the system clock before to branch to main program.
Sergunb 0:8f0d870509fe 28 *
Sergunb 0:8f0d870509fe 29 * 3. If the system clock source selected by user fails to startup, the SystemInit()
Sergunb 0:8f0d870509fe 30 * function will do nothing and HSI still used as system clock source. User can
Sergunb 0:8f0d870509fe 31 * add some code to deal with this issue inside the SetSysClock() function.
Sergunb 0:8f0d870509fe 32 *
Sergunb 0:8f0d870509fe 33 * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
Sergunb 0:8f0d870509fe 34 * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
Sergunb 0:8f0d870509fe 35 * When HSE is used as system clock source, directly or through PLL, and you
Sergunb 0:8f0d870509fe 36 * are using different crystal you have to adapt the HSE value to your own
Sergunb 0:8f0d870509fe 37 * configuration.
Sergunb 0:8f0d870509fe 38 *
Sergunb 0:8f0d870509fe 39 ******************************************************************************
Sergunb 0:8f0d870509fe 40 * @attention
Sergunb 0:8f0d870509fe 41 *
Sergunb 0:8f0d870509fe 42 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
Sergunb 0:8f0d870509fe 43 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
Sergunb 0:8f0d870509fe 44 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
Sergunb 0:8f0d870509fe 45 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
Sergunb 0:8f0d870509fe 46 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
Sergunb 0:8f0d870509fe 47 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
Sergunb 0:8f0d870509fe 48 *
Sergunb 0:8f0d870509fe 49 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
Sergunb 0:8f0d870509fe 50 ******************************************************************************
Sergunb 0:8f0d870509fe 51 */
Sergunb 0:8f0d870509fe 52
Sergunb 0:8f0d870509fe 53 /** @addtogroup CMSIS
Sergunb 0:8f0d870509fe 54 * @{
Sergunb 0:8f0d870509fe 55 */
Sergunb 0:8f0d870509fe 56
Sergunb 0:8f0d870509fe 57 /** @addtogroup stm32f10x_system
Sergunb 0:8f0d870509fe 58 * @{
Sergunb 0:8f0d870509fe 59 */
Sergunb 0:8f0d870509fe 60
Sergunb 0:8f0d870509fe 61 /** @addtogroup STM32F10x_System_Private_Includes
Sergunb 0:8f0d870509fe 62 * @{
Sergunb 0:8f0d870509fe 63 */
Sergunb 0:8f0d870509fe 64
Sergunb 0:8f0d870509fe 65 #include "stm32f10x.h"
Sergunb 0:8f0d870509fe 66
Sergunb 0:8f0d870509fe 67 /**
Sergunb 0:8f0d870509fe 68 * @}
Sergunb 0:8f0d870509fe 69 */
Sergunb 0:8f0d870509fe 70
Sergunb 0:8f0d870509fe 71 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
Sergunb 0:8f0d870509fe 72 * @{
Sergunb 0:8f0d870509fe 73 */
Sergunb 0:8f0d870509fe 74
Sergunb 0:8f0d870509fe 75 /**
Sergunb 0:8f0d870509fe 76 * @}
Sergunb 0:8f0d870509fe 77 */
Sergunb 0:8f0d870509fe 78
Sergunb 0:8f0d870509fe 79 /** @addtogroup STM32F10x_System_Private_Defines
Sergunb 0:8f0d870509fe 80 * @{
Sergunb 0:8f0d870509fe 81 */
Sergunb 0:8f0d870509fe 82
Sergunb 0:8f0d870509fe 83 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
Sergunb 0:8f0d870509fe 84 frequency (after reset the HSI is used as SYSCLK source)
Sergunb 0:8f0d870509fe 85
Sergunb 0:8f0d870509fe 86 IMPORTANT NOTE:
Sergunb 0:8f0d870509fe 87 ==============
Sergunb 0:8f0d870509fe 88 1. After each device reset the HSI is used as System clock source.
Sergunb 0:8f0d870509fe 89
Sergunb 0:8f0d870509fe 90 2. Please make sure that the selected System clock doesn't exceed your device's
Sergunb 0:8f0d870509fe 91 maximum frequency.
Sergunb 0:8f0d870509fe 92
Sergunb 0:8f0d870509fe 93 3. If none of the define below is enabled, the HSI is used as System clock
Sergunb 0:8f0d870509fe 94 source.
Sergunb 0:8f0d870509fe 95
Sergunb 0:8f0d870509fe 96 4. The System clock configuration functions provided within this file assume that:
Sergunb 0:8f0d870509fe 97 - For Low, Medium and High density Value line devices an external 8MHz
Sergunb 0:8f0d870509fe 98 crystal is used to drive the System clock.
Sergunb 0:8f0d870509fe 99 - For Low, Medium and High density devices an external 8MHz crystal is
Sergunb 0:8f0d870509fe 100 used to drive the System clock.
Sergunb 0:8f0d870509fe 101 - For Connectivity line devices an external 25MHz crystal is used to drive
Sergunb 0:8f0d870509fe 102 the System clock.
Sergunb 0:8f0d870509fe 103 If you are using different crystal you have to adapt those functions accordingly.
Sergunb 0:8f0d870509fe 104 */
Sergunb 0:8f0d870509fe 105
Sergunb 0:8f0d870509fe 106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 107 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
Sergunb 0:8f0d870509fe 108 #define SYSCLK_FREQ_24MHz 24000000
Sergunb 0:8f0d870509fe 109 #else
Sergunb 0:8f0d870509fe 110 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
Sergunb 0:8f0d870509fe 111 /* #define SYSCLK_FREQ_24MHz 24000000 */
Sergunb 0:8f0d870509fe 112 /* #define SYSCLK_FREQ_36MHz 36000000 */
Sergunb 0:8f0d870509fe 113 /* #define SYSCLK_FREQ_48MHz 48000000 */
Sergunb 0:8f0d870509fe 114 /* #define SYSCLK_FREQ_56MHz 56000000 */
Sergunb 0:8f0d870509fe 115 #define SYSCLK_FREQ_72MHz 72000000
Sergunb 0:8f0d870509fe 116 #endif
Sergunb 0:8f0d870509fe 117
Sergunb 0:8f0d870509fe 118 /*!< Uncomment the following line if you need to use external SRAM mounted
Sergunb 0:8f0d870509fe 119 on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
Sergunb 0:8f0d870509fe 120 STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
Sergunb 0:8f0d870509fe 121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 122 /* #define DATA_IN_ExtSRAM */
Sergunb 0:8f0d870509fe 123 #endif
Sergunb 0:8f0d870509fe 124
Sergunb 0:8f0d870509fe 125 /*!< Uncomment the following line if you need to relocate your vector Table in
Sergunb 0:8f0d870509fe 126 Internal SRAM. */
Sergunb 0:8f0d870509fe 127 /* #define VECT_TAB_SRAM */
Sergunb 0:8f0d870509fe 128 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
Sergunb 0:8f0d870509fe 129 This value must be a multiple of 0x200. */
Sergunb 0:8f0d870509fe 130
Sergunb 0:8f0d870509fe 131
Sergunb 0:8f0d870509fe 132 /**
Sergunb 0:8f0d870509fe 133 * @}
Sergunb 0:8f0d870509fe 134 */
Sergunb 0:8f0d870509fe 135
Sergunb 0:8f0d870509fe 136 /** @addtogroup STM32F10x_System_Private_Macros
Sergunb 0:8f0d870509fe 137 * @{
Sergunb 0:8f0d870509fe 138 */
Sergunb 0:8f0d870509fe 139
Sergunb 0:8f0d870509fe 140 /**
Sergunb 0:8f0d870509fe 141 * @}
Sergunb 0:8f0d870509fe 142 */
Sergunb 0:8f0d870509fe 143
Sergunb 0:8f0d870509fe 144 /** @addtogroup STM32F10x_System_Private_Variables
Sergunb 0:8f0d870509fe 145 * @{
Sergunb 0:8f0d870509fe 146 */
Sergunb 0:8f0d870509fe 147
Sergunb 0:8f0d870509fe 148 /*******************************************************************************
Sergunb 0:8f0d870509fe 149 * Clock Definitions
Sergunb 0:8f0d870509fe 150 *******************************************************************************/
Sergunb 0:8f0d870509fe 151 #ifdef SYSCLK_FREQ_HSE
Sergunb 0:8f0d870509fe 152 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:8f0d870509fe 153 #elif defined SYSCLK_FREQ_24MHz
Sergunb 0:8f0d870509fe 154 uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:8f0d870509fe 155 #elif defined SYSCLK_FREQ_36MHz
Sergunb 0:8f0d870509fe 156 uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:8f0d870509fe 157 #elif defined SYSCLK_FREQ_48MHz
Sergunb 0:8f0d870509fe 158 uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:8f0d870509fe 159 #elif defined SYSCLK_FREQ_56MHz
Sergunb 0:8f0d870509fe 160 uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:8f0d870509fe 161 #elif defined SYSCLK_FREQ_72MHz
Sergunb 0:8f0d870509fe 162 uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:8f0d870509fe 163 #else /*!< HSI Selected as System Clock source */
Sergunb 0:8f0d870509fe 164 uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:8f0d870509fe 165 #endif
Sergunb 0:8f0d870509fe 166
Sergunb 0:8f0d870509fe 167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
Sergunb 0:8f0d870509fe 168 /**
Sergunb 0:8f0d870509fe 169 * @}
Sergunb 0:8f0d870509fe 170 */
Sergunb 0:8f0d870509fe 171
Sergunb 0:8f0d870509fe 172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
Sergunb 0:8f0d870509fe 173 * @{
Sergunb 0:8f0d870509fe 174 */
Sergunb 0:8f0d870509fe 175
Sergunb 0:8f0d870509fe 176 static void SetSysClock(void);
Sergunb 0:8f0d870509fe 177
Sergunb 0:8f0d870509fe 178 #ifdef SYSCLK_FREQ_HSE
Sergunb 0:8f0d870509fe 179 static void SetSysClockToHSE(void);
Sergunb 0:8f0d870509fe 180 #elif defined SYSCLK_FREQ_24MHz
Sergunb 0:8f0d870509fe 181 static void SetSysClockTo24(void);
Sergunb 0:8f0d870509fe 182 #elif defined SYSCLK_FREQ_36MHz
Sergunb 0:8f0d870509fe 183 static void SetSysClockTo36(void);
Sergunb 0:8f0d870509fe 184 #elif defined SYSCLK_FREQ_48MHz
Sergunb 0:8f0d870509fe 185 static void SetSysClockTo48(void);
Sergunb 0:8f0d870509fe 186 #elif defined SYSCLK_FREQ_56MHz
Sergunb 0:8f0d870509fe 187 static void SetSysClockTo56(void);
Sergunb 0:8f0d870509fe 188 #elif defined SYSCLK_FREQ_72MHz
Sergunb 0:8f0d870509fe 189 static void SetSysClockTo72(void);
Sergunb 0:8f0d870509fe 190 #endif
Sergunb 0:8f0d870509fe 191
Sergunb 0:8f0d870509fe 192 #ifdef DATA_IN_ExtSRAM
Sergunb 0:8f0d870509fe 193 static void SystemInit_ExtMemCtl(void);
Sergunb 0:8f0d870509fe 194 #endif /* DATA_IN_ExtSRAM */
Sergunb 0:8f0d870509fe 195
Sergunb 0:8f0d870509fe 196 /**
Sergunb 0:8f0d870509fe 197 * @}
Sergunb 0:8f0d870509fe 198 */
Sergunb 0:8f0d870509fe 199
Sergunb 0:8f0d870509fe 200 /** @addtogroup STM32F10x_System_Private_Functions
Sergunb 0:8f0d870509fe 201 * @{
Sergunb 0:8f0d870509fe 202 */
Sergunb 0:8f0d870509fe 203
Sergunb 0:8f0d870509fe 204 /**
Sergunb 0:8f0d870509fe 205 * @brief Setup the microcontroller system
Sergunb 0:8f0d870509fe 206 * Initialize the Embedded Flash Interface, the PLL and update the
Sergunb 0:8f0d870509fe 207 * SystemCoreClock variable.
Sergunb 0:8f0d870509fe 208 * @note This function should be used only after reset.
Sergunb 0:8f0d870509fe 209 * @param None
Sergunb 0:8f0d870509fe 210 * @retval None
Sergunb 0:8f0d870509fe 211 */
Sergunb 0:8f0d870509fe 212 void SystemInit (void)
Sergunb 0:8f0d870509fe 213 {
Sergunb 0:8f0d870509fe 214 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
Sergunb 0:8f0d870509fe 215 /* Set HSION bit */
Sergunb 0:8f0d870509fe 216 RCC->CR |= (uint32_t)0x00000001;
Sergunb 0:8f0d870509fe 217
Sergunb 0:8f0d870509fe 218 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
Sergunb 0:8f0d870509fe 219 #ifndef STM32F10X_CL
Sergunb 0:8f0d870509fe 220 RCC->CFGR &= (uint32_t)0xF8FF0000;
Sergunb 0:8f0d870509fe 221 #else
Sergunb 0:8f0d870509fe 222 RCC->CFGR &= (uint32_t)0xF0FF0000;
Sergunb 0:8f0d870509fe 223 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 224
Sergunb 0:8f0d870509fe 225 /* Reset HSEON, CSSON and PLLON bits */
Sergunb 0:8f0d870509fe 226 RCC->CR &= (uint32_t)0xFEF6FFFF;
Sergunb 0:8f0d870509fe 227
Sergunb 0:8f0d870509fe 228 /* Reset HSEBYP bit */
Sergunb 0:8f0d870509fe 229 RCC->CR &= (uint32_t)0xFFFBFFFF;
Sergunb 0:8f0d870509fe 230
Sergunb 0:8f0d870509fe 231 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
Sergunb 0:8f0d870509fe 232 RCC->CFGR &= (uint32_t)0xFF80FFFF;
Sergunb 0:8f0d870509fe 233
Sergunb 0:8f0d870509fe 234 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 235 /* Reset PLL2ON and PLL3ON bits */
Sergunb 0:8f0d870509fe 236 RCC->CR &= (uint32_t)0xEBFFFFFF;
Sergunb 0:8f0d870509fe 237
Sergunb 0:8f0d870509fe 238 /* Disable all interrupts and clear pending bits */
Sergunb 0:8f0d870509fe 239 RCC->CIR = 0x00FF0000;
Sergunb 0:8f0d870509fe 240
Sergunb 0:8f0d870509fe 241 /* Reset CFGR2 register */
Sergunb 0:8f0d870509fe 242 RCC->CFGR2 = 0x00000000;
Sergunb 0:8f0d870509fe 243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 244 /* Disable all interrupts and clear pending bits */
Sergunb 0:8f0d870509fe 245 RCC->CIR = 0x009F0000;
Sergunb 0:8f0d870509fe 246
Sergunb 0:8f0d870509fe 247 /* Reset CFGR2 register */
Sergunb 0:8f0d870509fe 248 RCC->CFGR2 = 0x00000000;
Sergunb 0:8f0d870509fe 249 #else
Sergunb 0:8f0d870509fe 250 /* Disable all interrupts and clear pending bits */
Sergunb 0:8f0d870509fe 251 RCC->CIR = 0x009F0000;
Sergunb 0:8f0d870509fe 252 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 253
Sergunb 0:8f0d870509fe 254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 255 #ifdef DATA_IN_ExtSRAM
Sergunb 0:8f0d870509fe 256 SystemInit_ExtMemCtl();
Sergunb 0:8f0d870509fe 257 #endif /* DATA_IN_ExtSRAM */
Sergunb 0:8f0d870509fe 258 #endif
Sergunb 0:8f0d870509fe 259
Sergunb 0:8f0d870509fe 260 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
Sergunb 0:8f0d870509fe 261 /* Configure the Flash Latency cycles and enable prefetch buffer */
Sergunb 0:8f0d870509fe 262 SetSysClock();
Sergunb 0:8f0d870509fe 263
Sergunb 0:8f0d870509fe 264 #ifdef VECT_TAB_SRAM
Sergunb 0:8f0d870509fe 265 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
Sergunb 0:8f0d870509fe 266 #else
Sergunb 0:8f0d870509fe 267 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
Sergunb 0:8f0d870509fe 268 #endif
Sergunb 0:8f0d870509fe 269 }
Sergunb 0:8f0d870509fe 270
Sergunb 0:8f0d870509fe 271 /**
Sergunb 0:8f0d870509fe 272 * @brief Update SystemCoreClock variable according to Clock Register Values.
Sergunb 0:8f0d870509fe 273 * The SystemCoreClock variable contains the core clock (HCLK), it can
Sergunb 0:8f0d870509fe 274 * be used by the user application to setup the SysTick timer or configure
Sergunb 0:8f0d870509fe 275 * other parameters.
Sergunb 0:8f0d870509fe 276 *
Sergunb 0:8f0d870509fe 277 * @note Each time the core clock (HCLK) changes, this function must be called
Sergunb 0:8f0d870509fe 278 * to update SystemCoreClock variable value. Otherwise, any configuration
Sergunb 0:8f0d870509fe 279 * based on this variable will be incorrect.
Sergunb 0:8f0d870509fe 280 *
Sergunb 0:8f0d870509fe 281 * @note - The system frequency computed by this function is not the real
Sergunb 0:8f0d870509fe 282 * frequency in the chip. It is calculated based on the predefined
Sergunb 0:8f0d870509fe 283 * constant and the selected clock source:
Sergunb 0:8f0d870509fe 284 *
Sergunb 0:8f0d870509fe 285 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
Sergunb 0:8f0d870509fe 286 *
Sergunb 0:8f0d870509fe 287 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
Sergunb 0:8f0d870509fe 288 *
Sergunb 0:8f0d870509fe 289 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
Sergunb 0:8f0d870509fe 290 * or HSI_VALUE(*) multiplied by the PLL factors.
Sergunb 0:8f0d870509fe 291 *
Sergunb 0:8f0d870509fe 292 * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
Sergunb 0:8f0d870509fe 293 * 8 MHz) but the real value may vary depending on the variations
Sergunb 0:8f0d870509fe 294 * in voltage and temperature.
Sergunb 0:8f0d870509fe 295 *
Sergunb 0:8f0d870509fe 296 * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
Sergunb 0:8f0d870509fe 297 * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
Sergunb 0:8f0d870509fe 298 * that HSE_VALUE is same as the real frequency of the crystal used.
Sergunb 0:8f0d870509fe 299 * Otherwise, this function may have wrong result.
Sergunb 0:8f0d870509fe 300 *
Sergunb 0:8f0d870509fe 301 * - The result of this function could be not correct when using fractional
Sergunb 0:8f0d870509fe 302 * value for HSE crystal.
Sergunb 0:8f0d870509fe 303 * @param None
Sergunb 0:8f0d870509fe 304 * @retval None
Sergunb 0:8f0d870509fe 305 */
Sergunb 0:8f0d870509fe 306 void SystemCoreClockUpdate (void)
Sergunb 0:8f0d870509fe 307 {
Sergunb 0:8f0d870509fe 308 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
Sergunb 0:8f0d870509fe 309
Sergunb 0:8f0d870509fe 310 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 311 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
Sergunb 0:8f0d870509fe 312 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 313
Sergunb 0:8f0d870509fe 314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 315 uint32_t prediv1factor = 0;
Sergunb 0:8f0d870509fe 316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
Sergunb 0:8f0d870509fe 317
Sergunb 0:8f0d870509fe 318 /* Get SYSCLK source -------------------------------------------------------*/
Sergunb 0:8f0d870509fe 319 tmp = RCC->CFGR & RCC_CFGR_SWS;
Sergunb 0:8f0d870509fe 320
Sergunb 0:8f0d870509fe 321 switch (tmp)
Sergunb 0:8f0d870509fe 322 {
Sergunb 0:8f0d870509fe 323 case 0x00: /* HSI used as system clock */
Sergunb 0:8f0d870509fe 324 SystemCoreClock = HSI_VALUE;
Sergunb 0:8f0d870509fe 325 break;
Sergunb 0:8f0d870509fe 326 case 0x04: /* HSE used as system clock */
Sergunb 0:8f0d870509fe 327 SystemCoreClock = HSE_VALUE;
Sergunb 0:8f0d870509fe 328 break;
Sergunb 0:8f0d870509fe 329 case 0x08: /* PLL used as system clock */
Sergunb 0:8f0d870509fe 330
Sergunb 0:8f0d870509fe 331 /* Get PLL clock source and multiplication factor ----------------------*/
Sergunb 0:8f0d870509fe 332 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
Sergunb 0:8f0d870509fe 333 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
Sergunb 0:8f0d870509fe 334
Sergunb 0:8f0d870509fe 335 #ifndef STM32F10X_CL
Sergunb 0:8f0d870509fe 336 pllmull = ( pllmull >> 18) + 2;
Sergunb 0:8f0d870509fe 337
Sergunb 0:8f0d870509fe 338 if (pllsource == 0x00)
Sergunb 0:8f0d870509fe 339 {
Sergunb 0:8f0d870509fe 340 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
Sergunb 0:8f0d870509fe 341 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
Sergunb 0:8f0d870509fe 342 }
Sergunb 0:8f0d870509fe 343 else
Sergunb 0:8f0d870509fe 344 {
Sergunb 0:8f0d870509fe 345 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 346 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
Sergunb 0:8f0d870509fe 347 /* HSE oscillator clock selected as PREDIV1 clock entry */
Sergunb 0:8f0d870509fe 348 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
Sergunb 0:8f0d870509fe 349 #else
Sergunb 0:8f0d870509fe 350 /* HSE selected as PLL clock entry */
Sergunb 0:8f0d870509fe 351 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
Sergunb 0:8f0d870509fe 352 {/* HSE oscillator clock divided by 2 */
Sergunb 0:8f0d870509fe 353 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
Sergunb 0:8f0d870509fe 354 }
Sergunb 0:8f0d870509fe 355 else
Sergunb 0:8f0d870509fe 356 {
Sergunb 0:8f0d870509fe 357 SystemCoreClock = HSE_VALUE * pllmull;
Sergunb 0:8f0d870509fe 358 }
Sergunb 0:8f0d870509fe 359 #endif
Sergunb 0:8f0d870509fe 360 }
Sergunb 0:8f0d870509fe 361 #else
Sergunb 0:8f0d870509fe 362 pllmull = pllmull >> 18;
Sergunb 0:8f0d870509fe 363
Sergunb 0:8f0d870509fe 364 if (pllmull != 0x0D)
Sergunb 0:8f0d870509fe 365 {
Sergunb 0:8f0d870509fe 366 pllmull += 2;
Sergunb 0:8f0d870509fe 367 }
Sergunb 0:8f0d870509fe 368 else
Sergunb 0:8f0d870509fe 369 { /* PLL multiplication factor = PLL input clock * 6.5 */
Sergunb 0:8f0d870509fe 370 pllmull = 13 / 2;
Sergunb 0:8f0d870509fe 371 }
Sergunb 0:8f0d870509fe 372
Sergunb 0:8f0d870509fe 373 if (pllsource == 0x00)
Sergunb 0:8f0d870509fe 374 {
Sergunb 0:8f0d870509fe 375 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
Sergunb 0:8f0d870509fe 376 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
Sergunb 0:8f0d870509fe 377 }
Sergunb 0:8f0d870509fe 378 else
Sergunb 0:8f0d870509fe 379 {/* PREDIV1 selected as PLL clock entry */
Sergunb 0:8f0d870509fe 380
Sergunb 0:8f0d870509fe 381 /* Get PREDIV1 clock source and division factor */
Sergunb 0:8f0d870509fe 382 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
Sergunb 0:8f0d870509fe 383 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
Sergunb 0:8f0d870509fe 384
Sergunb 0:8f0d870509fe 385 if (prediv1source == 0)
Sergunb 0:8f0d870509fe 386 {
Sergunb 0:8f0d870509fe 387 /* HSE oscillator clock selected as PREDIV1 clock entry */
Sergunb 0:8f0d870509fe 388 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
Sergunb 0:8f0d870509fe 389 }
Sergunb 0:8f0d870509fe 390 else
Sergunb 0:8f0d870509fe 391 {/* PLL2 clock selected as PREDIV1 clock entry */
Sergunb 0:8f0d870509fe 392
Sergunb 0:8f0d870509fe 393 /* Get PREDIV2 division factor and PLL2 multiplication factor */
Sergunb 0:8f0d870509fe 394 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
Sergunb 0:8f0d870509fe 395 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
Sergunb 0:8f0d870509fe 396 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
Sergunb 0:8f0d870509fe 397 }
Sergunb 0:8f0d870509fe 398 }
Sergunb 0:8f0d870509fe 399 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 400 break;
Sergunb 0:8f0d870509fe 401
Sergunb 0:8f0d870509fe 402 default:
Sergunb 0:8f0d870509fe 403 SystemCoreClock = HSI_VALUE;
Sergunb 0:8f0d870509fe 404 break;
Sergunb 0:8f0d870509fe 405 }
Sergunb 0:8f0d870509fe 406
Sergunb 0:8f0d870509fe 407 /* Compute HCLK clock frequency ----------------*/
Sergunb 0:8f0d870509fe 408 /* Get HCLK prescaler */
Sergunb 0:8f0d870509fe 409 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
Sergunb 0:8f0d870509fe 410 /* HCLK clock frequency */
Sergunb 0:8f0d870509fe 411 SystemCoreClock >>= tmp;
Sergunb 0:8f0d870509fe 412 }
Sergunb 0:8f0d870509fe 413
Sergunb 0:8f0d870509fe 414 /**
Sergunb 0:8f0d870509fe 415 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
Sergunb 0:8f0d870509fe 416 * @param None
Sergunb 0:8f0d870509fe 417 * @retval None
Sergunb 0:8f0d870509fe 418 */
Sergunb 0:8f0d870509fe 419 static void SetSysClock(void)
Sergunb 0:8f0d870509fe 420 {
Sergunb 0:8f0d870509fe 421 #ifdef SYSCLK_FREQ_HSE
Sergunb 0:8f0d870509fe 422 SetSysClockToHSE();
Sergunb 0:8f0d870509fe 423 #elif defined SYSCLK_FREQ_24MHz
Sergunb 0:8f0d870509fe 424 SetSysClockTo24();
Sergunb 0:8f0d870509fe 425 #elif defined SYSCLK_FREQ_36MHz
Sergunb 0:8f0d870509fe 426 SetSysClockTo36();
Sergunb 0:8f0d870509fe 427 #elif defined SYSCLK_FREQ_48MHz
Sergunb 0:8f0d870509fe 428 SetSysClockTo48();
Sergunb 0:8f0d870509fe 429 #elif defined SYSCLK_FREQ_56MHz
Sergunb 0:8f0d870509fe 430 SetSysClockTo56();
Sergunb 0:8f0d870509fe 431 #elif defined SYSCLK_FREQ_72MHz
Sergunb 0:8f0d870509fe 432 SetSysClockTo72();
Sergunb 0:8f0d870509fe 433 #endif
Sergunb 0:8f0d870509fe 434
Sergunb 0:8f0d870509fe 435 /* If none of the define above is enabled, the HSI is used as System clock
Sergunb 0:8f0d870509fe 436 source (default after reset) */
Sergunb 0:8f0d870509fe 437 }
Sergunb 0:8f0d870509fe 438
Sergunb 0:8f0d870509fe 439 /**
Sergunb 0:8f0d870509fe 440 * @brief Setup the external memory controller. Called in startup_stm32f10x.s
Sergunb 0:8f0d870509fe 441 * before jump to __main
Sergunb 0:8f0d870509fe 442 * @param None
Sergunb 0:8f0d870509fe 443 * @retval None
Sergunb 0:8f0d870509fe 444 */
Sergunb 0:8f0d870509fe 445 #ifdef DATA_IN_ExtSRAM
Sergunb 0:8f0d870509fe 446 /**
Sergunb 0:8f0d870509fe 447 * @brief Setup the external memory controller.
Sergunb 0:8f0d870509fe 448 * Called in startup_stm32f10x_xx.s/.c before jump to main.
Sergunb 0:8f0d870509fe 449 * This function configures the external SRAM mounted on STM3210E-EVAL
Sergunb 0:8f0d870509fe 450 * board (STM32 High density devices). This SRAM will be used as program
Sergunb 0:8f0d870509fe 451 * data memory (including heap and stack).
Sergunb 0:8f0d870509fe 452 * @param None
Sergunb 0:8f0d870509fe 453 * @retval None
Sergunb 0:8f0d870509fe 454 */
Sergunb 0:8f0d870509fe 455 void SystemInit_ExtMemCtl(void)
Sergunb 0:8f0d870509fe 456 {
Sergunb 0:8f0d870509fe 457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
Sergunb 0:8f0d870509fe 458 required, then adjust the Register Addresses */
Sergunb 0:8f0d870509fe 459
Sergunb 0:8f0d870509fe 460 /* Enable FSMC clock */
Sergunb 0:8f0d870509fe 461 RCC->AHBENR = 0x00000114;
Sergunb 0:8f0d870509fe 462
Sergunb 0:8f0d870509fe 463 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
Sergunb 0:8f0d870509fe 464 RCC->APB2ENR = 0x000001E0;
Sergunb 0:8f0d870509fe 465
Sergunb 0:8f0d870509fe 466 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
Sergunb 0:8f0d870509fe 467 /*---------------- SRAM Address lines configuration -------------------------*/
Sergunb 0:8f0d870509fe 468 /*---------------- NOE and NWE configuration --------------------------------*/
Sergunb 0:8f0d870509fe 469 /*---------------- NE3 configuration ----------------------------------------*/
Sergunb 0:8f0d870509fe 470 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
Sergunb 0:8f0d870509fe 471
Sergunb 0:8f0d870509fe 472 GPIOD->CRL = 0x44BB44BB;
Sergunb 0:8f0d870509fe 473 GPIOD->CRH = 0xBBBBBBBB;
Sergunb 0:8f0d870509fe 474
Sergunb 0:8f0d870509fe 475 GPIOE->CRL = 0xB44444BB;
Sergunb 0:8f0d870509fe 476 GPIOE->CRH = 0xBBBBBBBB;
Sergunb 0:8f0d870509fe 477
Sergunb 0:8f0d870509fe 478 GPIOF->CRL = 0x44BBBBBB;
Sergunb 0:8f0d870509fe 479 GPIOF->CRH = 0xBBBB4444;
Sergunb 0:8f0d870509fe 480
Sergunb 0:8f0d870509fe 481 GPIOG->CRL = 0x44BBBBBB;
Sergunb 0:8f0d870509fe 482 GPIOG->CRH = 0x44444B44;
Sergunb 0:8f0d870509fe 483
Sergunb 0:8f0d870509fe 484 /*---------------- FSMC Configuration ---------------------------------------*/
Sergunb 0:8f0d870509fe 485 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
Sergunb 0:8f0d870509fe 486
Sergunb 0:8f0d870509fe 487 FSMC_Bank1->BTCR[4] = 0x00001011;
Sergunb 0:8f0d870509fe 488 FSMC_Bank1->BTCR[5] = 0x00000200;
Sergunb 0:8f0d870509fe 489 }
Sergunb 0:8f0d870509fe 490 #endif /* DATA_IN_ExtSRAM */
Sergunb 0:8f0d870509fe 491
Sergunb 0:8f0d870509fe 492 #ifdef SYSCLK_FREQ_HSE
Sergunb 0:8f0d870509fe 493 /**
Sergunb 0:8f0d870509fe 494 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
Sergunb 0:8f0d870509fe 495 * and PCLK1 prescalers.
Sergunb 0:8f0d870509fe 496 * @note This function should be used only after reset.
Sergunb 0:8f0d870509fe 497 * @param None
Sergunb 0:8f0d870509fe 498 * @retval None
Sergunb 0:8f0d870509fe 499 */
Sergunb 0:8f0d870509fe 500 static void SetSysClockToHSE(void)
Sergunb 0:8f0d870509fe 501 {
Sergunb 0:8f0d870509fe 502 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:8f0d870509fe 503
Sergunb 0:8f0d870509fe 504 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:8f0d870509fe 505 /* Enable HSE */
Sergunb 0:8f0d870509fe 506 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:8f0d870509fe 507
Sergunb 0:8f0d870509fe 508 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:8f0d870509fe 509 do
Sergunb 0:8f0d870509fe 510 {
Sergunb 0:8f0d870509fe 511 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:8f0d870509fe 512 StartUpCounter++;
Sergunb 0:8f0d870509fe 513 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:8f0d870509fe 514
Sergunb 0:8f0d870509fe 515 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:8f0d870509fe 516 {
Sergunb 0:8f0d870509fe 517 HSEStatus = (uint32_t)0x01;
Sergunb 0:8f0d870509fe 518 }
Sergunb 0:8f0d870509fe 519 else
Sergunb 0:8f0d870509fe 520 {
Sergunb 0:8f0d870509fe 521 HSEStatus = (uint32_t)0x00;
Sergunb 0:8f0d870509fe 522 }
Sergunb 0:8f0d870509fe 523
Sergunb 0:8f0d870509fe 524 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:8f0d870509fe 525 {
Sergunb 0:8f0d870509fe 526
Sergunb 0:8f0d870509fe 527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
Sergunb 0:8f0d870509fe 528 /* Enable Prefetch Buffer */
Sergunb 0:8f0d870509fe 529 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:8f0d870509fe 530
Sergunb 0:8f0d870509fe 531 /* Flash 0 wait state */
Sergunb 0:8f0d870509fe 532 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:8f0d870509fe 533
Sergunb 0:8f0d870509fe 534 #ifndef STM32F10X_CL
Sergunb 0:8f0d870509fe 535 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
Sergunb 0:8f0d870509fe 536 #else
Sergunb 0:8f0d870509fe 537 if (HSE_VALUE <= 24000000)
Sergunb 0:8f0d870509fe 538 {
Sergunb 0:8f0d870509fe 539 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
Sergunb 0:8f0d870509fe 540 }
Sergunb 0:8f0d870509fe 541 else
Sergunb 0:8f0d870509fe 542 {
Sergunb 0:8f0d870509fe 543 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
Sergunb 0:8f0d870509fe 544 }
Sergunb 0:8f0d870509fe 545 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 546 #endif
Sergunb 0:8f0d870509fe 547
Sergunb 0:8f0d870509fe 548 /* HCLK = SYSCLK */
Sergunb 0:8f0d870509fe 549 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:8f0d870509fe 550
Sergunb 0:8f0d870509fe 551 /* PCLK2 = HCLK */
Sergunb 0:8f0d870509fe 552 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:8f0d870509fe 553
Sergunb 0:8f0d870509fe 554 /* PCLK1 = HCLK */
Sergunb 0:8f0d870509fe 555 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
Sergunb 0:8f0d870509fe 556
Sergunb 0:8f0d870509fe 557 /* Select HSE as system clock source */
Sergunb 0:8f0d870509fe 558 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:8f0d870509fe 559 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
Sergunb 0:8f0d870509fe 560
Sergunb 0:8f0d870509fe 561 /* Wait till HSE is used as system clock source */
Sergunb 0:8f0d870509fe 562 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
Sergunb 0:8f0d870509fe 563 {
Sergunb 0:8f0d870509fe 564 }
Sergunb 0:8f0d870509fe 565 }
Sergunb 0:8f0d870509fe 566 else
Sergunb 0:8f0d870509fe 567 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:8f0d870509fe 568 configuration. User can add here some code to deal with this error */
Sergunb 0:8f0d870509fe 569 }
Sergunb 0:8f0d870509fe 570 }
Sergunb 0:8f0d870509fe 571 #elif defined SYSCLK_FREQ_24MHz
Sergunb 0:8f0d870509fe 572 /**
Sergunb 0:8f0d870509fe 573 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
Sergunb 0:8f0d870509fe 574 * and PCLK1 prescalers.
Sergunb 0:8f0d870509fe 575 * @note This function should be used only after reset.
Sergunb 0:8f0d870509fe 576 * @param None
Sergunb 0:8f0d870509fe 577 * @retval None
Sergunb 0:8f0d870509fe 578 */
Sergunb 0:8f0d870509fe 579 static void SetSysClockTo24(void)
Sergunb 0:8f0d870509fe 580 {
Sergunb 0:8f0d870509fe 581 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:8f0d870509fe 582
Sergunb 0:8f0d870509fe 583 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:8f0d870509fe 584 /* Enable HSE */
Sergunb 0:8f0d870509fe 585 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:8f0d870509fe 586
Sergunb 0:8f0d870509fe 587 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:8f0d870509fe 588 do
Sergunb 0:8f0d870509fe 589 {
Sergunb 0:8f0d870509fe 590 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:8f0d870509fe 591 StartUpCounter++;
Sergunb 0:8f0d870509fe 592 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:8f0d870509fe 593
Sergunb 0:8f0d870509fe 594 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:8f0d870509fe 595 {
Sergunb 0:8f0d870509fe 596 HSEStatus = (uint32_t)0x01;
Sergunb 0:8f0d870509fe 597 }
Sergunb 0:8f0d870509fe 598 else
Sergunb 0:8f0d870509fe 599 {
Sergunb 0:8f0d870509fe 600 HSEStatus = (uint32_t)0x00;
Sergunb 0:8f0d870509fe 601 }
Sergunb 0:8f0d870509fe 602
Sergunb 0:8f0d870509fe 603 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:8f0d870509fe 604 {
Sergunb 0:8f0d870509fe 605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
Sergunb 0:8f0d870509fe 606 /* Enable Prefetch Buffer */
Sergunb 0:8f0d870509fe 607 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:8f0d870509fe 608
Sergunb 0:8f0d870509fe 609 /* Flash 0 wait state */
Sergunb 0:8f0d870509fe 610 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:8f0d870509fe 611 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
Sergunb 0:8f0d870509fe 612 #endif
Sergunb 0:8f0d870509fe 613
Sergunb 0:8f0d870509fe 614 /* HCLK = SYSCLK */
Sergunb 0:8f0d870509fe 615 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:8f0d870509fe 616
Sergunb 0:8f0d870509fe 617 /* PCLK2 = HCLK */
Sergunb 0:8f0d870509fe 618 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:8f0d870509fe 619
Sergunb 0:8f0d870509fe 620 /* PCLK1 = HCLK */
Sergunb 0:8f0d870509fe 621 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
Sergunb 0:8f0d870509fe 622
Sergunb 0:8f0d870509fe 623 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 624 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:8f0d870509fe 625 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
Sergunb 0:8f0d870509fe 626 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:8f0d870509fe 627 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:8f0d870509fe 628 RCC_CFGR_PLLMULL6);
Sergunb 0:8f0d870509fe 629
Sergunb 0:8f0d870509fe 630 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:8f0d870509fe 631 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
Sergunb 0:8f0d870509fe 632 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:8f0d870509fe 633 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:8f0d870509fe 634 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:8f0d870509fe 635 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
Sergunb 0:8f0d870509fe 636
Sergunb 0:8f0d870509fe 637 /* Enable PLL2 */
Sergunb 0:8f0d870509fe 638 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:8f0d870509fe 639 /* Wait till PLL2 is ready */
Sergunb 0:8f0d870509fe 640 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:8f0d870509fe 641 {
Sergunb 0:8f0d870509fe 642 }
Sergunb 0:8f0d870509fe 643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
Sergunb 0:8f0d870509fe 644 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
Sergunb 0:8f0d870509fe 645 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:8f0d870509fe 646 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
Sergunb 0:8f0d870509fe 647 #else
Sergunb 0:8f0d870509fe 648 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
Sergunb 0:8f0d870509fe 649 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:8f0d870509fe 650 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
Sergunb 0:8f0d870509fe 651 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 652
Sergunb 0:8f0d870509fe 653 /* Enable PLL */
Sergunb 0:8f0d870509fe 654 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:8f0d870509fe 655
Sergunb 0:8f0d870509fe 656 /* Wait till PLL is ready */
Sergunb 0:8f0d870509fe 657 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:8f0d870509fe 658 {
Sergunb 0:8f0d870509fe 659 }
Sergunb 0:8f0d870509fe 660
Sergunb 0:8f0d870509fe 661 /* Select PLL as system clock source */
Sergunb 0:8f0d870509fe 662 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:8f0d870509fe 663 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:8f0d870509fe 664
Sergunb 0:8f0d870509fe 665 /* Wait till PLL is used as system clock source */
Sergunb 0:8f0d870509fe 666 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:8f0d870509fe 667 {
Sergunb 0:8f0d870509fe 668 }
Sergunb 0:8f0d870509fe 669 }
Sergunb 0:8f0d870509fe 670 else
Sergunb 0:8f0d870509fe 671 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:8f0d870509fe 672 configuration. User can add here some code to deal with this error */
Sergunb 0:8f0d870509fe 673 }
Sergunb 0:8f0d870509fe 674 }
Sergunb 0:8f0d870509fe 675 #elif defined SYSCLK_FREQ_36MHz
Sergunb 0:8f0d870509fe 676 /**
Sergunb 0:8f0d870509fe 677 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
Sergunb 0:8f0d870509fe 678 * and PCLK1 prescalers.
Sergunb 0:8f0d870509fe 679 * @note This function should be used only after reset.
Sergunb 0:8f0d870509fe 680 * @param None
Sergunb 0:8f0d870509fe 681 * @retval None
Sergunb 0:8f0d870509fe 682 */
Sergunb 0:8f0d870509fe 683 static void SetSysClockTo36(void)
Sergunb 0:8f0d870509fe 684 {
Sergunb 0:8f0d870509fe 685 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:8f0d870509fe 686
Sergunb 0:8f0d870509fe 687 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:8f0d870509fe 688 /* Enable HSE */
Sergunb 0:8f0d870509fe 689 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:8f0d870509fe 690
Sergunb 0:8f0d870509fe 691 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:8f0d870509fe 692 do
Sergunb 0:8f0d870509fe 693 {
Sergunb 0:8f0d870509fe 694 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:8f0d870509fe 695 StartUpCounter++;
Sergunb 0:8f0d870509fe 696 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:8f0d870509fe 697
Sergunb 0:8f0d870509fe 698 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:8f0d870509fe 699 {
Sergunb 0:8f0d870509fe 700 HSEStatus = (uint32_t)0x01;
Sergunb 0:8f0d870509fe 701 }
Sergunb 0:8f0d870509fe 702 else
Sergunb 0:8f0d870509fe 703 {
Sergunb 0:8f0d870509fe 704 HSEStatus = (uint32_t)0x00;
Sergunb 0:8f0d870509fe 705 }
Sergunb 0:8f0d870509fe 706
Sergunb 0:8f0d870509fe 707 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:8f0d870509fe 708 {
Sergunb 0:8f0d870509fe 709 /* Enable Prefetch Buffer */
Sergunb 0:8f0d870509fe 710 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:8f0d870509fe 711
Sergunb 0:8f0d870509fe 712 /* Flash 1 wait state */
Sergunb 0:8f0d870509fe 713 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:8f0d870509fe 714 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
Sergunb 0:8f0d870509fe 715
Sergunb 0:8f0d870509fe 716 /* HCLK = SYSCLK */
Sergunb 0:8f0d870509fe 717 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:8f0d870509fe 718
Sergunb 0:8f0d870509fe 719 /* PCLK2 = HCLK */
Sergunb 0:8f0d870509fe 720 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:8f0d870509fe 721
Sergunb 0:8f0d870509fe 722 /* PCLK1 = HCLK */
Sergunb 0:8f0d870509fe 723 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
Sergunb 0:8f0d870509fe 724
Sergunb 0:8f0d870509fe 725 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 726 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:8f0d870509fe 727
Sergunb 0:8f0d870509fe 728 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
Sergunb 0:8f0d870509fe 729 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:8f0d870509fe 730 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:8f0d870509fe 731 RCC_CFGR_PLLMULL9);
Sergunb 0:8f0d870509fe 732
Sergunb 0:8f0d870509fe 733 /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:8f0d870509fe 734 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
Sergunb 0:8f0d870509fe 735
Sergunb 0:8f0d870509fe 736 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:8f0d870509fe 737 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:8f0d870509fe 738 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:8f0d870509fe 739 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
Sergunb 0:8f0d870509fe 740
Sergunb 0:8f0d870509fe 741 /* Enable PLL2 */
Sergunb 0:8f0d870509fe 742 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:8f0d870509fe 743 /* Wait till PLL2 is ready */
Sergunb 0:8f0d870509fe 744 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:8f0d870509fe 745 {
Sergunb 0:8f0d870509fe 746 }
Sergunb 0:8f0d870509fe 747
Sergunb 0:8f0d870509fe 748 #else
Sergunb 0:8f0d870509fe 749 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
Sergunb 0:8f0d870509fe 750 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:8f0d870509fe 751 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
Sergunb 0:8f0d870509fe 752 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 753
Sergunb 0:8f0d870509fe 754 /* Enable PLL */
Sergunb 0:8f0d870509fe 755 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:8f0d870509fe 756
Sergunb 0:8f0d870509fe 757 /* Wait till PLL is ready */
Sergunb 0:8f0d870509fe 758 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:8f0d870509fe 759 {
Sergunb 0:8f0d870509fe 760 }
Sergunb 0:8f0d870509fe 761
Sergunb 0:8f0d870509fe 762 /* Select PLL as system clock source */
Sergunb 0:8f0d870509fe 763 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:8f0d870509fe 764 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:8f0d870509fe 765
Sergunb 0:8f0d870509fe 766 /* Wait till PLL is used as system clock source */
Sergunb 0:8f0d870509fe 767 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:8f0d870509fe 768 {
Sergunb 0:8f0d870509fe 769 }
Sergunb 0:8f0d870509fe 770 }
Sergunb 0:8f0d870509fe 771 else
Sergunb 0:8f0d870509fe 772 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:8f0d870509fe 773 configuration. User can add here some code to deal with this error */
Sergunb 0:8f0d870509fe 774 }
Sergunb 0:8f0d870509fe 775 }
Sergunb 0:8f0d870509fe 776 #elif defined SYSCLK_FREQ_48MHz
Sergunb 0:8f0d870509fe 777 /**
Sergunb 0:8f0d870509fe 778 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
Sergunb 0:8f0d870509fe 779 * and PCLK1 prescalers.
Sergunb 0:8f0d870509fe 780 * @note This function should be used only after reset.
Sergunb 0:8f0d870509fe 781 * @param None
Sergunb 0:8f0d870509fe 782 * @retval None
Sergunb 0:8f0d870509fe 783 */
Sergunb 0:8f0d870509fe 784 static void SetSysClockTo48(void)
Sergunb 0:8f0d870509fe 785 {
Sergunb 0:8f0d870509fe 786 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:8f0d870509fe 787
Sergunb 0:8f0d870509fe 788 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:8f0d870509fe 789 /* Enable HSE */
Sergunb 0:8f0d870509fe 790 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:8f0d870509fe 791
Sergunb 0:8f0d870509fe 792 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:8f0d870509fe 793 do
Sergunb 0:8f0d870509fe 794 {
Sergunb 0:8f0d870509fe 795 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:8f0d870509fe 796 StartUpCounter++;
Sergunb 0:8f0d870509fe 797 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:8f0d870509fe 798
Sergunb 0:8f0d870509fe 799 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:8f0d870509fe 800 {
Sergunb 0:8f0d870509fe 801 HSEStatus = (uint32_t)0x01;
Sergunb 0:8f0d870509fe 802 }
Sergunb 0:8f0d870509fe 803 else
Sergunb 0:8f0d870509fe 804 {
Sergunb 0:8f0d870509fe 805 HSEStatus = (uint32_t)0x00;
Sergunb 0:8f0d870509fe 806 }
Sergunb 0:8f0d870509fe 807
Sergunb 0:8f0d870509fe 808 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:8f0d870509fe 809 {
Sergunb 0:8f0d870509fe 810 /* Enable Prefetch Buffer */
Sergunb 0:8f0d870509fe 811 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:8f0d870509fe 812
Sergunb 0:8f0d870509fe 813 /* Flash 1 wait state */
Sergunb 0:8f0d870509fe 814 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:8f0d870509fe 815 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
Sergunb 0:8f0d870509fe 816
Sergunb 0:8f0d870509fe 817 /* HCLK = SYSCLK */
Sergunb 0:8f0d870509fe 818 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:8f0d870509fe 819
Sergunb 0:8f0d870509fe 820 /* PCLK2 = HCLK */
Sergunb 0:8f0d870509fe 821 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:8f0d870509fe 822
Sergunb 0:8f0d870509fe 823 /* PCLK1 = HCLK */
Sergunb 0:8f0d870509fe 824 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
Sergunb 0:8f0d870509fe 825
Sergunb 0:8f0d870509fe 826 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 827 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:8f0d870509fe 828 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:8f0d870509fe 829 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
Sergunb 0:8f0d870509fe 830
Sergunb 0:8f0d870509fe 831 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:8f0d870509fe 832 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:8f0d870509fe 833 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:8f0d870509fe 834 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
Sergunb 0:8f0d870509fe 835
Sergunb 0:8f0d870509fe 836 /* Enable PLL2 */
Sergunb 0:8f0d870509fe 837 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:8f0d870509fe 838 /* Wait till PLL2 is ready */
Sergunb 0:8f0d870509fe 839 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:8f0d870509fe 840 {
Sergunb 0:8f0d870509fe 841 }
Sergunb 0:8f0d870509fe 842
Sergunb 0:8f0d870509fe 843
Sergunb 0:8f0d870509fe 844 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
Sergunb 0:8f0d870509fe 845 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:8f0d870509fe 846 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:8f0d870509fe 847 RCC_CFGR_PLLMULL6);
Sergunb 0:8f0d870509fe 848 #else
Sergunb 0:8f0d870509fe 849 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
Sergunb 0:8f0d870509fe 850 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:8f0d870509fe 851 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
Sergunb 0:8f0d870509fe 852 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 853
Sergunb 0:8f0d870509fe 854 /* Enable PLL */
Sergunb 0:8f0d870509fe 855 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:8f0d870509fe 856
Sergunb 0:8f0d870509fe 857 /* Wait till PLL is ready */
Sergunb 0:8f0d870509fe 858 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:8f0d870509fe 859 {
Sergunb 0:8f0d870509fe 860 }
Sergunb 0:8f0d870509fe 861
Sergunb 0:8f0d870509fe 862 /* Select PLL as system clock source */
Sergunb 0:8f0d870509fe 863 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:8f0d870509fe 864 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:8f0d870509fe 865
Sergunb 0:8f0d870509fe 866 /* Wait till PLL is used as system clock source */
Sergunb 0:8f0d870509fe 867 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:8f0d870509fe 868 {
Sergunb 0:8f0d870509fe 869 }
Sergunb 0:8f0d870509fe 870 }
Sergunb 0:8f0d870509fe 871 else
Sergunb 0:8f0d870509fe 872 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:8f0d870509fe 873 configuration. User can add here some code to deal with this error */
Sergunb 0:8f0d870509fe 874 }
Sergunb 0:8f0d870509fe 875 }
Sergunb 0:8f0d870509fe 876
Sergunb 0:8f0d870509fe 877 #elif defined SYSCLK_FREQ_56MHz
Sergunb 0:8f0d870509fe 878 /**
Sergunb 0:8f0d870509fe 879 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
Sergunb 0:8f0d870509fe 880 * and PCLK1 prescalers.
Sergunb 0:8f0d870509fe 881 * @note This function should be used only after reset.
Sergunb 0:8f0d870509fe 882 * @param None
Sergunb 0:8f0d870509fe 883 * @retval None
Sergunb 0:8f0d870509fe 884 */
Sergunb 0:8f0d870509fe 885 static void SetSysClockTo56(void)
Sergunb 0:8f0d870509fe 886 {
Sergunb 0:8f0d870509fe 887 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:8f0d870509fe 888
Sergunb 0:8f0d870509fe 889 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:8f0d870509fe 890 /* Enable HSE */
Sergunb 0:8f0d870509fe 891 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:8f0d870509fe 892
Sergunb 0:8f0d870509fe 893 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:8f0d870509fe 894 do
Sergunb 0:8f0d870509fe 895 {
Sergunb 0:8f0d870509fe 896 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:8f0d870509fe 897 StartUpCounter++;
Sergunb 0:8f0d870509fe 898 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:8f0d870509fe 899
Sergunb 0:8f0d870509fe 900 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:8f0d870509fe 901 {
Sergunb 0:8f0d870509fe 902 HSEStatus = (uint32_t)0x01;
Sergunb 0:8f0d870509fe 903 }
Sergunb 0:8f0d870509fe 904 else
Sergunb 0:8f0d870509fe 905 {
Sergunb 0:8f0d870509fe 906 HSEStatus = (uint32_t)0x00;
Sergunb 0:8f0d870509fe 907 }
Sergunb 0:8f0d870509fe 908
Sergunb 0:8f0d870509fe 909 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:8f0d870509fe 910 {
Sergunb 0:8f0d870509fe 911 /* Enable Prefetch Buffer */
Sergunb 0:8f0d870509fe 912 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:8f0d870509fe 913
Sergunb 0:8f0d870509fe 914 /* Flash 2 wait state */
Sergunb 0:8f0d870509fe 915 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:8f0d870509fe 916 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
Sergunb 0:8f0d870509fe 917
Sergunb 0:8f0d870509fe 918 /* HCLK = SYSCLK */
Sergunb 0:8f0d870509fe 919 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:8f0d870509fe 920
Sergunb 0:8f0d870509fe 921 /* PCLK2 = HCLK */
Sergunb 0:8f0d870509fe 922 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:8f0d870509fe 923
Sergunb 0:8f0d870509fe 924 /* PCLK1 = HCLK */
Sergunb 0:8f0d870509fe 925 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
Sergunb 0:8f0d870509fe 926
Sergunb 0:8f0d870509fe 927 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 928 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:8f0d870509fe 929 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:8f0d870509fe 930 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
Sergunb 0:8f0d870509fe 931
Sergunb 0:8f0d870509fe 932 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:8f0d870509fe 933 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:8f0d870509fe 934 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:8f0d870509fe 935 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
Sergunb 0:8f0d870509fe 936
Sergunb 0:8f0d870509fe 937 /* Enable PLL2 */
Sergunb 0:8f0d870509fe 938 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:8f0d870509fe 939 /* Wait till PLL2 is ready */
Sergunb 0:8f0d870509fe 940 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:8f0d870509fe 941 {
Sergunb 0:8f0d870509fe 942 }
Sergunb 0:8f0d870509fe 943
Sergunb 0:8f0d870509fe 944
Sergunb 0:8f0d870509fe 945 /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
Sergunb 0:8f0d870509fe 946 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:8f0d870509fe 947 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:8f0d870509fe 948 RCC_CFGR_PLLMULL7);
Sergunb 0:8f0d870509fe 949 #else
Sergunb 0:8f0d870509fe 950 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
Sergunb 0:8f0d870509fe 951 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:8f0d870509fe 952 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
Sergunb 0:8f0d870509fe 953
Sergunb 0:8f0d870509fe 954 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 955
Sergunb 0:8f0d870509fe 956 /* Enable PLL */
Sergunb 0:8f0d870509fe 957 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:8f0d870509fe 958
Sergunb 0:8f0d870509fe 959 /* Wait till PLL is ready */
Sergunb 0:8f0d870509fe 960 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:8f0d870509fe 961 {
Sergunb 0:8f0d870509fe 962 }
Sergunb 0:8f0d870509fe 963
Sergunb 0:8f0d870509fe 964 /* Select PLL as system clock source */
Sergunb 0:8f0d870509fe 965 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:8f0d870509fe 966 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:8f0d870509fe 967
Sergunb 0:8f0d870509fe 968 /* Wait till PLL is used as system clock source */
Sergunb 0:8f0d870509fe 969 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:8f0d870509fe 970 {
Sergunb 0:8f0d870509fe 971 }
Sergunb 0:8f0d870509fe 972 }
Sergunb 0:8f0d870509fe 973 else
Sergunb 0:8f0d870509fe 974 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:8f0d870509fe 975 configuration. User can add here some code to deal with this error */
Sergunb 0:8f0d870509fe 976 }
Sergunb 0:8f0d870509fe 977 }
Sergunb 0:8f0d870509fe 978
Sergunb 0:8f0d870509fe 979 #elif defined SYSCLK_FREQ_72MHz
Sergunb 0:8f0d870509fe 980 /**
Sergunb 0:8f0d870509fe 981 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
Sergunb 0:8f0d870509fe 982 * and PCLK1 prescalers.
Sergunb 0:8f0d870509fe 983 * @note This function should be used only after reset.
Sergunb 0:8f0d870509fe 984 * @param None
Sergunb 0:8f0d870509fe 985 * @retval None
Sergunb 0:8f0d870509fe 986 */
Sergunb 0:8f0d870509fe 987 static void SetSysClockTo72(void)
Sergunb 0:8f0d870509fe 988 {
Sergunb 0:8f0d870509fe 989 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:8f0d870509fe 990
Sergunb 0:8f0d870509fe 991 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:8f0d870509fe 992 /* Enable HSE */
Sergunb 0:8f0d870509fe 993 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:8f0d870509fe 994
Sergunb 0:8f0d870509fe 995 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:8f0d870509fe 996 do
Sergunb 0:8f0d870509fe 997 {
Sergunb 0:8f0d870509fe 998 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:8f0d870509fe 999 StartUpCounter++;
Sergunb 0:8f0d870509fe 1000 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:8f0d870509fe 1001
Sergunb 0:8f0d870509fe 1002 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:8f0d870509fe 1003 {
Sergunb 0:8f0d870509fe 1004 HSEStatus = (uint32_t)0x01;
Sergunb 0:8f0d870509fe 1005 }
Sergunb 0:8f0d870509fe 1006 else
Sergunb 0:8f0d870509fe 1007 {
Sergunb 0:8f0d870509fe 1008 HSEStatus = (uint32_t)0x00;
Sergunb 0:8f0d870509fe 1009 }
Sergunb 0:8f0d870509fe 1010
Sergunb 0:8f0d870509fe 1011 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:8f0d870509fe 1012 {
Sergunb 0:8f0d870509fe 1013 /* Enable Prefetch Buffer */
Sergunb 0:8f0d870509fe 1014 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:8f0d870509fe 1015
Sergunb 0:8f0d870509fe 1016 /* Flash 2 wait state */
Sergunb 0:8f0d870509fe 1017 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:8f0d870509fe 1018 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
Sergunb 0:8f0d870509fe 1019
Sergunb 0:8f0d870509fe 1020
Sergunb 0:8f0d870509fe 1021 /* HCLK = SYSCLK */
Sergunb 0:8f0d870509fe 1022 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:8f0d870509fe 1023
Sergunb 0:8f0d870509fe 1024 /* PCLK2 = HCLK */
Sergunb 0:8f0d870509fe 1025 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:8f0d870509fe 1026
Sergunb 0:8f0d870509fe 1027 /* PCLK1 = HCLK */
Sergunb 0:8f0d870509fe 1028 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
Sergunb 0:8f0d870509fe 1029
Sergunb 0:8f0d870509fe 1030 #ifdef STM32F10X_CL
Sergunb 0:8f0d870509fe 1031 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:8f0d870509fe 1032 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:8f0d870509fe 1033 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
Sergunb 0:8f0d870509fe 1034
Sergunb 0:8f0d870509fe 1035 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:8f0d870509fe 1036 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:8f0d870509fe 1037 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:8f0d870509fe 1038 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
Sergunb 0:8f0d870509fe 1039
Sergunb 0:8f0d870509fe 1040 /* Enable PLL2 */
Sergunb 0:8f0d870509fe 1041 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:8f0d870509fe 1042 /* Wait till PLL2 is ready */
Sergunb 0:8f0d870509fe 1043 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:8f0d870509fe 1044 {
Sergunb 0:8f0d870509fe 1045 }
Sergunb 0:8f0d870509fe 1046
Sergunb 0:8f0d870509fe 1047
Sergunb 0:8f0d870509fe 1048 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
Sergunb 0:8f0d870509fe 1049 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:8f0d870509fe 1050 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:8f0d870509fe 1051 RCC_CFGR_PLLMULL9);
Sergunb 0:8f0d870509fe 1052 #else
Sergunb 0:8f0d870509fe 1053 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
Sergunb 0:8f0d870509fe 1054 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
Sergunb 0:8f0d870509fe 1055 RCC_CFGR_PLLMULL));
Sergunb 0:8f0d870509fe 1056 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
Sergunb 0:8f0d870509fe 1057 #endif /* STM32F10X_CL */
Sergunb 0:8f0d870509fe 1058
Sergunb 0:8f0d870509fe 1059 /* Enable PLL */
Sergunb 0:8f0d870509fe 1060 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:8f0d870509fe 1061
Sergunb 0:8f0d870509fe 1062 /* Wait till PLL is ready */
Sergunb 0:8f0d870509fe 1063 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:8f0d870509fe 1064 {
Sergunb 0:8f0d870509fe 1065 }
Sergunb 0:8f0d870509fe 1066
Sergunb 0:8f0d870509fe 1067 /* Select PLL as system clock source */
Sergunb 0:8f0d870509fe 1068 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:8f0d870509fe 1069 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:8f0d870509fe 1070
Sergunb 0:8f0d870509fe 1071 /* Wait till PLL is used as system clock source */
Sergunb 0:8f0d870509fe 1072 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:8f0d870509fe 1073 {
Sergunb 0:8f0d870509fe 1074 }
Sergunb 0:8f0d870509fe 1075 }
Sergunb 0:8f0d870509fe 1076 else
Sergunb 0:8f0d870509fe 1077 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:8f0d870509fe 1078 configuration. User can add here some code to deal with this error */
Sergunb 0:8f0d870509fe 1079 }
Sergunb 0:8f0d870509fe 1080 }
Sergunb 0:8f0d870509fe 1081 #endif
Sergunb 0:8f0d870509fe 1082
Sergunb 0:8f0d870509fe 1083 /**
Sergunb 0:8f0d870509fe 1084 * @}
Sergunb 0:8f0d870509fe 1085 */
Sergunb 0:8f0d870509fe 1086
Sergunb 0:8f0d870509fe 1087 /**
Sergunb 0:8f0d870509fe 1088 * @}
Sergunb 0:8f0d870509fe 1089 */
Sergunb 0:8f0d870509fe 1090
Sergunb 0:8f0d870509fe 1091 /**
Sergunb 0:8f0d870509fe 1092 * @}
Sergunb 0:8f0d870509fe 1093 */
Sergunb 0:8f0d870509fe 1094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/