Sergey Pastor / grbl1

I'm trying to port GRBL 1.1 to the STM32F746 chip. Tell me the solution, thanks.

cmsis/core_cmInstr.h@0:8f0d870509fe, 2017-09-04 (annotated)

Committer:
Sergunb
Date:
Mon Sep 04 12:04:13 2017 +0000
Revision:
0:8f0d870509fe
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8f0d870509fe 1 /**************************************************************************//**
Sergunb 0:8f0d870509fe 2 * @file core_cmInstr.h
Sergunb 0:8f0d870509fe 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
Sergunb 0:8f0d870509fe 4 * @version V3.01
Sergunb 0:8f0d870509fe 5 * @date 06. March 2012
Sergunb 0:8f0d870509fe 6 *
Sergunb 0:8f0d870509fe 7 * @note
Sergunb 0:8f0d870509fe 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
Sergunb 0:8f0d870509fe 9 *
Sergunb 0:8f0d870509fe 10 * @par
Sergunb 0:8f0d870509fe 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Sergunb 0:8f0d870509fe 12 * processor based microcontrollers. This file can be freely distributed
Sergunb 0:8f0d870509fe 13 * within development tools that are supporting such ARM based processors.
Sergunb 0:8f0d870509fe 14 *
Sergunb 0:8f0d870509fe 15 * @par
Sergunb 0:8f0d870509fe 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Sergunb 0:8f0d870509fe 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Sergunb 0:8f0d870509fe 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Sergunb 0:8f0d870509fe 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Sergunb 0:8f0d870509fe 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Sergunb 0:8f0d870509fe 21 *
Sergunb 0:8f0d870509fe 22 ******************************************************************************/
Sergunb 0:8f0d870509fe 23
Sergunb 0:8f0d870509fe 24 #ifndef __CORE_CMINSTR_H
Sergunb 0:8f0d870509fe 25 #define __CORE_CMINSTR_H
Sergunb 0:8f0d870509fe 26
Sergunb 0:8f0d870509fe 27
Sergunb 0:8f0d870509fe 28 /* ########################## Core Instruction Access ######################### */
Sergunb 0:8f0d870509fe 29 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Sergunb 0:8f0d870509fe 30 Access to dedicated instructions
Sergunb 0:8f0d870509fe 31 @{
Sergunb 0:8f0d870509fe 32 */
Sergunb 0:8f0d870509fe 33
Sergunb 0:8f0d870509fe 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Sergunb 0:8f0d870509fe 35 /* ARM armcc specific functions */
Sergunb 0:8f0d870509fe 36
Sergunb 0:8f0d870509fe 37 #if (__ARMCC_VERSION < 400677)
Sergunb 0:8f0d870509fe 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Sergunb 0:8f0d870509fe 39 #endif
Sergunb 0:8f0d870509fe 40
Sergunb 0:8f0d870509fe 41
Sergunb 0:8f0d870509fe 42 /** \brief No Operation
Sergunb 0:8f0d870509fe 43
Sergunb 0:8f0d870509fe 44 No Operation does nothing. This instruction can be used for code alignment purposes.
Sergunb 0:8f0d870509fe 45 */
Sergunb 0:8f0d870509fe 46 #define __NOP __nop
Sergunb 0:8f0d870509fe 47
Sergunb 0:8f0d870509fe 48
Sergunb 0:8f0d870509fe 49 /** \brief Wait For Interrupt
Sergunb 0:8f0d870509fe 50
Sergunb 0:8f0d870509fe 51 Wait For Interrupt is a hint instruction that suspends execution
Sergunb 0:8f0d870509fe 52 until one of a number of events occurs.
Sergunb 0:8f0d870509fe 53 */
Sergunb 0:8f0d870509fe 54 #define __WFI __wfi
Sergunb 0:8f0d870509fe 55
Sergunb 0:8f0d870509fe 56
Sergunb 0:8f0d870509fe 57 /** \brief Wait For Event
Sergunb 0:8f0d870509fe 58
Sergunb 0:8f0d870509fe 59 Wait For Event is a hint instruction that permits the processor to enter
Sergunb 0:8f0d870509fe 60 a low-power state until one of a number of events occurs.
Sergunb 0:8f0d870509fe 61 */
Sergunb 0:8f0d870509fe 62 #define __WFE __wfe
Sergunb 0:8f0d870509fe 63
Sergunb 0:8f0d870509fe 64
Sergunb 0:8f0d870509fe 65 /** \brief Send Event
Sergunb 0:8f0d870509fe 66
Sergunb 0:8f0d870509fe 67 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
Sergunb 0:8f0d870509fe 68 */
Sergunb 0:8f0d870509fe 69 #define __SEV __sev
Sergunb 0:8f0d870509fe 70
Sergunb 0:8f0d870509fe 71
Sergunb 0:8f0d870509fe 72 /** \brief Instruction Synchronization Barrier
Sergunb 0:8f0d870509fe 73
Sergunb 0:8f0d870509fe 74 Instruction Synchronization Barrier flushes the pipeline in the processor,
Sergunb 0:8f0d870509fe 75 so that all instructions following the ISB are fetched from cache or
Sergunb 0:8f0d870509fe 76 memory, after the instruction has been completed.
Sergunb 0:8f0d870509fe 77 */
Sergunb 0:8f0d870509fe 78 #define __ISB() __isb(0xF)
Sergunb 0:8f0d870509fe 79
Sergunb 0:8f0d870509fe 80
Sergunb 0:8f0d870509fe 81 /** \brief Data Synchronization Barrier
Sergunb 0:8f0d870509fe 82
Sergunb 0:8f0d870509fe 83 This function acts as a special kind of Data Memory Barrier.
Sergunb 0:8f0d870509fe 84 It completes when all explicit memory accesses before this instruction complete.
Sergunb 0:8f0d870509fe 85 */
Sergunb 0:8f0d870509fe 86 #define __DSB() __dsb(0xF)
Sergunb 0:8f0d870509fe 87
Sergunb 0:8f0d870509fe 88
Sergunb 0:8f0d870509fe 89 /** \brief Data Memory Barrier
Sergunb 0:8f0d870509fe 90
Sergunb 0:8f0d870509fe 91 This function ensures the apparent order of the explicit memory operations before
Sergunb 0:8f0d870509fe 92 and after the instruction, without ensuring their completion.
Sergunb 0:8f0d870509fe 93 */
Sergunb 0:8f0d870509fe 94 #define __DMB() __dmb(0xF)
Sergunb 0:8f0d870509fe 95
Sergunb 0:8f0d870509fe 96
Sergunb 0:8f0d870509fe 97 /** \brief Reverse byte order (32 bit)
Sergunb 0:8f0d870509fe 98
Sergunb 0:8f0d870509fe 99 This function reverses the byte order in integer value.
Sergunb 0:8f0d870509fe 100
Sergunb 0:8f0d870509fe 101 \param [in] value Value to reverse
Sergunb 0:8f0d870509fe 102 \return Reversed value
Sergunb 0:8f0d870509fe 103 */
Sergunb 0:8f0d870509fe 104 #define __REV __rev
Sergunb 0:8f0d870509fe 105
Sergunb 0:8f0d870509fe 106
Sergunb 0:8f0d870509fe 107 /** \brief Reverse byte order (16 bit)
Sergunb 0:8f0d870509fe 108
Sergunb 0:8f0d870509fe 109 This function reverses the byte order in two unsigned short values.
Sergunb 0:8f0d870509fe 110
Sergunb 0:8f0d870509fe 111 \param [in] value Value to reverse
Sergunb 0:8f0d870509fe 112 \return Reversed value
Sergunb 0:8f0d870509fe 113 */
Sergunb 0:8f0d870509fe 114 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
Sergunb 0:8f0d870509fe 115 {
Sergunb 0:8f0d870509fe 116 rev16 r0, r0
Sergunb 0:8f0d870509fe 117 bx lr
Sergunb 0:8f0d870509fe 118 }
Sergunb 0:8f0d870509fe 119
Sergunb 0:8f0d870509fe 120
Sergunb 0:8f0d870509fe 121 /** \brief Reverse byte order in signed short value
Sergunb 0:8f0d870509fe 122
Sergunb 0:8f0d870509fe 123 This function reverses the byte order in a signed short value with sign extension to integer.
Sergunb 0:8f0d870509fe 124
Sergunb 0:8f0d870509fe 125 \param [in] value Value to reverse
Sergunb 0:8f0d870509fe 126 \return Reversed value
Sergunb 0:8f0d870509fe 127 */
Sergunb 0:8f0d870509fe 128 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
Sergunb 0:8f0d870509fe 129 {
Sergunb 0:8f0d870509fe 130 revsh r0, r0
Sergunb 0:8f0d870509fe 131 bx lr
Sergunb 0:8f0d870509fe 132 }
Sergunb 0:8f0d870509fe 133
Sergunb 0:8f0d870509fe 134
Sergunb 0:8f0d870509fe 135 /** \brief Rotate Right in unsigned value (32 bit)
Sergunb 0:8f0d870509fe 136
Sergunb 0:8f0d870509fe 137 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
Sergunb 0:8f0d870509fe 138
Sergunb 0:8f0d870509fe 139 \param [in] value Value to rotate
Sergunb 0:8f0d870509fe 140 \param [in] value Number of Bits to rotate
Sergunb 0:8f0d870509fe 141 \return Rotated value
Sergunb 0:8f0d870509fe 142 */
Sergunb 0:8f0d870509fe 143 #define __ROR __ror
Sergunb 0:8f0d870509fe 144
Sergunb 0:8f0d870509fe 145
Sergunb 0:8f0d870509fe 146 #if (__CORTEX_M >= 0x03)
Sergunb 0:8f0d870509fe 147
Sergunb 0:8f0d870509fe 148 /** \brief Reverse bit order of value
Sergunb 0:8f0d870509fe 149
Sergunb 0:8f0d870509fe 150 This function reverses the bit order of the given value.
Sergunb 0:8f0d870509fe 151
Sergunb 0:8f0d870509fe 152 \param [in] value Value to reverse
Sergunb 0:8f0d870509fe 153 \return Reversed value
Sergunb 0:8f0d870509fe 154 */
Sergunb 0:8f0d870509fe 155 #define __RBIT __rbit
Sergunb 0:8f0d870509fe 156
Sergunb 0:8f0d870509fe 157
Sergunb 0:8f0d870509fe 158 /** \brief LDR Exclusive (8 bit)
Sergunb 0:8f0d870509fe 159
Sergunb 0:8f0d870509fe 160 This function performs a exclusive LDR command for 8 bit value.
Sergunb 0:8f0d870509fe 161
Sergunb 0:8f0d870509fe 162 \param [in] ptr Pointer to data
Sergunb 0:8f0d870509fe 163 \return value of type uint8_t at (*ptr)
Sergunb 0:8f0d870509fe 164 */
Sergunb 0:8f0d870509fe 165 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
Sergunb 0:8f0d870509fe 166
Sergunb 0:8f0d870509fe 167
Sergunb 0:8f0d870509fe 168 /** \brief LDR Exclusive (16 bit)
Sergunb 0:8f0d870509fe 169
Sergunb 0:8f0d870509fe 170 This function performs a exclusive LDR command for 16 bit values.
Sergunb 0:8f0d870509fe 171
Sergunb 0:8f0d870509fe 172 \param [in] ptr Pointer to data
Sergunb 0:8f0d870509fe 173 \return value of type uint16_t at (*ptr)
Sergunb 0:8f0d870509fe 174 */
Sergunb 0:8f0d870509fe 175 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
Sergunb 0:8f0d870509fe 176
Sergunb 0:8f0d870509fe 177
Sergunb 0:8f0d870509fe 178 /** \brief LDR Exclusive (32 bit)
Sergunb 0:8f0d870509fe 179
Sergunb 0:8f0d870509fe 180 This function performs a exclusive LDR command for 32 bit values.
Sergunb 0:8f0d870509fe 181
Sergunb 0:8f0d870509fe 182 \param [in] ptr Pointer to data
Sergunb 0:8f0d870509fe 183 \return value of type uint32_t at (*ptr)
Sergunb 0:8f0d870509fe 184 */
Sergunb 0:8f0d870509fe 185 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
Sergunb 0:8f0d870509fe 186
Sergunb 0:8f0d870509fe 187
Sergunb 0:8f0d870509fe 188 /** \brief STR Exclusive (8 bit)
Sergunb 0:8f0d870509fe 189
Sergunb 0:8f0d870509fe 190 This function performs a exclusive STR command for 8 bit values.
Sergunb 0:8f0d870509fe 191
Sergunb 0:8f0d870509fe 192 \param [in] value Value to store
Sergunb 0:8f0d870509fe 193 \param [in] ptr Pointer to location
Sergunb 0:8f0d870509fe 194 \return 0 Function succeeded
Sergunb 0:8f0d870509fe 195 \return 1 Function failed
Sergunb 0:8f0d870509fe 196 */
Sergunb 0:8f0d870509fe 197 #define __STREXB(value, ptr) __strex(value, ptr)
Sergunb 0:8f0d870509fe 198
Sergunb 0:8f0d870509fe 199
Sergunb 0:8f0d870509fe 200 /** \brief STR Exclusive (16 bit)
Sergunb 0:8f0d870509fe 201
Sergunb 0:8f0d870509fe 202 This function performs a exclusive STR command for 16 bit values.
Sergunb 0:8f0d870509fe 203
Sergunb 0:8f0d870509fe 204 \param [in] value Value to store
Sergunb 0:8f0d870509fe 205 \param [in] ptr Pointer to location
Sergunb 0:8f0d870509fe 206 \return 0 Function succeeded
Sergunb 0:8f0d870509fe 207 \return 1 Function failed
Sergunb 0:8f0d870509fe 208 */
Sergunb 0:8f0d870509fe 209 #define __STREXH(value, ptr) __strex(value, ptr)
Sergunb 0:8f0d870509fe 210
Sergunb 0:8f0d870509fe 211
Sergunb 0:8f0d870509fe 212 /** \brief STR Exclusive (32 bit)
Sergunb 0:8f0d870509fe 213
Sergunb 0:8f0d870509fe 214 This function performs a exclusive STR command for 32 bit values.
Sergunb 0:8f0d870509fe 215
Sergunb 0:8f0d870509fe 216 \param [in] value Value to store
Sergunb 0:8f0d870509fe 217 \param [in] ptr Pointer to location
Sergunb 0:8f0d870509fe 218 \return 0 Function succeeded
Sergunb 0:8f0d870509fe 219 \return 1 Function failed
Sergunb 0:8f0d870509fe 220 */
Sergunb 0:8f0d870509fe 221 #define __STREXW(value, ptr) __strex(value, ptr)
Sergunb 0:8f0d870509fe 222
Sergunb 0:8f0d870509fe 223
Sergunb 0:8f0d870509fe 224 /** \brief Remove the exclusive lock
Sergunb 0:8f0d870509fe 225
Sergunb 0:8f0d870509fe 226 This function removes the exclusive lock which is created by LDREX.
Sergunb 0:8f0d870509fe 227
Sergunb 0:8f0d870509fe 228 */
Sergunb 0:8f0d870509fe 229 #define __CLREX __clrex
Sergunb 0:8f0d870509fe 230
Sergunb 0:8f0d870509fe 231
Sergunb 0:8f0d870509fe 232 /** \brief Signed Saturate
Sergunb 0:8f0d870509fe 233
Sergunb 0:8f0d870509fe 234 This function saturates a signed value.
Sergunb 0:8f0d870509fe 235
Sergunb 0:8f0d870509fe 236 \param [in] value Value to be saturated
Sergunb 0:8f0d870509fe 237 \param [in] sat Bit position to saturate to (1..32)
Sergunb 0:8f0d870509fe 238 \return Saturated value
Sergunb 0:8f0d870509fe 239 */
Sergunb 0:8f0d870509fe 240 #define __SSAT __ssat
Sergunb 0:8f0d870509fe 241
Sergunb 0:8f0d870509fe 242
Sergunb 0:8f0d870509fe 243 /** \brief Unsigned Saturate
Sergunb 0:8f0d870509fe 244
Sergunb 0:8f0d870509fe 245 This function saturates an unsigned value.
Sergunb 0:8f0d870509fe 246
Sergunb 0:8f0d870509fe 247 \param [in] value Value to be saturated
Sergunb 0:8f0d870509fe 248 \param [in] sat Bit position to saturate to (0..31)
Sergunb 0:8f0d870509fe 249 \return Saturated value
Sergunb 0:8f0d870509fe 250 */
Sergunb 0:8f0d870509fe 251 #define __USAT __usat
Sergunb 0:8f0d870509fe 252
Sergunb 0:8f0d870509fe 253
Sergunb 0:8f0d870509fe 254 /** \brief Count leading zeros
Sergunb 0:8f0d870509fe 255
Sergunb 0:8f0d870509fe 256 This function counts the number of leading zeros of a data value.
Sergunb 0:8f0d870509fe 257
Sergunb 0:8f0d870509fe 258 \param [in] value Value to count the leading zeros
Sergunb 0:8f0d870509fe 259 \return number of leading zeros in value
Sergunb 0:8f0d870509fe 260 */
Sergunb 0:8f0d870509fe 261 #define __CLZ __clz
Sergunb 0:8f0d870509fe 262
Sergunb 0:8f0d870509fe 263 #endif /* (__CORTEX_M >= 0x03) */
Sergunb 0:8f0d870509fe 264
Sergunb 0:8f0d870509fe 265
Sergunb 0:8f0d870509fe 266
Sergunb 0:8f0d870509fe 267 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
Sergunb 0:8f0d870509fe 268 /* IAR iccarm specific functions */
Sergunb 0:8f0d870509fe 269
Sergunb 0:8f0d870509fe 270 #include <cmsis_iar.h>
Sergunb 0:8f0d870509fe 271
Sergunb 0:8f0d870509fe 272
Sergunb 0:8f0d870509fe 273 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
Sergunb 0:8f0d870509fe 274 /* TI CCS specific functions */
Sergunb 0:8f0d870509fe 275
Sergunb 0:8f0d870509fe 276 #include <cmsis_ccs.h>
Sergunb 0:8f0d870509fe 277
Sergunb 0:8f0d870509fe 278
Sergunb 0:8f0d870509fe 279 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
Sergunb 0:8f0d870509fe 280 /* GNU gcc specific functions */
Sergunb 0:8f0d870509fe 281
Sergunb 0:8f0d870509fe 282 /** \brief No Operation
Sergunb 0:8f0d870509fe 283
Sergunb 0:8f0d870509fe 284 No Operation does nothing. This instruction can be used for code alignment purposes.
Sergunb 0:8f0d870509fe 285 */
Sergunb 0:8f0d870509fe 286 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
Sergunb 0:8f0d870509fe 287 {
Sergunb 0:8f0d870509fe 288 __ASM volatile ("nop");
Sergunb 0:8f0d870509fe 289 }
Sergunb 0:8f0d870509fe 290
Sergunb 0:8f0d870509fe 291
Sergunb 0:8f0d870509fe 292 /** \brief Wait For Interrupt
Sergunb 0:8f0d870509fe 293
Sergunb 0:8f0d870509fe 294 Wait For Interrupt is a hint instruction that suspends execution
Sergunb 0:8f0d870509fe 295 until one of a number of events occurs.
Sergunb 0:8f0d870509fe 296 */
Sergunb 0:8f0d870509fe 297 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
Sergunb 0:8f0d870509fe 298 {
Sergunb 0:8f0d870509fe 299 __ASM volatile ("wfi");
Sergunb 0:8f0d870509fe 300 }
Sergunb 0:8f0d870509fe 301
Sergunb 0:8f0d870509fe 302
Sergunb 0:8f0d870509fe 303 /** \brief Wait For Event
Sergunb 0:8f0d870509fe 304
Sergunb 0:8f0d870509fe 305 Wait For Event is a hint instruction that permits the processor to enter
Sergunb 0:8f0d870509fe 306 a low-power state until one of a number of events occurs.
Sergunb 0:8f0d870509fe 307 */
Sergunb 0:8f0d870509fe 308 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
Sergunb 0:8f0d870509fe 309 {
Sergunb 0:8f0d870509fe 310 __ASM volatile ("wfe");
Sergunb 0:8f0d870509fe 311 }
Sergunb 0:8f0d870509fe 312
Sergunb 0:8f0d870509fe 313
Sergunb 0:8f0d870509fe 314 /** \brief Send Event
Sergunb 0:8f0d870509fe 315
Sergunb 0:8f0d870509fe 316 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
Sergunb 0:8f0d870509fe 317 */
Sergunb 0:8f0d870509fe 318 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
Sergunb 0:8f0d870509fe 319 {
Sergunb 0:8f0d870509fe 320 __ASM volatile ("sev");
Sergunb 0:8f0d870509fe 321 }
Sergunb 0:8f0d870509fe 322
Sergunb 0:8f0d870509fe 323
Sergunb 0:8f0d870509fe 324 /** \brief Instruction Synchronization Barrier
Sergunb 0:8f0d870509fe 325
Sergunb 0:8f0d870509fe 326 Instruction Synchronization Barrier flushes the pipeline in the processor,
Sergunb 0:8f0d870509fe 327 so that all instructions following the ISB are fetched from cache or
Sergunb 0:8f0d870509fe 328 memory, after the instruction has been completed.
Sergunb 0:8f0d870509fe 329 */
Sergunb 0:8f0d870509fe 330 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
Sergunb 0:8f0d870509fe 331 {
Sergunb 0:8f0d870509fe 332 __ASM volatile ("isb");
Sergunb 0:8f0d870509fe 333 }
Sergunb 0:8f0d870509fe 334
Sergunb 0:8f0d870509fe 335
Sergunb 0:8f0d870509fe 336 /** \brief Data Synchronization Barrier
Sergunb 0:8f0d870509fe 337
Sergunb 0:8f0d870509fe 338 This function acts as a special kind of Data Memory Barrier.
Sergunb 0:8f0d870509fe 339 It completes when all explicit memory accesses before this instruction complete.
Sergunb 0:8f0d870509fe 340 */
Sergunb 0:8f0d870509fe 341 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
Sergunb 0:8f0d870509fe 342 {
Sergunb 0:8f0d870509fe 343 __ASM volatile ("dsb");
Sergunb 0:8f0d870509fe 344 }
Sergunb 0:8f0d870509fe 345
Sergunb 0:8f0d870509fe 346
Sergunb 0:8f0d870509fe 347 /** \brief Data Memory Barrier
Sergunb 0:8f0d870509fe 348
Sergunb 0:8f0d870509fe 349 This function ensures the apparent order of the explicit memory operations before
Sergunb 0:8f0d870509fe 350 and after the instruction, without ensuring their completion.
Sergunb 0:8f0d870509fe 351 */
Sergunb 0:8f0d870509fe 352 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
Sergunb 0:8f0d870509fe 353 {
Sergunb 0:8f0d870509fe 354 __ASM volatile ("dmb");
Sergunb 0:8f0d870509fe 355 }
Sergunb 0:8f0d870509fe 356
Sergunb 0:8f0d870509fe 357
Sergunb 0:8f0d870509fe 358 /** \brief Reverse byte order (32 bit)
Sergunb 0:8f0d870509fe 359
Sergunb 0:8f0d870509fe 360 This function reverses the byte order in integer value.
Sergunb 0:8f0d870509fe 361
Sergunb 0:8f0d870509fe 362 \param [in] value Value to reverse
Sergunb 0:8f0d870509fe 363 \return Reversed value
Sergunb 0:8f0d870509fe 364 */
Sergunb 0:8f0d870509fe 365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
Sergunb 0:8f0d870509fe 366 {
Sergunb 0:8f0d870509fe 367 uint32_t result;
Sergunb 0:8f0d870509fe 368
Sergunb 0:8f0d870509fe 369 __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
Sergunb 0:8f0d870509fe 370 return(result);
Sergunb 0:8f0d870509fe 371 }
Sergunb 0:8f0d870509fe 372
Sergunb 0:8f0d870509fe 373
Sergunb 0:8f0d870509fe 374 /** \brief Reverse byte order (16 bit)
Sergunb 0:8f0d870509fe 375
Sergunb 0:8f0d870509fe 376 This function reverses the byte order in two unsigned short values.
Sergunb 0:8f0d870509fe 377
Sergunb 0:8f0d870509fe 378 \param [in] value Value to reverse
Sergunb 0:8f0d870509fe 379 \return Reversed value
Sergunb 0:8f0d870509fe 380 */
Sergunb 0:8f0d870509fe 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
Sergunb 0:8f0d870509fe 382 {
Sergunb 0:8f0d870509fe 383 uint32_t result;
Sergunb 0:8f0d870509fe 384
Sergunb 0:8f0d870509fe 385 __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
Sergunb 0:8f0d870509fe 386 return(result);
Sergunb 0:8f0d870509fe 387 }
Sergunb 0:8f0d870509fe 388
Sergunb 0:8f0d870509fe 389
Sergunb 0:8f0d870509fe 390 /** \brief Reverse byte order in signed short value
Sergunb 0:8f0d870509fe 391
Sergunb 0:8f0d870509fe 392 This function reverses the byte order in a signed short value with sign extension to integer.
Sergunb 0:8f0d870509fe 393
Sergunb 0:8f0d870509fe 394 \param [in] value Value to reverse
Sergunb 0:8f0d870509fe 395 \return Reversed value
Sergunb 0:8f0d870509fe 396 */
Sergunb 0:8f0d870509fe 397 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
Sergunb 0:8f0d870509fe 398 {
Sergunb 0:8f0d870509fe 399 uint32_t result;
Sergunb 0:8f0d870509fe 400
Sergunb 0:8f0d870509fe 401 __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
Sergunb 0:8f0d870509fe 402 return(result);
Sergunb 0:8f0d870509fe 403 }
Sergunb 0:8f0d870509fe 404
Sergunb 0:8f0d870509fe 405
Sergunb 0:8f0d870509fe 406 /** \brief Rotate Right in unsigned value (32 bit)
Sergunb 0:8f0d870509fe 407
Sergunb 0:8f0d870509fe 408 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
Sergunb 0:8f0d870509fe 409
Sergunb 0:8f0d870509fe 410 \param [in] value Value to rotate
Sergunb 0:8f0d870509fe 411 \param [in] value Number of Bits to rotate
Sergunb 0:8f0d870509fe 412 \return Rotated value
Sergunb 0:8f0d870509fe 413 */
Sergunb 0:8f0d870509fe 414 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
Sergunb 0:8f0d870509fe 415 {
Sergunb 0:8f0d870509fe 416
Sergunb 0:8f0d870509fe 417 __ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
Sergunb 0:8f0d870509fe 418 return(op1);
Sergunb 0:8f0d870509fe 419 }
Sergunb 0:8f0d870509fe 420
Sergunb 0:8f0d870509fe 421
Sergunb 0:8f0d870509fe 422 #if (__CORTEX_M >= 0x03)
Sergunb 0:8f0d870509fe 423
Sergunb 0:8f0d870509fe 424 /** \brief Reverse bit order of value
Sergunb 0:8f0d870509fe 425
Sergunb 0:8f0d870509fe 426 This function reverses the bit order of the given value.
Sergunb 0:8f0d870509fe 427
Sergunb 0:8f0d870509fe 428 \param [in] value Value to reverse
Sergunb 0:8f0d870509fe 429 \return Reversed value
Sergunb 0:8f0d870509fe 430 */
Sergunb 0:8f0d870509fe 431 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
Sergunb 0:8f0d870509fe 432 {
Sergunb 0:8f0d870509fe 433 uint32_t result;
Sergunb 0:8f0d870509fe 434
Sergunb 0:8f0d870509fe 435 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
Sergunb 0:8f0d870509fe 436 return(result);
Sergunb 0:8f0d870509fe 437 }
Sergunb 0:8f0d870509fe 438
Sergunb 0:8f0d870509fe 439
Sergunb 0:8f0d870509fe 440 /** \brief LDR Exclusive (8 bit)
Sergunb 0:8f0d870509fe 441
Sergunb 0:8f0d870509fe 442 This function performs a exclusive LDR command for 8 bit value.
Sergunb 0:8f0d870509fe 443
Sergunb 0:8f0d870509fe 444 \param [in] ptr Pointer to data
Sergunb 0:8f0d870509fe 445 \return value of type uint8_t at (*ptr)
Sergunb 0:8f0d870509fe 446 */
Sergunb 0:8f0d870509fe 447 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
Sergunb 0:8f0d870509fe 448 {
Sergunb 0:8f0d870509fe 449 uint8_t result;
Sergunb 0:8f0d870509fe 450
Sergunb 0:8f0d870509fe 451 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
Sergunb 0:8f0d870509fe 452 return(result);
Sergunb 0:8f0d870509fe 453 }
Sergunb 0:8f0d870509fe 454
Sergunb 0:8f0d870509fe 455
Sergunb 0:8f0d870509fe 456 /** \brief LDR Exclusive (16 bit)
Sergunb 0:8f0d870509fe 457
Sergunb 0:8f0d870509fe 458 This function performs a exclusive LDR command for 16 bit values.
Sergunb 0:8f0d870509fe 459
Sergunb 0:8f0d870509fe 460 \param [in] ptr Pointer to data
Sergunb 0:8f0d870509fe 461 \return value of type uint16_t at (*ptr)
Sergunb 0:8f0d870509fe 462 */
Sergunb 0:8f0d870509fe 463 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
Sergunb 0:8f0d870509fe 464 {
Sergunb 0:8f0d870509fe 465 uint16_t result;
Sergunb 0:8f0d870509fe 466
Sergunb 0:8f0d870509fe 467 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
Sergunb 0:8f0d870509fe 468 return(result);
Sergunb 0:8f0d870509fe 469 }
Sergunb 0:8f0d870509fe 470
Sergunb 0:8f0d870509fe 471
Sergunb 0:8f0d870509fe 472 /** \brief LDR Exclusive (32 bit)
Sergunb 0:8f0d870509fe 473
Sergunb 0:8f0d870509fe 474 This function performs a exclusive LDR command for 32 bit values.
Sergunb 0:8f0d870509fe 475
Sergunb 0:8f0d870509fe 476 \param [in] ptr Pointer to data
Sergunb 0:8f0d870509fe 477 \return value of type uint32_t at (*ptr)
Sergunb 0:8f0d870509fe 478 */
Sergunb 0:8f0d870509fe 479 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
Sergunb 0:8f0d870509fe 480 {
Sergunb 0:8f0d870509fe 481 uint32_t result;
Sergunb 0:8f0d870509fe 482
Sergunb 0:8f0d870509fe 483 __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
Sergunb 0:8f0d870509fe 484 return(result);
Sergunb 0:8f0d870509fe 485 }
Sergunb 0:8f0d870509fe 486
Sergunb 0:8f0d870509fe 487
Sergunb 0:8f0d870509fe 488 /** \brief STR Exclusive (8 bit)
Sergunb 0:8f0d870509fe 489
Sergunb 0:8f0d870509fe 490 This function performs a exclusive STR command for 8 bit values.
Sergunb 0:8f0d870509fe 491
Sergunb 0:8f0d870509fe 492 \param [in] value Value to store
Sergunb 0:8f0d870509fe 493 \param [in] ptr Pointer to location
Sergunb 0:8f0d870509fe 494 \return 0 Function succeeded
Sergunb 0:8f0d870509fe 495 \return 1 Function failed
Sergunb 0:8f0d870509fe 496 */
Sergunb 0:8f0d870509fe 497 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
Sergunb 0:8f0d870509fe 498 {
Sergunb 0:8f0d870509fe 499 uint32_t result;
Sergunb 0:8f0d870509fe 500
Sergunb 0:8f0d870509fe 501 __ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
Sergunb 0:8f0d870509fe 502 return(result);
Sergunb 0:8f0d870509fe 503 }
Sergunb 0:8f0d870509fe 504
Sergunb 0:8f0d870509fe 505
Sergunb 0:8f0d870509fe 506 /** \brief STR Exclusive (16 bit)
Sergunb 0:8f0d870509fe 507
Sergunb 0:8f0d870509fe 508 This function performs a exclusive STR command for 16 bit values.
Sergunb 0:8f0d870509fe 509
Sergunb 0:8f0d870509fe 510 \param [in] value Value to store
Sergunb 0:8f0d870509fe 511 \param [in] ptr Pointer to location
Sergunb 0:8f0d870509fe 512 \return 0 Function succeeded
Sergunb 0:8f0d870509fe 513 \return 1 Function failed
Sergunb 0:8f0d870509fe 514 */
Sergunb 0:8f0d870509fe 515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
Sergunb 0:8f0d870509fe 516 {
Sergunb 0:8f0d870509fe 517 uint32_t result;
Sergunb 0:8f0d870509fe 518
Sergunb 0:8f0d870509fe 519 __ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
Sergunb 0:8f0d870509fe 520 return(result);
Sergunb 0:8f0d870509fe 521 }
Sergunb 0:8f0d870509fe 522
Sergunb 0:8f0d870509fe 523
Sergunb 0:8f0d870509fe 524 /** \brief STR Exclusive (32 bit)
Sergunb 0:8f0d870509fe 525
Sergunb 0:8f0d870509fe 526 This function performs a exclusive STR command for 32 bit values.
Sergunb 0:8f0d870509fe 527
Sergunb 0:8f0d870509fe 528 \param [in] value Value to store
Sergunb 0:8f0d870509fe 529 \param [in] ptr Pointer to location
Sergunb 0:8f0d870509fe 530 \return 0 Function succeeded
Sergunb 0:8f0d870509fe 531 \return 1 Function failed
Sergunb 0:8f0d870509fe 532 */
Sergunb 0:8f0d870509fe 533 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
Sergunb 0:8f0d870509fe 534 {
Sergunb 0:8f0d870509fe 535 uint32_t result;
Sergunb 0:8f0d870509fe 536
Sergunb 0:8f0d870509fe 537 __ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
Sergunb 0:8f0d870509fe 538 return(result);
Sergunb 0:8f0d870509fe 539 }
Sergunb 0:8f0d870509fe 540
Sergunb 0:8f0d870509fe 541
Sergunb 0:8f0d870509fe 542 /** \brief Remove the exclusive lock
Sergunb 0:8f0d870509fe 543
Sergunb 0:8f0d870509fe 544 This function removes the exclusive lock which is created by LDREX.
Sergunb 0:8f0d870509fe 545
Sergunb 0:8f0d870509fe 546 */
Sergunb 0:8f0d870509fe 547 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
Sergunb 0:8f0d870509fe 548 {
Sergunb 0:8f0d870509fe 549 __ASM volatile ("clrex");
Sergunb 0:8f0d870509fe 550 }
Sergunb 0:8f0d870509fe 551
Sergunb 0:8f0d870509fe 552
Sergunb 0:8f0d870509fe 553 /** \brief Signed Saturate
Sergunb 0:8f0d870509fe 554
Sergunb 0:8f0d870509fe 555 This function saturates a signed value.
Sergunb 0:8f0d870509fe 556
Sergunb 0:8f0d870509fe 557 \param [in] value Value to be saturated
Sergunb 0:8f0d870509fe 558 \param [in] sat Bit position to saturate to (1..32)
Sergunb 0:8f0d870509fe 559 \return Saturated value
Sergunb 0:8f0d870509fe 560 */
Sergunb 0:8f0d870509fe 561 #define __SSAT(ARG1,ARG2) \
Sergunb 0:8f0d870509fe 562 ({ \
Sergunb 0:8f0d870509fe 563 uint32_t __RES, __ARG1 = (ARG1); \
Sergunb 0:8f0d870509fe 564 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
Sergunb 0:8f0d870509fe 565 __RES; \
Sergunb 0:8f0d870509fe 566 })
Sergunb 0:8f0d870509fe 567
Sergunb 0:8f0d870509fe 568
Sergunb 0:8f0d870509fe 569 /** \brief Unsigned Saturate
Sergunb 0:8f0d870509fe 570
Sergunb 0:8f0d870509fe 571 This function saturates an unsigned value.
Sergunb 0:8f0d870509fe 572
Sergunb 0:8f0d870509fe 573 \param [in] value Value to be saturated
Sergunb 0:8f0d870509fe 574 \param [in] sat Bit position to saturate to (0..31)
Sergunb 0:8f0d870509fe 575 \return Saturated value
Sergunb 0:8f0d870509fe 576 */
Sergunb 0:8f0d870509fe 577 #define __USAT(ARG1,ARG2) \
Sergunb 0:8f0d870509fe 578 ({ \
Sergunb 0:8f0d870509fe 579 uint32_t __RES, __ARG1 = (ARG1); \
Sergunb 0:8f0d870509fe 580 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
Sergunb 0:8f0d870509fe 581 __RES; \
Sergunb 0:8f0d870509fe 582 })
Sergunb 0:8f0d870509fe 583
Sergunb 0:8f0d870509fe 584
Sergunb 0:8f0d870509fe 585 /** \brief Count leading zeros
Sergunb 0:8f0d870509fe 586
Sergunb 0:8f0d870509fe 587 This function counts the number of leading zeros of a data value.
Sergunb 0:8f0d870509fe 588
Sergunb 0:8f0d870509fe 589 \param [in] value Value to count the leading zeros
Sergunb 0:8f0d870509fe 590 \return number of leading zeros in value
Sergunb 0:8f0d870509fe 591 */
Sergunb 0:8f0d870509fe 592 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
Sergunb 0:8f0d870509fe 593 {
Sergunb 0:8f0d870509fe 594 uint8_t result;
Sergunb 0:8f0d870509fe 595
Sergunb 0:8f0d870509fe 596 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
Sergunb 0:8f0d870509fe 597 return(result);
Sergunb 0:8f0d870509fe 598 }
Sergunb 0:8f0d870509fe 599
Sergunb 0:8f0d870509fe 600 #endif /* (__CORTEX_M >= 0x03) */
Sergunb 0:8f0d870509fe 601
Sergunb 0:8f0d870509fe 602
Sergunb 0:8f0d870509fe 603
Sergunb 0:8f0d870509fe 604
Sergunb 0:8f0d870509fe 605 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
Sergunb 0:8f0d870509fe 606 /* TASKING carm specific functions */
Sergunb 0:8f0d870509fe 607
Sergunb 0:8f0d870509fe 608 /*
Sergunb 0:8f0d870509fe 609 * The CMSIS functions have been implemented as intrinsics in the compiler.
Sergunb 0:8f0d870509fe 610 * Please use "carm -?i" to get an up to date list of all intrinsics,
Sergunb 0:8f0d870509fe 611 * Including the CMSIS ones.
Sergunb 0:8f0d870509fe 612 */
Sergunb 0:8f0d870509fe 613
Sergunb 0:8f0d870509fe 614 #endif
Sergunb 0:8f0d870509fe 615
Sergunb 0:8f0d870509fe 616 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
Sergunb 0:8f0d870509fe 617
Sergunb 0:8f0d870509fe 618 #endif /* __CORE_CMINSTR_H */