Sergey Pastor / grbl1

cmsis/core_cmFunc.h@0:8f0d870509fe, 2017-09-04 (annotated)

Committer:
Sergunb
Date:
Mon Sep 04 12:04:13 2017 +0000
Revision:
0:8f0d870509fe
Initial commit

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Sergunb 0:8f0d870509fe 1 /**************************************************************************//**
Sergunb 0:8f0d870509fe 2 * @file core_cmFunc.h
Sergunb 0:8f0d870509fe 3 * @brief CMSIS Cortex-M Core Function Access Header File
Sergunb 0:8f0d870509fe 4 * @version V3.01
Sergunb 0:8f0d870509fe 5 * @date 06. March 2012
Sergunb 0:8f0d870509fe 6 *
Sergunb 0:8f0d870509fe 7 * @note
Sergunb 0:8f0d870509fe 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
Sergunb 0:8f0d870509fe 9 *
Sergunb 0:8f0d870509fe 10 * @par
Sergunb 0:8f0d870509fe 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Sergunb 0:8f0d870509fe 12 * processor based microcontrollers. This file can be freely distributed
Sergunb 0:8f0d870509fe 13 * within development tools that are supporting such ARM based processors.
Sergunb 0:8f0d870509fe 14 *
Sergunb 0:8f0d870509fe 15 * @par
Sergunb 0:8f0d870509fe 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Sergunb 0:8f0d870509fe 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Sergunb 0:8f0d870509fe 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Sergunb 0:8f0d870509fe 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Sergunb 0:8f0d870509fe 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Sergunb 0:8f0d870509fe 21 *
Sergunb 0:8f0d870509fe 22 ******************************************************************************/
Sergunb 0:8f0d870509fe 23
Sergunb 0:8f0d870509fe 24 #ifndef __CORE_CMFUNC_H
Sergunb 0:8f0d870509fe 25 #define __CORE_CMFUNC_H
Sergunb 0:8f0d870509fe 26
Sergunb 0:8f0d870509fe 27
Sergunb 0:8f0d870509fe 28 /* ########################### Core Function Access ########################### */
Sergunb 0:8f0d870509fe 29 /** \ingroup CMSIS_Core_FunctionInterface
Sergunb 0:8f0d870509fe 30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Sergunb 0:8f0d870509fe 31 @{
Sergunb 0:8f0d870509fe 32 */
Sergunb 0:8f0d870509fe 33
Sergunb 0:8f0d870509fe 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Sergunb 0:8f0d870509fe 35 /* ARM armcc specific functions */
Sergunb 0:8f0d870509fe 36
Sergunb 0:8f0d870509fe 37 #if (__ARMCC_VERSION < 400677)
Sergunb 0:8f0d870509fe 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Sergunb 0:8f0d870509fe 39 #endif
Sergunb 0:8f0d870509fe 40
Sergunb 0:8f0d870509fe 41 /* intrinsic void __enable_irq(); */
Sergunb 0:8f0d870509fe 42 /* intrinsic void __disable_irq(); */
Sergunb 0:8f0d870509fe 43
Sergunb 0:8f0d870509fe 44 /** \brief Get Control Register
Sergunb 0:8f0d870509fe 45
Sergunb 0:8f0d870509fe 46 This function returns the content of the Control Register.
Sergunb 0:8f0d870509fe 47
Sergunb 0:8f0d870509fe 48 \return Control Register value
Sergunb 0:8f0d870509fe 49 */
Sergunb 0:8f0d870509fe 50 __STATIC_INLINE uint32_t __get_CONTROL(void)
Sergunb 0:8f0d870509fe 51 {
Sergunb 0:8f0d870509fe 52 register uint32_t __regControl __ASM("control");
Sergunb 0:8f0d870509fe 53 return(__regControl);
Sergunb 0:8f0d870509fe 54 }
Sergunb 0:8f0d870509fe 55
Sergunb 0:8f0d870509fe 56
Sergunb 0:8f0d870509fe 57 /** \brief Set Control Register
Sergunb 0:8f0d870509fe 58
Sergunb 0:8f0d870509fe 59 This function writes the given value to the Control Register.
Sergunb 0:8f0d870509fe 60
Sergunb 0:8f0d870509fe 61 \param [in] control Control Register value to set
Sergunb 0:8f0d870509fe 62 */
Sergunb 0:8f0d870509fe 63 __STATIC_INLINE void __set_CONTROL(uint32_t control)
Sergunb 0:8f0d870509fe 64 {
Sergunb 0:8f0d870509fe 65 register uint32_t __regControl __ASM("control");
Sergunb 0:8f0d870509fe 66 __regControl = control;
Sergunb 0:8f0d870509fe 67 }
Sergunb 0:8f0d870509fe 68
Sergunb 0:8f0d870509fe 69
Sergunb 0:8f0d870509fe 70 /** \brief Get IPSR Register
Sergunb 0:8f0d870509fe 71
Sergunb 0:8f0d870509fe 72 This function returns the content of the IPSR Register.
Sergunb 0:8f0d870509fe 73
Sergunb 0:8f0d870509fe 74 \return IPSR Register value
Sergunb 0:8f0d870509fe 75 */
Sergunb 0:8f0d870509fe 76 __STATIC_INLINE uint32_t __get_IPSR(void)
Sergunb 0:8f0d870509fe 77 {
Sergunb 0:8f0d870509fe 78 register uint32_t __regIPSR __ASM("ipsr");
Sergunb 0:8f0d870509fe 79 return(__regIPSR);
Sergunb 0:8f0d870509fe 80 }
Sergunb 0:8f0d870509fe 81
Sergunb 0:8f0d870509fe 82
Sergunb 0:8f0d870509fe 83 /** \brief Get APSR Register
Sergunb 0:8f0d870509fe 84
Sergunb 0:8f0d870509fe 85 This function returns the content of the APSR Register.
Sergunb 0:8f0d870509fe 86
Sergunb 0:8f0d870509fe 87 \return APSR Register value
Sergunb 0:8f0d870509fe 88 */
Sergunb 0:8f0d870509fe 89 __STATIC_INLINE uint32_t __get_APSR(void)
Sergunb 0:8f0d870509fe 90 {
Sergunb 0:8f0d870509fe 91 register uint32_t __regAPSR __ASM("apsr");
Sergunb 0:8f0d870509fe 92 return(__regAPSR);
Sergunb 0:8f0d870509fe 93 }
Sergunb 0:8f0d870509fe 94
Sergunb 0:8f0d870509fe 95
Sergunb 0:8f0d870509fe 96 /** \brief Get xPSR Register
Sergunb 0:8f0d870509fe 97
Sergunb 0:8f0d870509fe 98 This function returns the content of the xPSR Register.
Sergunb 0:8f0d870509fe 99
Sergunb 0:8f0d870509fe 100 \return xPSR Register value
Sergunb 0:8f0d870509fe 101 */
Sergunb 0:8f0d870509fe 102 __STATIC_INLINE uint32_t __get_xPSR(void)
Sergunb 0:8f0d870509fe 103 {
Sergunb 0:8f0d870509fe 104 register uint32_t __regXPSR __ASM("xpsr");
Sergunb 0:8f0d870509fe 105 return(__regXPSR);
Sergunb 0:8f0d870509fe 106 }
Sergunb 0:8f0d870509fe 107
Sergunb 0:8f0d870509fe 108
Sergunb 0:8f0d870509fe 109 /** \brief Get Process Stack Pointer
Sergunb 0:8f0d870509fe 110
Sergunb 0:8f0d870509fe 111 This function returns the current value of the Process Stack Pointer (PSP).
Sergunb 0:8f0d870509fe 112
Sergunb 0:8f0d870509fe 113 \return PSP Register value
Sergunb 0:8f0d870509fe 114 */
Sergunb 0:8f0d870509fe 115 __STATIC_INLINE uint32_t __get_PSP(void)
Sergunb 0:8f0d870509fe 116 {
Sergunb 0:8f0d870509fe 117 register uint32_t __regProcessStackPointer __ASM("psp");
Sergunb 0:8f0d870509fe 118 return(__regProcessStackPointer);
Sergunb 0:8f0d870509fe 119 }
Sergunb 0:8f0d870509fe 120
Sergunb 0:8f0d870509fe 121
Sergunb 0:8f0d870509fe 122 /** \brief Set Process Stack Pointer
Sergunb 0:8f0d870509fe 123
Sergunb 0:8f0d870509fe 124 This function assigns the given value to the Process Stack Pointer (PSP).
Sergunb 0:8f0d870509fe 125
Sergunb 0:8f0d870509fe 126 \param [in] topOfProcStack Process Stack Pointer value to set
Sergunb 0:8f0d870509fe 127 */
Sergunb 0:8f0d870509fe 128 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Sergunb 0:8f0d870509fe 129 {
Sergunb 0:8f0d870509fe 130 register uint32_t __regProcessStackPointer __ASM("psp");
Sergunb 0:8f0d870509fe 131 __regProcessStackPointer = topOfProcStack;
Sergunb 0:8f0d870509fe 132 }
Sergunb 0:8f0d870509fe 133
Sergunb 0:8f0d870509fe 134
Sergunb 0:8f0d870509fe 135 /** \brief Get Main Stack Pointer
Sergunb 0:8f0d870509fe 136
Sergunb 0:8f0d870509fe 137 This function returns the current value of the Main Stack Pointer (MSP).
Sergunb 0:8f0d870509fe 138
Sergunb 0:8f0d870509fe 139 \return MSP Register value
Sergunb 0:8f0d870509fe 140 */
Sergunb 0:8f0d870509fe 141 __STATIC_INLINE uint32_t __get_MSP(void)
Sergunb 0:8f0d870509fe 142 {
Sergunb 0:8f0d870509fe 143 register uint32_t __regMainStackPointer __ASM("msp");
Sergunb 0:8f0d870509fe 144 return(__regMainStackPointer);
Sergunb 0:8f0d870509fe 145 }
Sergunb 0:8f0d870509fe 146
Sergunb 0:8f0d870509fe 147
Sergunb 0:8f0d870509fe 148 /** \brief Set Main Stack Pointer
Sergunb 0:8f0d870509fe 149
Sergunb 0:8f0d870509fe 150 This function assigns the given value to the Main Stack Pointer (MSP).
Sergunb 0:8f0d870509fe 151
Sergunb 0:8f0d870509fe 152 \param [in] topOfMainStack Main Stack Pointer value to set
Sergunb 0:8f0d870509fe 153 */
Sergunb 0:8f0d870509fe 154 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Sergunb 0:8f0d870509fe 155 {
Sergunb 0:8f0d870509fe 156 register uint32_t __regMainStackPointer __ASM("msp");
Sergunb 0:8f0d870509fe 157 __regMainStackPointer = topOfMainStack;
Sergunb 0:8f0d870509fe 158 }
Sergunb 0:8f0d870509fe 159
Sergunb 0:8f0d870509fe 160
Sergunb 0:8f0d870509fe 161 /** \brief Get Priority Mask
Sergunb 0:8f0d870509fe 162
Sergunb 0:8f0d870509fe 163 This function returns the current state of the priority mask bit from the Priority Mask Register.
Sergunb 0:8f0d870509fe 164
Sergunb 0:8f0d870509fe 165 \return Priority Mask value
Sergunb 0:8f0d870509fe 166 */
Sergunb 0:8f0d870509fe 167 __STATIC_INLINE uint32_t __get_PRIMASK(void)
Sergunb 0:8f0d870509fe 168 {
Sergunb 0:8f0d870509fe 169 register uint32_t __regPriMask __ASM("primask");
Sergunb 0:8f0d870509fe 170 return(__regPriMask);
Sergunb 0:8f0d870509fe 171 }
Sergunb 0:8f0d870509fe 172
Sergunb 0:8f0d870509fe 173
Sergunb 0:8f0d870509fe 174 /** \brief Set Priority Mask
Sergunb 0:8f0d870509fe 175
Sergunb 0:8f0d870509fe 176 This function assigns the given value to the Priority Mask Register.
Sergunb 0:8f0d870509fe 177
Sergunb 0:8f0d870509fe 178 \param [in] priMask Priority Mask
Sergunb 0:8f0d870509fe 179 */
Sergunb 0:8f0d870509fe 180 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Sergunb 0:8f0d870509fe 181 {
Sergunb 0:8f0d870509fe 182 register uint32_t __regPriMask __ASM("primask");
Sergunb 0:8f0d870509fe 183 __regPriMask = (priMask);
Sergunb 0:8f0d870509fe 184 }
Sergunb 0:8f0d870509fe 185
Sergunb 0:8f0d870509fe 186
Sergunb 0:8f0d870509fe 187 #if (__CORTEX_M >= 0x03)
Sergunb 0:8f0d870509fe 188
Sergunb 0:8f0d870509fe 189 /** \brief Enable FIQ
Sergunb 0:8f0d870509fe 190
Sergunb 0:8f0d870509fe 191 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Sergunb 0:8f0d870509fe 192 Can only be executed in Privileged modes.
Sergunb 0:8f0d870509fe 193 */
Sergunb 0:8f0d870509fe 194 #define __enable_fault_irq __enable_fiq
Sergunb 0:8f0d870509fe 195
Sergunb 0:8f0d870509fe 196
Sergunb 0:8f0d870509fe 197 /** \brief Disable FIQ
Sergunb 0:8f0d870509fe 198
Sergunb 0:8f0d870509fe 199 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Sergunb 0:8f0d870509fe 200 Can only be executed in Privileged modes.
Sergunb 0:8f0d870509fe 201 */
Sergunb 0:8f0d870509fe 202 #define __disable_fault_irq __disable_fiq
Sergunb 0:8f0d870509fe 203
Sergunb 0:8f0d870509fe 204
Sergunb 0:8f0d870509fe 205 /** \brief Get Base Priority
Sergunb 0:8f0d870509fe 206
Sergunb 0:8f0d870509fe 207 This function returns the current value of the Base Priority register.
Sergunb 0:8f0d870509fe 208
Sergunb 0:8f0d870509fe 209 \return Base Priority register value
Sergunb 0:8f0d870509fe 210 */
Sergunb 0:8f0d870509fe 211 __STATIC_INLINE uint32_t __get_BASEPRI(void)
Sergunb 0:8f0d870509fe 212 {
Sergunb 0:8f0d870509fe 213 register uint32_t __regBasePri __ASM("basepri");
Sergunb 0:8f0d870509fe 214 return(__regBasePri);
Sergunb 0:8f0d870509fe 215 }
Sergunb 0:8f0d870509fe 216
Sergunb 0:8f0d870509fe 217
Sergunb 0:8f0d870509fe 218 /** \brief Set Base Priority
Sergunb 0:8f0d870509fe 219
Sergunb 0:8f0d870509fe 220 This function assigns the given value to the Base Priority register.
Sergunb 0:8f0d870509fe 221
Sergunb 0:8f0d870509fe 222 \param [in] basePri Base Priority value to set
Sergunb 0:8f0d870509fe 223 */
Sergunb 0:8f0d870509fe 224 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
Sergunb 0:8f0d870509fe 225 {
Sergunb 0:8f0d870509fe 226 register uint32_t __regBasePri __ASM("basepri");
Sergunb 0:8f0d870509fe 227 __regBasePri = (basePri & 0xff);
Sergunb 0:8f0d870509fe 228 }
Sergunb 0:8f0d870509fe 229
Sergunb 0:8f0d870509fe 230
Sergunb 0:8f0d870509fe 231 /** \brief Get Fault Mask
Sergunb 0:8f0d870509fe 232
Sergunb 0:8f0d870509fe 233 This function returns the current value of the Fault Mask register.
Sergunb 0:8f0d870509fe 234
Sergunb 0:8f0d870509fe 235 \return Fault Mask register value
Sergunb 0:8f0d870509fe 236 */
Sergunb 0:8f0d870509fe 237 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
Sergunb 0:8f0d870509fe 238 {
Sergunb 0:8f0d870509fe 239 register uint32_t __regFaultMask __ASM("faultmask");
Sergunb 0:8f0d870509fe 240 return(__regFaultMask);
Sergunb 0:8f0d870509fe 241 }
Sergunb 0:8f0d870509fe 242
Sergunb 0:8f0d870509fe 243
Sergunb 0:8f0d870509fe 244 /** \brief Set Fault Mask
Sergunb 0:8f0d870509fe 245
Sergunb 0:8f0d870509fe 246 This function assigns the given value to the Fault Mask register.
Sergunb 0:8f0d870509fe 247
Sergunb 0:8f0d870509fe 248 \param [in] faultMask Fault Mask value to set
Sergunb 0:8f0d870509fe 249 */
Sergunb 0:8f0d870509fe 250 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
Sergunb 0:8f0d870509fe 251 {
Sergunb 0:8f0d870509fe 252 register uint32_t __regFaultMask __ASM("faultmask");
Sergunb 0:8f0d870509fe 253 __regFaultMask = (faultMask & (uint32_t)1);
Sergunb 0:8f0d870509fe 254 }
Sergunb 0:8f0d870509fe 255
Sergunb 0:8f0d870509fe 256 #endif /* (__CORTEX_M >= 0x03) */
Sergunb 0:8f0d870509fe 257
Sergunb 0:8f0d870509fe 258
Sergunb 0:8f0d870509fe 259 #if (__CORTEX_M == 0x04)
Sergunb 0:8f0d870509fe 260
Sergunb 0:8f0d870509fe 261 /** \brief Get FPSCR
Sergunb 0:8f0d870509fe 262
Sergunb 0:8f0d870509fe 263 This function returns the current value of the Floating Point Status/Control register.
Sergunb 0:8f0d870509fe 264
Sergunb 0:8f0d870509fe 265 \return Floating Point Status/Control register value
Sergunb 0:8f0d870509fe 266 */
Sergunb 0:8f0d870509fe 267 __STATIC_INLINE uint32_t __get_FPSCR(void)
Sergunb 0:8f0d870509fe 268 {
Sergunb 0:8f0d870509fe 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Sergunb 0:8f0d870509fe 270 register uint32_t __regfpscr __ASM("fpscr");
Sergunb 0:8f0d870509fe 271 return(__regfpscr);
Sergunb 0:8f0d870509fe 272 #else
Sergunb 0:8f0d870509fe 273 return(0);
Sergunb 0:8f0d870509fe 274 #endif
Sergunb 0:8f0d870509fe 275 }
Sergunb 0:8f0d870509fe 276
Sergunb 0:8f0d870509fe 277
Sergunb 0:8f0d870509fe 278 /** \brief Set FPSCR
Sergunb 0:8f0d870509fe 279
Sergunb 0:8f0d870509fe 280 This function assigns the given value to the Floating Point Status/Control register.
Sergunb 0:8f0d870509fe 281
Sergunb 0:8f0d870509fe 282 \param [in] fpscr Floating Point Status/Control value to set
Sergunb 0:8f0d870509fe 283 */
Sergunb 0:8f0d870509fe 284 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Sergunb 0:8f0d870509fe 285 {
Sergunb 0:8f0d870509fe 286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Sergunb 0:8f0d870509fe 287 register uint32_t __regfpscr __ASM("fpscr");
Sergunb 0:8f0d870509fe 288 __regfpscr = (fpscr);
Sergunb 0:8f0d870509fe 289 #endif
Sergunb 0:8f0d870509fe 290 }
Sergunb 0:8f0d870509fe 291
Sergunb 0:8f0d870509fe 292 #endif /* (__CORTEX_M == 0x04) */
Sergunb 0:8f0d870509fe 293
Sergunb 0:8f0d870509fe 294
Sergunb 0:8f0d870509fe 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
Sergunb 0:8f0d870509fe 296 /* IAR iccarm specific functions */
Sergunb 0:8f0d870509fe 297
Sergunb 0:8f0d870509fe 298 #include <cmsis_iar.h>
Sergunb 0:8f0d870509fe 299
Sergunb 0:8f0d870509fe 300
Sergunb 0:8f0d870509fe 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
Sergunb 0:8f0d870509fe 302 /* TI CCS specific functions */
Sergunb 0:8f0d870509fe 303
Sergunb 0:8f0d870509fe 304 #include <cmsis_ccs.h>
Sergunb 0:8f0d870509fe 305
Sergunb 0:8f0d870509fe 306
Sergunb 0:8f0d870509fe 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
Sergunb 0:8f0d870509fe 308 /* GNU gcc specific functions */
Sergunb 0:8f0d870509fe 309
Sergunb 0:8f0d870509fe 310 /** \brief Enable IRQ Interrupts
Sergunb 0:8f0d870509fe 311
Sergunb 0:8f0d870509fe 312 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Sergunb 0:8f0d870509fe 313 Can only be executed in Privileged modes.
Sergunb 0:8f0d870509fe 314 */
Sergunb 0:8f0d870509fe 315 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Sergunb 0:8f0d870509fe 316 {
Sergunb 0:8f0d870509fe 317 __ASM volatile ("cpsie i");
Sergunb 0:8f0d870509fe 318 }
Sergunb 0:8f0d870509fe 319
Sergunb 0:8f0d870509fe 320
Sergunb 0:8f0d870509fe 321 /** \brief Disable IRQ Interrupts
Sergunb 0:8f0d870509fe 322
Sergunb 0:8f0d870509fe 323 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Sergunb 0:8f0d870509fe 324 Can only be executed in Privileged modes.
Sergunb 0:8f0d870509fe 325 */
Sergunb 0:8f0d870509fe 326 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
Sergunb 0:8f0d870509fe 327 {
Sergunb 0:8f0d870509fe 328 __ASM volatile ("cpsid i");
Sergunb 0:8f0d870509fe 329 }
Sergunb 0:8f0d870509fe 330
Sergunb 0:8f0d870509fe 331
Sergunb 0:8f0d870509fe 332 /** \brief Get Control Register
Sergunb 0:8f0d870509fe 333
Sergunb 0:8f0d870509fe 334 This function returns the content of the Control Register.
Sergunb 0:8f0d870509fe 335
Sergunb 0:8f0d870509fe 336 \return Control Register value
Sergunb 0:8f0d870509fe 337 */
Sergunb 0:8f0d870509fe 338 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
Sergunb 0:8f0d870509fe 339 {
Sergunb 0:8f0d870509fe 340 uint32_t result;
Sergunb 0:8f0d870509fe 341
Sergunb 0:8f0d870509fe 342 __ASM volatile ("MRS %0, control" : "=r" (result) );
Sergunb 0:8f0d870509fe 343 return(result);
Sergunb 0:8f0d870509fe 344 }
Sergunb 0:8f0d870509fe 345
Sergunb 0:8f0d870509fe 346
Sergunb 0:8f0d870509fe 347 /** \brief Set Control Register
Sergunb 0:8f0d870509fe 348
Sergunb 0:8f0d870509fe 349 This function writes the given value to the Control Register.
Sergunb 0:8f0d870509fe 350
Sergunb 0:8f0d870509fe 351 \param [in] control Control Register value to set
Sergunb 0:8f0d870509fe 352 */
Sergunb 0:8f0d870509fe 353 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
Sergunb 0:8f0d870509fe 354 {
Sergunb 0:8f0d870509fe 355 __ASM volatile ("MSR control, %0" : : "r" (control) );
Sergunb 0:8f0d870509fe 356 }
Sergunb 0:8f0d870509fe 357
Sergunb 0:8f0d870509fe 358
Sergunb 0:8f0d870509fe 359 /** \brief Get IPSR Register
Sergunb 0:8f0d870509fe 360
Sergunb 0:8f0d870509fe 361 This function returns the content of the IPSR Register.
Sergunb 0:8f0d870509fe 362
Sergunb 0:8f0d870509fe 363 \return IPSR Register value
Sergunb 0:8f0d870509fe 364 */
Sergunb 0:8f0d870509fe 365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
Sergunb 0:8f0d870509fe 366 {
Sergunb 0:8f0d870509fe 367 uint32_t result;
Sergunb 0:8f0d870509fe 368
Sergunb 0:8f0d870509fe 369 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
Sergunb 0:8f0d870509fe 370 return(result);
Sergunb 0:8f0d870509fe 371 }
Sergunb 0:8f0d870509fe 372
Sergunb 0:8f0d870509fe 373
Sergunb 0:8f0d870509fe 374 /** \brief Get APSR Register
Sergunb 0:8f0d870509fe 375
Sergunb 0:8f0d870509fe 376 This function returns the content of the APSR Register.
Sergunb 0:8f0d870509fe 377
Sergunb 0:8f0d870509fe 378 \return APSR Register value
Sergunb 0:8f0d870509fe 379 */
Sergunb 0:8f0d870509fe 380 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Sergunb 0:8f0d870509fe 381 {
Sergunb 0:8f0d870509fe 382 uint32_t result;
Sergunb 0:8f0d870509fe 383
Sergunb 0:8f0d870509fe 384 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
Sergunb 0:8f0d870509fe 385 return(result);
Sergunb 0:8f0d870509fe 386 }
Sergunb 0:8f0d870509fe 387
Sergunb 0:8f0d870509fe 388
Sergunb 0:8f0d870509fe 389 /** \brief Get xPSR Register
Sergunb 0:8f0d870509fe 390
Sergunb 0:8f0d870509fe 391 This function returns the content of the xPSR Register.
Sergunb 0:8f0d870509fe 392
Sergunb 0:8f0d870509fe 393 \return xPSR Register value
Sergunb 0:8f0d870509fe 394 */
Sergunb 0:8f0d870509fe 395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
Sergunb 0:8f0d870509fe 396 {
Sergunb 0:8f0d870509fe 397 uint32_t result;
Sergunb 0:8f0d870509fe 398
Sergunb 0:8f0d870509fe 399 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
Sergunb 0:8f0d870509fe 400 return(result);
Sergunb 0:8f0d870509fe 401 }
Sergunb 0:8f0d870509fe 402
Sergunb 0:8f0d870509fe 403
Sergunb 0:8f0d870509fe 404 /** \brief Get Process Stack Pointer
Sergunb 0:8f0d870509fe 405
Sergunb 0:8f0d870509fe 406 This function returns the current value of the Process Stack Pointer (PSP).
Sergunb 0:8f0d870509fe 407
Sergunb 0:8f0d870509fe 408 \return PSP Register value
Sergunb 0:8f0d870509fe 409 */
Sergunb 0:8f0d870509fe 410 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
Sergunb 0:8f0d870509fe 411 {
Sergunb 0:8f0d870509fe 412 register uint32_t result;
Sergunb 0:8f0d870509fe 413
Sergunb 0:8f0d870509fe 414 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
Sergunb 0:8f0d870509fe 415 return(result);
Sergunb 0:8f0d870509fe 416 }
Sergunb 0:8f0d870509fe 417
Sergunb 0:8f0d870509fe 418
Sergunb 0:8f0d870509fe 419 /** \brief Set Process Stack Pointer
Sergunb 0:8f0d870509fe 420
Sergunb 0:8f0d870509fe 421 This function assigns the given value to the Process Stack Pointer (PSP).
Sergunb 0:8f0d870509fe 422
Sergunb 0:8f0d870509fe 423 \param [in] topOfProcStack Process Stack Pointer value to set
Sergunb 0:8f0d870509fe 424 */
Sergunb 0:8f0d870509fe 425 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Sergunb 0:8f0d870509fe 426 {
Sergunb 0:8f0d870509fe 427 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
Sergunb 0:8f0d870509fe 428 }
Sergunb 0:8f0d870509fe 429
Sergunb 0:8f0d870509fe 430
Sergunb 0:8f0d870509fe 431 /** \brief Get Main Stack Pointer
Sergunb 0:8f0d870509fe 432
Sergunb 0:8f0d870509fe 433 This function returns the current value of the Main Stack Pointer (MSP).
Sergunb 0:8f0d870509fe 434
Sergunb 0:8f0d870509fe 435 \return MSP Register value
Sergunb 0:8f0d870509fe 436 */
Sergunb 0:8f0d870509fe 437 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
Sergunb 0:8f0d870509fe 438 {
Sergunb 0:8f0d870509fe 439 register uint32_t result;
Sergunb 0:8f0d870509fe 440
Sergunb 0:8f0d870509fe 441 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
Sergunb 0:8f0d870509fe 442 return(result);
Sergunb 0:8f0d870509fe 443 }
Sergunb 0:8f0d870509fe 444
Sergunb 0:8f0d870509fe 445
Sergunb 0:8f0d870509fe 446 /** \brief Set Main Stack Pointer
Sergunb 0:8f0d870509fe 447
Sergunb 0:8f0d870509fe 448 This function assigns the given value to the Main Stack Pointer (MSP).
Sergunb 0:8f0d870509fe 449
Sergunb 0:8f0d870509fe 450 \param [in] topOfMainStack Main Stack Pointer value to set
Sergunb 0:8f0d870509fe 451 */
Sergunb 0:8f0d870509fe 452 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Sergunb 0:8f0d870509fe 453 {
Sergunb 0:8f0d870509fe 454 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
Sergunb 0:8f0d870509fe 455 }
Sergunb 0:8f0d870509fe 456
Sergunb 0:8f0d870509fe 457
Sergunb 0:8f0d870509fe 458 /** \brief Get Priority Mask
Sergunb 0:8f0d870509fe 459
Sergunb 0:8f0d870509fe 460 This function returns the current state of the priority mask bit from the Priority Mask Register.
Sergunb 0:8f0d870509fe 461
Sergunb 0:8f0d870509fe 462 \return Priority Mask value
Sergunb 0:8f0d870509fe 463 */
Sergunb 0:8f0d870509fe 464 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
Sergunb 0:8f0d870509fe 465 {
Sergunb 0:8f0d870509fe 466 uint32_t result;
Sergunb 0:8f0d870509fe 467
Sergunb 0:8f0d870509fe 468 __ASM volatile ("MRS %0, primask" : "=r" (result) );
Sergunb 0:8f0d870509fe 469 return(result);
Sergunb 0:8f0d870509fe 470 }
Sergunb 0:8f0d870509fe 471
Sergunb 0:8f0d870509fe 472
Sergunb 0:8f0d870509fe 473 /** \brief Set Priority Mask
Sergunb 0:8f0d870509fe 474
Sergunb 0:8f0d870509fe 475 This function assigns the given value to the Priority Mask Register.
Sergunb 0:8f0d870509fe 476
Sergunb 0:8f0d870509fe 477 \param [in] priMask Priority Mask
Sergunb 0:8f0d870509fe 478 */
Sergunb 0:8f0d870509fe 479 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Sergunb 0:8f0d870509fe 480 {
Sergunb 0:8f0d870509fe 481 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
Sergunb 0:8f0d870509fe 482 }
Sergunb 0:8f0d870509fe 483
Sergunb 0:8f0d870509fe 484
Sergunb 0:8f0d870509fe 485 #if (__CORTEX_M >= 0x03)
Sergunb 0:8f0d870509fe 486
Sergunb 0:8f0d870509fe 487 /** \brief Enable FIQ
Sergunb 0:8f0d870509fe 488
Sergunb 0:8f0d870509fe 489 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Sergunb 0:8f0d870509fe 490 Can only be executed in Privileged modes.
Sergunb 0:8f0d870509fe 491 */
Sergunb 0:8f0d870509fe 492 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
Sergunb 0:8f0d870509fe 493 {
Sergunb 0:8f0d870509fe 494 __ASM volatile ("cpsie f");
Sergunb 0:8f0d870509fe 495 }
Sergunb 0:8f0d870509fe 496
Sergunb 0:8f0d870509fe 497
Sergunb 0:8f0d870509fe 498 /** \brief Disable FIQ
Sergunb 0:8f0d870509fe 499
Sergunb 0:8f0d870509fe 500 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Sergunb 0:8f0d870509fe 501 Can only be executed in Privileged modes.
Sergunb 0:8f0d870509fe 502 */
Sergunb 0:8f0d870509fe 503 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
Sergunb 0:8f0d870509fe 504 {
Sergunb 0:8f0d870509fe 505 __ASM volatile ("cpsid f");
Sergunb 0:8f0d870509fe 506 }
Sergunb 0:8f0d870509fe 507
Sergunb 0:8f0d870509fe 508
Sergunb 0:8f0d870509fe 509 /** \brief Get Base Priority
Sergunb 0:8f0d870509fe 510
Sergunb 0:8f0d870509fe 511 This function returns the current value of the Base Priority register.
Sergunb 0:8f0d870509fe 512
Sergunb 0:8f0d870509fe 513 \return Base Priority register value
Sergunb 0:8f0d870509fe 514 */
Sergunb 0:8f0d870509fe 515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
Sergunb 0:8f0d870509fe 516 {
Sergunb 0:8f0d870509fe 517 uint32_t result;
Sergunb 0:8f0d870509fe 518
Sergunb 0:8f0d870509fe 519 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
Sergunb 0:8f0d870509fe 520 return(result);
Sergunb 0:8f0d870509fe 521 }
Sergunb 0:8f0d870509fe 522
Sergunb 0:8f0d870509fe 523
Sergunb 0:8f0d870509fe 524 /** \brief Set Base Priority
Sergunb 0:8f0d870509fe 525
Sergunb 0:8f0d870509fe 526 This function assigns the given value to the Base Priority register.
Sergunb 0:8f0d870509fe 527
Sergunb 0:8f0d870509fe 528 \param [in] basePri Base Priority value to set
Sergunb 0:8f0d870509fe 529 */
Sergunb 0:8f0d870509fe 530 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
Sergunb 0:8f0d870509fe 531 {
Sergunb 0:8f0d870509fe 532 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
Sergunb 0:8f0d870509fe 533 }
Sergunb 0:8f0d870509fe 534
Sergunb 0:8f0d870509fe 535
Sergunb 0:8f0d870509fe 536 /** \brief Get Fault Mask
Sergunb 0:8f0d870509fe 537
Sergunb 0:8f0d870509fe 538 This function returns the current value of the Fault Mask register.
Sergunb 0:8f0d870509fe 539
Sergunb 0:8f0d870509fe 540 \return Fault Mask register value
Sergunb 0:8f0d870509fe 541 */
Sergunb 0:8f0d870509fe 542 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
Sergunb 0:8f0d870509fe 543 {
Sergunb 0:8f0d870509fe 544 uint32_t result;
Sergunb 0:8f0d870509fe 545
Sergunb 0:8f0d870509fe 546 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
Sergunb 0:8f0d870509fe 547 return(result);
Sergunb 0:8f0d870509fe 548 }
Sergunb 0:8f0d870509fe 549
Sergunb 0:8f0d870509fe 550
Sergunb 0:8f0d870509fe 551 /** \brief Set Fault Mask
Sergunb 0:8f0d870509fe 552
Sergunb 0:8f0d870509fe 553 This function assigns the given value to the Fault Mask register.
Sergunb 0:8f0d870509fe 554
Sergunb 0:8f0d870509fe 555 \param [in] faultMask Fault Mask value to set
Sergunb 0:8f0d870509fe 556 */
Sergunb 0:8f0d870509fe 557 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
Sergunb 0:8f0d870509fe 558 {
Sergunb 0:8f0d870509fe 559 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
Sergunb 0:8f0d870509fe 560 }
Sergunb 0:8f0d870509fe 561
Sergunb 0:8f0d870509fe 562 #endif /* (__CORTEX_M >= 0x03) */
Sergunb 0:8f0d870509fe 563
Sergunb 0:8f0d870509fe 564
Sergunb 0:8f0d870509fe 565 #if (__CORTEX_M == 0x04)
Sergunb 0:8f0d870509fe 566
Sergunb 0:8f0d870509fe 567 /** \brief Get FPSCR
Sergunb 0:8f0d870509fe 568
Sergunb 0:8f0d870509fe 569 This function returns the current value of the Floating Point Status/Control register.
Sergunb 0:8f0d870509fe 570
Sergunb 0:8f0d870509fe 571 \return Floating Point Status/Control register value
Sergunb 0:8f0d870509fe 572 */
Sergunb 0:8f0d870509fe 573 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Sergunb 0:8f0d870509fe 574 {
Sergunb 0:8f0d870509fe 575 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Sergunb 0:8f0d870509fe 576 uint32_t result;
Sergunb 0:8f0d870509fe 577
Sergunb 0:8f0d870509fe 578 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
Sergunb 0:8f0d870509fe 579 return(result);
Sergunb 0:8f0d870509fe 580 #else
Sergunb 0:8f0d870509fe 581 return(0);
Sergunb 0:8f0d870509fe 582 #endif
Sergunb 0:8f0d870509fe 583 }
Sergunb 0:8f0d870509fe 584
Sergunb 0:8f0d870509fe 585
Sergunb 0:8f0d870509fe 586 /** \brief Set FPSCR
Sergunb 0:8f0d870509fe 587
Sergunb 0:8f0d870509fe 588 This function assigns the given value to the Floating Point Status/Control register.
Sergunb 0:8f0d870509fe 589
Sergunb 0:8f0d870509fe 590 \param [in] fpscr Floating Point Status/Control value to set
Sergunb 0:8f0d870509fe 591 */
Sergunb 0:8f0d870509fe 592 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Sergunb 0:8f0d870509fe 593 {
Sergunb 0:8f0d870509fe 594 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Sergunb 0:8f0d870509fe 595 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
Sergunb 0:8f0d870509fe 596 #endif
Sergunb 0:8f0d870509fe 597 }
Sergunb 0:8f0d870509fe 598
Sergunb 0:8f0d870509fe 599 #endif /* (__CORTEX_M == 0x04) */
Sergunb 0:8f0d870509fe 600
Sergunb 0:8f0d870509fe 601
Sergunb 0:8f0d870509fe 602 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
Sergunb 0:8f0d870509fe 603 /* TASKING carm specific functions */
Sergunb 0:8f0d870509fe 604
Sergunb 0:8f0d870509fe 605 /*
Sergunb 0:8f0d870509fe 606 * The CMSIS functions have been implemented as intrinsics in the compiler.
Sergunb 0:8f0d870509fe 607 * Please use "carm -?i" to get an up to date list of all instrinsics,
Sergunb 0:8f0d870509fe 608 * Including the CMSIS ones.
Sergunb 0:8f0d870509fe 609 */
Sergunb 0:8f0d870509fe 610
Sergunb 0:8f0d870509fe 611 #endif
Sergunb 0:8f0d870509fe 612
Sergunb 0:8f0d870509fe 613 /*@} end of CMSIS_Core_RegAccFunctions */
Sergunb 0:8f0d870509fe 614
Sergunb 0:8f0d870509fe 615
Sergunb 0:8f0d870509fe 616 #endif /* __CORE_CMFUNC_H */