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cmsis/core_cmFunc.h@0:f1834a63f7c1, 2017-09-04 (annotated)

Committer:
Sergunb
Date:
Mon Sep 04 12:03:42 2017 +0000
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0:f1834a63f7c1
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Sergunb 0:f1834a63f7c1 1 /**************************************************************************//**
Sergunb 0:f1834a63f7c1 2 * @file core_cmFunc.h
Sergunb 0:f1834a63f7c1 3 * @brief CMSIS Cortex-M Core Function Access Header File
Sergunb 0:f1834a63f7c1 4 * @version V3.01
Sergunb 0:f1834a63f7c1 5 * @date 06. March 2012
Sergunb 0:f1834a63f7c1 6 *
Sergunb 0:f1834a63f7c1 7 * @note
Sergunb 0:f1834a63f7c1 8 * Copyright (C) 2009-2012 ARM Limited. All rights reserved.
Sergunb 0:f1834a63f7c1 9 *
Sergunb 0:f1834a63f7c1 10 * @par
Sergunb 0:f1834a63f7c1 11 * ARM Limited (ARM) is supplying this software for use with Cortex-M
Sergunb 0:f1834a63f7c1 12 * processor based microcontrollers. This file can be freely distributed
Sergunb 0:f1834a63f7c1 13 * within development tools that are supporting such ARM based processors.
Sergunb 0:f1834a63f7c1 14 *
Sergunb 0:f1834a63f7c1 15 * @par
Sergunb 0:f1834a63f7c1 16 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
Sergunb 0:f1834a63f7c1 17 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
Sergunb 0:f1834a63f7c1 18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
Sergunb 0:f1834a63f7c1 19 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
Sergunb 0:f1834a63f7c1 20 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
Sergunb 0:f1834a63f7c1 21 *
Sergunb 0:f1834a63f7c1 22 ******************************************************************************/
Sergunb 0:f1834a63f7c1 23
Sergunb 0:f1834a63f7c1 24 #ifndef __CORE_CMFUNC_H
Sergunb 0:f1834a63f7c1 25 #define __CORE_CMFUNC_H
Sergunb 0:f1834a63f7c1 26
Sergunb 0:f1834a63f7c1 27
Sergunb 0:f1834a63f7c1 28 /* ########################### Core Function Access ########################### */
Sergunb 0:f1834a63f7c1 29 /** \ingroup CMSIS_Core_FunctionInterface
Sergunb 0:f1834a63f7c1 30 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
Sergunb 0:f1834a63f7c1 31 @{
Sergunb 0:f1834a63f7c1 32 */
Sergunb 0:f1834a63f7c1 33
Sergunb 0:f1834a63f7c1 34 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
Sergunb 0:f1834a63f7c1 35 /* ARM armcc specific functions */
Sergunb 0:f1834a63f7c1 36
Sergunb 0:f1834a63f7c1 37 #if (__ARMCC_VERSION < 400677)
Sergunb 0:f1834a63f7c1 38 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
Sergunb 0:f1834a63f7c1 39 #endif
Sergunb 0:f1834a63f7c1 40
Sergunb 0:f1834a63f7c1 41 /* intrinsic void __enable_irq(); */
Sergunb 0:f1834a63f7c1 42 /* intrinsic void __disable_irq(); */
Sergunb 0:f1834a63f7c1 43
Sergunb 0:f1834a63f7c1 44 /** \brief Get Control Register
Sergunb 0:f1834a63f7c1 45
Sergunb 0:f1834a63f7c1 46 This function returns the content of the Control Register.
Sergunb 0:f1834a63f7c1 47
Sergunb 0:f1834a63f7c1 48 \return Control Register value
Sergunb 0:f1834a63f7c1 49 */
Sergunb 0:f1834a63f7c1 50 __STATIC_INLINE uint32_t __get_CONTROL(void)
Sergunb 0:f1834a63f7c1 51 {
Sergunb 0:f1834a63f7c1 52 register uint32_t __regControl __ASM("control");
Sergunb 0:f1834a63f7c1 53 return(__regControl);
Sergunb 0:f1834a63f7c1 54 }
Sergunb 0:f1834a63f7c1 55
Sergunb 0:f1834a63f7c1 56
Sergunb 0:f1834a63f7c1 57 /** \brief Set Control Register
Sergunb 0:f1834a63f7c1 58
Sergunb 0:f1834a63f7c1 59 This function writes the given value to the Control Register.
Sergunb 0:f1834a63f7c1 60
Sergunb 0:f1834a63f7c1 61 \param [in] control Control Register value to set
Sergunb 0:f1834a63f7c1 62 */
Sergunb 0:f1834a63f7c1 63 __STATIC_INLINE void __set_CONTROL(uint32_t control)
Sergunb 0:f1834a63f7c1 64 {
Sergunb 0:f1834a63f7c1 65 register uint32_t __regControl __ASM("control");
Sergunb 0:f1834a63f7c1 66 __regControl = control;
Sergunb 0:f1834a63f7c1 67 }
Sergunb 0:f1834a63f7c1 68
Sergunb 0:f1834a63f7c1 69
Sergunb 0:f1834a63f7c1 70 /** \brief Get IPSR Register
Sergunb 0:f1834a63f7c1 71
Sergunb 0:f1834a63f7c1 72 This function returns the content of the IPSR Register.
Sergunb 0:f1834a63f7c1 73
Sergunb 0:f1834a63f7c1 74 \return IPSR Register value
Sergunb 0:f1834a63f7c1 75 */
Sergunb 0:f1834a63f7c1 76 __STATIC_INLINE uint32_t __get_IPSR(void)
Sergunb 0:f1834a63f7c1 77 {
Sergunb 0:f1834a63f7c1 78 register uint32_t __regIPSR __ASM("ipsr");
Sergunb 0:f1834a63f7c1 79 return(__regIPSR);
Sergunb 0:f1834a63f7c1 80 }
Sergunb 0:f1834a63f7c1 81
Sergunb 0:f1834a63f7c1 82
Sergunb 0:f1834a63f7c1 83 /** \brief Get APSR Register
Sergunb 0:f1834a63f7c1 84
Sergunb 0:f1834a63f7c1 85 This function returns the content of the APSR Register.
Sergunb 0:f1834a63f7c1 86
Sergunb 0:f1834a63f7c1 87 \return APSR Register value
Sergunb 0:f1834a63f7c1 88 */
Sergunb 0:f1834a63f7c1 89 __STATIC_INLINE uint32_t __get_APSR(void)
Sergunb 0:f1834a63f7c1 90 {
Sergunb 0:f1834a63f7c1 91 register uint32_t __regAPSR __ASM("apsr");
Sergunb 0:f1834a63f7c1 92 return(__regAPSR);
Sergunb 0:f1834a63f7c1 93 }
Sergunb 0:f1834a63f7c1 94
Sergunb 0:f1834a63f7c1 95
Sergunb 0:f1834a63f7c1 96 /** \brief Get xPSR Register
Sergunb 0:f1834a63f7c1 97
Sergunb 0:f1834a63f7c1 98 This function returns the content of the xPSR Register.
Sergunb 0:f1834a63f7c1 99
Sergunb 0:f1834a63f7c1 100 \return xPSR Register value
Sergunb 0:f1834a63f7c1 101 */
Sergunb 0:f1834a63f7c1 102 __STATIC_INLINE uint32_t __get_xPSR(void)
Sergunb 0:f1834a63f7c1 103 {
Sergunb 0:f1834a63f7c1 104 register uint32_t __regXPSR __ASM("xpsr");
Sergunb 0:f1834a63f7c1 105 return(__regXPSR);
Sergunb 0:f1834a63f7c1 106 }
Sergunb 0:f1834a63f7c1 107
Sergunb 0:f1834a63f7c1 108
Sergunb 0:f1834a63f7c1 109 /** \brief Get Process Stack Pointer
Sergunb 0:f1834a63f7c1 110
Sergunb 0:f1834a63f7c1 111 This function returns the current value of the Process Stack Pointer (PSP).
Sergunb 0:f1834a63f7c1 112
Sergunb 0:f1834a63f7c1 113 \return PSP Register value
Sergunb 0:f1834a63f7c1 114 */
Sergunb 0:f1834a63f7c1 115 __STATIC_INLINE uint32_t __get_PSP(void)
Sergunb 0:f1834a63f7c1 116 {
Sergunb 0:f1834a63f7c1 117 register uint32_t __regProcessStackPointer __ASM("psp");
Sergunb 0:f1834a63f7c1 118 return(__regProcessStackPointer);
Sergunb 0:f1834a63f7c1 119 }
Sergunb 0:f1834a63f7c1 120
Sergunb 0:f1834a63f7c1 121
Sergunb 0:f1834a63f7c1 122 /** \brief Set Process Stack Pointer
Sergunb 0:f1834a63f7c1 123
Sergunb 0:f1834a63f7c1 124 This function assigns the given value to the Process Stack Pointer (PSP).
Sergunb 0:f1834a63f7c1 125
Sergunb 0:f1834a63f7c1 126 \param [in] topOfProcStack Process Stack Pointer value to set
Sergunb 0:f1834a63f7c1 127 */
Sergunb 0:f1834a63f7c1 128 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Sergunb 0:f1834a63f7c1 129 {
Sergunb 0:f1834a63f7c1 130 register uint32_t __regProcessStackPointer __ASM("psp");
Sergunb 0:f1834a63f7c1 131 __regProcessStackPointer = topOfProcStack;
Sergunb 0:f1834a63f7c1 132 }
Sergunb 0:f1834a63f7c1 133
Sergunb 0:f1834a63f7c1 134
Sergunb 0:f1834a63f7c1 135 /** \brief Get Main Stack Pointer
Sergunb 0:f1834a63f7c1 136
Sergunb 0:f1834a63f7c1 137 This function returns the current value of the Main Stack Pointer (MSP).
Sergunb 0:f1834a63f7c1 138
Sergunb 0:f1834a63f7c1 139 \return MSP Register value
Sergunb 0:f1834a63f7c1 140 */
Sergunb 0:f1834a63f7c1 141 __STATIC_INLINE uint32_t __get_MSP(void)
Sergunb 0:f1834a63f7c1 142 {
Sergunb 0:f1834a63f7c1 143 register uint32_t __regMainStackPointer __ASM("msp");
Sergunb 0:f1834a63f7c1 144 return(__regMainStackPointer);
Sergunb 0:f1834a63f7c1 145 }
Sergunb 0:f1834a63f7c1 146
Sergunb 0:f1834a63f7c1 147
Sergunb 0:f1834a63f7c1 148 /** \brief Set Main Stack Pointer
Sergunb 0:f1834a63f7c1 149
Sergunb 0:f1834a63f7c1 150 This function assigns the given value to the Main Stack Pointer (MSP).
Sergunb 0:f1834a63f7c1 151
Sergunb 0:f1834a63f7c1 152 \param [in] topOfMainStack Main Stack Pointer value to set
Sergunb 0:f1834a63f7c1 153 */
Sergunb 0:f1834a63f7c1 154 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Sergunb 0:f1834a63f7c1 155 {
Sergunb 0:f1834a63f7c1 156 register uint32_t __regMainStackPointer __ASM("msp");
Sergunb 0:f1834a63f7c1 157 __regMainStackPointer = topOfMainStack;
Sergunb 0:f1834a63f7c1 158 }
Sergunb 0:f1834a63f7c1 159
Sergunb 0:f1834a63f7c1 160
Sergunb 0:f1834a63f7c1 161 /** \brief Get Priority Mask
Sergunb 0:f1834a63f7c1 162
Sergunb 0:f1834a63f7c1 163 This function returns the current state of the priority mask bit from the Priority Mask Register.
Sergunb 0:f1834a63f7c1 164
Sergunb 0:f1834a63f7c1 165 \return Priority Mask value
Sergunb 0:f1834a63f7c1 166 */
Sergunb 0:f1834a63f7c1 167 __STATIC_INLINE uint32_t __get_PRIMASK(void)
Sergunb 0:f1834a63f7c1 168 {
Sergunb 0:f1834a63f7c1 169 register uint32_t __regPriMask __ASM("primask");
Sergunb 0:f1834a63f7c1 170 return(__regPriMask);
Sergunb 0:f1834a63f7c1 171 }
Sergunb 0:f1834a63f7c1 172
Sergunb 0:f1834a63f7c1 173
Sergunb 0:f1834a63f7c1 174 /** \brief Set Priority Mask
Sergunb 0:f1834a63f7c1 175
Sergunb 0:f1834a63f7c1 176 This function assigns the given value to the Priority Mask Register.
Sergunb 0:f1834a63f7c1 177
Sergunb 0:f1834a63f7c1 178 \param [in] priMask Priority Mask
Sergunb 0:f1834a63f7c1 179 */
Sergunb 0:f1834a63f7c1 180 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Sergunb 0:f1834a63f7c1 181 {
Sergunb 0:f1834a63f7c1 182 register uint32_t __regPriMask __ASM("primask");
Sergunb 0:f1834a63f7c1 183 __regPriMask = (priMask);
Sergunb 0:f1834a63f7c1 184 }
Sergunb 0:f1834a63f7c1 185
Sergunb 0:f1834a63f7c1 186
Sergunb 0:f1834a63f7c1 187 #if (__CORTEX_M >= 0x03)
Sergunb 0:f1834a63f7c1 188
Sergunb 0:f1834a63f7c1 189 /** \brief Enable FIQ
Sergunb 0:f1834a63f7c1 190
Sergunb 0:f1834a63f7c1 191 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Sergunb 0:f1834a63f7c1 192 Can only be executed in Privileged modes.
Sergunb 0:f1834a63f7c1 193 */
Sergunb 0:f1834a63f7c1 194 #define __enable_fault_irq __enable_fiq
Sergunb 0:f1834a63f7c1 195
Sergunb 0:f1834a63f7c1 196
Sergunb 0:f1834a63f7c1 197 /** \brief Disable FIQ
Sergunb 0:f1834a63f7c1 198
Sergunb 0:f1834a63f7c1 199 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Sergunb 0:f1834a63f7c1 200 Can only be executed in Privileged modes.
Sergunb 0:f1834a63f7c1 201 */
Sergunb 0:f1834a63f7c1 202 #define __disable_fault_irq __disable_fiq
Sergunb 0:f1834a63f7c1 203
Sergunb 0:f1834a63f7c1 204
Sergunb 0:f1834a63f7c1 205 /** \brief Get Base Priority
Sergunb 0:f1834a63f7c1 206
Sergunb 0:f1834a63f7c1 207 This function returns the current value of the Base Priority register.
Sergunb 0:f1834a63f7c1 208
Sergunb 0:f1834a63f7c1 209 \return Base Priority register value
Sergunb 0:f1834a63f7c1 210 */
Sergunb 0:f1834a63f7c1 211 __STATIC_INLINE uint32_t __get_BASEPRI(void)
Sergunb 0:f1834a63f7c1 212 {
Sergunb 0:f1834a63f7c1 213 register uint32_t __regBasePri __ASM("basepri");
Sergunb 0:f1834a63f7c1 214 return(__regBasePri);
Sergunb 0:f1834a63f7c1 215 }
Sergunb 0:f1834a63f7c1 216
Sergunb 0:f1834a63f7c1 217
Sergunb 0:f1834a63f7c1 218 /** \brief Set Base Priority
Sergunb 0:f1834a63f7c1 219
Sergunb 0:f1834a63f7c1 220 This function assigns the given value to the Base Priority register.
Sergunb 0:f1834a63f7c1 221
Sergunb 0:f1834a63f7c1 222 \param [in] basePri Base Priority value to set
Sergunb 0:f1834a63f7c1 223 */
Sergunb 0:f1834a63f7c1 224 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
Sergunb 0:f1834a63f7c1 225 {
Sergunb 0:f1834a63f7c1 226 register uint32_t __regBasePri __ASM("basepri");
Sergunb 0:f1834a63f7c1 227 __regBasePri = (basePri & 0xff);
Sergunb 0:f1834a63f7c1 228 }
Sergunb 0:f1834a63f7c1 229
Sergunb 0:f1834a63f7c1 230
Sergunb 0:f1834a63f7c1 231 /** \brief Get Fault Mask
Sergunb 0:f1834a63f7c1 232
Sergunb 0:f1834a63f7c1 233 This function returns the current value of the Fault Mask register.
Sergunb 0:f1834a63f7c1 234
Sergunb 0:f1834a63f7c1 235 \return Fault Mask register value
Sergunb 0:f1834a63f7c1 236 */
Sergunb 0:f1834a63f7c1 237 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
Sergunb 0:f1834a63f7c1 238 {
Sergunb 0:f1834a63f7c1 239 register uint32_t __regFaultMask __ASM("faultmask");
Sergunb 0:f1834a63f7c1 240 return(__regFaultMask);
Sergunb 0:f1834a63f7c1 241 }
Sergunb 0:f1834a63f7c1 242
Sergunb 0:f1834a63f7c1 243
Sergunb 0:f1834a63f7c1 244 /** \brief Set Fault Mask
Sergunb 0:f1834a63f7c1 245
Sergunb 0:f1834a63f7c1 246 This function assigns the given value to the Fault Mask register.
Sergunb 0:f1834a63f7c1 247
Sergunb 0:f1834a63f7c1 248 \param [in] faultMask Fault Mask value to set
Sergunb 0:f1834a63f7c1 249 */
Sergunb 0:f1834a63f7c1 250 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
Sergunb 0:f1834a63f7c1 251 {
Sergunb 0:f1834a63f7c1 252 register uint32_t __regFaultMask __ASM("faultmask");
Sergunb 0:f1834a63f7c1 253 __regFaultMask = (faultMask & (uint32_t)1);
Sergunb 0:f1834a63f7c1 254 }
Sergunb 0:f1834a63f7c1 255
Sergunb 0:f1834a63f7c1 256 #endif /* (__CORTEX_M >= 0x03) */
Sergunb 0:f1834a63f7c1 257
Sergunb 0:f1834a63f7c1 258
Sergunb 0:f1834a63f7c1 259 #if (__CORTEX_M == 0x04)
Sergunb 0:f1834a63f7c1 260
Sergunb 0:f1834a63f7c1 261 /** \brief Get FPSCR
Sergunb 0:f1834a63f7c1 262
Sergunb 0:f1834a63f7c1 263 This function returns the current value of the Floating Point Status/Control register.
Sergunb 0:f1834a63f7c1 264
Sergunb 0:f1834a63f7c1 265 \return Floating Point Status/Control register value
Sergunb 0:f1834a63f7c1 266 */
Sergunb 0:f1834a63f7c1 267 __STATIC_INLINE uint32_t __get_FPSCR(void)
Sergunb 0:f1834a63f7c1 268 {
Sergunb 0:f1834a63f7c1 269 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Sergunb 0:f1834a63f7c1 270 register uint32_t __regfpscr __ASM("fpscr");
Sergunb 0:f1834a63f7c1 271 return(__regfpscr);
Sergunb 0:f1834a63f7c1 272 #else
Sergunb 0:f1834a63f7c1 273 return(0);
Sergunb 0:f1834a63f7c1 274 #endif
Sergunb 0:f1834a63f7c1 275 }
Sergunb 0:f1834a63f7c1 276
Sergunb 0:f1834a63f7c1 277
Sergunb 0:f1834a63f7c1 278 /** \brief Set FPSCR
Sergunb 0:f1834a63f7c1 279
Sergunb 0:f1834a63f7c1 280 This function assigns the given value to the Floating Point Status/Control register.
Sergunb 0:f1834a63f7c1 281
Sergunb 0:f1834a63f7c1 282 \param [in] fpscr Floating Point Status/Control value to set
Sergunb 0:f1834a63f7c1 283 */
Sergunb 0:f1834a63f7c1 284 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Sergunb 0:f1834a63f7c1 285 {
Sergunb 0:f1834a63f7c1 286 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Sergunb 0:f1834a63f7c1 287 register uint32_t __regfpscr __ASM("fpscr");
Sergunb 0:f1834a63f7c1 288 __regfpscr = (fpscr);
Sergunb 0:f1834a63f7c1 289 #endif
Sergunb 0:f1834a63f7c1 290 }
Sergunb 0:f1834a63f7c1 291
Sergunb 0:f1834a63f7c1 292 #endif /* (__CORTEX_M == 0x04) */
Sergunb 0:f1834a63f7c1 293
Sergunb 0:f1834a63f7c1 294
Sergunb 0:f1834a63f7c1 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
Sergunb 0:f1834a63f7c1 296 /* IAR iccarm specific functions */
Sergunb 0:f1834a63f7c1 297
Sergunb 0:f1834a63f7c1 298 #include <cmsis_iar.h>
Sergunb 0:f1834a63f7c1 299
Sergunb 0:f1834a63f7c1 300
Sergunb 0:f1834a63f7c1 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
Sergunb 0:f1834a63f7c1 302 /* TI CCS specific functions */
Sergunb 0:f1834a63f7c1 303
Sergunb 0:f1834a63f7c1 304 #include <cmsis_ccs.h>
Sergunb 0:f1834a63f7c1 305
Sergunb 0:f1834a63f7c1 306
Sergunb 0:f1834a63f7c1 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
Sergunb 0:f1834a63f7c1 308 /* GNU gcc specific functions */
Sergunb 0:f1834a63f7c1 309
Sergunb 0:f1834a63f7c1 310 /** \brief Enable IRQ Interrupts
Sergunb 0:f1834a63f7c1 311
Sergunb 0:f1834a63f7c1 312 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Sergunb 0:f1834a63f7c1 313 Can only be executed in Privileged modes.
Sergunb 0:f1834a63f7c1 314 */
Sergunb 0:f1834a63f7c1 315 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
Sergunb 0:f1834a63f7c1 316 {
Sergunb 0:f1834a63f7c1 317 __ASM volatile ("cpsie i");
Sergunb 0:f1834a63f7c1 318 }
Sergunb 0:f1834a63f7c1 319
Sergunb 0:f1834a63f7c1 320
Sergunb 0:f1834a63f7c1 321 /** \brief Disable IRQ Interrupts
Sergunb 0:f1834a63f7c1 322
Sergunb 0:f1834a63f7c1 323 This function disables IRQ interrupts by setting the I-bit in the CPSR.
Sergunb 0:f1834a63f7c1 324 Can only be executed in Privileged modes.
Sergunb 0:f1834a63f7c1 325 */
Sergunb 0:f1834a63f7c1 326 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
Sergunb 0:f1834a63f7c1 327 {
Sergunb 0:f1834a63f7c1 328 __ASM volatile ("cpsid i");
Sergunb 0:f1834a63f7c1 329 }
Sergunb 0:f1834a63f7c1 330
Sergunb 0:f1834a63f7c1 331
Sergunb 0:f1834a63f7c1 332 /** \brief Get Control Register
Sergunb 0:f1834a63f7c1 333
Sergunb 0:f1834a63f7c1 334 This function returns the content of the Control Register.
Sergunb 0:f1834a63f7c1 335
Sergunb 0:f1834a63f7c1 336 \return Control Register value
Sergunb 0:f1834a63f7c1 337 */
Sergunb 0:f1834a63f7c1 338 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
Sergunb 0:f1834a63f7c1 339 {
Sergunb 0:f1834a63f7c1 340 uint32_t result;
Sergunb 0:f1834a63f7c1 341
Sergunb 0:f1834a63f7c1 342 __ASM volatile ("MRS %0, control" : "=r" (result) );
Sergunb 0:f1834a63f7c1 343 return(result);
Sergunb 0:f1834a63f7c1 344 }
Sergunb 0:f1834a63f7c1 345
Sergunb 0:f1834a63f7c1 346
Sergunb 0:f1834a63f7c1 347 /** \brief Set Control Register
Sergunb 0:f1834a63f7c1 348
Sergunb 0:f1834a63f7c1 349 This function writes the given value to the Control Register.
Sergunb 0:f1834a63f7c1 350
Sergunb 0:f1834a63f7c1 351 \param [in] control Control Register value to set
Sergunb 0:f1834a63f7c1 352 */
Sergunb 0:f1834a63f7c1 353 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
Sergunb 0:f1834a63f7c1 354 {
Sergunb 0:f1834a63f7c1 355 __ASM volatile ("MSR control, %0" : : "r" (control) );
Sergunb 0:f1834a63f7c1 356 }
Sergunb 0:f1834a63f7c1 357
Sergunb 0:f1834a63f7c1 358
Sergunb 0:f1834a63f7c1 359 /** \brief Get IPSR Register
Sergunb 0:f1834a63f7c1 360
Sergunb 0:f1834a63f7c1 361 This function returns the content of the IPSR Register.
Sergunb 0:f1834a63f7c1 362
Sergunb 0:f1834a63f7c1 363 \return IPSR Register value
Sergunb 0:f1834a63f7c1 364 */
Sergunb 0:f1834a63f7c1 365 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
Sergunb 0:f1834a63f7c1 366 {
Sergunb 0:f1834a63f7c1 367 uint32_t result;
Sergunb 0:f1834a63f7c1 368
Sergunb 0:f1834a63f7c1 369 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
Sergunb 0:f1834a63f7c1 370 return(result);
Sergunb 0:f1834a63f7c1 371 }
Sergunb 0:f1834a63f7c1 372
Sergunb 0:f1834a63f7c1 373
Sergunb 0:f1834a63f7c1 374 /** \brief Get APSR Register
Sergunb 0:f1834a63f7c1 375
Sergunb 0:f1834a63f7c1 376 This function returns the content of the APSR Register.
Sergunb 0:f1834a63f7c1 377
Sergunb 0:f1834a63f7c1 378 \return APSR Register value
Sergunb 0:f1834a63f7c1 379 */
Sergunb 0:f1834a63f7c1 380 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
Sergunb 0:f1834a63f7c1 381 {
Sergunb 0:f1834a63f7c1 382 uint32_t result;
Sergunb 0:f1834a63f7c1 383
Sergunb 0:f1834a63f7c1 384 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
Sergunb 0:f1834a63f7c1 385 return(result);
Sergunb 0:f1834a63f7c1 386 }
Sergunb 0:f1834a63f7c1 387
Sergunb 0:f1834a63f7c1 388
Sergunb 0:f1834a63f7c1 389 /** \brief Get xPSR Register
Sergunb 0:f1834a63f7c1 390
Sergunb 0:f1834a63f7c1 391 This function returns the content of the xPSR Register.
Sergunb 0:f1834a63f7c1 392
Sergunb 0:f1834a63f7c1 393 \return xPSR Register value
Sergunb 0:f1834a63f7c1 394 */
Sergunb 0:f1834a63f7c1 395 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
Sergunb 0:f1834a63f7c1 396 {
Sergunb 0:f1834a63f7c1 397 uint32_t result;
Sergunb 0:f1834a63f7c1 398
Sergunb 0:f1834a63f7c1 399 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
Sergunb 0:f1834a63f7c1 400 return(result);
Sergunb 0:f1834a63f7c1 401 }
Sergunb 0:f1834a63f7c1 402
Sergunb 0:f1834a63f7c1 403
Sergunb 0:f1834a63f7c1 404 /** \brief Get Process Stack Pointer
Sergunb 0:f1834a63f7c1 405
Sergunb 0:f1834a63f7c1 406 This function returns the current value of the Process Stack Pointer (PSP).
Sergunb 0:f1834a63f7c1 407
Sergunb 0:f1834a63f7c1 408 \return PSP Register value
Sergunb 0:f1834a63f7c1 409 */
Sergunb 0:f1834a63f7c1 410 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
Sergunb 0:f1834a63f7c1 411 {
Sergunb 0:f1834a63f7c1 412 register uint32_t result;
Sergunb 0:f1834a63f7c1 413
Sergunb 0:f1834a63f7c1 414 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
Sergunb 0:f1834a63f7c1 415 return(result);
Sergunb 0:f1834a63f7c1 416 }
Sergunb 0:f1834a63f7c1 417
Sergunb 0:f1834a63f7c1 418
Sergunb 0:f1834a63f7c1 419 /** \brief Set Process Stack Pointer
Sergunb 0:f1834a63f7c1 420
Sergunb 0:f1834a63f7c1 421 This function assigns the given value to the Process Stack Pointer (PSP).
Sergunb 0:f1834a63f7c1 422
Sergunb 0:f1834a63f7c1 423 \param [in] topOfProcStack Process Stack Pointer value to set
Sergunb 0:f1834a63f7c1 424 */
Sergunb 0:f1834a63f7c1 425 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
Sergunb 0:f1834a63f7c1 426 {
Sergunb 0:f1834a63f7c1 427 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
Sergunb 0:f1834a63f7c1 428 }
Sergunb 0:f1834a63f7c1 429
Sergunb 0:f1834a63f7c1 430
Sergunb 0:f1834a63f7c1 431 /** \brief Get Main Stack Pointer
Sergunb 0:f1834a63f7c1 432
Sergunb 0:f1834a63f7c1 433 This function returns the current value of the Main Stack Pointer (MSP).
Sergunb 0:f1834a63f7c1 434
Sergunb 0:f1834a63f7c1 435 \return MSP Register value
Sergunb 0:f1834a63f7c1 436 */
Sergunb 0:f1834a63f7c1 437 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
Sergunb 0:f1834a63f7c1 438 {
Sergunb 0:f1834a63f7c1 439 register uint32_t result;
Sergunb 0:f1834a63f7c1 440
Sergunb 0:f1834a63f7c1 441 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
Sergunb 0:f1834a63f7c1 442 return(result);
Sergunb 0:f1834a63f7c1 443 }
Sergunb 0:f1834a63f7c1 444
Sergunb 0:f1834a63f7c1 445
Sergunb 0:f1834a63f7c1 446 /** \brief Set Main Stack Pointer
Sergunb 0:f1834a63f7c1 447
Sergunb 0:f1834a63f7c1 448 This function assigns the given value to the Main Stack Pointer (MSP).
Sergunb 0:f1834a63f7c1 449
Sergunb 0:f1834a63f7c1 450 \param [in] topOfMainStack Main Stack Pointer value to set
Sergunb 0:f1834a63f7c1 451 */
Sergunb 0:f1834a63f7c1 452 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
Sergunb 0:f1834a63f7c1 453 {
Sergunb 0:f1834a63f7c1 454 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
Sergunb 0:f1834a63f7c1 455 }
Sergunb 0:f1834a63f7c1 456
Sergunb 0:f1834a63f7c1 457
Sergunb 0:f1834a63f7c1 458 /** \brief Get Priority Mask
Sergunb 0:f1834a63f7c1 459
Sergunb 0:f1834a63f7c1 460 This function returns the current state of the priority mask bit from the Priority Mask Register.
Sergunb 0:f1834a63f7c1 461
Sergunb 0:f1834a63f7c1 462 \return Priority Mask value
Sergunb 0:f1834a63f7c1 463 */
Sergunb 0:f1834a63f7c1 464 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
Sergunb 0:f1834a63f7c1 465 {
Sergunb 0:f1834a63f7c1 466 uint32_t result;
Sergunb 0:f1834a63f7c1 467
Sergunb 0:f1834a63f7c1 468 __ASM volatile ("MRS %0, primask" : "=r" (result) );
Sergunb 0:f1834a63f7c1 469 return(result);
Sergunb 0:f1834a63f7c1 470 }
Sergunb 0:f1834a63f7c1 471
Sergunb 0:f1834a63f7c1 472
Sergunb 0:f1834a63f7c1 473 /** \brief Set Priority Mask
Sergunb 0:f1834a63f7c1 474
Sergunb 0:f1834a63f7c1 475 This function assigns the given value to the Priority Mask Register.
Sergunb 0:f1834a63f7c1 476
Sergunb 0:f1834a63f7c1 477 \param [in] priMask Priority Mask
Sergunb 0:f1834a63f7c1 478 */
Sergunb 0:f1834a63f7c1 479 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
Sergunb 0:f1834a63f7c1 480 {
Sergunb 0:f1834a63f7c1 481 __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
Sergunb 0:f1834a63f7c1 482 }
Sergunb 0:f1834a63f7c1 483
Sergunb 0:f1834a63f7c1 484
Sergunb 0:f1834a63f7c1 485 #if (__CORTEX_M >= 0x03)
Sergunb 0:f1834a63f7c1 486
Sergunb 0:f1834a63f7c1 487 /** \brief Enable FIQ
Sergunb 0:f1834a63f7c1 488
Sergunb 0:f1834a63f7c1 489 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Sergunb 0:f1834a63f7c1 490 Can only be executed in Privileged modes.
Sergunb 0:f1834a63f7c1 491 */
Sergunb 0:f1834a63f7c1 492 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
Sergunb 0:f1834a63f7c1 493 {
Sergunb 0:f1834a63f7c1 494 __ASM volatile ("cpsie f");
Sergunb 0:f1834a63f7c1 495 }
Sergunb 0:f1834a63f7c1 496
Sergunb 0:f1834a63f7c1 497
Sergunb 0:f1834a63f7c1 498 /** \brief Disable FIQ
Sergunb 0:f1834a63f7c1 499
Sergunb 0:f1834a63f7c1 500 This function disables FIQ interrupts by setting the F-bit in the CPSR.
Sergunb 0:f1834a63f7c1 501 Can only be executed in Privileged modes.
Sergunb 0:f1834a63f7c1 502 */
Sergunb 0:f1834a63f7c1 503 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
Sergunb 0:f1834a63f7c1 504 {
Sergunb 0:f1834a63f7c1 505 __ASM volatile ("cpsid f");
Sergunb 0:f1834a63f7c1 506 }
Sergunb 0:f1834a63f7c1 507
Sergunb 0:f1834a63f7c1 508
Sergunb 0:f1834a63f7c1 509 /** \brief Get Base Priority
Sergunb 0:f1834a63f7c1 510
Sergunb 0:f1834a63f7c1 511 This function returns the current value of the Base Priority register.
Sergunb 0:f1834a63f7c1 512
Sergunb 0:f1834a63f7c1 513 \return Base Priority register value
Sergunb 0:f1834a63f7c1 514 */
Sergunb 0:f1834a63f7c1 515 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
Sergunb 0:f1834a63f7c1 516 {
Sergunb 0:f1834a63f7c1 517 uint32_t result;
Sergunb 0:f1834a63f7c1 518
Sergunb 0:f1834a63f7c1 519 __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
Sergunb 0:f1834a63f7c1 520 return(result);
Sergunb 0:f1834a63f7c1 521 }
Sergunb 0:f1834a63f7c1 522
Sergunb 0:f1834a63f7c1 523
Sergunb 0:f1834a63f7c1 524 /** \brief Set Base Priority
Sergunb 0:f1834a63f7c1 525
Sergunb 0:f1834a63f7c1 526 This function assigns the given value to the Base Priority register.
Sergunb 0:f1834a63f7c1 527
Sergunb 0:f1834a63f7c1 528 \param [in] basePri Base Priority value to set
Sergunb 0:f1834a63f7c1 529 */
Sergunb 0:f1834a63f7c1 530 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
Sergunb 0:f1834a63f7c1 531 {
Sergunb 0:f1834a63f7c1 532 __ASM volatile ("MSR basepri, %0" : : "r" (value) );
Sergunb 0:f1834a63f7c1 533 }
Sergunb 0:f1834a63f7c1 534
Sergunb 0:f1834a63f7c1 535
Sergunb 0:f1834a63f7c1 536 /** \brief Get Fault Mask
Sergunb 0:f1834a63f7c1 537
Sergunb 0:f1834a63f7c1 538 This function returns the current value of the Fault Mask register.
Sergunb 0:f1834a63f7c1 539
Sergunb 0:f1834a63f7c1 540 \return Fault Mask register value
Sergunb 0:f1834a63f7c1 541 */
Sergunb 0:f1834a63f7c1 542 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
Sergunb 0:f1834a63f7c1 543 {
Sergunb 0:f1834a63f7c1 544 uint32_t result;
Sergunb 0:f1834a63f7c1 545
Sergunb 0:f1834a63f7c1 546 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
Sergunb 0:f1834a63f7c1 547 return(result);
Sergunb 0:f1834a63f7c1 548 }
Sergunb 0:f1834a63f7c1 549
Sergunb 0:f1834a63f7c1 550
Sergunb 0:f1834a63f7c1 551 /** \brief Set Fault Mask
Sergunb 0:f1834a63f7c1 552
Sergunb 0:f1834a63f7c1 553 This function assigns the given value to the Fault Mask register.
Sergunb 0:f1834a63f7c1 554
Sergunb 0:f1834a63f7c1 555 \param [in] faultMask Fault Mask value to set
Sergunb 0:f1834a63f7c1 556 */
Sergunb 0:f1834a63f7c1 557 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
Sergunb 0:f1834a63f7c1 558 {
Sergunb 0:f1834a63f7c1 559 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
Sergunb 0:f1834a63f7c1 560 }
Sergunb 0:f1834a63f7c1 561
Sergunb 0:f1834a63f7c1 562 #endif /* (__CORTEX_M >= 0x03) */
Sergunb 0:f1834a63f7c1 563
Sergunb 0:f1834a63f7c1 564
Sergunb 0:f1834a63f7c1 565 #if (__CORTEX_M == 0x04)
Sergunb 0:f1834a63f7c1 566
Sergunb 0:f1834a63f7c1 567 /** \brief Get FPSCR
Sergunb 0:f1834a63f7c1 568
Sergunb 0:f1834a63f7c1 569 This function returns the current value of the Floating Point Status/Control register.
Sergunb 0:f1834a63f7c1 570
Sergunb 0:f1834a63f7c1 571 \return Floating Point Status/Control register value
Sergunb 0:f1834a63f7c1 572 */
Sergunb 0:f1834a63f7c1 573 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
Sergunb 0:f1834a63f7c1 574 {
Sergunb 0:f1834a63f7c1 575 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Sergunb 0:f1834a63f7c1 576 uint32_t result;
Sergunb 0:f1834a63f7c1 577
Sergunb 0:f1834a63f7c1 578 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
Sergunb 0:f1834a63f7c1 579 return(result);
Sergunb 0:f1834a63f7c1 580 #else
Sergunb 0:f1834a63f7c1 581 return(0);
Sergunb 0:f1834a63f7c1 582 #endif
Sergunb 0:f1834a63f7c1 583 }
Sergunb 0:f1834a63f7c1 584
Sergunb 0:f1834a63f7c1 585
Sergunb 0:f1834a63f7c1 586 /** \brief Set FPSCR
Sergunb 0:f1834a63f7c1 587
Sergunb 0:f1834a63f7c1 588 This function assigns the given value to the Floating Point Status/Control register.
Sergunb 0:f1834a63f7c1 589
Sergunb 0:f1834a63f7c1 590 \param [in] fpscr Floating Point Status/Control value to set
Sergunb 0:f1834a63f7c1 591 */
Sergunb 0:f1834a63f7c1 592 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
Sergunb 0:f1834a63f7c1 593 {
Sergunb 0:f1834a63f7c1 594 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
Sergunb 0:f1834a63f7c1 595 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
Sergunb 0:f1834a63f7c1 596 #endif
Sergunb 0:f1834a63f7c1 597 }
Sergunb 0:f1834a63f7c1 598
Sergunb 0:f1834a63f7c1 599 #endif /* (__CORTEX_M == 0x04) */
Sergunb 0:f1834a63f7c1 600
Sergunb 0:f1834a63f7c1 601
Sergunb 0:f1834a63f7c1 602 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
Sergunb 0:f1834a63f7c1 603 /* TASKING carm specific functions */
Sergunb 0:f1834a63f7c1 604
Sergunb 0:f1834a63f7c1 605 /*
Sergunb 0:f1834a63f7c1 606 * The CMSIS functions have been implemented as intrinsics in the compiler.
Sergunb 0:f1834a63f7c1 607 * Please use "carm -?i" to get an up to date list of all instrinsics,
Sergunb 0:f1834a63f7c1 608 * Including the CMSIS ones.
Sergunb 0:f1834a63f7c1 609 */
Sergunb 0:f1834a63f7c1 610
Sergunb 0:f1834a63f7c1 611 #endif
Sergunb 0:f1834a63f7c1 612
Sergunb 0:f1834a63f7c1 613 /*@} end of CMSIS_Core_RegAccFunctions */
Sergunb 0:f1834a63f7c1 614
Sergunb 0:f1834a63f7c1 615
Sergunb 0:f1834a63f7c1 616 #endif /* __CORE_CMFUNC_H */