Sergey Pastor / grbl

stm_usb_fs_lib/inc/usb_regs.h@0:f1834a63f7c1, 2017-09-04 (annotated)

Committer:
Sergunb
Date:
Mon Sep 04 12:03:42 2017 +0000
Revision:
0:f1834a63f7c1
Initial commit

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Sergunb 0:f1834a63f7c1 1 /******************** (C) COPYRIGHT 2010 STMicroelectronics ********************
Sergunb 0:f1834a63f7c1 2 * File Name : usb_regs.h
Sergunb 0:f1834a63f7c1 3 * Author : MCD Application Team
Sergunb 0:f1834a63f7c1 4 * Version : V3.2.1
Sergunb 0:f1834a63f7c1 5 * Date : 07/05/2010
Sergunb 0:f1834a63f7c1 6 * Description : Interface prototype functions to USB cell registers
Sergunb 0:f1834a63f7c1 7 ********************************************************************************
Sergunb 0:f1834a63f7c1 8 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
Sergunb 0:f1834a63f7c1 9 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
Sergunb 0:f1834a63f7c1 10 * AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
Sergunb 0:f1834a63f7c1 11 * INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
Sergunb 0:f1834a63f7c1 12 * CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
Sergunb 0:f1834a63f7c1 13 * INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
Sergunb 0:f1834a63f7c1 14 *******************************************************************************/
Sergunb 0:f1834a63f7c1 15
Sergunb 0:f1834a63f7c1 16 /* Define to prevent recursive inclusion -------------------------------------*/
Sergunb 0:f1834a63f7c1 17 #ifndef __USB_REGS_H
Sergunb 0:f1834a63f7c1 18 #define __USB_REGS_H
Sergunb 0:f1834a63f7c1 19
Sergunb 0:f1834a63f7c1 20 #ifndef STM32F10X_CL
Sergunb 0:f1834a63f7c1 21
Sergunb 0:f1834a63f7c1 22 /* Includes ------------------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 23 /* Exported types ------------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 24 typedef enum _EP_DBUF_DIR
Sergunb 0:f1834a63f7c1 25 {
Sergunb 0:f1834a63f7c1 26 /* double buffered endpoint direction */
Sergunb 0:f1834a63f7c1 27 EP_DBUF_ERR,
Sergunb 0:f1834a63f7c1 28 EP_DBUF_OUT,
Sergunb 0:f1834a63f7c1 29 EP_DBUF_IN
Sergunb 0:f1834a63f7c1 30 }EP_DBUF_DIR;
Sergunb 0:f1834a63f7c1 31
Sergunb 0:f1834a63f7c1 32 /* endpoint buffer number */
Sergunb 0:f1834a63f7c1 33 enum EP_BUF_NUM
Sergunb 0:f1834a63f7c1 34 {
Sergunb 0:f1834a63f7c1 35 EP_NOBUF,
Sergunb 0:f1834a63f7c1 36 EP_BUF0,
Sergunb 0:f1834a63f7c1 37 EP_BUF1
Sergunb 0:f1834a63f7c1 38 };
Sergunb 0:f1834a63f7c1 39
Sergunb 0:f1834a63f7c1 40 /* Exported constants --------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 41 #define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
Sergunb 0:f1834a63f7c1 42 #define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */
Sergunb 0:f1834a63f7c1 43
Sergunb 0:f1834a63f7c1 44 /******************************************************************************/
Sergunb 0:f1834a63f7c1 45 /* General registers */
Sergunb 0:f1834a63f7c1 46 /******************************************************************************/
Sergunb 0:f1834a63f7c1 47
Sergunb 0:f1834a63f7c1 48 /* Control register */
Sergunb 0:f1834a63f7c1 49 #define CNTR ((__IO unsigned *)(RegBase + 0x40))
Sergunb 0:f1834a63f7c1 50 /* Interrupt status register */
Sergunb 0:f1834a63f7c1 51 #define ISTR ((__IO unsigned *)(RegBase + 0x44))
Sergunb 0:f1834a63f7c1 52 /* Frame number register */
Sergunb 0:f1834a63f7c1 53 #define FNR ((__IO unsigned *)(RegBase + 0x48))
Sergunb 0:f1834a63f7c1 54 /* Device address register */
Sergunb 0:f1834a63f7c1 55 #define DADDR ((__IO unsigned *)(RegBase + 0x4C))
Sergunb 0:f1834a63f7c1 56 /* Buffer Table address register */
Sergunb 0:f1834a63f7c1 57 #define BTABLE ((__IO unsigned *)(RegBase + 0x50))
Sergunb 0:f1834a63f7c1 58 /******************************************************************************/
Sergunb 0:f1834a63f7c1 59 /* Endpoint registers */
Sergunb 0:f1834a63f7c1 60 /******************************************************************************/
Sergunb 0:f1834a63f7c1 61 #define EP0REG ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */
Sergunb 0:f1834a63f7c1 62
Sergunb 0:f1834a63f7c1 63 /* Endpoint Addresses (w/direction) */
Sergunb 0:f1834a63f7c1 64 #define EP0_OUT ((uint8_t)0x00)
Sergunb 0:f1834a63f7c1 65 #define EP0_IN ((uint8_t)0x80)
Sergunb 0:f1834a63f7c1 66 #define EP1_OUT ((uint8_t)0x01)
Sergunb 0:f1834a63f7c1 67 #define EP1_IN ((uint8_t)0x81)
Sergunb 0:f1834a63f7c1 68 #define EP2_OUT ((uint8_t)0x02)
Sergunb 0:f1834a63f7c1 69 #define EP2_IN ((uint8_t)0x82)
Sergunb 0:f1834a63f7c1 70 #define EP3_OUT ((uint8_t)0x03)
Sergunb 0:f1834a63f7c1 71 #define EP3_IN ((uint8_t)0x83)
Sergunb 0:f1834a63f7c1 72 #define EP4_OUT ((uint8_t)0x04)
Sergunb 0:f1834a63f7c1 73 #define EP4_IN ((uint8_t)0x84)
Sergunb 0:f1834a63f7c1 74 #define EP5_OUT ((uint8_t)0x05)
Sergunb 0:f1834a63f7c1 75 #define EP5_IN ((uint8_t)0x85)
Sergunb 0:f1834a63f7c1 76 #define EP6_OUT ((uint8_t)0x06)
Sergunb 0:f1834a63f7c1 77 #define EP6_IN ((uint8_t)0x86)
Sergunb 0:f1834a63f7c1 78 #define EP7_OUT ((uint8_t)0x07)
Sergunb 0:f1834a63f7c1 79 #define EP7_IN ((uint8_t)0x87)
Sergunb 0:f1834a63f7c1 80
Sergunb 0:f1834a63f7c1 81 /* endpoints enumeration */
Sergunb 0:f1834a63f7c1 82 #define ENDP0 ((uint8_t)0)
Sergunb 0:f1834a63f7c1 83 #define ENDP1 ((uint8_t)1)
Sergunb 0:f1834a63f7c1 84 #define ENDP2 ((uint8_t)2)
Sergunb 0:f1834a63f7c1 85 #define ENDP3 ((uint8_t)3)
Sergunb 0:f1834a63f7c1 86 #define ENDP4 ((uint8_t)4)
Sergunb 0:f1834a63f7c1 87 #define ENDP5 ((uint8_t)5)
Sergunb 0:f1834a63f7c1 88 #define ENDP6 ((uint8_t)6)
Sergunb 0:f1834a63f7c1 89 #define ENDP7 ((uint8_t)7)
Sergunb 0:f1834a63f7c1 90
Sergunb 0:f1834a63f7c1 91 /******************************************************************************/
Sergunb 0:f1834a63f7c1 92 /* ISTR interrupt events */
Sergunb 0:f1834a63f7c1 93 /******************************************************************************/
Sergunb 0:f1834a63f7c1 94 #define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */
Sergunb 0:f1834a63f7c1 95 #define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */
Sergunb 0:f1834a63f7c1 96 #define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */
Sergunb 0:f1834a63f7c1 97 #define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */
Sergunb 0:f1834a63f7c1 98 #define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */
Sergunb 0:f1834a63f7c1 99 #define ISTR_RESET (0x0400) /* RESET (clear-only bit) */
Sergunb 0:f1834a63f7c1 100 #define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */
Sergunb 0:f1834a63f7c1 101 #define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */
Sergunb 0:f1834a63f7c1 102
Sergunb 0:f1834a63f7c1 103
Sergunb 0:f1834a63f7c1 104 #define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */
Sergunb 0:f1834a63f7c1 105 #define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
Sergunb 0:f1834a63f7c1 106
Sergunb 0:f1834a63f7c1 107 #define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */
Sergunb 0:f1834a63f7c1 108 #define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/
Sergunb 0:f1834a63f7c1 109 #define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */
Sergunb 0:f1834a63f7c1 110 #define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */
Sergunb 0:f1834a63f7c1 111 #define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */
Sergunb 0:f1834a63f7c1 112 #define CLR_RESET (~ISTR_RESET) /* clear RESET bit */
Sergunb 0:f1834a63f7c1 113 #define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */
Sergunb 0:f1834a63f7c1 114 #define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */
Sergunb 0:f1834a63f7c1 115
Sergunb 0:f1834a63f7c1 116 /******************************************************************************/
Sergunb 0:f1834a63f7c1 117 /* CNTR control register bits definitions */
Sergunb 0:f1834a63f7c1 118 /******************************************************************************/
Sergunb 0:f1834a63f7c1 119 #define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */
Sergunb 0:f1834a63f7c1 120 #define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */
Sergunb 0:f1834a63f7c1 121 #define CNTR_ERRM (0x2000) /* ERRor Mask */
Sergunb 0:f1834a63f7c1 122 #define CNTR_WKUPM (0x1000) /* WaKe UP Mask */
Sergunb 0:f1834a63f7c1 123 #define CNTR_SUSPM (0x0800) /* SUSPend Mask */
Sergunb 0:f1834a63f7c1 124 #define CNTR_RESETM (0x0400) /* RESET Mask */
Sergunb 0:f1834a63f7c1 125 #define CNTR_SOFM (0x0200) /* Start Of Frame Mask */
Sergunb 0:f1834a63f7c1 126 #define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */
Sergunb 0:f1834a63f7c1 127
Sergunb 0:f1834a63f7c1 128
Sergunb 0:f1834a63f7c1 129 #define CNTR_RESUME (0x0010) /* RESUME request */
Sergunb 0:f1834a63f7c1 130 #define CNTR_FSUSP (0x0008) /* Force SUSPend */
Sergunb 0:f1834a63f7c1 131 #define CNTR_LPMODE (0x0004) /* Low-power MODE */
Sergunb 0:f1834a63f7c1 132 #define CNTR_PDWN (0x0002) /* Power DoWN */
Sergunb 0:f1834a63f7c1 133 #define CNTR_FRES (0x0001) /* Force USB RESet */
Sergunb 0:f1834a63f7c1 134
Sergunb 0:f1834a63f7c1 135 /******************************************************************************/
Sergunb 0:f1834a63f7c1 136 /* FNR Frame Number Register bit definitions */
Sergunb 0:f1834a63f7c1 137 /******************************************************************************/
Sergunb 0:f1834a63f7c1 138 #define FNR_RXDP (0x8000) /* status of D+ data line */
Sergunb 0:f1834a63f7c1 139 #define FNR_RXDM (0x4000) /* status of D- data line */
Sergunb 0:f1834a63f7c1 140 #define FNR_LCK (0x2000) /* LoCKed */
Sergunb 0:f1834a63f7c1 141 #define FNR_LSOF (0x1800) /* Lost SOF */
Sergunb 0:f1834a63f7c1 142 #define FNR_FN (0x07FF) /* Frame Number */
Sergunb 0:f1834a63f7c1 143 /******************************************************************************/
Sergunb 0:f1834a63f7c1 144 /* DADDR Device ADDRess bit definitions */
Sergunb 0:f1834a63f7c1 145 /******************************************************************************/
Sergunb 0:f1834a63f7c1 146 #define DADDR_EF (0x80)
Sergunb 0:f1834a63f7c1 147 #define DADDR_ADD (0x7F)
Sergunb 0:f1834a63f7c1 148 /******************************************************************************/
Sergunb 0:f1834a63f7c1 149 /* Endpoint register */
Sergunb 0:f1834a63f7c1 150 /******************************************************************************/
Sergunb 0:f1834a63f7c1 151 /* bit positions */
Sergunb 0:f1834a63f7c1 152 #define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */
Sergunb 0:f1834a63f7c1 153 #define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
Sergunb 0:f1834a63f7c1 154 #define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */
Sergunb 0:f1834a63f7c1 155 #define EP_SETUP (0x0800) /* EndPoint SETUP */
Sergunb 0:f1834a63f7c1 156 #define EP_T_FIELD (0x0600) /* EndPoint TYPE */
Sergunb 0:f1834a63f7c1 157 #define EP_KIND (0x0100) /* EndPoint KIND */
Sergunb 0:f1834a63f7c1 158 #define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */
Sergunb 0:f1834a63f7c1 159 #define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
Sergunb 0:f1834a63f7c1 160 #define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */
Sergunb 0:f1834a63f7c1 161 #define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
Sergunb 0:f1834a63f7c1 162
Sergunb 0:f1834a63f7c1 163 /* EndPoint REGister MASK (no toggle fields) */
Sergunb 0:f1834a63f7c1 164 #define EPREG_MASK (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD)
Sergunb 0:f1834a63f7c1 165
Sergunb 0:f1834a63f7c1 166 /* EP_TYPE[1:0] EndPoint TYPE */
Sergunb 0:f1834a63f7c1 167 #define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */
Sergunb 0:f1834a63f7c1 168 #define EP_BULK (0x0000) /* EndPoint BULK */
Sergunb 0:f1834a63f7c1 169 #define EP_CONTROL (0x0200) /* EndPoint CONTROL */
Sergunb 0:f1834a63f7c1 170 #define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
Sergunb 0:f1834a63f7c1 171 #define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */
Sergunb 0:f1834a63f7c1 172 #define EP_T_MASK (~EP_T_FIELD & EPREG_MASK)
Sergunb 0:f1834a63f7c1 173
Sergunb 0:f1834a63f7c1 174
Sergunb 0:f1834a63f7c1 175 /* EP_KIND EndPoint KIND */
Sergunb 0:f1834a63f7c1 176 #define EPKIND_MASK (~EP_KIND & EPREG_MASK)
Sergunb 0:f1834a63f7c1 177
Sergunb 0:f1834a63f7c1 178 /* STAT_TX[1:0] STATus for TX transfer */
Sergunb 0:f1834a63f7c1 179 #define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */
Sergunb 0:f1834a63f7c1 180 #define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */
Sergunb 0:f1834a63f7c1 181 #define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */
Sergunb 0:f1834a63f7c1 182 #define EP_TX_VALID (0x0030) /* EndPoint TX VALID */
Sergunb 0:f1834a63f7c1 183 #define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */
Sergunb 0:f1834a63f7c1 184 #define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */
Sergunb 0:f1834a63f7c1 185 #define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK)
Sergunb 0:f1834a63f7c1 186
Sergunb 0:f1834a63f7c1 187 /* STAT_RX[1:0] STATus for RX transfer */
Sergunb 0:f1834a63f7c1 188 #define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */
Sergunb 0:f1834a63f7c1 189 #define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */
Sergunb 0:f1834a63f7c1 190 #define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */
Sergunb 0:f1834a63f7c1 191 #define EP_RX_VALID (0x3000) /* EndPoint RX VALID */
Sergunb 0:f1834a63f7c1 192 #define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */
Sergunb 0:f1834a63f7c1 193 #define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */
Sergunb 0:f1834a63f7c1 194 #define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK)
Sergunb 0:f1834a63f7c1 195 /* Exported macro ------------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 196 /* SetCNTR */
Sergunb 0:f1834a63f7c1 197 #define _SetCNTR(wRegValue) (*CNTR = (uint16_t)wRegValue)
Sergunb 0:f1834a63f7c1 198
Sergunb 0:f1834a63f7c1 199 /* SetISTR */
Sergunb 0:f1834a63f7c1 200 #define _SetISTR(wRegValue) (*ISTR = (uint16_t)wRegValue)
Sergunb 0:f1834a63f7c1 201
Sergunb 0:f1834a63f7c1 202 /* SetDADDR */
Sergunb 0:f1834a63f7c1 203 #define _SetDADDR(wRegValue) (*DADDR = (uint16_t)wRegValue)
Sergunb 0:f1834a63f7c1 204
Sergunb 0:f1834a63f7c1 205 /* SetBTABLE */
Sergunb 0:f1834a63f7c1 206 #define _SetBTABLE(wRegValue)(*BTABLE = (uint16_t)(wRegValue & 0xFFF8))
Sergunb 0:f1834a63f7c1 207
Sergunb 0:f1834a63f7c1 208 /* GetCNTR */
Sergunb 0:f1834a63f7c1 209 #define _GetCNTR() ((uint16_t) *CNTR)
Sergunb 0:f1834a63f7c1 210
Sergunb 0:f1834a63f7c1 211 /* GetISTR */
Sergunb 0:f1834a63f7c1 212 #define _GetISTR() ((uint16_t) *ISTR)
Sergunb 0:f1834a63f7c1 213
Sergunb 0:f1834a63f7c1 214 /* GetFNR */
Sergunb 0:f1834a63f7c1 215 #define _GetFNR() ((uint16_t) *FNR)
Sergunb 0:f1834a63f7c1 216
Sergunb 0:f1834a63f7c1 217 /* GetDADDR */
Sergunb 0:f1834a63f7c1 218 #define _GetDADDR() ((uint16_t) *DADDR)
Sergunb 0:f1834a63f7c1 219
Sergunb 0:f1834a63f7c1 220 /* GetBTABLE */
Sergunb 0:f1834a63f7c1 221 #define _GetBTABLE() ((uint16_t) *BTABLE)
Sergunb 0:f1834a63f7c1 222
Sergunb 0:f1834a63f7c1 223 /* SetENDPOINT */
Sergunb 0:f1834a63f7c1 224 #define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \
Sergunb 0:f1834a63f7c1 225 (uint16_t)wRegValue)
Sergunb 0:f1834a63f7c1 226
Sergunb 0:f1834a63f7c1 227 /* GetENDPOINT */
Sergunb 0:f1834a63f7c1 228 #define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
Sergunb 0:f1834a63f7c1 229
Sergunb 0:f1834a63f7c1 230 /*******************************************************************************
Sergunb 0:f1834a63f7c1 231 * Macro Name : SetEPType
Sergunb 0:f1834a63f7c1 232 * Description : sets the type in the endpoint register(bits EP_TYPE[1:0])
Sergunb 0:f1834a63f7c1 233 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 234 * wType
Sergunb 0:f1834a63f7c1 235 * Output : None.
Sergunb 0:f1834a63f7c1 236 * Return : None.
Sergunb 0:f1834a63f7c1 237 *******************************************************************************/
Sergunb 0:f1834a63f7c1 238 #define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\
Sergunb 0:f1834a63f7c1 239 ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType )))
Sergunb 0:f1834a63f7c1 240
Sergunb 0:f1834a63f7c1 241 /*******************************************************************************
Sergunb 0:f1834a63f7c1 242 * Macro Name : GetEPType
Sergunb 0:f1834a63f7c1 243 * Description : gets the type in the endpoint register(bits EP_TYPE[1:0])
Sergunb 0:f1834a63f7c1 244 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 245 * Output : None.
Sergunb 0:f1834a63f7c1 246 * Return : Endpoint Type
Sergunb 0:f1834a63f7c1 247 *******************************************************************************/
Sergunb 0:f1834a63f7c1 248 #define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
Sergunb 0:f1834a63f7c1 249
Sergunb 0:f1834a63f7c1 250 /*******************************************************************************
Sergunb 0:f1834a63f7c1 251 * Macro Name : SetEPTxStatus
Sergunb 0:f1834a63f7c1 252 * Description : sets the status for tx transfer (bits STAT_TX[1:0]).
Sergunb 0:f1834a63f7c1 253 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 254 * wState: new state
Sergunb 0:f1834a63f7c1 255 * Output : None.
Sergunb 0:f1834a63f7c1 256 * Return : None.
Sergunb 0:f1834a63f7c1 257 *******************************************************************************/
Sergunb 0:f1834a63f7c1 258 #define _SetEPTxStatus(bEpNum,wState) {\
Sergunb 0:f1834a63f7c1 259 register uint16_t _wRegVal; \
Sergunb 0:f1834a63f7c1 260 _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\
Sergunb 0:f1834a63f7c1 261 /* toggle first bit ? */ \
Sergunb 0:f1834a63f7c1 262 if((EPTX_DTOG1 & wState)!= 0) \
Sergunb 0:f1834a63f7c1 263 _wRegVal ^= EPTX_DTOG1; \
Sergunb 0:f1834a63f7c1 264 /* toggle second bit ? */ \
Sergunb 0:f1834a63f7c1 265 if((EPTX_DTOG2 & wState)!= 0) \
Sergunb 0:f1834a63f7c1 266 _wRegVal ^= EPTX_DTOG2; \
Sergunb 0:f1834a63f7c1 267 _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \
Sergunb 0:f1834a63f7c1 268 } /* _SetEPTxStatus */
Sergunb 0:f1834a63f7c1 269
Sergunb 0:f1834a63f7c1 270 /*******************************************************************************
Sergunb 0:f1834a63f7c1 271 * Macro Name : SetEPRxStatus
Sergunb 0:f1834a63f7c1 272 * Description : sets the status for rx transfer (bits STAT_TX[1:0])
Sergunb 0:f1834a63f7c1 273 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 274 * wState: new state.
Sergunb 0:f1834a63f7c1 275 * Output : None.
Sergunb 0:f1834a63f7c1 276 * Return : None.
Sergunb 0:f1834a63f7c1 277 *******************************************************************************/
Sergunb 0:f1834a63f7c1 278 #define _SetEPRxStatus(bEpNum,wState) {\
Sergunb 0:f1834a63f7c1 279 register uint16_t _wRegVal; \
Sergunb 0:f1834a63f7c1 280 \
Sergunb 0:f1834a63f7c1 281 _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\
Sergunb 0:f1834a63f7c1 282 /* toggle first bit ? */ \
Sergunb 0:f1834a63f7c1 283 if((EPRX_DTOG1 & wState)!= 0) \
Sergunb 0:f1834a63f7c1 284 _wRegVal ^= EPRX_DTOG1; \
Sergunb 0:f1834a63f7c1 285 /* toggle second bit ? */ \
Sergunb 0:f1834a63f7c1 286 if((EPRX_DTOG2 & wState)!= 0) \
Sergunb 0:f1834a63f7c1 287 _wRegVal ^= EPRX_DTOG2; \
Sergunb 0:f1834a63f7c1 288 _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \
Sergunb 0:f1834a63f7c1 289 } /* _SetEPRxStatus */
Sergunb 0:f1834a63f7c1 290
Sergunb 0:f1834a63f7c1 291 /*******************************************************************************
Sergunb 0:f1834a63f7c1 292 * Macro Name : SetEPRxTxStatus
Sergunb 0:f1834a63f7c1 293 * Description : sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
Sergunb 0:f1834a63f7c1 294 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 295 * wStaterx: new state.
Sergunb 0:f1834a63f7c1 296 * wStatetx: new state.
Sergunb 0:f1834a63f7c1 297 * Output : None.
Sergunb 0:f1834a63f7c1 298 * Return : None.
Sergunb 0:f1834a63f7c1 299 *******************************************************************************/
Sergunb 0:f1834a63f7c1 300 #define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\
Sergunb 0:f1834a63f7c1 301 register uint32_t _wRegVal; \
Sergunb 0:f1834a63f7c1 302 \
Sergunb 0:f1834a63f7c1 303 _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EPTX_STAT) ;\
Sergunb 0:f1834a63f7c1 304 /* toggle first bit ? */ \
Sergunb 0:f1834a63f7c1 305 if((EPRX_DTOG1 & wStaterx)!= 0) \
Sergunb 0:f1834a63f7c1 306 _wRegVal ^= EPRX_DTOG1; \
Sergunb 0:f1834a63f7c1 307 /* toggle second bit ? */ \
Sergunb 0:f1834a63f7c1 308 if((EPRX_DTOG2 & wStaterx)!= 0) \
Sergunb 0:f1834a63f7c1 309 _wRegVal ^= EPRX_DTOG2; \
Sergunb 0:f1834a63f7c1 310 /* toggle first bit ? */ \
Sergunb 0:f1834a63f7c1 311 if((EPTX_DTOG1 & wStatetx)!= 0) \
Sergunb 0:f1834a63f7c1 312 _wRegVal ^= EPTX_DTOG1; \
Sergunb 0:f1834a63f7c1 313 /* toggle second bit ? */ \
Sergunb 0:f1834a63f7c1 314 if((EPTX_DTOG2 & wStatetx)!= 0) \
Sergunb 0:f1834a63f7c1 315 _wRegVal ^= EPTX_DTOG2; \
Sergunb 0:f1834a63f7c1 316 _SetENDPOINT(bEpNum, _wRegVal | EP_CTR_RX|EP_CTR_TX); \
Sergunb 0:f1834a63f7c1 317 } /* _SetEPRxTxStatus */
Sergunb 0:f1834a63f7c1 318 /*******************************************************************************
Sergunb 0:f1834a63f7c1 319 * Macro Name : GetEPTxStatus / GetEPRxStatus
Sergunb 0:f1834a63f7c1 320 * Description : gets the status for tx/rx transfer (bits STAT_TX[1:0]
Sergunb 0:f1834a63f7c1 321 * /STAT_RX[1:0])
Sergunb 0:f1834a63f7c1 322 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 323 * Output : None.
Sergunb 0:f1834a63f7c1 324 * Return : status .
Sergunb 0:f1834a63f7c1 325 *******************************************************************************/
Sergunb 0:f1834a63f7c1 326 #define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STAT)
Sergunb 0:f1834a63f7c1 327
Sergunb 0:f1834a63f7c1 328 #define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STAT)
Sergunb 0:f1834a63f7c1 329
Sergunb 0:f1834a63f7c1 330 /*******************************************************************************
Sergunb 0:f1834a63f7c1 331 * Macro Name : SetEPTxValid / SetEPRxValid
Sergunb 0:f1834a63f7c1 332 * Description : sets directly the VALID tx/rx-status into the enpoint register
Sergunb 0:f1834a63f7c1 333 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 334 * Output : None.
Sergunb 0:f1834a63f7c1 335 * Return : None.
Sergunb 0:f1834a63f7c1 336 *******************************************************************************/
Sergunb 0:f1834a63f7c1 337 #define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
Sergunb 0:f1834a63f7c1 338
Sergunb 0:f1834a63f7c1 339 #define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
Sergunb 0:f1834a63f7c1 340
Sergunb 0:f1834a63f7c1 341 /*******************************************************************************
Sergunb 0:f1834a63f7c1 342 * Macro Name : GetTxStallStatus / GetRxStallStatus.
Sergunb 0:f1834a63f7c1 343 * Description : checks stall condition in an endpoint.
Sergunb 0:f1834a63f7c1 344 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 345 * Output : None.
Sergunb 0:f1834a63f7c1 346 * Return : TRUE = endpoint in stall condition.
Sergunb 0:f1834a63f7c1 347 *******************************************************************************/
Sergunb 0:f1834a63f7c1 348 #define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \
Sergunb 0:f1834a63f7c1 349 == EP_TX_STALL)
Sergunb 0:f1834a63f7c1 350 #define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \
Sergunb 0:f1834a63f7c1 351 == EP_RX_STALL)
Sergunb 0:f1834a63f7c1 352
Sergunb 0:f1834a63f7c1 353 /*******************************************************************************
Sergunb 0:f1834a63f7c1 354 * Macro Name : SetEP_KIND / ClearEP_KIND.
Sergunb 0:f1834a63f7c1 355 * Description : set & clear EP_KIND bit.
Sergunb 0:f1834a63f7c1 356 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 357 * Output : None.
Sergunb 0:f1834a63f7c1 358 * Return : None.
Sergunb 0:f1834a63f7c1 359 *******************************************************************************/
Sergunb 0:f1834a63f7c1 360 #define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \
Sergunb 0:f1834a63f7c1 361 (EP_CTR_RX|EP_CTR_TX|((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
Sergunb 0:f1834a63f7c1 362 #define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \
Sergunb 0:f1834a63f7c1 363 (EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK))))
Sergunb 0:f1834a63f7c1 364
Sergunb 0:f1834a63f7c1 365 /*******************************************************************************
Sergunb 0:f1834a63f7c1 366 * Macro Name : Set_Status_Out / Clear_Status_Out.
Sergunb 0:f1834a63f7c1 367 * Description : Sets/clears directly STATUS_OUT bit in the endpoint register.
Sergunb 0:f1834a63f7c1 368 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 369 * Output : None.
Sergunb 0:f1834a63f7c1 370 * Return : None.
Sergunb 0:f1834a63f7c1 371 *******************************************************************************/
Sergunb 0:f1834a63f7c1 372 #define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum)
Sergunb 0:f1834a63f7c1 373 #define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum)
Sergunb 0:f1834a63f7c1 374
Sergunb 0:f1834a63f7c1 375 /*******************************************************************************
Sergunb 0:f1834a63f7c1 376 * Macro Name : SetEPDoubleBuff / ClearEPDoubleBuff.
Sergunb 0:f1834a63f7c1 377 * Description : Sets/clears directly EP_KIND bit in the endpoint register.
Sergunb 0:f1834a63f7c1 378 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 379 * Output : None.
Sergunb 0:f1834a63f7c1 380 * Return : None.
Sergunb 0:f1834a63f7c1 381 *******************************************************************************/
Sergunb 0:f1834a63f7c1 382 #define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum)
Sergunb 0:f1834a63f7c1 383 #define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
Sergunb 0:f1834a63f7c1 384
Sergunb 0:f1834a63f7c1 385 /*******************************************************************************
Sergunb 0:f1834a63f7c1 386 * Macro Name : ClearEP_CTR_RX / ClearEP_CTR_TX.
Sergunb 0:f1834a63f7c1 387 * Description : Clears bit CTR_RX / CTR_TX in the endpoint register.
Sergunb 0:f1834a63f7c1 388 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 389 * Output : None.
Sergunb 0:f1834a63f7c1 390 * Return : None.
Sergunb 0:f1834a63f7c1 391 *******************************************************************************/
Sergunb 0:f1834a63f7c1 392 #define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\
Sergunb 0:f1834a63f7c1 393 _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
Sergunb 0:f1834a63f7c1 394 #define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\
Sergunb 0:f1834a63f7c1 395 _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
Sergunb 0:f1834a63f7c1 396
Sergunb 0:f1834a63f7c1 397 /*******************************************************************************
Sergunb 0:f1834a63f7c1 398 * Macro Name : ToggleDTOG_RX / ToggleDTOG_TX .
Sergunb 0:f1834a63f7c1 399 * Description : Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
Sergunb 0:f1834a63f7c1 400 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 401 * Output : None.
Sergunb 0:f1834a63f7c1 402 * Return : None.
Sergunb 0:f1834a63f7c1 403 *******************************************************************************/
Sergunb 0:f1834a63f7c1 404 #define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \
Sergunb 0:f1834a63f7c1 405 EP_CTR_RX|EP_CTR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
Sergunb 0:f1834a63f7c1 406 #define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \
Sergunb 0:f1834a63f7c1 407 EP_CTR_RX|EP_CTR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
Sergunb 0:f1834a63f7c1 408
Sergunb 0:f1834a63f7c1 409 /*******************************************************************************
Sergunb 0:f1834a63f7c1 410 * Macro Name : ClearDTOG_RX / ClearDTOG_TX.
Sergunb 0:f1834a63f7c1 411 * Description : Clears DTOG_RX / DTOG_TX bit in the endpoint register.
Sergunb 0:f1834a63f7c1 412 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 413 * Output : None.
Sergunb 0:f1834a63f7c1 414 * Return : None.
Sergunb 0:f1834a63f7c1 415 *******************************************************************************/
Sergunb 0:f1834a63f7c1 416 #define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\
Sergunb 0:f1834a63f7c1 417 _ToggleDTOG_RX(bEpNum)
Sergunb 0:f1834a63f7c1 418 #define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\
Sergunb 0:f1834a63f7c1 419 _ToggleDTOG_TX(bEpNum)
Sergunb 0:f1834a63f7c1 420 /*******************************************************************************
Sergunb 0:f1834a63f7c1 421 * Macro Name : SetEPAddress.
Sergunb 0:f1834a63f7c1 422 * Description : Sets address in an endpoint register.
Sergunb 0:f1834a63f7c1 423 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 424 * bAddr: Address.
Sergunb 0:f1834a63f7c1 425 * Output : None.
Sergunb 0:f1834a63f7c1 426 * Return : None.
Sergunb 0:f1834a63f7c1 427 *******************************************************************************/
Sergunb 0:f1834a63f7c1 428 #define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\
Sergunb 0:f1834a63f7c1 429 EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
Sergunb 0:f1834a63f7c1 430
Sergunb 0:f1834a63f7c1 431 /*******************************************************************************
Sergunb 0:f1834a63f7c1 432 * Macro Name : GetEPAddress.
Sergunb 0:f1834a63f7c1 433 * Description : Gets address in an endpoint register.
Sergunb 0:f1834a63f7c1 434 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 435 * Output : None.
Sergunb 0:f1834a63f7c1 436 * Return : None.
Sergunb 0:f1834a63f7c1 437 *******************************************************************************/
Sergunb 0:f1834a63f7c1 438 #define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
Sergunb 0:f1834a63f7c1 439
Sergunb 0:f1834a63f7c1 440 #define _pEPTxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8 )*2 + PMAAddr))
Sergunb 0:f1834a63f7c1 441 #define _pEPTxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+2)*2 + PMAAddr))
Sergunb 0:f1834a63f7c1 442 #define _pEPRxAddr(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+4)*2 + PMAAddr))
Sergunb 0:f1834a63f7c1 443 #define _pEPRxCount(bEpNum) ((uint32_t *)((_GetBTABLE()+bEpNum*8+6)*2 + PMAAddr))
Sergunb 0:f1834a63f7c1 444
Sergunb 0:f1834a63f7c1 445 /*******************************************************************************
Sergunb 0:f1834a63f7c1 446 * Macro Name : SetEPTxAddr / SetEPRxAddr.
Sergunb 0:f1834a63f7c1 447 * Description : sets address of the tx/rx buffer.
Sergunb 0:f1834a63f7c1 448 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 449 * wAddr: address to be set (must be word aligned).
Sergunb 0:f1834a63f7c1 450 * Output : None.
Sergunb 0:f1834a63f7c1 451 * Return : None.
Sergunb 0:f1834a63f7c1 452 *******************************************************************************/
Sergunb 0:f1834a63f7c1 453 #define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
Sergunb 0:f1834a63f7c1 454 #define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
Sergunb 0:f1834a63f7c1 455
Sergunb 0:f1834a63f7c1 456 /*******************************************************************************
Sergunb 0:f1834a63f7c1 457 * Macro Name : GetEPTxAddr / GetEPRxAddr.
Sergunb 0:f1834a63f7c1 458 * Description : Gets address of the tx/rx buffer.
Sergunb 0:f1834a63f7c1 459 * Input : bEpNum: Endpoint Number.
Sergunb 0:f1834a63f7c1 460 * Output : None.
Sergunb 0:f1834a63f7c1 461 * Return : address of the buffer.
Sergunb 0:f1834a63f7c1 462 *******************************************************************************/
Sergunb 0:f1834a63f7c1 463 #define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
Sergunb 0:f1834a63f7c1 464 #define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
Sergunb 0:f1834a63f7c1 465
Sergunb 0:f1834a63f7c1 466 /*******************************************************************************
Sergunb 0:f1834a63f7c1 467 * Macro Name : SetEPCountRxReg.
Sergunb 0:f1834a63f7c1 468 * Description : Sets counter of rx buffer with no. of blocks.
Sergunb 0:f1834a63f7c1 469 * Input : pdwReg: pointer to counter.
Sergunb 0:f1834a63f7c1 470 * wCount: Counter.
Sergunb 0:f1834a63f7c1 471 * Output : None.
Sergunb 0:f1834a63f7c1 472 * Return : None.
Sergunb 0:f1834a63f7c1 473 *******************************************************************************/
Sergunb 0:f1834a63f7c1 474 #define _BlocksOf32(dwReg,wCount,wNBlocks) {\
Sergunb 0:f1834a63f7c1 475 wNBlocks = wCount >> 5;\
Sergunb 0:f1834a63f7c1 476 if((wCount & 0x1f) == 0)\
Sergunb 0:f1834a63f7c1 477 wNBlocks--;\
Sergunb 0:f1834a63f7c1 478 *pdwReg = (uint32_t)((wNBlocks << 10) | 0x8000);\
Sergunb 0:f1834a63f7c1 479 }/* _BlocksOf32 */
Sergunb 0:f1834a63f7c1 480
Sergunb 0:f1834a63f7c1 481 #define _BlocksOf2(dwReg,wCount,wNBlocks) {\
Sergunb 0:f1834a63f7c1 482 wNBlocks = wCount >> 1;\
Sergunb 0:f1834a63f7c1 483 if((wCount & 0x1) != 0)\
Sergunb 0:f1834a63f7c1 484 wNBlocks++;\
Sergunb 0:f1834a63f7c1 485 *pdwReg = (uint32_t)(wNBlocks << 10);\
Sergunb 0:f1834a63f7c1 486 }/* _BlocksOf2 */
Sergunb 0:f1834a63f7c1 487
Sergunb 0:f1834a63f7c1 488 #define _SetEPCountRxReg(dwReg,wCount) {\
Sergunb 0:f1834a63f7c1 489 uint16_t wNBlocks;\
Sergunb 0:f1834a63f7c1 490 if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\
Sergunb 0:f1834a63f7c1 491 else {_BlocksOf2(dwReg,wCount,wNBlocks);}\
Sergunb 0:f1834a63f7c1 492 }/* _SetEPCountRxReg */
Sergunb 0:f1834a63f7c1 493
Sergunb 0:f1834a63f7c1 494
Sergunb 0:f1834a63f7c1 495
Sergunb 0:f1834a63f7c1 496 #define _SetEPRxDblBuf0Count(bEpNum,wCount) {\
Sergunb 0:f1834a63f7c1 497 uint32_t *pdwReg = _pEPTxCount(bEpNum); \
Sergunb 0:f1834a63f7c1 498 _SetEPCountRxReg(pdwReg, wCount);\
Sergunb 0:f1834a63f7c1 499 }
Sergunb 0:f1834a63f7c1 500 /*******************************************************************************
Sergunb 0:f1834a63f7c1 501 * Macro Name : SetEPTxCount / SetEPRxCount.
Sergunb 0:f1834a63f7c1 502 * Description : sets counter for the tx/rx buffer.
Sergunb 0:f1834a63f7c1 503 * Input : bEpNum: endpoint number.
Sergunb 0:f1834a63f7c1 504 * wCount: Counter value.
Sergunb 0:f1834a63f7c1 505 * Output : None.
Sergunb 0:f1834a63f7c1 506 * Return : None.
Sergunb 0:f1834a63f7c1 507 *******************************************************************************/
Sergunb 0:f1834a63f7c1 508 #define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount)
Sergunb 0:f1834a63f7c1 509 #define _SetEPRxCount(bEpNum,wCount) {\
Sergunb 0:f1834a63f7c1 510 uint32_t *pdwReg = _pEPRxCount(bEpNum); \
Sergunb 0:f1834a63f7c1 511 _SetEPCountRxReg(pdwReg, wCount);\
Sergunb 0:f1834a63f7c1 512 }
Sergunb 0:f1834a63f7c1 513 /*******************************************************************************
Sergunb 0:f1834a63f7c1 514 * Macro Name : GetEPTxCount / GetEPRxCount.
Sergunb 0:f1834a63f7c1 515 * Description : gets counter of the tx buffer.
Sergunb 0:f1834a63f7c1 516 * Input : bEpNum: endpoint number.
Sergunb 0:f1834a63f7c1 517 * Output : None.
Sergunb 0:f1834a63f7c1 518 * Return : Counter value.
Sergunb 0:f1834a63f7c1 519 *******************************************************************************/
Sergunb 0:f1834a63f7c1 520 #define _GetEPTxCount(bEpNum)((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
Sergunb 0:f1834a63f7c1 521 #define _GetEPRxCount(bEpNum)((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
Sergunb 0:f1834a63f7c1 522
Sergunb 0:f1834a63f7c1 523 /*******************************************************************************
Sergunb 0:f1834a63f7c1 524 * Macro Name : SetEPDblBuf0Addr / SetEPDblBuf1Addr.
Sergunb 0:f1834a63f7c1 525 * Description : Sets buffer 0/1 address in a double buffer endpoint.
Sergunb 0:f1834a63f7c1 526 * Input : bEpNum: endpoint number.
Sergunb 0:f1834a63f7c1 527 * : wBuf0Addr: buffer 0 address.
Sergunb 0:f1834a63f7c1 528 * Output : None.
Sergunb 0:f1834a63f7c1 529 * Return : None.
Sergunb 0:f1834a63f7c1 530 *******************************************************************************/
Sergunb 0:f1834a63f7c1 531 #define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);}
Sergunb 0:f1834a63f7c1 532 #define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);}
Sergunb 0:f1834a63f7c1 533
Sergunb 0:f1834a63f7c1 534 /*******************************************************************************
Sergunb 0:f1834a63f7c1 535 * Macro Name : SetEPDblBuffAddr.
Sergunb 0:f1834a63f7c1 536 * Description : Sets addresses in a double buffer endpoint.
Sergunb 0:f1834a63f7c1 537 * Input : bEpNum: endpoint number.
Sergunb 0:f1834a63f7c1 538 * : wBuf0Addr: buffer 0 address.
Sergunb 0:f1834a63f7c1 539 * : wBuf1Addr = buffer 1 address.
Sergunb 0:f1834a63f7c1 540 * Output : None.
Sergunb 0:f1834a63f7c1 541 * Return : None.
Sergunb 0:f1834a63f7c1 542 *******************************************************************************/
Sergunb 0:f1834a63f7c1 543 #define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \
Sergunb 0:f1834a63f7c1 544 _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\
Sergunb 0:f1834a63f7c1 545 _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\
Sergunb 0:f1834a63f7c1 546 } /* _SetEPDblBuffAddr */
Sergunb 0:f1834a63f7c1 547
Sergunb 0:f1834a63f7c1 548 /*******************************************************************************
Sergunb 0:f1834a63f7c1 549 * Macro Name : GetEPDblBuf0Addr / GetEPDblBuf1Addr.
Sergunb 0:f1834a63f7c1 550 * Description : Gets buffer 0/1 address of a double buffer endpoint.
Sergunb 0:f1834a63f7c1 551 * Input : bEpNum: endpoint number.
Sergunb 0:f1834a63f7c1 552 * Output : None.
Sergunb 0:f1834a63f7c1 553 * Return : None.
Sergunb 0:f1834a63f7c1 554 *******************************************************************************/
Sergunb 0:f1834a63f7c1 555 #define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
Sergunb 0:f1834a63f7c1 556 #define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
Sergunb 0:f1834a63f7c1 557
Sergunb 0:f1834a63f7c1 558 /*******************************************************************************
Sergunb 0:f1834a63f7c1 559 * Macro Name : SetEPDblBuffCount / SetEPDblBuf0Count / SetEPDblBuf1Count.
Sergunb 0:f1834a63f7c1 560 * Description : Gets buffer 0/1 address of a double buffer endpoint.
Sergunb 0:f1834a63f7c1 561 * Input : bEpNum: endpoint number.
Sergunb 0:f1834a63f7c1 562 * : bDir: endpoint dir EP_DBUF_OUT = OUT
Sergunb 0:f1834a63f7c1 563 * EP_DBUF_IN = IN
Sergunb 0:f1834a63f7c1 564 * : wCount: Counter value
Sergunb 0:f1834a63f7c1 565 * Output : None.
Sergunb 0:f1834a63f7c1 566 * Return : None.
Sergunb 0:f1834a63f7c1 567 *******************************************************************************/
Sergunb 0:f1834a63f7c1 568 #define _SetEPDblBuf0Count(bEpNum, bDir, wCount) { \
Sergunb 0:f1834a63f7c1 569 if(bDir == EP_DBUF_OUT)\
Sergunb 0:f1834a63f7c1 570 /* OUT endpoint */ \
Sergunb 0:f1834a63f7c1 571 {_SetEPRxDblBuf0Count(bEpNum,wCount);} \
Sergunb 0:f1834a63f7c1 572 else if(bDir == EP_DBUF_IN)\
Sergunb 0:f1834a63f7c1 573 /* IN endpoint */ \
Sergunb 0:f1834a63f7c1 574 *_pEPTxCount(bEpNum) = (uint32_t)wCount; \
Sergunb 0:f1834a63f7c1 575 } /* SetEPDblBuf0Count*/
Sergunb 0:f1834a63f7c1 576
Sergunb 0:f1834a63f7c1 577 #define _SetEPDblBuf1Count(bEpNum, bDir, wCount) { \
Sergunb 0:f1834a63f7c1 578 if(bDir == EP_DBUF_OUT)\
Sergunb 0:f1834a63f7c1 579 /* OUT endpoint */ \
Sergunb 0:f1834a63f7c1 580 {_SetEPRxCount(bEpNum,wCount);}\
Sergunb 0:f1834a63f7c1 581 else if(bDir == EP_DBUF_IN)\
Sergunb 0:f1834a63f7c1 582 /* IN endpoint */\
Sergunb 0:f1834a63f7c1 583 *_pEPRxCount(bEpNum) = (uint32_t)wCount; \
Sergunb 0:f1834a63f7c1 584 } /* SetEPDblBuf1Count */
Sergunb 0:f1834a63f7c1 585
Sergunb 0:f1834a63f7c1 586 #define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\
Sergunb 0:f1834a63f7c1 587 _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
Sergunb 0:f1834a63f7c1 588 _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
Sergunb 0:f1834a63f7c1 589 } /* _SetEPDblBuffCount */
Sergunb 0:f1834a63f7c1 590
Sergunb 0:f1834a63f7c1 591 /*******************************************************************************
Sergunb 0:f1834a63f7c1 592 * Macro Name : GetEPDblBuf0Count / GetEPDblBuf1Count.
Sergunb 0:f1834a63f7c1 593 * Description : Gets buffer 0/1 rx/tx counter for double buffering.
Sergunb 0:f1834a63f7c1 594 * Input : bEpNum: endpoint number.
Sergunb 0:f1834a63f7c1 595 * Output : None.
Sergunb 0:f1834a63f7c1 596 * Return : None.
Sergunb 0:f1834a63f7c1 597 *******************************************************************************/
Sergunb 0:f1834a63f7c1 598 #define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
Sergunb 0:f1834a63f7c1 599 #define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
Sergunb 0:f1834a63f7c1 600
Sergunb 0:f1834a63f7c1 601
Sergunb 0:f1834a63f7c1 602 /* External variables --------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 603 extern __IO uint16_t wIstr; /* ISTR register last read value */
Sergunb 0:f1834a63f7c1 604
Sergunb 0:f1834a63f7c1 605 /* Exported functions ------------------------------------------------------- */
Sergunb 0:f1834a63f7c1 606 void SetCNTR(uint16_t /*wRegValue*/);
Sergunb 0:f1834a63f7c1 607 void SetISTR(uint16_t /*wRegValue*/);
Sergunb 0:f1834a63f7c1 608 void SetDADDR(uint16_t /*wRegValue*/);
Sergunb 0:f1834a63f7c1 609 void SetBTABLE(uint16_t /*wRegValue*/);
Sergunb 0:f1834a63f7c1 610 void SetBTABLE(uint16_t /*wRegValue*/);
Sergunb 0:f1834a63f7c1 611 uint16_t GetCNTR(void);
Sergunb 0:f1834a63f7c1 612 uint16_t GetISTR(void);
Sergunb 0:f1834a63f7c1 613 uint16_t GetFNR(void);
Sergunb 0:f1834a63f7c1 614 uint16_t GetDADDR(void);
Sergunb 0:f1834a63f7c1 615 uint16_t GetBTABLE(void);
Sergunb 0:f1834a63f7c1 616 void SetENDPOINT(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
Sergunb 0:f1834a63f7c1 617 uint16_t GetENDPOINT(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 618 void SetEPType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
Sergunb 0:f1834a63f7c1 619 uint16_t GetEPType(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 620 void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
Sergunb 0:f1834a63f7c1 621 void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
Sergunb 0:f1834a63f7c1 622 void SetDouBleBuffEPStall(uint8_t /*bEpNum*/, uint8_t bDir);
Sergunb 0:f1834a63f7c1 623 uint16_t GetEPTxStatus(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 624 uint16_t GetEPRxStatus(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 625 void SetEPTxValid(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 626 void SetEPRxValid(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 627 uint16_t GetTxStallStatus(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 628 uint16_t GetRxStallStatus(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 629 void SetEP_KIND(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 630 void ClearEP_KIND(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 631 void Set_Status_Out(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 632 void Clear_Status_Out(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 633 void SetEPDoubleBuff(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 634 void ClearEPDoubleBuff(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 635 void ClearEP_CTR_RX(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 636 void ClearEP_CTR_TX(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 637 void ToggleDTOG_RX(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 638 void ToggleDTOG_TX(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 639 void ClearDTOG_RX(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 640 void ClearDTOG_TX(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 641 void SetEPAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
Sergunb 0:f1834a63f7c1 642 uint8_t GetEPAddress(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 643 void SetEPTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
Sergunb 0:f1834a63f7c1 644 void SetEPRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
Sergunb 0:f1834a63f7c1 645 uint16_t GetEPTxAddr(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 646 uint16_t GetEPRxAddr(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 647 void SetEPCountRxReg(uint32_t * /*pdwReg*/, uint16_t /*wCount*/);
Sergunb 0:f1834a63f7c1 648 void SetEPTxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
Sergunb 0:f1834a63f7c1 649 void SetEPRxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
Sergunb 0:f1834a63f7c1 650 uint16_t GetEPTxCount(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 651 uint16_t GetEPRxCount(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 652 void SetEPDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
Sergunb 0:f1834a63f7c1 653 void SetEPDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
Sergunb 0:f1834a63f7c1 654 void SetEPDblBuffAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
Sergunb 0:f1834a63f7c1 655 uint16_t GetEPDblBuf0Addr(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 656 uint16_t GetEPDblBuf1Addr(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 657 void SetEPDblBuffCount(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
Sergunb 0:f1834a63f7c1 658 void SetEPDblBuf0Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
Sergunb 0:f1834a63f7c1 659 void SetEPDblBuf1Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
Sergunb 0:f1834a63f7c1 660 uint16_t GetEPDblBuf0Count(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 661 uint16_t GetEPDblBuf1Count(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 662 EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
Sergunb 0:f1834a63f7c1 663 void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir);
Sergunb 0:f1834a63f7c1 664 uint16_t ToWord(uint8_t, uint8_t);
Sergunb 0:f1834a63f7c1 665 uint16_t ByteSwap(uint16_t);
Sergunb 0:f1834a63f7c1 666
Sergunb 0:f1834a63f7c1 667 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 668
Sergunb 0:f1834a63f7c1 669 #endif /* __USB_REGS_H */
Sergunb 0:f1834a63f7c1 670
Sergunb 0:f1834a63f7c1 671 /******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/