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/**
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******************************************************************************
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* @file stm32f10x_tim.c
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* @author MCD Application Team
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* @version V3.5.0
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* @date 11-March-2011
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* @brief This file provides all the TIM firmware functions.
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******************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x_tim.h"
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#include "stm32f10x_rcc.h"
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/** @addtogroup STM32F10x_StdPeriph_Driver
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* @{
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*/
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/** @defgroup TIM
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* @brief TIM driver modules
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* @{
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*/
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/** @defgroup TIM_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Defines
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* @{
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*/
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/* ---------------------- TIM registers bit mask ------------------------ */
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#define SMCR_ETR_Mask ((uint16_t)0x00FF)
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#define CCMR_Offset ((uint16_t)0x0018)
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#define CCER_CCE_Set ((uint16_t)0x0001)
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#define CCER_CCNE_Set ((uint16_t)0x0004)
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_FunctionPrototypes
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* @{
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*/
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static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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uint16_t TIM_ICFilter);
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static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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uint16_t TIM_ICFilter);
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static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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uint16_t TIM_ICFilter);
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static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
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uint16_t TIM_ICFilter);
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Variables
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup TIM_Private_Functions
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* @{
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*/
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/**
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* @brief Deinitializes the TIMx peripheral registers to their default reset values.
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* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
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* @retval None
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*/
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void TIM_DeInit(TIM_TypeDef* TIMx)
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{
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/* Check the parameters */
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assert_param(IS_TIM_ALL_PERIPH(TIMx));
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if (TIMx == TIM1)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
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}
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else if (TIMx == TIM2)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
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}
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else if (TIMx == TIM3)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
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}
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else if (TIMx == TIM4)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
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}
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else if (TIMx == TIM5)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
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}
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else if (TIMx == TIM6)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
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}
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else if (TIMx == TIM7)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
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}
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else if (TIMx == TIM8)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);
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}
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else if (TIMx == TIM9)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);
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}
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else if (TIMx == TIM10)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);
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}
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else if (TIMx == TIM11)
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{
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);
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}
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else if (TIMx == TIM12)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);
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}
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else if (TIMx == TIM13)
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{
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);
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|
191
|
}
|
| Sergunb |
0:f1834a63f7c1
|
192
|
else if (TIMx == TIM14)
|
| Sergunb |
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|
193
|
{
|
| Sergunb |
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|
194
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
|
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195
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
|
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|
196
|
}
|
| Sergunb |
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|
197
|
else if (TIMx == TIM15)
|
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198
|
{
|
| Sergunb |
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199
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
|
| Sergunb |
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|
200
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
|
| Sergunb |
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|
201
|
}
|
| Sergunb |
0:f1834a63f7c1
|
202
|
else if (TIMx == TIM16)
|
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|
203
|
{
|
| Sergunb |
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|
204
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
|
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205
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
|
| Sergunb |
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|
206
|
}
|
| Sergunb |
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|
207
|
else
|
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|
208
|
{
|
| Sergunb |
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|
209
|
if (TIMx == TIM17)
|
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|
210
|
{
|
| Sergunb |
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|
211
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
|
| Sergunb |
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|
212
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
|
| Sergunb |
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|
213
|
}
|
| Sergunb |
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|
214
|
}
|
| Sergunb |
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|
215
|
}
|
| Sergunb |
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|
216
|
|
| Sergunb |
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|
217
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
218
|
* @brief Initializes the TIMx Time Base Unit peripheral according to
|
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0:f1834a63f7c1
|
219
|
* the specified parameters in the TIM_TimeBaseInitStruct.
|
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|
220
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
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|
221
|
* @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
|
| Sergunb |
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|
222
|
* structure that contains the configuration information for the
|
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0:f1834a63f7c1
|
223
|
* specified TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
224
|
* @retval None
|
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0:f1834a63f7c1
|
225
|
*/
|
| Sergunb |
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|
226
|
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
227
|
{
|
| Sergunb |
0:f1834a63f7c1
|
228
|
uint16_t tmpcr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
229
|
|
| Sergunb |
0:f1834a63f7c1
|
230
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
231
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
232
|
assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
|
| Sergunb |
0:f1834a63f7c1
|
233
|
assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
|
| Sergunb |
0:f1834a63f7c1
|
234
|
|
| Sergunb |
0:f1834a63f7c1
|
235
|
tmpcr1 = TIMx->CR1;
|
| Sergunb |
0:f1834a63f7c1
|
236
|
|
| Sergunb |
0:f1834a63f7c1
|
237
|
if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM2) || (TIMx == TIM3)||
|
| Sergunb |
0:f1834a63f7c1
|
238
|
(TIMx == TIM4) || (TIMx == TIM5))
|
| Sergunb |
0:f1834a63f7c1
|
239
|
{
|
| Sergunb |
0:f1834a63f7c1
|
240
|
/* Select the Counter Mode */
|
| Sergunb |
0:f1834a63f7c1
|
241
|
tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
|
| Sergunb |
0:f1834a63f7c1
|
242
|
tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
|
| Sergunb |
0:f1834a63f7c1
|
243
|
}
|
| Sergunb |
0:f1834a63f7c1
|
244
|
|
| Sergunb |
0:f1834a63f7c1
|
245
|
if((TIMx != TIM6) && (TIMx != TIM7))
|
| Sergunb |
0:f1834a63f7c1
|
246
|
{
|
| Sergunb |
0:f1834a63f7c1
|
247
|
/* Set the clock division */
|
| Sergunb |
0:f1834a63f7c1
|
248
|
tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
|
| Sergunb |
0:f1834a63f7c1
|
249
|
tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
|
| Sergunb |
0:f1834a63f7c1
|
250
|
}
|
| Sergunb |
0:f1834a63f7c1
|
251
|
|
| Sergunb |
0:f1834a63f7c1
|
252
|
TIMx->CR1 = tmpcr1;
|
| Sergunb |
0:f1834a63f7c1
|
253
|
|
| Sergunb |
0:f1834a63f7c1
|
254
|
/* Set the Autoreload value */
|
| Sergunb |
0:f1834a63f7c1
|
255
|
TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
|
| Sergunb |
0:f1834a63f7c1
|
256
|
|
| Sergunb |
0:f1834a63f7c1
|
257
|
/* Set the Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
258
|
TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
|
| Sergunb |
0:f1834a63f7c1
|
259
|
|
| Sergunb |
0:f1834a63f7c1
|
260
|
if ((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
|
| Sergunb |
0:f1834a63f7c1
|
261
|
{
|
| Sergunb |
0:f1834a63f7c1
|
262
|
/* Set the Repetition Counter value */
|
| Sergunb |
0:f1834a63f7c1
|
263
|
TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
|
| Sergunb |
0:f1834a63f7c1
|
264
|
}
|
| Sergunb |
0:f1834a63f7c1
|
265
|
|
| Sergunb |
0:f1834a63f7c1
|
266
|
/* Generate an update event to reload the Prescaler and the Repetition counter
|
| Sergunb |
0:f1834a63f7c1
|
267
|
values immediately */
|
| Sergunb |
0:f1834a63f7c1
|
268
|
TIMx->EGR = TIM_PSCReloadMode_Immediate;
|
| Sergunb |
0:f1834a63f7c1
|
269
|
}
|
| Sergunb |
0:f1834a63f7c1
|
270
|
|
| Sergunb |
0:f1834a63f7c1
|
271
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
272
|
* @brief Initializes the TIMx Channel1 according to the specified
|
| Sergunb |
0:f1834a63f7c1
|
273
|
* parameters in the TIM_OCInitStruct.
|
| Sergunb |
0:f1834a63f7c1
|
274
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
275
|
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
|
| Sergunb |
0:f1834a63f7c1
|
276
|
* that contains the configuration information for the specified TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
277
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
278
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
279
|
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
280
|
{
|
| Sergunb |
0:f1834a63f7c1
|
281
|
uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
282
|
|
| Sergunb |
0:f1834a63f7c1
|
283
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
284
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
285
|
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
|
| Sergunb |
0:f1834a63f7c1
|
286
|
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
|
| Sergunb |
0:f1834a63f7c1
|
287
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
288
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
289
|
TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
|
| Sergunb |
0:f1834a63f7c1
|
290
|
/* Get the TIMx CCER register value */
|
| Sergunb |
0:f1834a63f7c1
|
291
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
292
|
/* Get the TIMx CR2 register value */
|
| Sergunb |
0:f1834a63f7c1
|
293
|
tmpcr2 = TIMx->CR2;
|
| Sergunb |
0:f1834a63f7c1
|
294
|
|
| Sergunb |
0:f1834a63f7c1
|
295
|
/* Get the TIMx CCMR1 register value */
|
| Sergunb |
0:f1834a63f7c1
|
296
|
tmpccmrx = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
297
|
|
| Sergunb |
0:f1834a63f7c1
|
298
|
/* Reset the Output Compare Mode Bits */
|
| Sergunb |
0:f1834a63f7c1
|
299
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
|
| Sergunb |
0:f1834a63f7c1
|
300
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
|
| Sergunb |
0:f1834a63f7c1
|
301
|
|
| Sergunb |
0:f1834a63f7c1
|
302
|
/* Select the Output Compare Mode */
|
| Sergunb |
0:f1834a63f7c1
|
303
|
tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
|
| Sergunb |
0:f1834a63f7c1
|
304
|
|
| Sergunb |
0:f1834a63f7c1
|
305
|
/* Reset the Output Polarity level */
|
| Sergunb |
0:f1834a63f7c1
|
306
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
|
| Sergunb |
0:f1834a63f7c1
|
307
|
/* Set the Output Compare Polarity */
|
| Sergunb |
0:f1834a63f7c1
|
308
|
tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
|
| Sergunb |
0:f1834a63f7c1
|
309
|
|
| Sergunb |
0:f1834a63f7c1
|
310
|
/* Set the Output State */
|
| Sergunb |
0:f1834a63f7c1
|
311
|
tmpccer |= TIM_OCInitStruct->TIM_OutputState;
|
| Sergunb |
0:f1834a63f7c1
|
312
|
|
| Sergunb |
0:f1834a63f7c1
|
313
|
if((TIMx == TIM1) || (TIMx == TIM8)|| (TIMx == TIM15)||
|
| Sergunb |
0:f1834a63f7c1
|
314
|
(TIMx == TIM16)|| (TIMx == TIM17))
|
| Sergunb |
0:f1834a63f7c1
|
315
|
{
|
| Sergunb |
0:f1834a63f7c1
|
316
|
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
|
| Sergunb |
0:f1834a63f7c1
|
317
|
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
318
|
assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
|
| Sergunb |
0:f1834a63f7c1
|
319
|
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
|
| Sergunb |
0:f1834a63f7c1
|
320
|
|
| Sergunb |
0:f1834a63f7c1
|
321
|
/* Reset the Output N Polarity level */
|
| Sergunb |
0:f1834a63f7c1
|
322
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
|
| Sergunb |
0:f1834a63f7c1
|
323
|
/* Set the Output N Polarity */
|
| Sergunb |
0:f1834a63f7c1
|
324
|
tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
|
| Sergunb |
0:f1834a63f7c1
|
325
|
|
| Sergunb |
0:f1834a63f7c1
|
326
|
/* Reset the Output N State */
|
| Sergunb |
0:f1834a63f7c1
|
327
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
|
| Sergunb |
0:f1834a63f7c1
|
328
|
/* Set the Output N State */
|
| Sergunb |
0:f1834a63f7c1
|
329
|
tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
|
| Sergunb |
0:f1834a63f7c1
|
330
|
|
| Sergunb |
0:f1834a63f7c1
|
331
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
| Sergunb |
0:f1834a63f7c1
|
332
|
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
|
| Sergunb |
0:f1834a63f7c1
|
333
|
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
|
| Sergunb |
0:f1834a63f7c1
|
334
|
|
| Sergunb |
0:f1834a63f7c1
|
335
|
/* Set the Output Idle state */
|
| Sergunb |
0:f1834a63f7c1
|
336
|
tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
|
| Sergunb |
0:f1834a63f7c1
|
337
|
/* Set the Output N Idle state */
|
| Sergunb |
0:f1834a63f7c1
|
338
|
tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
|
| Sergunb |
0:f1834a63f7c1
|
339
|
}
|
| Sergunb |
0:f1834a63f7c1
|
340
|
/* Write to TIMx CR2 */
|
| Sergunb |
0:f1834a63f7c1
|
341
|
TIMx->CR2 = tmpcr2;
|
| Sergunb |
0:f1834a63f7c1
|
342
|
|
| Sergunb |
0:f1834a63f7c1
|
343
|
/* Write to TIMx CCMR1 */
|
| Sergunb |
0:f1834a63f7c1
|
344
|
TIMx->CCMR1 = tmpccmrx;
|
| Sergunb |
0:f1834a63f7c1
|
345
|
|
| Sergunb |
0:f1834a63f7c1
|
346
|
/* Set the Capture Compare Register value */
|
| Sergunb |
0:f1834a63f7c1
|
347
|
TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
|
| Sergunb |
0:f1834a63f7c1
|
348
|
|
| Sergunb |
0:f1834a63f7c1
|
349
|
/* Write to TIMx CCER */
|
| Sergunb |
0:f1834a63f7c1
|
350
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
351
|
}
|
| Sergunb |
0:f1834a63f7c1
|
352
|
|
| Sergunb |
0:f1834a63f7c1
|
353
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
354
|
* @brief Initializes the TIMx Channel2 according to the specified
|
| Sergunb |
0:f1834a63f7c1
|
355
|
* parameters in the TIM_OCInitStruct.
|
| Sergunb |
0:f1834a63f7c1
|
356
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
|
| Sergunb |
0:f1834a63f7c1
|
357
|
* the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
358
|
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
|
| Sergunb |
0:f1834a63f7c1
|
359
|
* that contains the configuration information for the specified TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
360
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
361
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
362
|
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
363
|
{
|
| Sergunb |
0:f1834a63f7c1
|
364
|
uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
365
|
|
| Sergunb |
0:f1834a63f7c1
|
366
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
367
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
368
|
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
|
| Sergunb |
0:f1834a63f7c1
|
369
|
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
|
| Sergunb |
0:f1834a63f7c1
|
370
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
371
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
372
|
TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
|
| Sergunb |
0:f1834a63f7c1
|
373
|
|
| Sergunb |
0:f1834a63f7c1
|
374
|
/* Get the TIMx CCER register value */
|
| Sergunb |
0:f1834a63f7c1
|
375
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
376
|
/* Get the TIMx CR2 register value */
|
| Sergunb |
0:f1834a63f7c1
|
377
|
tmpcr2 = TIMx->CR2;
|
| Sergunb |
0:f1834a63f7c1
|
378
|
|
| Sergunb |
0:f1834a63f7c1
|
379
|
/* Get the TIMx CCMR1 register value */
|
| Sergunb |
0:f1834a63f7c1
|
380
|
tmpccmrx = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
381
|
|
| Sergunb |
0:f1834a63f7c1
|
382
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
| Sergunb |
0:f1834a63f7c1
|
383
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
|
| Sergunb |
0:f1834a63f7c1
|
384
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
|
| Sergunb |
0:f1834a63f7c1
|
385
|
|
| Sergunb |
0:f1834a63f7c1
|
386
|
/* Select the Output Compare Mode */
|
| Sergunb |
0:f1834a63f7c1
|
387
|
tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
|
| Sergunb |
0:f1834a63f7c1
|
388
|
|
| Sergunb |
0:f1834a63f7c1
|
389
|
/* Reset the Output Polarity level */
|
| Sergunb |
0:f1834a63f7c1
|
390
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
|
| Sergunb |
0:f1834a63f7c1
|
391
|
/* Set the Output Compare Polarity */
|
| Sergunb |
0:f1834a63f7c1
|
392
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
|
| Sergunb |
0:f1834a63f7c1
|
393
|
|
| Sergunb |
0:f1834a63f7c1
|
394
|
/* Set the Output State */
|
| Sergunb |
0:f1834a63f7c1
|
395
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
|
| Sergunb |
0:f1834a63f7c1
|
396
|
|
| Sergunb |
0:f1834a63f7c1
|
397
|
if((TIMx == TIM1) || (TIMx == TIM8))
|
| Sergunb |
0:f1834a63f7c1
|
398
|
{
|
| Sergunb |
0:f1834a63f7c1
|
399
|
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
|
| Sergunb |
0:f1834a63f7c1
|
400
|
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
401
|
assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
|
| Sergunb |
0:f1834a63f7c1
|
402
|
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
|
| Sergunb |
0:f1834a63f7c1
|
403
|
|
| Sergunb |
0:f1834a63f7c1
|
404
|
/* Reset the Output N Polarity level */
|
| Sergunb |
0:f1834a63f7c1
|
405
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
|
| Sergunb |
0:f1834a63f7c1
|
406
|
/* Set the Output N Polarity */
|
| Sergunb |
0:f1834a63f7c1
|
407
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
|
| Sergunb |
0:f1834a63f7c1
|
408
|
|
| Sergunb |
0:f1834a63f7c1
|
409
|
/* Reset the Output N State */
|
| Sergunb |
0:f1834a63f7c1
|
410
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
|
| Sergunb |
0:f1834a63f7c1
|
411
|
/* Set the Output N State */
|
| Sergunb |
0:f1834a63f7c1
|
412
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
|
| Sergunb |
0:f1834a63f7c1
|
413
|
|
| Sergunb |
0:f1834a63f7c1
|
414
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
| Sergunb |
0:f1834a63f7c1
|
415
|
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
|
| Sergunb |
0:f1834a63f7c1
|
416
|
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
|
| Sergunb |
0:f1834a63f7c1
|
417
|
|
| Sergunb |
0:f1834a63f7c1
|
418
|
/* Set the Output Idle state */
|
| Sergunb |
0:f1834a63f7c1
|
419
|
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
|
| Sergunb |
0:f1834a63f7c1
|
420
|
/* Set the Output N Idle state */
|
| Sergunb |
0:f1834a63f7c1
|
421
|
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
|
| Sergunb |
0:f1834a63f7c1
|
422
|
}
|
| Sergunb |
0:f1834a63f7c1
|
423
|
/* Write to TIMx CR2 */
|
| Sergunb |
0:f1834a63f7c1
|
424
|
TIMx->CR2 = tmpcr2;
|
| Sergunb |
0:f1834a63f7c1
|
425
|
|
| Sergunb |
0:f1834a63f7c1
|
426
|
/* Write to TIMx CCMR1 */
|
| Sergunb |
0:f1834a63f7c1
|
427
|
TIMx->CCMR1 = tmpccmrx;
|
| Sergunb |
0:f1834a63f7c1
|
428
|
|
| Sergunb |
0:f1834a63f7c1
|
429
|
/* Set the Capture Compare Register value */
|
| Sergunb |
0:f1834a63f7c1
|
430
|
TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
|
| Sergunb |
0:f1834a63f7c1
|
431
|
|
| Sergunb |
0:f1834a63f7c1
|
432
|
/* Write to TIMx CCER */
|
| Sergunb |
0:f1834a63f7c1
|
433
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
434
|
}
|
| Sergunb |
0:f1834a63f7c1
|
435
|
|
| Sergunb |
0:f1834a63f7c1
|
436
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
437
|
* @brief Initializes the TIMx Channel3 according to the specified
|
| Sergunb |
0:f1834a63f7c1
|
438
|
* parameters in the TIM_OCInitStruct.
|
| Sergunb |
0:f1834a63f7c1
|
439
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
440
|
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
|
| Sergunb |
0:f1834a63f7c1
|
441
|
* that contains the configuration information for the specified TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
442
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
443
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
444
|
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
445
|
{
|
| Sergunb |
0:f1834a63f7c1
|
446
|
uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
447
|
|
| Sergunb |
0:f1834a63f7c1
|
448
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
449
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
450
|
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
|
| Sergunb |
0:f1834a63f7c1
|
451
|
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
|
| Sergunb |
0:f1834a63f7c1
|
452
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
453
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
454
|
TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
|
| Sergunb |
0:f1834a63f7c1
|
455
|
|
| Sergunb |
0:f1834a63f7c1
|
456
|
/* Get the TIMx CCER register value */
|
| Sergunb |
0:f1834a63f7c1
|
457
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
458
|
/* Get the TIMx CR2 register value */
|
| Sergunb |
0:f1834a63f7c1
|
459
|
tmpcr2 = TIMx->CR2;
|
| Sergunb |
0:f1834a63f7c1
|
460
|
|
| Sergunb |
0:f1834a63f7c1
|
461
|
/* Get the TIMx CCMR2 register value */
|
| Sergunb |
0:f1834a63f7c1
|
462
|
tmpccmrx = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
463
|
|
| Sergunb |
0:f1834a63f7c1
|
464
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
| Sergunb |
0:f1834a63f7c1
|
465
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
|
| Sergunb |
0:f1834a63f7c1
|
466
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
|
| Sergunb |
0:f1834a63f7c1
|
467
|
/* Select the Output Compare Mode */
|
| Sergunb |
0:f1834a63f7c1
|
468
|
tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
|
| Sergunb |
0:f1834a63f7c1
|
469
|
|
| Sergunb |
0:f1834a63f7c1
|
470
|
/* Reset the Output Polarity level */
|
| Sergunb |
0:f1834a63f7c1
|
471
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
|
| Sergunb |
0:f1834a63f7c1
|
472
|
/* Set the Output Compare Polarity */
|
| Sergunb |
0:f1834a63f7c1
|
473
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
|
| Sergunb |
0:f1834a63f7c1
|
474
|
|
| Sergunb |
0:f1834a63f7c1
|
475
|
/* Set the Output State */
|
| Sergunb |
0:f1834a63f7c1
|
476
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
|
| Sergunb |
0:f1834a63f7c1
|
477
|
|
| Sergunb |
0:f1834a63f7c1
|
478
|
if((TIMx == TIM1) || (TIMx == TIM8))
|
| Sergunb |
0:f1834a63f7c1
|
479
|
{
|
| Sergunb |
0:f1834a63f7c1
|
480
|
assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
|
| Sergunb |
0:f1834a63f7c1
|
481
|
assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
482
|
assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
|
| Sergunb |
0:f1834a63f7c1
|
483
|
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
|
| Sergunb |
0:f1834a63f7c1
|
484
|
|
| Sergunb |
0:f1834a63f7c1
|
485
|
/* Reset the Output N Polarity level */
|
| Sergunb |
0:f1834a63f7c1
|
486
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
|
| Sergunb |
0:f1834a63f7c1
|
487
|
/* Set the Output N Polarity */
|
| Sergunb |
0:f1834a63f7c1
|
488
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
|
| Sergunb |
0:f1834a63f7c1
|
489
|
/* Reset the Output N State */
|
| Sergunb |
0:f1834a63f7c1
|
490
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
|
| Sergunb |
0:f1834a63f7c1
|
491
|
|
| Sergunb |
0:f1834a63f7c1
|
492
|
/* Set the Output N State */
|
| Sergunb |
0:f1834a63f7c1
|
493
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
|
| Sergunb |
0:f1834a63f7c1
|
494
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
| Sergunb |
0:f1834a63f7c1
|
495
|
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
|
| Sergunb |
0:f1834a63f7c1
|
496
|
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
|
| Sergunb |
0:f1834a63f7c1
|
497
|
/* Set the Output Idle state */
|
| Sergunb |
0:f1834a63f7c1
|
498
|
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
|
| Sergunb |
0:f1834a63f7c1
|
499
|
/* Set the Output N Idle state */
|
| Sergunb |
0:f1834a63f7c1
|
500
|
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
|
| Sergunb |
0:f1834a63f7c1
|
501
|
}
|
| Sergunb |
0:f1834a63f7c1
|
502
|
/* Write to TIMx CR2 */
|
| Sergunb |
0:f1834a63f7c1
|
503
|
TIMx->CR2 = tmpcr2;
|
| Sergunb |
0:f1834a63f7c1
|
504
|
|
| Sergunb |
0:f1834a63f7c1
|
505
|
/* Write to TIMx CCMR2 */
|
| Sergunb |
0:f1834a63f7c1
|
506
|
TIMx->CCMR2 = tmpccmrx;
|
| Sergunb |
0:f1834a63f7c1
|
507
|
|
| Sergunb |
0:f1834a63f7c1
|
508
|
/* Set the Capture Compare Register value */
|
| Sergunb |
0:f1834a63f7c1
|
509
|
TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
|
| Sergunb |
0:f1834a63f7c1
|
510
|
|
| Sergunb |
0:f1834a63f7c1
|
511
|
/* Write to TIMx CCER */
|
| Sergunb |
0:f1834a63f7c1
|
512
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
513
|
}
|
| Sergunb |
0:f1834a63f7c1
|
514
|
|
| Sergunb |
0:f1834a63f7c1
|
515
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
516
|
* @brief Initializes the TIMx Channel4 according to the specified
|
| Sergunb |
0:f1834a63f7c1
|
517
|
* parameters in the TIM_OCInitStruct.
|
| Sergunb |
0:f1834a63f7c1
|
518
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
519
|
* @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
|
| Sergunb |
0:f1834a63f7c1
|
520
|
* that contains the configuration information for the specified TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
521
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
522
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
523
|
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
524
|
{
|
| Sergunb |
0:f1834a63f7c1
|
525
|
uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
526
|
|
| Sergunb |
0:f1834a63f7c1
|
527
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
528
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
529
|
assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
|
| Sergunb |
0:f1834a63f7c1
|
530
|
assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
|
| Sergunb |
0:f1834a63f7c1
|
531
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
532
|
/* Disable the Channel 2: Reset the CC4E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
533
|
TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
|
| Sergunb |
0:f1834a63f7c1
|
534
|
|
| Sergunb |
0:f1834a63f7c1
|
535
|
/* Get the TIMx CCER register value */
|
| Sergunb |
0:f1834a63f7c1
|
536
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
537
|
/* Get the TIMx CR2 register value */
|
| Sergunb |
0:f1834a63f7c1
|
538
|
tmpcr2 = TIMx->CR2;
|
| Sergunb |
0:f1834a63f7c1
|
539
|
|
| Sergunb |
0:f1834a63f7c1
|
540
|
/* Get the TIMx CCMR2 register value */
|
| Sergunb |
0:f1834a63f7c1
|
541
|
tmpccmrx = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
542
|
|
| Sergunb |
0:f1834a63f7c1
|
543
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
| Sergunb |
0:f1834a63f7c1
|
544
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
|
| Sergunb |
0:f1834a63f7c1
|
545
|
tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
|
| Sergunb |
0:f1834a63f7c1
|
546
|
|
| Sergunb |
0:f1834a63f7c1
|
547
|
/* Select the Output Compare Mode */
|
| Sergunb |
0:f1834a63f7c1
|
548
|
tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
|
| Sergunb |
0:f1834a63f7c1
|
549
|
|
| Sergunb |
0:f1834a63f7c1
|
550
|
/* Reset the Output Polarity level */
|
| Sergunb |
0:f1834a63f7c1
|
551
|
tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
|
| Sergunb |
0:f1834a63f7c1
|
552
|
/* Set the Output Compare Polarity */
|
| Sergunb |
0:f1834a63f7c1
|
553
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
|
| Sergunb |
0:f1834a63f7c1
|
554
|
|
| Sergunb |
0:f1834a63f7c1
|
555
|
/* Set the Output State */
|
| Sergunb |
0:f1834a63f7c1
|
556
|
tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
|
| Sergunb |
0:f1834a63f7c1
|
557
|
|
| Sergunb |
0:f1834a63f7c1
|
558
|
if((TIMx == TIM1) || (TIMx == TIM8))
|
| Sergunb |
0:f1834a63f7c1
|
559
|
{
|
| Sergunb |
0:f1834a63f7c1
|
560
|
assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
|
| Sergunb |
0:f1834a63f7c1
|
561
|
/* Reset the Output Compare IDLE State */
|
| Sergunb |
0:f1834a63f7c1
|
562
|
tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
|
| Sergunb |
0:f1834a63f7c1
|
563
|
/* Set the Output Idle state */
|
| Sergunb |
0:f1834a63f7c1
|
564
|
tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
|
| Sergunb |
0:f1834a63f7c1
|
565
|
}
|
| Sergunb |
0:f1834a63f7c1
|
566
|
/* Write to TIMx CR2 */
|
| Sergunb |
0:f1834a63f7c1
|
567
|
TIMx->CR2 = tmpcr2;
|
| Sergunb |
0:f1834a63f7c1
|
568
|
|
| Sergunb |
0:f1834a63f7c1
|
569
|
/* Write to TIMx CCMR2 */
|
| Sergunb |
0:f1834a63f7c1
|
570
|
TIMx->CCMR2 = tmpccmrx;
|
| Sergunb |
0:f1834a63f7c1
|
571
|
|
| Sergunb |
0:f1834a63f7c1
|
572
|
/* Set the Capture Compare Register value */
|
| Sergunb |
0:f1834a63f7c1
|
573
|
TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
|
| Sergunb |
0:f1834a63f7c1
|
574
|
|
| Sergunb |
0:f1834a63f7c1
|
575
|
/* Write to TIMx CCER */
|
| Sergunb |
0:f1834a63f7c1
|
576
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
577
|
}
|
| Sergunb |
0:f1834a63f7c1
|
578
|
|
| Sergunb |
0:f1834a63f7c1
|
579
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
580
|
* @brief Initializes the TIM peripheral according to the specified
|
| Sergunb |
0:f1834a63f7c1
|
581
|
* parameters in the TIM_ICInitStruct.
|
| Sergunb |
0:f1834a63f7c1
|
582
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
583
|
* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
|
| Sergunb |
0:f1834a63f7c1
|
584
|
* that contains the configuration information for the specified TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
585
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
586
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
587
|
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
588
|
{
|
| Sergunb |
0:f1834a63f7c1
|
589
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
590
|
assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
|
| Sergunb |
0:f1834a63f7c1
|
591
|
assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
|
| Sergunb |
0:f1834a63f7c1
|
592
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
|
| Sergunb |
0:f1834a63f7c1
|
593
|
assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
|
| Sergunb |
0:f1834a63f7c1
|
594
|
|
| Sergunb |
0:f1834a63f7c1
|
595
|
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
|
| Sergunb |
0:f1834a63f7c1
|
596
|
(TIMx == TIM4) ||(TIMx == TIM5))
|
| Sergunb |
0:f1834a63f7c1
|
597
|
{
|
| Sergunb |
0:f1834a63f7c1
|
598
|
assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
599
|
}
|
| Sergunb |
0:f1834a63f7c1
|
600
|
else
|
| Sergunb |
0:f1834a63f7c1
|
601
|
{
|
| Sergunb |
0:f1834a63f7c1
|
602
|
assert_param(IS_TIM_IC_POLARITY_LITE(TIM_ICInitStruct->TIM_ICPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
603
|
}
|
| Sergunb |
0:f1834a63f7c1
|
604
|
if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
|
| Sergunb |
0:f1834a63f7c1
|
605
|
{
|
| Sergunb |
0:f1834a63f7c1
|
606
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
607
|
/* TI1 Configuration */
|
| Sergunb |
0:f1834a63f7c1
|
608
|
TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
|
| Sergunb |
0:f1834a63f7c1
|
609
|
TIM_ICInitStruct->TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
610
|
TIM_ICInitStruct->TIM_ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
611
|
/* Set the Input Capture Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
612
|
TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
| Sergunb |
0:f1834a63f7c1
|
613
|
}
|
| Sergunb |
0:f1834a63f7c1
|
614
|
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
|
| Sergunb |
0:f1834a63f7c1
|
615
|
{
|
| Sergunb |
0:f1834a63f7c1
|
616
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
617
|
/* TI2 Configuration */
|
| Sergunb |
0:f1834a63f7c1
|
618
|
TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
|
| Sergunb |
0:f1834a63f7c1
|
619
|
TIM_ICInitStruct->TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
620
|
TIM_ICInitStruct->TIM_ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
621
|
/* Set the Input Capture Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
622
|
TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
| Sergunb |
0:f1834a63f7c1
|
623
|
}
|
| Sergunb |
0:f1834a63f7c1
|
624
|
else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
|
| Sergunb |
0:f1834a63f7c1
|
625
|
{
|
| Sergunb |
0:f1834a63f7c1
|
626
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
627
|
/* TI3 Configuration */
|
| Sergunb |
0:f1834a63f7c1
|
628
|
TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
|
| Sergunb |
0:f1834a63f7c1
|
629
|
TIM_ICInitStruct->TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
630
|
TIM_ICInitStruct->TIM_ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
631
|
/* Set the Input Capture Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
632
|
TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
| Sergunb |
0:f1834a63f7c1
|
633
|
}
|
| Sergunb |
0:f1834a63f7c1
|
634
|
else
|
| Sergunb |
0:f1834a63f7c1
|
635
|
{
|
| Sergunb |
0:f1834a63f7c1
|
636
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
637
|
/* TI4 Configuration */
|
| Sergunb |
0:f1834a63f7c1
|
638
|
TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
|
| Sergunb |
0:f1834a63f7c1
|
639
|
TIM_ICInitStruct->TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
640
|
TIM_ICInitStruct->TIM_ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
641
|
/* Set the Input Capture Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
642
|
TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
| Sergunb |
0:f1834a63f7c1
|
643
|
}
|
| Sergunb |
0:f1834a63f7c1
|
644
|
}
|
| Sergunb |
0:f1834a63f7c1
|
645
|
|
| Sergunb |
0:f1834a63f7c1
|
646
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
647
|
* @brief Configures the TIM peripheral according to the specified
|
| Sergunb |
0:f1834a63f7c1
|
648
|
* parameters in the TIM_ICInitStruct to measure an external PWM signal.
|
| Sergunb |
0:f1834a63f7c1
|
649
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
650
|
* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
|
| Sergunb |
0:f1834a63f7c1
|
651
|
* that contains the configuration information for the specified TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
652
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
653
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
654
|
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
655
|
{
|
| Sergunb |
0:f1834a63f7c1
|
656
|
uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
|
| Sergunb |
0:f1834a63f7c1
|
657
|
uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
|
| Sergunb |
0:f1834a63f7c1
|
658
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
659
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
660
|
/* Select the Opposite Input Polarity */
|
| Sergunb |
0:f1834a63f7c1
|
661
|
if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
|
| Sergunb |
0:f1834a63f7c1
|
662
|
{
|
| Sergunb |
0:f1834a63f7c1
|
663
|
icoppositepolarity = TIM_ICPolarity_Falling;
|
| Sergunb |
0:f1834a63f7c1
|
664
|
}
|
| Sergunb |
0:f1834a63f7c1
|
665
|
else
|
| Sergunb |
0:f1834a63f7c1
|
666
|
{
|
| Sergunb |
0:f1834a63f7c1
|
667
|
icoppositepolarity = TIM_ICPolarity_Rising;
|
| Sergunb |
0:f1834a63f7c1
|
668
|
}
|
| Sergunb |
0:f1834a63f7c1
|
669
|
/* Select the Opposite Input */
|
| Sergunb |
0:f1834a63f7c1
|
670
|
if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
|
| Sergunb |
0:f1834a63f7c1
|
671
|
{
|
| Sergunb |
0:f1834a63f7c1
|
672
|
icoppositeselection = TIM_ICSelection_IndirectTI;
|
| Sergunb |
0:f1834a63f7c1
|
673
|
}
|
| Sergunb |
0:f1834a63f7c1
|
674
|
else
|
| Sergunb |
0:f1834a63f7c1
|
675
|
{
|
| Sergunb |
0:f1834a63f7c1
|
676
|
icoppositeselection = TIM_ICSelection_DirectTI;
|
| Sergunb |
0:f1834a63f7c1
|
677
|
}
|
| Sergunb |
0:f1834a63f7c1
|
678
|
if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
|
| Sergunb |
0:f1834a63f7c1
|
679
|
{
|
| Sergunb |
0:f1834a63f7c1
|
680
|
/* TI1 Configuration */
|
| Sergunb |
0:f1834a63f7c1
|
681
|
TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
682
|
TIM_ICInitStruct->TIM_ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
683
|
/* Set the Input Capture Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
684
|
TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
| Sergunb |
0:f1834a63f7c1
|
685
|
/* TI2 Configuration */
|
| Sergunb |
0:f1834a63f7c1
|
686
|
TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
687
|
/* Set the Input Capture Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
688
|
TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
| Sergunb |
0:f1834a63f7c1
|
689
|
}
|
| Sergunb |
0:f1834a63f7c1
|
690
|
else
|
| Sergunb |
0:f1834a63f7c1
|
691
|
{
|
| Sergunb |
0:f1834a63f7c1
|
692
|
/* TI2 Configuration */
|
| Sergunb |
0:f1834a63f7c1
|
693
|
TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
694
|
TIM_ICInitStruct->TIM_ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
695
|
/* Set the Input Capture Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
696
|
TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
| Sergunb |
0:f1834a63f7c1
|
697
|
/* TI1 Configuration */
|
| Sergunb |
0:f1834a63f7c1
|
698
|
TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
699
|
/* Set the Input Capture Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
700
|
TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
|
| Sergunb |
0:f1834a63f7c1
|
701
|
}
|
| Sergunb |
0:f1834a63f7c1
|
702
|
}
|
| Sergunb |
0:f1834a63f7c1
|
703
|
|
| Sergunb |
0:f1834a63f7c1
|
704
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
705
|
* @brief Configures the: Break feature, dead time, Lock level, the OSSI,
|
| Sergunb |
0:f1834a63f7c1
|
706
|
* the OSSR State and the AOE(automatic output enable).
|
| Sergunb |
0:f1834a63f7c1
|
707
|
* @param TIMx: where x can be 1 or 8 to select the TIM
|
| Sergunb |
0:f1834a63f7c1
|
708
|
* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
|
| Sergunb |
0:f1834a63f7c1
|
709
|
* contains the BDTR Register configuration information for the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
710
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
711
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
712
|
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
713
|
{
|
| Sergunb |
0:f1834a63f7c1
|
714
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
715
|
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
716
|
assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
|
| Sergunb |
0:f1834a63f7c1
|
717
|
assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
|
| Sergunb |
0:f1834a63f7c1
|
718
|
assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
|
| Sergunb |
0:f1834a63f7c1
|
719
|
assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
|
| Sergunb |
0:f1834a63f7c1
|
720
|
assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
721
|
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
|
| Sergunb |
0:f1834a63f7c1
|
722
|
/* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
|
| Sergunb |
0:f1834a63f7c1
|
723
|
the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
| Sergunb |
0:f1834a63f7c1
|
724
|
TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
|
| Sergunb |
0:f1834a63f7c1
|
725
|
TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
|
| Sergunb |
0:f1834a63f7c1
|
726
|
TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
|
| Sergunb |
0:f1834a63f7c1
|
727
|
TIM_BDTRInitStruct->TIM_AutomaticOutput;
|
| Sergunb |
0:f1834a63f7c1
|
728
|
}
|
| Sergunb |
0:f1834a63f7c1
|
729
|
|
| Sergunb |
0:f1834a63f7c1
|
730
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
731
|
* @brief Fills each TIM_TimeBaseInitStruct member with its default value.
|
| Sergunb |
0:f1834a63f7c1
|
732
|
* @param TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
|
| Sergunb |
0:f1834a63f7c1
|
733
|
* structure which will be initialized.
|
| Sergunb |
0:f1834a63f7c1
|
734
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
735
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
736
|
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
737
|
{
|
| Sergunb |
0:f1834a63f7c1
|
738
|
/* Set the default configuration */
|
| Sergunb |
0:f1834a63f7c1
|
739
|
TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF;
|
| Sergunb |
0:f1834a63f7c1
|
740
|
TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
|
| Sergunb |
0:f1834a63f7c1
|
741
|
TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
|
| Sergunb |
0:f1834a63f7c1
|
742
|
TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
|
| Sergunb |
0:f1834a63f7c1
|
743
|
TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
|
| Sergunb |
0:f1834a63f7c1
|
744
|
}
|
| Sergunb |
0:f1834a63f7c1
|
745
|
|
| Sergunb |
0:f1834a63f7c1
|
746
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
747
|
* @brief Fills each TIM_OCInitStruct member with its default value.
|
| Sergunb |
0:f1834a63f7c1
|
748
|
* @param TIM_OCInitStruct : pointer to a TIM_OCInitTypeDef structure which will
|
| Sergunb |
0:f1834a63f7c1
|
749
|
* be initialized.
|
| Sergunb |
0:f1834a63f7c1
|
750
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
751
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
752
|
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
753
|
{
|
| Sergunb |
0:f1834a63f7c1
|
754
|
/* Set the default configuration */
|
| Sergunb |
0:f1834a63f7c1
|
755
|
TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
|
| Sergunb |
0:f1834a63f7c1
|
756
|
TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
|
| Sergunb |
0:f1834a63f7c1
|
757
|
TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
|
| Sergunb |
0:f1834a63f7c1
|
758
|
TIM_OCInitStruct->TIM_Pulse = 0x0000;
|
| Sergunb |
0:f1834a63f7c1
|
759
|
TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
|
| Sergunb |
0:f1834a63f7c1
|
760
|
TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
|
| Sergunb |
0:f1834a63f7c1
|
761
|
TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
|
| Sergunb |
0:f1834a63f7c1
|
762
|
TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
|
| Sergunb |
0:f1834a63f7c1
|
763
|
}
|
| Sergunb |
0:f1834a63f7c1
|
764
|
|
| Sergunb |
0:f1834a63f7c1
|
765
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
766
|
* @brief Fills each TIM_ICInitStruct member with its default value.
|
| Sergunb |
0:f1834a63f7c1
|
767
|
* @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
|
| Sergunb |
0:f1834a63f7c1
|
768
|
* be initialized.
|
| Sergunb |
0:f1834a63f7c1
|
769
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
770
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
771
|
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
772
|
{
|
| Sergunb |
0:f1834a63f7c1
|
773
|
/* Set the default configuration */
|
| Sergunb |
0:f1834a63f7c1
|
774
|
TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
|
| Sergunb |
0:f1834a63f7c1
|
775
|
TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
|
| Sergunb |
0:f1834a63f7c1
|
776
|
TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
|
| Sergunb |
0:f1834a63f7c1
|
777
|
TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
|
| Sergunb |
0:f1834a63f7c1
|
778
|
TIM_ICInitStruct->TIM_ICFilter = 0x00;
|
| Sergunb |
0:f1834a63f7c1
|
779
|
}
|
| Sergunb |
0:f1834a63f7c1
|
780
|
|
| Sergunb |
0:f1834a63f7c1
|
781
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
782
|
* @brief Fills each TIM_BDTRInitStruct member with its default value.
|
| Sergunb |
0:f1834a63f7c1
|
783
|
* @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
|
| Sergunb |
0:f1834a63f7c1
|
784
|
* will be initialized.
|
| Sergunb |
0:f1834a63f7c1
|
785
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
786
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
787
|
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
|
| Sergunb |
0:f1834a63f7c1
|
788
|
{
|
| Sergunb |
0:f1834a63f7c1
|
789
|
/* Set the default configuration */
|
| Sergunb |
0:f1834a63f7c1
|
790
|
TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
|
| Sergunb |
0:f1834a63f7c1
|
791
|
TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
|
| Sergunb |
0:f1834a63f7c1
|
792
|
TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
|
| Sergunb |
0:f1834a63f7c1
|
793
|
TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
|
| Sergunb |
0:f1834a63f7c1
|
794
|
TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
|
| Sergunb |
0:f1834a63f7c1
|
795
|
TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
|
| Sergunb |
0:f1834a63f7c1
|
796
|
TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
|
| Sergunb |
0:f1834a63f7c1
|
797
|
}
|
| Sergunb |
0:f1834a63f7c1
|
798
|
|
| Sergunb |
0:f1834a63f7c1
|
799
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
800
|
* @brief Enables or disables the specified TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
801
|
* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
802
|
* @param NewState: new state of the TIMx peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
803
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
804
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
805
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
806
|
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
807
|
{
|
| Sergunb |
0:f1834a63f7c1
|
808
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
809
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
810
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
811
|
|
| Sergunb |
0:f1834a63f7c1
|
812
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
813
|
{
|
| Sergunb |
0:f1834a63f7c1
|
814
|
/* Enable the TIM Counter */
|
| Sergunb |
0:f1834a63f7c1
|
815
|
TIMx->CR1 |= TIM_CR1_CEN;
|
| Sergunb |
0:f1834a63f7c1
|
816
|
}
|
| Sergunb |
0:f1834a63f7c1
|
817
|
else
|
| Sergunb |
0:f1834a63f7c1
|
818
|
{
|
| Sergunb |
0:f1834a63f7c1
|
819
|
/* Disable the TIM Counter */
|
| Sergunb |
0:f1834a63f7c1
|
820
|
TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
|
| Sergunb |
0:f1834a63f7c1
|
821
|
}
|
| Sergunb |
0:f1834a63f7c1
|
822
|
}
|
| Sergunb |
0:f1834a63f7c1
|
823
|
|
| Sergunb |
0:f1834a63f7c1
|
824
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
825
|
* @brief Enables or disables the TIM peripheral Main Outputs.
|
| Sergunb |
0:f1834a63f7c1
|
826
|
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
827
|
* @param NewState: new state of the TIM peripheral Main Outputs.
|
| Sergunb |
0:f1834a63f7c1
|
828
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
829
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
830
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
831
|
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
832
|
{
|
| Sergunb |
0:f1834a63f7c1
|
833
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
834
|
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
835
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
836
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
837
|
{
|
| Sergunb |
0:f1834a63f7c1
|
838
|
/* Enable the TIM Main Output */
|
| Sergunb |
0:f1834a63f7c1
|
839
|
TIMx->BDTR |= TIM_BDTR_MOE;
|
| Sergunb |
0:f1834a63f7c1
|
840
|
}
|
| Sergunb |
0:f1834a63f7c1
|
841
|
else
|
| Sergunb |
0:f1834a63f7c1
|
842
|
{
|
| Sergunb |
0:f1834a63f7c1
|
843
|
/* Disable the TIM Main Output */
|
| Sergunb |
0:f1834a63f7c1
|
844
|
TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
|
| Sergunb |
0:f1834a63f7c1
|
845
|
}
|
| Sergunb |
0:f1834a63f7c1
|
846
|
}
|
| Sergunb |
0:f1834a63f7c1
|
847
|
|
| Sergunb |
0:f1834a63f7c1
|
848
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
849
|
* @brief Enables or disables the specified TIM interrupts.
|
| Sergunb |
0:f1834a63f7c1
|
850
|
* @param TIMx: where x can be 1 to 17 to select the TIMx peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
851
|
* @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
|
| Sergunb |
0:f1834a63f7c1
|
852
|
* This parameter can be any combination of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
853
|
* @arg TIM_IT_Update: TIM update Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
854
|
* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
855
|
* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
856
|
* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
857
|
* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
858
|
* @arg TIM_IT_COM: TIM Commutation Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
859
|
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
860
|
* @arg TIM_IT_Break: TIM Break Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
861
|
* @note
|
| Sergunb |
0:f1834a63f7c1
|
862
|
* - TIM6 and TIM7 can only generate an update interrupt.
|
| Sergunb |
0:f1834a63f7c1
|
863
|
* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
|
| Sergunb |
0:f1834a63f7c1
|
864
|
* TIM_IT_CC2 or TIM_IT_Trigger.
|
| Sergunb |
0:f1834a63f7c1
|
865
|
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
|
| Sergunb |
0:f1834a63f7c1
|
866
|
* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
|
| Sergunb |
0:f1834a63f7c1
|
867
|
* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
|
| Sergunb |
0:f1834a63f7c1
|
868
|
* @param NewState: new state of the TIM interrupts.
|
| Sergunb |
0:f1834a63f7c1
|
869
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
870
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
871
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
872
|
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
873
|
{
|
| Sergunb |
0:f1834a63f7c1
|
874
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
875
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
876
|
assert_param(IS_TIM_IT(TIM_IT));
|
| Sergunb |
0:f1834a63f7c1
|
877
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
878
|
|
| Sergunb |
0:f1834a63f7c1
|
879
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
880
|
{
|
| Sergunb |
0:f1834a63f7c1
|
881
|
/* Enable the Interrupt sources */
|
| Sergunb |
0:f1834a63f7c1
|
882
|
TIMx->DIER |= TIM_IT;
|
| Sergunb |
0:f1834a63f7c1
|
883
|
}
|
| Sergunb |
0:f1834a63f7c1
|
884
|
else
|
| Sergunb |
0:f1834a63f7c1
|
885
|
{
|
| Sergunb |
0:f1834a63f7c1
|
886
|
/* Disable the Interrupt sources */
|
| Sergunb |
0:f1834a63f7c1
|
887
|
TIMx->DIER &= (uint16_t)~TIM_IT;
|
| Sergunb |
0:f1834a63f7c1
|
888
|
}
|
| Sergunb |
0:f1834a63f7c1
|
889
|
}
|
| Sergunb |
0:f1834a63f7c1
|
890
|
|
| Sergunb |
0:f1834a63f7c1
|
891
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
892
|
* @brief Configures the TIMx event to be generate by software.
|
| Sergunb |
0:f1834a63f7c1
|
893
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
894
|
* @param TIM_EventSource: specifies the event source.
|
| Sergunb |
0:f1834a63f7c1
|
895
|
* This parameter can be one or more of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
896
|
* @arg TIM_EventSource_Update: Timer update Event source
|
| Sergunb |
0:f1834a63f7c1
|
897
|
* @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
|
| Sergunb |
0:f1834a63f7c1
|
898
|
* @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
|
| Sergunb |
0:f1834a63f7c1
|
899
|
* @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
|
| Sergunb |
0:f1834a63f7c1
|
900
|
* @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
|
| Sergunb |
0:f1834a63f7c1
|
901
|
* @arg TIM_EventSource_COM: Timer COM event source
|
| Sergunb |
0:f1834a63f7c1
|
902
|
* @arg TIM_EventSource_Trigger: Timer Trigger Event source
|
| Sergunb |
0:f1834a63f7c1
|
903
|
* @arg TIM_EventSource_Break: Timer Break event source
|
| Sergunb |
0:f1834a63f7c1
|
904
|
* @note
|
| Sergunb |
0:f1834a63f7c1
|
905
|
* - TIM6 and TIM7 can only generate an update event.
|
| Sergunb |
0:f1834a63f7c1
|
906
|
* - TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
|
| Sergunb |
0:f1834a63f7c1
|
907
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
908
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
909
|
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
|
| Sergunb |
0:f1834a63f7c1
|
910
|
{
|
| Sergunb |
0:f1834a63f7c1
|
911
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
912
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
913
|
assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
|
| Sergunb |
0:f1834a63f7c1
|
914
|
|
| Sergunb |
0:f1834a63f7c1
|
915
|
/* Set the event sources */
|
| Sergunb |
0:f1834a63f7c1
|
916
|
TIMx->EGR = TIM_EventSource;
|
| Sergunb |
0:f1834a63f7c1
|
917
|
}
|
| Sergunb |
0:f1834a63f7c1
|
918
|
|
| Sergunb |
0:f1834a63f7c1
|
919
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
920
|
* @brief Configures the TIMx's DMA interface.
|
| Sergunb |
0:f1834a63f7c1
|
921
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
|
| Sergunb |
0:f1834a63f7c1
|
922
|
* the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
923
|
* @param TIM_DMABase: DMA Base address.
|
| Sergunb |
0:f1834a63f7c1
|
924
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
925
|
* @arg TIM_DMABase_CR, TIM_DMABase_CR2, TIM_DMABase_SMCR,
|
| Sergunb |
0:f1834a63f7c1
|
926
|
* TIM_DMABase_DIER, TIM1_DMABase_SR, TIM_DMABase_EGR,
|
| Sergunb |
0:f1834a63f7c1
|
927
|
* TIM_DMABase_CCMR1, TIM_DMABase_CCMR2, TIM_DMABase_CCER,
|
| Sergunb |
0:f1834a63f7c1
|
928
|
* TIM_DMABase_CNT, TIM_DMABase_PSC, TIM_DMABase_ARR,
|
| Sergunb |
0:f1834a63f7c1
|
929
|
* TIM_DMABase_RCR, TIM_DMABase_CCR1, TIM_DMABase_CCR2,
|
| Sergunb |
0:f1834a63f7c1
|
930
|
* TIM_DMABase_CCR3, TIM_DMABase_CCR4, TIM_DMABase_BDTR,
|
| Sergunb |
0:f1834a63f7c1
|
931
|
* TIM_DMABase_DCR.
|
| Sergunb |
0:f1834a63f7c1
|
932
|
* @param TIM_DMABurstLength: DMA Burst length.
|
| Sergunb |
0:f1834a63f7c1
|
933
|
* This parameter can be one value between:
|
| Sergunb |
0:f1834a63f7c1
|
934
|
* TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
|
| Sergunb |
0:f1834a63f7c1
|
935
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
936
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
937
|
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
|
| Sergunb |
0:f1834a63f7c1
|
938
|
{
|
| Sergunb |
0:f1834a63f7c1
|
939
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
940
|
assert_param(IS_TIM_LIST4_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
941
|
assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
|
| Sergunb |
0:f1834a63f7c1
|
942
|
assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
|
| Sergunb |
0:f1834a63f7c1
|
943
|
/* Set the DMA Base and the DMA Burst Length */
|
| Sergunb |
0:f1834a63f7c1
|
944
|
TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
|
| Sergunb |
0:f1834a63f7c1
|
945
|
}
|
| Sergunb |
0:f1834a63f7c1
|
946
|
|
| Sergunb |
0:f1834a63f7c1
|
947
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
948
|
* @brief Enables or disables the TIMx's DMA Requests.
|
| Sergunb |
0:f1834a63f7c1
|
949
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 15, 16 or 17
|
| Sergunb |
0:f1834a63f7c1
|
950
|
* to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
951
|
* @param TIM_DMASource: specifies the DMA Request sources.
|
| Sergunb |
0:f1834a63f7c1
|
952
|
* This parameter can be any combination of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
953
|
* @arg TIM_DMA_Update: TIM update Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
954
|
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
|
| Sergunb |
0:f1834a63f7c1
|
955
|
* @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
|
| Sergunb |
0:f1834a63f7c1
|
956
|
* @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
|
| Sergunb |
0:f1834a63f7c1
|
957
|
* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
|
| Sergunb |
0:f1834a63f7c1
|
958
|
* @arg TIM_DMA_COM: TIM Commutation DMA source
|
| Sergunb |
0:f1834a63f7c1
|
959
|
* @arg TIM_DMA_Trigger: TIM Trigger DMA source
|
| Sergunb |
0:f1834a63f7c1
|
960
|
* @param NewState: new state of the DMA Request sources.
|
| Sergunb |
0:f1834a63f7c1
|
961
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
962
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
963
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
964
|
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
965
|
{
|
| Sergunb |
0:f1834a63f7c1
|
966
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
967
|
assert_param(IS_TIM_LIST9_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
968
|
assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
|
| Sergunb |
0:f1834a63f7c1
|
969
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
970
|
|
| Sergunb |
0:f1834a63f7c1
|
971
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
972
|
{
|
| Sergunb |
0:f1834a63f7c1
|
973
|
/* Enable the DMA sources */
|
| Sergunb |
0:f1834a63f7c1
|
974
|
TIMx->DIER |= TIM_DMASource;
|
| Sergunb |
0:f1834a63f7c1
|
975
|
}
|
| Sergunb |
0:f1834a63f7c1
|
976
|
else
|
| Sergunb |
0:f1834a63f7c1
|
977
|
{
|
| Sergunb |
0:f1834a63f7c1
|
978
|
/* Disable the DMA sources */
|
| Sergunb |
0:f1834a63f7c1
|
979
|
TIMx->DIER &= (uint16_t)~TIM_DMASource;
|
| Sergunb |
0:f1834a63f7c1
|
980
|
}
|
| Sergunb |
0:f1834a63f7c1
|
981
|
}
|
| Sergunb |
0:f1834a63f7c1
|
982
|
|
| Sergunb |
0:f1834a63f7c1
|
983
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
984
|
* @brief Configures the TIMx internal Clock
|
| Sergunb |
0:f1834a63f7c1
|
985
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15
|
| Sergunb |
0:f1834a63f7c1
|
986
|
* to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
987
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
988
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
989
|
void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
|
| Sergunb |
0:f1834a63f7c1
|
990
|
{
|
| Sergunb |
0:f1834a63f7c1
|
991
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
992
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
993
|
/* Disable slave mode to clock the prescaler directly with the internal clock */
|
| Sergunb |
0:f1834a63f7c1
|
994
|
TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
|
| Sergunb |
0:f1834a63f7c1
|
995
|
}
|
| Sergunb |
0:f1834a63f7c1
|
996
|
|
| Sergunb |
0:f1834a63f7c1
|
997
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
998
|
* @brief Configures the TIMx Internal Trigger as External Clock
|
| Sergunb |
0:f1834a63f7c1
|
999
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1000
|
* @param TIM_ITRSource: Trigger source.
|
| Sergunb |
0:f1834a63f7c1
|
1001
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1002
|
* @param TIM_TS_ITR0: Internal Trigger 0
|
| Sergunb |
0:f1834a63f7c1
|
1003
|
* @param TIM_TS_ITR1: Internal Trigger 1
|
| Sergunb |
0:f1834a63f7c1
|
1004
|
* @param TIM_TS_ITR2: Internal Trigger 2
|
| Sergunb |
0:f1834a63f7c1
|
1005
|
* @param TIM_TS_ITR3: Internal Trigger 3
|
| Sergunb |
0:f1834a63f7c1
|
1006
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1007
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1008
|
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
|
| Sergunb |
0:f1834a63f7c1
|
1009
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1010
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1011
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1012
|
assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
|
| Sergunb |
0:f1834a63f7c1
|
1013
|
/* Select the Internal Trigger */
|
| Sergunb |
0:f1834a63f7c1
|
1014
|
TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
|
| Sergunb |
0:f1834a63f7c1
|
1015
|
/* Select the External clock mode1 */
|
| Sergunb |
0:f1834a63f7c1
|
1016
|
TIMx->SMCR |= TIM_SlaveMode_External1;
|
| Sergunb |
0:f1834a63f7c1
|
1017
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1018
|
|
| Sergunb |
0:f1834a63f7c1
|
1019
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1020
|
* @brief Configures the TIMx Trigger as External Clock
|
| Sergunb |
0:f1834a63f7c1
|
1021
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1022
|
* @param TIM_TIxExternalCLKSource: Trigger source.
|
| Sergunb |
0:f1834a63f7c1
|
1023
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1024
|
* @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
|
| Sergunb |
0:f1834a63f7c1
|
1025
|
* @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
|
| Sergunb |
0:f1834a63f7c1
|
1026
|
* @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
|
| Sergunb |
0:f1834a63f7c1
|
1027
|
* @param TIM_ICPolarity: specifies the TIx Polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1028
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1029
|
* @arg TIM_ICPolarity_Rising
|
| Sergunb |
0:f1834a63f7c1
|
1030
|
* @arg TIM_ICPolarity_Falling
|
| Sergunb |
0:f1834a63f7c1
|
1031
|
* @param ICFilter : specifies the filter value.
|
| Sergunb |
0:f1834a63f7c1
|
1032
|
* This parameter must be a value between 0x0 and 0xF.
|
| Sergunb |
0:f1834a63f7c1
|
1033
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1034
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1035
|
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
|
| Sergunb |
0:f1834a63f7c1
|
1036
|
uint16_t TIM_ICPolarity, uint16_t ICFilter)
|
| Sergunb |
0:f1834a63f7c1
|
1037
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1038
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1039
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1040
|
assert_param(IS_TIM_TIXCLK_SOURCE(TIM_TIxExternalCLKSource));
|
| Sergunb |
0:f1834a63f7c1
|
1041
|
assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1042
|
assert_param(IS_TIM_IC_FILTER(ICFilter));
|
| Sergunb |
0:f1834a63f7c1
|
1043
|
/* Configure the Timer Input Clock Source */
|
| Sergunb |
0:f1834a63f7c1
|
1044
|
if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
|
| Sergunb |
0:f1834a63f7c1
|
1045
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1046
|
TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
1047
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1048
|
else
|
| Sergunb |
0:f1834a63f7c1
|
1049
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1050
|
TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
1051
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1052
|
/* Select the Trigger source */
|
| Sergunb |
0:f1834a63f7c1
|
1053
|
TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
|
| Sergunb |
0:f1834a63f7c1
|
1054
|
/* Select the External clock mode1 */
|
| Sergunb |
0:f1834a63f7c1
|
1055
|
TIMx->SMCR |= TIM_SlaveMode_External1;
|
| Sergunb |
0:f1834a63f7c1
|
1056
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1057
|
|
| Sergunb |
0:f1834a63f7c1
|
1058
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1059
|
* @brief Configures the External clock Mode1
|
| Sergunb |
0:f1834a63f7c1
|
1060
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1061
|
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
| Sergunb |
0:f1834a63f7c1
|
1062
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1063
|
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
| Sergunb |
0:f1834a63f7c1
|
1064
|
* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
|
| Sergunb |
0:f1834a63f7c1
|
1065
|
* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
|
| Sergunb |
0:f1834a63f7c1
|
1066
|
* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
|
| Sergunb |
0:f1834a63f7c1
|
1067
|
* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1068
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1069
|
* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
|
| Sergunb |
0:f1834a63f7c1
|
1070
|
* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
|
| Sergunb |
0:f1834a63f7c1
|
1071
|
* @param ExtTRGFilter: External Trigger Filter.
|
| Sergunb |
0:f1834a63f7c1
|
1072
|
* This parameter must be a value between 0x00 and 0x0F
|
| Sergunb |
0:f1834a63f7c1
|
1073
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1074
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1075
|
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
| Sergunb |
0:f1834a63f7c1
|
1076
|
uint16_t ExtTRGFilter)
|
| Sergunb |
0:f1834a63f7c1
|
1077
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1078
|
uint16_t tmpsmcr = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1079
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1080
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1081
|
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
|
| Sergunb |
0:f1834a63f7c1
|
1082
|
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1083
|
assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
|
| Sergunb |
0:f1834a63f7c1
|
1084
|
/* Configure the ETR Clock source */
|
| Sergunb |
0:f1834a63f7c1
|
1085
|
TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
|
| Sergunb |
0:f1834a63f7c1
|
1086
|
|
| Sergunb |
0:f1834a63f7c1
|
1087
|
/* Get the TIMx SMCR register value */
|
| Sergunb |
0:f1834a63f7c1
|
1088
|
tmpsmcr = TIMx->SMCR;
|
| Sergunb |
0:f1834a63f7c1
|
1089
|
/* Reset the SMS Bits */
|
| Sergunb |
0:f1834a63f7c1
|
1090
|
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
|
| Sergunb |
0:f1834a63f7c1
|
1091
|
/* Select the External clock mode1 */
|
| Sergunb |
0:f1834a63f7c1
|
1092
|
tmpsmcr |= TIM_SlaveMode_External1;
|
| Sergunb |
0:f1834a63f7c1
|
1093
|
/* Select the Trigger selection : ETRF */
|
| Sergunb |
0:f1834a63f7c1
|
1094
|
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
|
| Sergunb |
0:f1834a63f7c1
|
1095
|
tmpsmcr |= TIM_TS_ETRF;
|
| Sergunb |
0:f1834a63f7c1
|
1096
|
/* Write to TIMx SMCR */
|
| Sergunb |
0:f1834a63f7c1
|
1097
|
TIMx->SMCR = tmpsmcr;
|
| Sergunb |
0:f1834a63f7c1
|
1098
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1099
|
|
| Sergunb |
0:f1834a63f7c1
|
1100
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1101
|
* @brief Configures the External clock Mode2
|
| Sergunb |
0:f1834a63f7c1
|
1102
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1103
|
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
| Sergunb |
0:f1834a63f7c1
|
1104
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1105
|
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
| Sergunb |
0:f1834a63f7c1
|
1106
|
* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
|
| Sergunb |
0:f1834a63f7c1
|
1107
|
* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
|
| Sergunb |
0:f1834a63f7c1
|
1108
|
* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
|
| Sergunb |
0:f1834a63f7c1
|
1109
|
* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1110
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1111
|
* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
|
| Sergunb |
0:f1834a63f7c1
|
1112
|
* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
|
| Sergunb |
0:f1834a63f7c1
|
1113
|
* @param ExtTRGFilter: External Trigger Filter.
|
| Sergunb |
0:f1834a63f7c1
|
1114
|
* This parameter must be a value between 0x00 and 0x0F
|
| Sergunb |
0:f1834a63f7c1
|
1115
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1116
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1117
|
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
|
| Sergunb |
0:f1834a63f7c1
|
1118
|
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
|
| Sergunb |
0:f1834a63f7c1
|
1119
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1120
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1121
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1122
|
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
|
| Sergunb |
0:f1834a63f7c1
|
1123
|
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1124
|
assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
|
| Sergunb |
0:f1834a63f7c1
|
1125
|
/* Configure the ETR Clock source */
|
| Sergunb |
0:f1834a63f7c1
|
1126
|
TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
|
| Sergunb |
0:f1834a63f7c1
|
1127
|
/* Enable the External clock mode2 */
|
| Sergunb |
0:f1834a63f7c1
|
1128
|
TIMx->SMCR |= TIM_SMCR_ECE;
|
| Sergunb |
0:f1834a63f7c1
|
1129
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1130
|
|
| Sergunb |
0:f1834a63f7c1
|
1131
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1132
|
* @brief Configures the TIMx External Trigger (ETR).
|
| Sergunb |
0:f1834a63f7c1
|
1133
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1134
|
* @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
|
| Sergunb |
0:f1834a63f7c1
|
1135
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1136
|
* @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
|
| Sergunb |
0:f1834a63f7c1
|
1137
|
* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
|
| Sergunb |
0:f1834a63f7c1
|
1138
|
* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
|
| Sergunb |
0:f1834a63f7c1
|
1139
|
* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
|
| Sergunb |
0:f1834a63f7c1
|
1140
|
* @param TIM_ExtTRGPolarity: The external Trigger Polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1141
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1142
|
* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
|
| Sergunb |
0:f1834a63f7c1
|
1143
|
* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
|
| Sergunb |
0:f1834a63f7c1
|
1144
|
* @param ExtTRGFilter: External Trigger Filter.
|
| Sergunb |
0:f1834a63f7c1
|
1145
|
* This parameter must be a value between 0x00 and 0x0F
|
| Sergunb |
0:f1834a63f7c1
|
1146
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1147
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1148
|
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
| Sergunb |
0:f1834a63f7c1
|
1149
|
uint16_t ExtTRGFilter)
|
| Sergunb |
0:f1834a63f7c1
|
1150
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1151
|
uint16_t tmpsmcr = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1152
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1153
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1154
|
assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
|
| Sergunb |
0:f1834a63f7c1
|
1155
|
assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1156
|
assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
|
| Sergunb |
0:f1834a63f7c1
|
1157
|
tmpsmcr = TIMx->SMCR;
|
| Sergunb |
0:f1834a63f7c1
|
1158
|
/* Reset the ETR Bits */
|
| Sergunb |
0:f1834a63f7c1
|
1159
|
tmpsmcr &= SMCR_ETR_Mask;
|
| Sergunb |
0:f1834a63f7c1
|
1160
|
/* Set the Prescaler, the Filter value and the Polarity */
|
| Sergunb |
0:f1834a63f7c1
|
1161
|
tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
|
| Sergunb |
0:f1834a63f7c1
|
1162
|
/* Write to TIMx SMCR */
|
| Sergunb |
0:f1834a63f7c1
|
1163
|
TIMx->SMCR = tmpsmcr;
|
| Sergunb |
0:f1834a63f7c1
|
1164
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1165
|
|
| Sergunb |
0:f1834a63f7c1
|
1166
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1167
|
* @brief Configures the TIMx Prescaler.
|
| Sergunb |
0:f1834a63f7c1
|
1168
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1169
|
* @param Prescaler: specifies the Prescaler Register value
|
| Sergunb |
0:f1834a63f7c1
|
1170
|
* @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
|
| Sergunb |
0:f1834a63f7c1
|
1171
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1172
|
* @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
|
| Sergunb |
0:f1834a63f7c1
|
1173
|
* @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediately.
|
| Sergunb |
0:f1834a63f7c1
|
1174
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1175
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1176
|
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
|
| Sergunb |
0:f1834a63f7c1
|
1177
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1178
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1179
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1180
|
assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
|
| Sergunb |
0:f1834a63f7c1
|
1181
|
/* Set the Prescaler value */
|
| Sergunb |
0:f1834a63f7c1
|
1182
|
TIMx->PSC = Prescaler;
|
| Sergunb |
0:f1834a63f7c1
|
1183
|
/* Set or reset the UG Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1184
|
TIMx->EGR = TIM_PSCReloadMode;
|
| Sergunb |
0:f1834a63f7c1
|
1185
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1186
|
|
| Sergunb |
0:f1834a63f7c1
|
1187
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1188
|
* @brief Specifies the TIMx Counter Mode to be used.
|
| Sergunb |
0:f1834a63f7c1
|
1189
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1190
|
* @param TIM_CounterMode: specifies the Counter Mode to be used
|
| Sergunb |
0:f1834a63f7c1
|
1191
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1192
|
* @arg TIM_CounterMode_Up: TIM Up Counting Mode
|
| Sergunb |
0:f1834a63f7c1
|
1193
|
* @arg TIM_CounterMode_Down: TIM Down Counting Mode
|
| Sergunb |
0:f1834a63f7c1
|
1194
|
* @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
|
| Sergunb |
0:f1834a63f7c1
|
1195
|
* @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
|
| Sergunb |
0:f1834a63f7c1
|
1196
|
* @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
|
| Sergunb |
0:f1834a63f7c1
|
1197
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1198
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1199
|
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
|
| Sergunb |
0:f1834a63f7c1
|
1200
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1201
|
uint16_t tmpcr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1202
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1203
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1204
|
assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
|
| Sergunb |
0:f1834a63f7c1
|
1205
|
tmpcr1 = TIMx->CR1;
|
| Sergunb |
0:f1834a63f7c1
|
1206
|
/* Reset the CMS and DIR Bits */
|
| Sergunb |
0:f1834a63f7c1
|
1207
|
tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
|
| Sergunb |
0:f1834a63f7c1
|
1208
|
/* Set the Counter Mode */
|
| Sergunb |
0:f1834a63f7c1
|
1209
|
tmpcr1 |= TIM_CounterMode;
|
| Sergunb |
0:f1834a63f7c1
|
1210
|
/* Write to TIMx CR1 register */
|
| Sergunb |
0:f1834a63f7c1
|
1211
|
TIMx->CR1 = tmpcr1;
|
| Sergunb |
0:f1834a63f7c1
|
1212
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1213
|
|
| Sergunb |
0:f1834a63f7c1
|
1214
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1215
|
* @brief Selects the Input Trigger source
|
| Sergunb |
0:f1834a63f7c1
|
1216
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1217
|
* @param TIM_InputTriggerSource: The Input Trigger source.
|
| Sergunb |
0:f1834a63f7c1
|
1218
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1219
|
* @arg TIM_TS_ITR0: Internal Trigger 0
|
| Sergunb |
0:f1834a63f7c1
|
1220
|
* @arg TIM_TS_ITR1: Internal Trigger 1
|
| Sergunb |
0:f1834a63f7c1
|
1221
|
* @arg TIM_TS_ITR2: Internal Trigger 2
|
| Sergunb |
0:f1834a63f7c1
|
1222
|
* @arg TIM_TS_ITR3: Internal Trigger 3
|
| Sergunb |
0:f1834a63f7c1
|
1223
|
* @arg TIM_TS_TI1F_ED: TI1 Edge Detector
|
| Sergunb |
0:f1834a63f7c1
|
1224
|
* @arg TIM_TS_TI1FP1: Filtered Timer Input 1
|
| Sergunb |
0:f1834a63f7c1
|
1225
|
* @arg TIM_TS_TI2FP2: Filtered Timer Input 2
|
| Sergunb |
0:f1834a63f7c1
|
1226
|
* @arg TIM_TS_ETRF: External Trigger input
|
| Sergunb |
0:f1834a63f7c1
|
1227
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1228
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1229
|
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
|
| Sergunb |
0:f1834a63f7c1
|
1230
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1231
|
uint16_t tmpsmcr = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1232
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1233
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1234
|
assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
|
| Sergunb |
0:f1834a63f7c1
|
1235
|
/* Get the TIMx SMCR register value */
|
| Sergunb |
0:f1834a63f7c1
|
1236
|
tmpsmcr = TIMx->SMCR;
|
| Sergunb |
0:f1834a63f7c1
|
1237
|
/* Reset the TS Bits */
|
| Sergunb |
0:f1834a63f7c1
|
1238
|
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
|
| Sergunb |
0:f1834a63f7c1
|
1239
|
/* Set the Input Trigger source */
|
| Sergunb |
0:f1834a63f7c1
|
1240
|
tmpsmcr |= TIM_InputTriggerSource;
|
| Sergunb |
0:f1834a63f7c1
|
1241
|
/* Write to TIMx SMCR */
|
| Sergunb |
0:f1834a63f7c1
|
1242
|
TIMx->SMCR = tmpsmcr;
|
| Sergunb |
0:f1834a63f7c1
|
1243
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1244
|
|
| Sergunb |
0:f1834a63f7c1
|
1245
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1246
|
* @brief Configures the TIMx Encoder Interface.
|
| Sergunb |
0:f1834a63f7c1
|
1247
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1248
|
* @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
|
| Sergunb |
0:f1834a63f7c1
|
1249
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1250
|
* @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
|
| Sergunb |
0:f1834a63f7c1
|
1251
|
* @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
|
| Sergunb |
0:f1834a63f7c1
|
1252
|
* @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
|
| Sergunb |
0:f1834a63f7c1
|
1253
|
* on the level of the other input.
|
| Sergunb |
0:f1834a63f7c1
|
1254
|
* @param TIM_IC1Polarity: specifies the IC1 Polarity
|
| Sergunb |
0:f1834a63f7c1
|
1255
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1256
|
* @arg TIM_ICPolarity_Falling: IC Falling edge.
|
| Sergunb |
0:f1834a63f7c1
|
1257
|
* @arg TIM_ICPolarity_Rising: IC Rising edge.
|
| Sergunb |
0:f1834a63f7c1
|
1258
|
* @param TIM_IC2Polarity: specifies the IC2 Polarity
|
| Sergunb |
0:f1834a63f7c1
|
1259
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1260
|
* @arg TIM_ICPolarity_Falling: IC Falling edge.
|
| Sergunb |
0:f1834a63f7c1
|
1261
|
* @arg TIM_ICPolarity_Rising: IC Rising edge.
|
| Sergunb |
0:f1834a63f7c1
|
1262
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1263
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1264
|
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
|
| Sergunb |
0:f1834a63f7c1
|
1265
|
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
|
| Sergunb |
0:f1834a63f7c1
|
1266
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1267
|
uint16_t tmpsmcr = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1268
|
uint16_t tmpccmr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1269
|
uint16_t tmpccer = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1270
|
|
| Sergunb |
0:f1834a63f7c1
|
1271
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1272
|
assert_param(IS_TIM_LIST5_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1273
|
assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
|
| Sergunb |
0:f1834a63f7c1
|
1274
|
assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
|
| Sergunb |
0:f1834a63f7c1
|
1275
|
assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
|
| Sergunb |
0:f1834a63f7c1
|
1276
|
|
| Sergunb |
0:f1834a63f7c1
|
1277
|
/* Get the TIMx SMCR register value */
|
| Sergunb |
0:f1834a63f7c1
|
1278
|
tmpsmcr = TIMx->SMCR;
|
| Sergunb |
0:f1834a63f7c1
|
1279
|
|
| Sergunb |
0:f1834a63f7c1
|
1280
|
/* Get the TIMx CCMR1 register value */
|
| Sergunb |
0:f1834a63f7c1
|
1281
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
1282
|
|
| Sergunb |
0:f1834a63f7c1
|
1283
|
/* Get the TIMx CCER register value */
|
| Sergunb |
0:f1834a63f7c1
|
1284
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
1285
|
|
| Sergunb |
0:f1834a63f7c1
|
1286
|
/* Set the encoder Mode */
|
| Sergunb |
0:f1834a63f7c1
|
1287
|
tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
|
| Sergunb |
0:f1834a63f7c1
|
1288
|
tmpsmcr |= TIM_EncoderMode;
|
| Sergunb |
0:f1834a63f7c1
|
1289
|
|
| Sergunb |
0:f1834a63f7c1
|
1290
|
/* Select the Capture Compare 1 and the Capture Compare 2 as input */
|
| Sergunb |
0:f1834a63f7c1
|
1291
|
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
|
| Sergunb |
0:f1834a63f7c1
|
1292
|
tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
|
| Sergunb |
0:f1834a63f7c1
|
1293
|
|
| Sergunb |
0:f1834a63f7c1
|
1294
|
/* Set the TI1 and the TI2 Polarities */
|
| Sergunb |
0:f1834a63f7c1
|
1295
|
tmpccer &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCER_CC1P)) & ((uint16_t)~((uint16_t)TIM_CCER_CC2P)));
|
| Sergunb |
0:f1834a63f7c1
|
1296
|
tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
|
| Sergunb |
0:f1834a63f7c1
|
1297
|
|
| Sergunb |
0:f1834a63f7c1
|
1298
|
/* Write to TIMx SMCR */
|
| Sergunb |
0:f1834a63f7c1
|
1299
|
TIMx->SMCR = tmpsmcr;
|
| Sergunb |
0:f1834a63f7c1
|
1300
|
/* Write to TIMx CCMR1 */
|
| Sergunb |
0:f1834a63f7c1
|
1301
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
1302
|
/* Write to TIMx CCER */
|
| Sergunb |
0:f1834a63f7c1
|
1303
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
1304
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1305
|
|
| Sergunb |
0:f1834a63f7c1
|
1306
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1307
|
* @brief Forces the TIMx output 1 waveform to active or inactive level.
|
| Sergunb |
0:f1834a63f7c1
|
1308
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1309
|
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
|
| Sergunb |
0:f1834a63f7c1
|
1310
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1311
|
* @arg TIM_ForcedAction_Active: Force active level on OC1REF
|
| Sergunb |
0:f1834a63f7c1
|
1312
|
* @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
|
| Sergunb |
0:f1834a63f7c1
|
1313
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1314
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1315
|
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
|
| Sergunb |
0:f1834a63f7c1
|
1316
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1317
|
uint16_t tmpccmr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1318
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1319
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1320
|
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
|
| Sergunb |
0:f1834a63f7c1
|
1321
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
1322
|
/* Reset the OC1M Bits */
|
| Sergunb |
0:f1834a63f7c1
|
1323
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
|
| Sergunb |
0:f1834a63f7c1
|
1324
|
/* Configure The Forced output Mode */
|
| Sergunb |
0:f1834a63f7c1
|
1325
|
tmpccmr1 |= TIM_ForcedAction;
|
| Sergunb |
0:f1834a63f7c1
|
1326
|
/* Write to TIMx CCMR1 register */
|
| Sergunb |
0:f1834a63f7c1
|
1327
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
1328
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1329
|
|
| Sergunb |
0:f1834a63f7c1
|
1330
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1331
|
* @brief Forces the TIMx output 2 waveform to active or inactive level.
|
| Sergunb |
0:f1834a63f7c1
|
1332
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1333
|
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
|
| Sergunb |
0:f1834a63f7c1
|
1334
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1335
|
* @arg TIM_ForcedAction_Active: Force active level on OC2REF
|
| Sergunb |
0:f1834a63f7c1
|
1336
|
* @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
|
| Sergunb |
0:f1834a63f7c1
|
1337
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1338
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1339
|
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
|
| Sergunb |
0:f1834a63f7c1
|
1340
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1341
|
uint16_t tmpccmr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1342
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1343
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1344
|
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
|
| Sergunb |
0:f1834a63f7c1
|
1345
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
1346
|
/* Reset the OC2M Bits */
|
| Sergunb |
0:f1834a63f7c1
|
1347
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
|
| Sergunb |
0:f1834a63f7c1
|
1348
|
/* Configure The Forced output Mode */
|
| Sergunb |
0:f1834a63f7c1
|
1349
|
tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1350
|
/* Write to TIMx CCMR1 register */
|
| Sergunb |
0:f1834a63f7c1
|
1351
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
1352
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1353
|
|
| Sergunb |
0:f1834a63f7c1
|
1354
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1355
|
* @brief Forces the TIMx output 3 waveform to active or inactive level.
|
| Sergunb |
0:f1834a63f7c1
|
1356
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1357
|
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
|
| Sergunb |
0:f1834a63f7c1
|
1358
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1359
|
* @arg TIM_ForcedAction_Active: Force active level on OC3REF
|
| Sergunb |
0:f1834a63f7c1
|
1360
|
* @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
|
| Sergunb |
0:f1834a63f7c1
|
1361
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1362
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1363
|
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
|
| Sergunb |
0:f1834a63f7c1
|
1364
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1365
|
uint16_t tmpccmr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1366
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1367
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1368
|
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
|
| Sergunb |
0:f1834a63f7c1
|
1369
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
1370
|
/* Reset the OC1M Bits */
|
| Sergunb |
0:f1834a63f7c1
|
1371
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
|
| Sergunb |
0:f1834a63f7c1
|
1372
|
/* Configure The Forced output Mode */
|
| Sergunb |
0:f1834a63f7c1
|
1373
|
tmpccmr2 |= TIM_ForcedAction;
|
| Sergunb |
0:f1834a63f7c1
|
1374
|
/* Write to TIMx CCMR2 register */
|
| Sergunb |
0:f1834a63f7c1
|
1375
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
1376
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1377
|
|
| Sergunb |
0:f1834a63f7c1
|
1378
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1379
|
* @brief Forces the TIMx output 4 waveform to active or inactive level.
|
| Sergunb |
0:f1834a63f7c1
|
1380
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1381
|
* @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
|
| Sergunb |
0:f1834a63f7c1
|
1382
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1383
|
* @arg TIM_ForcedAction_Active: Force active level on OC4REF
|
| Sergunb |
0:f1834a63f7c1
|
1384
|
* @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
|
| Sergunb |
0:f1834a63f7c1
|
1385
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1386
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1387
|
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
|
| Sergunb |
0:f1834a63f7c1
|
1388
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1389
|
uint16_t tmpccmr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1390
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1391
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1392
|
assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
|
| Sergunb |
0:f1834a63f7c1
|
1393
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
1394
|
/* Reset the OC2M Bits */
|
| Sergunb |
0:f1834a63f7c1
|
1395
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
|
| Sergunb |
0:f1834a63f7c1
|
1396
|
/* Configure The Forced output Mode */
|
| Sergunb |
0:f1834a63f7c1
|
1397
|
tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1398
|
/* Write to TIMx CCMR2 register */
|
| Sergunb |
0:f1834a63f7c1
|
1399
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
1400
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1401
|
|
| Sergunb |
0:f1834a63f7c1
|
1402
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1403
|
* @brief Enables or disables TIMx peripheral Preload register on ARR.
|
| Sergunb |
0:f1834a63f7c1
|
1404
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1405
|
* @param NewState: new state of the TIMx peripheral Preload register
|
| Sergunb |
0:f1834a63f7c1
|
1406
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
1407
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1408
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1409
|
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
1410
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1411
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1412
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1413
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
1414
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
1415
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1416
|
/* Set the ARR Preload Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1417
|
TIMx->CR1 |= TIM_CR1_ARPE;
|
| Sergunb |
0:f1834a63f7c1
|
1418
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1419
|
else
|
| Sergunb |
0:f1834a63f7c1
|
1420
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1421
|
/* Reset the ARR Preload Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1422
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
|
| Sergunb |
0:f1834a63f7c1
|
1423
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1424
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1425
|
|
| Sergunb |
0:f1834a63f7c1
|
1426
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1427
|
* @brief Selects the TIM peripheral Commutation event.
|
| Sergunb |
0:f1834a63f7c1
|
1428
|
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIMx peripheral
|
| Sergunb |
0:f1834a63f7c1
|
1429
|
* @param NewState: new state of the Commutation event.
|
| Sergunb |
0:f1834a63f7c1
|
1430
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
1431
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1432
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1433
|
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
1434
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1435
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1436
|
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1437
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
1438
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
1439
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1440
|
/* Set the COM Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1441
|
TIMx->CR2 |= TIM_CR2_CCUS;
|
| Sergunb |
0:f1834a63f7c1
|
1442
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1443
|
else
|
| Sergunb |
0:f1834a63f7c1
|
1444
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1445
|
/* Reset the COM Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1446
|
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
|
| Sergunb |
0:f1834a63f7c1
|
1447
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1448
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1449
|
|
| Sergunb |
0:f1834a63f7c1
|
1450
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1451
|
* @brief Selects the TIMx peripheral Capture Compare DMA source.
|
| Sergunb |
0:f1834a63f7c1
|
1452
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 15, 16 or 17 to select
|
| Sergunb |
0:f1834a63f7c1
|
1453
|
* the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1454
|
* @param NewState: new state of the Capture Compare DMA source
|
| Sergunb |
0:f1834a63f7c1
|
1455
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
1456
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1457
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1458
|
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
1459
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1460
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1461
|
assert_param(IS_TIM_LIST4_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1462
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
1463
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
1464
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1465
|
/* Set the CCDS Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1466
|
TIMx->CR2 |= TIM_CR2_CCDS;
|
| Sergunb |
0:f1834a63f7c1
|
1467
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1468
|
else
|
| Sergunb |
0:f1834a63f7c1
|
1469
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1470
|
/* Reset the CCDS Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1471
|
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
|
| Sergunb |
0:f1834a63f7c1
|
1472
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1473
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1474
|
|
| Sergunb |
0:f1834a63f7c1
|
1475
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1476
|
* @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
|
| Sergunb |
0:f1834a63f7c1
|
1477
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8 or 15
|
| Sergunb |
0:f1834a63f7c1
|
1478
|
* to select the TIMx peripheral
|
| Sergunb |
0:f1834a63f7c1
|
1479
|
* @param NewState: new state of the Capture Compare Preload Control bit
|
| Sergunb |
0:f1834a63f7c1
|
1480
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
1481
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1482
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1483
|
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
1484
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1485
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1486
|
assert_param(IS_TIM_LIST5_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1487
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
1488
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
1489
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1490
|
/* Set the CCPC Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1491
|
TIMx->CR2 |= TIM_CR2_CCPC;
|
| Sergunb |
0:f1834a63f7c1
|
1492
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1493
|
else
|
| Sergunb |
0:f1834a63f7c1
|
1494
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1495
|
/* Reset the CCPC Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1496
|
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
|
| Sergunb |
0:f1834a63f7c1
|
1497
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1498
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1499
|
|
| Sergunb |
0:f1834a63f7c1
|
1500
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1501
|
* @brief Enables or disables the TIMx peripheral Preload register on CCR1.
|
| Sergunb |
0:f1834a63f7c1
|
1502
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1503
|
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
|
| Sergunb |
0:f1834a63f7c1
|
1504
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1505
|
* @arg TIM_OCPreload_Enable
|
| Sergunb |
0:f1834a63f7c1
|
1506
|
* @arg TIM_OCPreload_Disable
|
| Sergunb |
0:f1834a63f7c1
|
1507
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1508
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1509
|
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
|
| Sergunb |
0:f1834a63f7c1
|
1510
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1511
|
uint16_t tmpccmr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1512
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1513
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1514
|
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
|
| Sergunb |
0:f1834a63f7c1
|
1515
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
1516
|
/* Reset the OC1PE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1517
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
|
| Sergunb |
0:f1834a63f7c1
|
1518
|
/* Enable or Disable the Output Compare Preload feature */
|
| Sergunb |
0:f1834a63f7c1
|
1519
|
tmpccmr1 |= TIM_OCPreload;
|
| Sergunb |
0:f1834a63f7c1
|
1520
|
/* Write to TIMx CCMR1 register */
|
| Sergunb |
0:f1834a63f7c1
|
1521
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
1522
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1523
|
|
| Sergunb |
0:f1834a63f7c1
|
1524
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1525
|
* @brief Enables or disables the TIMx peripheral Preload register on CCR2.
|
| Sergunb |
0:f1834a63f7c1
|
1526
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
|
| Sergunb |
0:f1834a63f7c1
|
1527
|
* the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1528
|
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
|
| Sergunb |
0:f1834a63f7c1
|
1529
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1530
|
* @arg TIM_OCPreload_Enable
|
| Sergunb |
0:f1834a63f7c1
|
1531
|
* @arg TIM_OCPreload_Disable
|
| Sergunb |
0:f1834a63f7c1
|
1532
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1533
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1534
|
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
|
| Sergunb |
0:f1834a63f7c1
|
1535
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1536
|
uint16_t tmpccmr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1537
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1538
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1539
|
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
|
| Sergunb |
0:f1834a63f7c1
|
1540
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
1541
|
/* Reset the OC2PE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1542
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
|
| Sergunb |
0:f1834a63f7c1
|
1543
|
/* Enable or Disable the Output Compare Preload feature */
|
| Sergunb |
0:f1834a63f7c1
|
1544
|
tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1545
|
/* Write to TIMx CCMR1 register */
|
| Sergunb |
0:f1834a63f7c1
|
1546
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
1547
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1548
|
|
| Sergunb |
0:f1834a63f7c1
|
1549
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1550
|
* @brief Enables or disables the TIMx peripheral Preload register on CCR3.
|
| Sergunb |
0:f1834a63f7c1
|
1551
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1552
|
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
|
| Sergunb |
0:f1834a63f7c1
|
1553
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1554
|
* @arg TIM_OCPreload_Enable
|
| Sergunb |
0:f1834a63f7c1
|
1555
|
* @arg TIM_OCPreload_Disable
|
| Sergunb |
0:f1834a63f7c1
|
1556
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1557
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1558
|
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
|
| Sergunb |
0:f1834a63f7c1
|
1559
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1560
|
uint16_t tmpccmr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1561
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1562
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1563
|
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
|
| Sergunb |
0:f1834a63f7c1
|
1564
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
1565
|
/* Reset the OC3PE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1566
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
|
| Sergunb |
0:f1834a63f7c1
|
1567
|
/* Enable or Disable the Output Compare Preload feature */
|
| Sergunb |
0:f1834a63f7c1
|
1568
|
tmpccmr2 |= TIM_OCPreload;
|
| Sergunb |
0:f1834a63f7c1
|
1569
|
/* Write to TIMx CCMR2 register */
|
| Sergunb |
0:f1834a63f7c1
|
1570
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
1571
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1572
|
|
| Sergunb |
0:f1834a63f7c1
|
1573
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1574
|
* @brief Enables or disables the TIMx peripheral Preload register on CCR4.
|
| Sergunb |
0:f1834a63f7c1
|
1575
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1576
|
* @param TIM_OCPreload: new state of the TIMx peripheral Preload register
|
| Sergunb |
0:f1834a63f7c1
|
1577
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1578
|
* @arg TIM_OCPreload_Enable
|
| Sergunb |
0:f1834a63f7c1
|
1579
|
* @arg TIM_OCPreload_Disable
|
| Sergunb |
0:f1834a63f7c1
|
1580
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1581
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1582
|
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
|
| Sergunb |
0:f1834a63f7c1
|
1583
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1584
|
uint16_t tmpccmr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1585
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1586
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1587
|
assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
|
| Sergunb |
0:f1834a63f7c1
|
1588
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
1589
|
/* Reset the OC4PE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1590
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
|
| Sergunb |
0:f1834a63f7c1
|
1591
|
/* Enable or Disable the Output Compare Preload feature */
|
| Sergunb |
0:f1834a63f7c1
|
1592
|
tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1593
|
/* Write to TIMx CCMR2 register */
|
| Sergunb |
0:f1834a63f7c1
|
1594
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
1595
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1596
|
|
| Sergunb |
0:f1834a63f7c1
|
1597
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1598
|
* @brief Configures the TIMx Output Compare 1 Fast feature.
|
| Sergunb |
0:f1834a63f7c1
|
1599
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1600
|
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
|
| Sergunb |
0:f1834a63f7c1
|
1601
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1602
|
* @arg TIM_OCFast_Enable: TIM output compare fast enable
|
| Sergunb |
0:f1834a63f7c1
|
1603
|
* @arg TIM_OCFast_Disable: TIM output compare fast disable
|
| Sergunb |
0:f1834a63f7c1
|
1604
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1605
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1606
|
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
|
| Sergunb |
0:f1834a63f7c1
|
1607
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1608
|
uint16_t tmpccmr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1609
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1610
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1611
|
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
|
| Sergunb |
0:f1834a63f7c1
|
1612
|
/* Get the TIMx CCMR1 register value */
|
| Sergunb |
0:f1834a63f7c1
|
1613
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
1614
|
/* Reset the OC1FE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1615
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
|
| Sergunb |
0:f1834a63f7c1
|
1616
|
/* Enable or Disable the Output Compare Fast Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1617
|
tmpccmr1 |= TIM_OCFast;
|
| Sergunb |
0:f1834a63f7c1
|
1618
|
/* Write to TIMx CCMR1 */
|
| Sergunb |
0:f1834a63f7c1
|
1619
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
1620
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1621
|
|
| Sergunb |
0:f1834a63f7c1
|
1622
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1623
|
* @brief Configures the TIMx Output Compare 2 Fast feature.
|
| Sergunb |
0:f1834a63f7c1
|
1624
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select
|
| Sergunb |
0:f1834a63f7c1
|
1625
|
* the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1626
|
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
|
| Sergunb |
0:f1834a63f7c1
|
1627
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1628
|
* @arg TIM_OCFast_Enable: TIM output compare fast enable
|
| Sergunb |
0:f1834a63f7c1
|
1629
|
* @arg TIM_OCFast_Disable: TIM output compare fast disable
|
| Sergunb |
0:f1834a63f7c1
|
1630
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1631
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1632
|
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
|
| Sergunb |
0:f1834a63f7c1
|
1633
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1634
|
uint16_t tmpccmr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1635
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1636
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1637
|
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
|
| Sergunb |
0:f1834a63f7c1
|
1638
|
/* Get the TIMx CCMR1 register value */
|
| Sergunb |
0:f1834a63f7c1
|
1639
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
1640
|
/* Reset the OC2FE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1641
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
|
| Sergunb |
0:f1834a63f7c1
|
1642
|
/* Enable or Disable the Output Compare Fast Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1643
|
tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1644
|
/* Write to TIMx CCMR1 */
|
| Sergunb |
0:f1834a63f7c1
|
1645
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
1646
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1647
|
|
| Sergunb |
0:f1834a63f7c1
|
1648
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1649
|
* @brief Configures the TIMx Output Compare 3 Fast feature.
|
| Sergunb |
0:f1834a63f7c1
|
1650
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1651
|
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
|
| Sergunb |
0:f1834a63f7c1
|
1652
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1653
|
* @arg TIM_OCFast_Enable: TIM output compare fast enable
|
| Sergunb |
0:f1834a63f7c1
|
1654
|
* @arg TIM_OCFast_Disable: TIM output compare fast disable
|
| Sergunb |
0:f1834a63f7c1
|
1655
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1656
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1657
|
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
|
| Sergunb |
0:f1834a63f7c1
|
1658
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1659
|
uint16_t tmpccmr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1660
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1661
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1662
|
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
|
| Sergunb |
0:f1834a63f7c1
|
1663
|
/* Get the TIMx CCMR2 register value */
|
| Sergunb |
0:f1834a63f7c1
|
1664
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
1665
|
/* Reset the OC3FE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1666
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
|
| Sergunb |
0:f1834a63f7c1
|
1667
|
/* Enable or Disable the Output Compare Fast Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1668
|
tmpccmr2 |= TIM_OCFast;
|
| Sergunb |
0:f1834a63f7c1
|
1669
|
/* Write to TIMx CCMR2 */
|
| Sergunb |
0:f1834a63f7c1
|
1670
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
1671
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1672
|
|
| Sergunb |
0:f1834a63f7c1
|
1673
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1674
|
* @brief Configures the TIMx Output Compare 4 Fast feature.
|
| Sergunb |
0:f1834a63f7c1
|
1675
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1676
|
* @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
|
| Sergunb |
0:f1834a63f7c1
|
1677
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1678
|
* @arg TIM_OCFast_Enable: TIM output compare fast enable
|
| Sergunb |
0:f1834a63f7c1
|
1679
|
* @arg TIM_OCFast_Disable: TIM output compare fast disable
|
| Sergunb |
0:f1834a63f7c1
|
1680
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1681
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1682
|
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
|
| Sergunb |
0:f1834a63f7c1
|
1683
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1684
|
uint16_t tmpccmr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1685
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1686
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1687
|
assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
|
| Sergunb |
0:f1834a63f7c1
|
1688
|
/* Get the TIMx CCMR2 register value */
|
| Sergunb |
0:f1834a63f7c1
|
1689
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
1690
|
/* Reset the OC4FE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1691
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
|
| Sergunb |
0:f1834a63f7c1
|
1692
|
/* Enable or Disable the Output Compare Fast Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1693
|
tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1694
|
/* Write to TIMx CCMR2 */
|
| Sergunb |
0:f1834a63f7c1
|
1695
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
1696
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1697
|
|
| Sergunb |
0:f1834a63f7c1
|
1698
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1699
|
* @brief Clears or safeguards the OCREF1 signal on an external event
|
| Sergunb |
0:f1834a63f7c1
|
1700
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1701
|
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
| Sergunb |
0:f1834a63f7c1
|
1702
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1703
|
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
| Sergunb |
0:f1834a63f7c1
|
1704
|
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
| Sergunb |
0:f1834a63f7c1
|
1705
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1706
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1707
|
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
|
| Sergunb |
0:f1834a63f7c1
|
1708
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1709
|
uint16_t tmpccmr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1710
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1711
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1712
|
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
|
| Sergunb |
0:f1834a63f7c1
|
1713
|
|
| Sergunb |
0:f1834a63f7c1
|
1714
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
1715
|
|
| Sergunb |
0:f1834a63f7c1
|
1716
|
/* Reset the OC1CE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1717
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
|
| Sergunb |
0:f1834a63f7c1
|
1718
|
/* Enable or Disable the Output Compare Clear Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1719
|
tmpccmr1 |= TIM_OCClear;
|
| Sergunb |
0:f1834a63f7c1
|
1720
|
/* Write to TIMx CCMR1 register */
|
| Sergunb |
0:f1834a63f7c1
|
1721
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
1722
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1723
|
|
| Sergunb |
0:f1834a63f7c1
|
1724
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1725
|
* @brief Clears or safeguards the OCREF2 signal on an external event
|
| Sergunb |
0:f1834a63f7c1
|
1726
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1727
|
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
| Sergunb |
0:f1834a63f7c1
|
1728
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1729
|
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
| Sergunb |
0:f1834a63f7c1
|
1730
|
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
| Sergunb |
0:f1834a63f7c1
|
1731
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1732
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1733
|
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
|
| Sergunb |
0:f1834a63f7c1
|
1734
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1735
|
uint16_t tmpccmr1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1736
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1737
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1738
|
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
|
| Sergunb |
0:f1834a63f7c1
|
1739
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
1740
|
/* Reset the OC2CE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1741
|
tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
|
| Sergunb |
0:f1834a63f7c1
|
1742
|
/* Enable or Disable the Output Compare Clear Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1743
|
tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1744
|
/* Write to TIMx CCMR1 register */
|
| Sergunb |
0:f1834a63f7c1
|
1745
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
1746
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1747
|
|
| Sergunb |
0:f1834a63f7c1
|
1748
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1749
|
* @brief Clears or safeguards the OCREF3 signal on an external event
|
| Sergunb |
0:f1834a63f7c1
|
1750
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1751
|
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
| Sergunb |
0:f1834a63f7c1
|
1752
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1753
|
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
| Sergunb |
0:f1834a63f7c1
|
1754
|
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
| Sergunb |
0:f1834a63f7c1
|
1755
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1756
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1757
|
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
|
| Sergunb |
0:f1834a63f7c1
|
1758
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1759
|
uint16_t tmpccmr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1760
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1761
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1762
|
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
|
| Sergunb |
0:f1834a63f7c1
|
1763
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
1764
|
/* Reset the OC3CE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1765
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
|
| Sergunb |
0:f1834a63f7c1
|
1766
|
/* Enable or Disable the Output Compare Clear Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1767
|
tmpccmr2 |= TIM_OCClear;
|
| Sergunb |
0:f1834a63f7c1
|
1768
|
/* Write to TIMx CCMR2 register */
|
| Sergunb |
0:f1834a63f7c1
|
1769
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
1770
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1771
|
|
| Sergunb |
0:f1834a63f7c1
|
1772
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1773
|
* @brief Clears or safeguards the OCREF4 signal on an external event
|
| Sergunb |
0:f1834a63f7c1
|
1774
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1775
|
* @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
|
| Sergunb |
0:f1834a63f7c1
|
1776
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1777
|
* @arg TIM_OCClear_Enable: TIM Output clear enable
|
| Sergunb |
0:f1834a63f7c1
|
1778
|
* @arg TIM_OCClear_Disable: TIM Output clear disable
|
| Sergunb |
0:f1834a63f7c1
|
1779
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1780
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1781
|
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
|
| Sergunb |
0:f1834a63f7c1
|
1782
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1783
|
uint16_t tmpccmr2 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1784
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1785
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1786
|
assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
|
| Sergunb |
0:f1834a63f7c1
|
1787
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
1788
|
/* Reset the OC4CE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1789
|
tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
|
| Sergunb |
0:f1834a63f7c1
|
1790
|
/* Enable or Disable the Output Compare Clear Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1791
|
tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1792
|
/* Write to TIMx CCMR2 register */
|
| Sergunb |
0:f1834a63f7c1
|
1793
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
1794
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1795
|
|
| Sergunb |
0:f1834a63f7c1
|
1796
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1797
|
* @brief Configures the TIMx channel 1 polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1798
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1799
|
* @param TIM_OCPolarity: specifies the OC1 Polarity
|
| Sergunb |
0:f1834a63f7c1
|
1800
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1801
|
* @arg TIM_OCPolarity_High: Output Compare active high
|
| Sergunb |
0:f1834a63f7c1
|
1802
|
* @arg TIM_OCPolarity_Low: Output Compare active low
|
| Sergunb |
0:f1834a63f7c1
|
1803
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1804
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1805
|
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
|
| Sergunb |
0:f1834a63f7c1
|
1806
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1807
|
uint16_t tmpccer = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1808
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1809
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1810
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1811
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
1812
|
/* Set or Reset the CC1P Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1813
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
|
| Sergunb |
0:f1834a63f7c1
|
1814
|
tmpccer |= TIM_OCPolarity;
|
| Sergunb |
0:f1834a63f7c1
|
1815
|
/* Write to TIMx CCER register */
|
| Sergunb |
0:f1834a63f7c1
|
1816
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
1817
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1818
|
|
| Sergunb |
0:f1834a63f7c1
|
1819
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1820
|
* @brief Configures the TIMx Channel 1N polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1821
|
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1822
|
* @param TIM_OCNPolarity: specifies the OC1N Polarity
|
| Sergunb |
0:f1834a63f7c1
|
1823
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1824
|
* @arg TIM_OCNPolarity_High: Output Compare active high
|
| Sergunb |
0:f1834a63f7c1
|
1825
|
* @arg TIM_OCNPolarity_Low: Output Compare active low
|
| Sergunb |
0:f1834a63f7c1
|
1826
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1827
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1828
|
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
|
| Sergunb |
0:f1834a63f7c1
|
1829
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1830
|
uint16_t tmpccer = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1831
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1832
|
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1833
|
assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1834
|
|
| Sergunb |
0:f1834a63f7c1
|
1835
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
1836
|
/* Set or Reset the CC1NP Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1837
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
|
| Sergunb |
0:f1834a63f7c1
|
1838
|
tmpccer |= TIM_OCNPolarity;
|
| Sergunb |
0:f1834a63f7c1
|
1839
|
/* Write to TIMx CCER register */
|
| Sergunb |
0:f1834a63f7c1
|
1840
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
1841
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1842
|
|
| Sergunb |
0:f1834a63f7c1
|
1843
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1844
|
* @brief Configures the TIMx channel 2 polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1845
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1846
|
* @param TIM_OCPolarity: specifies the OC2 Polarity
|
| Sergunb |
0:f1834a63f7c1
|
1847
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1848
|
* @arg TIM_OCPolarity_High: Output Compare active high
|
| Sergunb |
0:f1834a63f7c1
|
1849
|
* @arg TIM_OCPolarity_Low: Output Compare active low
|
| Sergunb |
0:f1834a63f7c1
|
1850
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1851
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1852
|
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
|
| Sergunb |
0:f1834a63f7c1
|
1853
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1854
|
uint16_t tmpccer = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1855
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1856
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1857
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1858
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
1859
|
/* Set or Reset the CC2P Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1860
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
|
| Sergunb |
0:f1834a63f7c1
|
1861
|
tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
|
| Sergunb |
0:f1834a63f7c1
|
1862
|
/* Write to TIMx CCER register */
|
| Sergunb |
0:f1834a63f7c1
|
1863
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
1864
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1865
|
|
| Sergunb |
0:f1834a63f7c1
|
1866
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1867
|
* @brief Configures the TIMx Channel 2N polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1868
|
* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1869
|
* @param TIM_OCNPolarity: specifies the OC2N Polarity
|
| Sergunb |
0:f1834a63f7c1
|
1870
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1871
|
* @arg TIM_OCNPolarity_High: Output Compare active high
|
| Sergunb |
0:f1834a63f7c1
|
1872
|
* @arg TIM_OCNPolarity_Low: Output Compare active low
|
| Sergunb |
0:f1834a63f7c1
|
1873
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1874
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1875
|
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
|
| Sergunb |
0:f1834a63f7c1
|
1876
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1877
|
uint16_t tmpccer = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1878
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1879
|
assert_param(IS_TIM_LIST1_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1880
|
assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1881
|
|
| Sergunb |
0:f1834a63f7c1
|
1882
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
1883
|
/* Set or Reset the CC2NP Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1884
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
|
| Sergunb |
0:f1834a63f7c1
|
1885
|
tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
|
| Sergunb |
0:f1834a63f7c1
|
1886
|
/* Write to TIMx CCER register */
|
| Sergunb |
0:f1834a63f7c1
|
1887
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
1888
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1889
|
|
| Sergunb |
0:f1834a63f7c1
|
1890
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1891
|
* @brief Configures the TIMx channel 3 polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1892
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1893
|
* @param TIM_OCPolarity: specifies the OC3 Polarity
|
| Sergunb |
0:f1834a63f7c1
|
1894
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1895
|
* @arg TIM_OCPolarity_High: Output Compare active high
|
| Sergunb |
0:f1834a63f7c1
|
1896
|
* @arg TIM_OCPolarity_Low: Output Compare active low
|
| Sergunb |
0:f1834a63f7c1
|
1897
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1898
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1899
|
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
|
| Sergunb |
0:f1834a63f7c1
|
1900
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1901
|
uint16_t tmpccer = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1902
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1903
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1904
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1905
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
1906
|
/* Set or Reset the CC3P Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1907
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
|
| Sergunb |
0:f1834a63f7c1
|
1908
|
tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1909
|
/* Write to TIMx CCER register */
|
| Sergunb |
0:f1834a63f7c1
|
1910
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
1911
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1912
|
|
| Sergunb |
0:f1834a63f7c1
|
1913
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1914
|
* @brief Configures the TIMx Channel 3N polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1915
|
* @param TIMx: where x can be 1 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1916
|
* @param TIM_OCNPolarity: specifies the OC3N Polarity
|
| Sergunb |
0:f1834a63f7c1
|
1917
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1918
|
* @arg TIM_OCNPolarity_High: Output Compare active high
|
| Sergunb |
0:f1834a63f7c1
|
1919
|
* @arg TIM_OCNPolarity_Low: Output Compare active low
|
| Sergunb |
0:f1834a63f7c1
|
1920
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1921
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1922
|
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
|
| Sergunb |
0:f1834a63f7c1
|
1923
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1924
|
uint16_t tmpccer = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1925
|
|
| Sergunb |
0:f1834a63f7c1
|
1926
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1927
|
assert_param(IS_TIM_LIST1_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1928
|
assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1929
|
|
| Sergunb |
0:f1834a63f7c1
|
1930
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
1931
|
/* Set or Reset the CC3NP Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1932
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
|
| Sergunb |
0:f1834a63f7c1
|
1933
|
tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
|
| Sergunb |
0:f1834a63f7c1
|
1934
|
/* Write to TIMx CCER register */
|
| Sergunb |
0:f1834a63f7c1
|
1935
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
1936
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1937
|
|
| Sergunb |
0:f1834a63f7c1
|
1938
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1939
|
* @brief Configures the TIMx channel 4 polarity.
|
| Sergunb |
0:f1834a63f7c1
|
1940
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1941
|
* @param TIM_OCPolarity: specifies the OC4 Polarity
|
| Sergunb |
0:f1834a63f7c1
|
1942
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1943
|
* @arg TIM_OCPolarity_High: Output Compare active high
|
| Sergunb |
0:f1834a63f7c1
|
1944
|
* @arg TIM_OCPolarity_Low: Output Compare active low
|
| Sergunb |
0:f1834a63f7c1
|
1945
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1946
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1947
|
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
|
| Sergunb |
0:f1834a63f7c1
|
1948
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1949
|
uint16_t tmpccer = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1950
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1951
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1952
|
assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
|
| Sergunb |
0:f1834a63f7c1
|
1953
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
1954
|
/* Set or Reset the CC4P Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1955
|
tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
|
| Sergunb |
0:f1834a63f7c1
|
1956
|
tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
|
| Sergunb |
0:f1834a63f7c1
|
1957
|
/* Write to TIMx CCER register */
|
| Sergunb |
0:f1834a63f7c1
|
1958
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
1959
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1960
|
|
| Sergunb |
0:f1834a63f7c1
|
1961
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1962
|
* @brief Enables or disables the TIM Capture Compare Channel x.
|
| Sergunb |
0:f1834a63f7c1
|
1963
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1964
|
* @param TIM_Channel: specifies the TIM Channel
|
| Sergunb |
0:f1834a63f7c1
|
1965
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1966
|
* @arg TIM_Channel_1: TIM Channel 1
|
| Sergunb |
0:f1834a63f7c1
|
1967
|
* @arg TIM_Channel_2: TIM Channel 2
|
| Sergunb |
0:f1834a63f7c1
|
1968
|
* @arg TIM_Channel_3: TIM Channel 3
|
| Sergunb |
0:f1834a63f7c1
|
1969
|
* @arg TIM_Channel_4: TIM Channel 4
|
| Sergunb |
0:f1834a63f7c1
|
1970
|
* @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
|
| Sergunb |
0:f1834a63f7c1
|
1971
|
* This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
|
| Sergunb |
0:f1834a63f7c1
|
1972
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
1973
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1974
|
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
|
| Sergunb |
0:f1834a63f7c1
|
1975
|
{
|
| Sergunb |
0:f1834a63f7c1
|
1976
|
uint16_t tmp = 0;
|
| Sergunb |
0:f1834a63f7c1
|
1977
|
|
| Sergunb |
0:f1834a63f7c1
|
1978
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
1979
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
1980
|
assert_param(IS_TIM_CHANNEL(TIM_Channel));
|
| Sergunb |
0:f1834a63f7c1
|
1981
|
assert_param(IS_TIM_CCX(TIM_CCx));
|
| Sergunb |
0:f1834a63f7c1
|
1982
|
|
| Sergunb |
0:f1834a63f7c1
|
1983
|
tmp = CCER_CCE_Set << TIM_Channel;
|
| Sergunb |
0:f1834a63f7c1
|
1984
|
|
| Sergunb |
0:f1834a63f7c1
|
1985
|
/* Reset the CCxE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1986
|
TIMx->CCER &= (uint16_t)~ tmp;
|
| Sergunb |
0:f1834a63f7c1
|
1987
|
|
| Sergunb |
0:f1834a63f7c1
|
1988
|
/* Set or reset the CCxE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
1989
|
TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
|
| Sergunb |
0:f1834a63f7c1
|
1990
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1991
|
|
| Sergunb |
0:f1834a63f7c1
|
1992
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1993
|
* @brief Enables or disables the TIM Capture Compare Channel xN.
|
| Sergunb |
0:f1834a63f7c1
|
1994
|
* @param TIMx: where x can be 1, 8, 15, 16 or 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
1995
|
* @param TIM_Channel: specifies the TIM Channel
|
| Sergunb |
0:f1834a63f7c1
|
1996
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
1997
|
* @arg TIM_Channel_1: TIM Channel 1
|
| Sergunb |
0:f1834a63f7c1
|
1998
|
* @arg TIM_Channel_2: TIM Channel 2
|
| Sergunb |
0:f1834a63f7c1
|
1999
|
* @arg TIM_Channel_3: TIM Channel 3
|
| Sergunb |
0:f1834a63f7c1
|
2000
|
* @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
|
| Sergunb |
0:f1834a63f7c1
|
2001
|
* This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
|
| Sergunb |
0:f1834a63f7c1
|
2002
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2003
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2004
|
void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
|
| Sergunb |
0:f1834a63f7c1
|
2005
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2006
|
uint16_t tmp = 0;
|
| Sergunb |
0:f1834a63f7c1
|
2007
|
|
| Sergunb |
0:f1834a63f7c1
|
2008
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2009
|
assert_param(IS_TIM_LIST2_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2010
|
assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
|
| Sergunb |
0:f1834a63f7c1
|
2011
|
assert_param(IS_TIM_CCXN(TIM_CCxN));
|
| Sergunb |
0:f1834a63f7c1
|
2012
|
|
| Sergunb |
0:f1834a63f7c1
|
2013
|
tmp = CCER_CCNE_Set << TIM_Channel;
|
| Sergunb |
0:f1834a63f7c1
|
2014
|
|
| Sergunb |
0:f1834a63f7c1
|
2015
|
/* Reset the CCxNE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2016
|
TIMx->CCER &= (uint16_t) ~tmp;
|
| Sergunb |
0:f1834a63f7c1
|
2017
|
|
| Sergunb |
0:f1834a63f7c1
|
2018
|
/* Set or reset the CCxNE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2019
|
TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
|
| Sergunb |
0:f1834a63f7c1
|
2020
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2021
|
|
| Sergunb |
0:f1834a63f7c1
|
2022
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2023
|
* @brief Selects the TIM Output Compare Mode.
|
| Sergunb |
0:f1834a63f7c1
|
2024
|
* @note This function disables the selected channel before changing the Output
|
| Sergunb |
0:f1834a63f7c1
|
2025
|
* Compare Mode.
|
| Sergunb |
0:f1834a63f7c1
|
2026
|
* User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
|
| Sergunb |
0:f1834a63f7c1
|
2027
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2028
|
* @param TIM_Channel: specifies the TIM Channel
|
| Sergunb |
0:f1834a63f7c1
|
2029
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2030
|
* @arg TIM_Channel_1: TIM Channel 1
|
| Sergunb |
0:f1834a63f7c1
|
2031
|
* @arg TIM_Channel_2: TIM Channel 2
|
| Sergunb |
0:f1834a63f7c1
|
2032
|
* @arg TIM_Channel_3: TIM Channel 3
|
| Sergunb |
0:f1834a63f7c1
|
2033
|
* @arg TIM_Channel_4: TIM Channel 4
|
| Sergunb |
0:f1834a63f7c1
|
2034
|
* @param TIM_OCMode: specifies the TIM Output Compare Mode.
|
| Sergunb |
0:f1834a63f7c1
|
2035
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2036
|
* @arg TIM_OCMode_Timing
|
| Sergunb |
0:f1834a63f7c1
|
2037
|
* @arg TIM_OCMode_Active
|
| Sergunb |
0:f1834a63f7c1
|
2038
|
* @arg TIM_OCMode_Toggle
|
| Sergunb |
0:f1834a63f7c1
|
2039
|
* @arg TIM_OCMode_PWM1
|
| Sergunb |
0:f1834a63f7c1
|
2040
|
* @arg TIM_OCMode_PWM2
|
| Sergunb |
0:f1834a63f7c1
|
2041
|
* @arg TIM_ForcedAction_Active
|
| Sergunb |
0:f1834a63f7c1
|
2042
|
* @arg TIM_ForcedAction_InActive
|
| Sergunb |
0:f1834a63f7c1
|
2043
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2044
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2045
|
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
|
| Sergunb |
0:f1834a63f7c1
|
2046
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2047
|
uint32_t tmp = 0;
|
| Sergunb |
0:f1834a63f7c1
|
2048
|
uint16_t tmp1 = 0;
|
| Sergunb |
0:f1834a63f7c1
|
2049
|
|
| Sergunb |
0:f1834a63f7c1
|
2050
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2051
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2052
|
assert_param(IS_TIM_CHANNEL(TIM_Channel));
|
| Sergunb |
0:f1834a63f7c1
|
2053
|
assert_param(IS_TIM_OCM(TIM_OCMode));
|
| Sergunb |
0:f1834a63f7c1
|
2054
|
|
| Sergunb |
0:f1834a63f7c1
|
2055
|
tmp = (uint32_t) TIMx;
|
| Sergunb |
0:f1834a63f7c1
|
2056
|
tmp += CCMR_Offset;
|
| Sergunb |
0:f1834a63f7c1
|
2057
|
|
| Sergunb |
0:f1834a63f7c1
|
2058
|
tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel;
|
| Sergunb |
0:f1834a63f7c1
|
2059
|
|
| Sergunb |
0:f1834a63f7c1
|
2060
|
/* Disable the Channel: Reset the CCxE Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2061
|
TIMx->CCER &= (uint16_t) ~tmp1;
|
| Sergunb |
0:f1834a63f7c1
|
2062
|
|
| Sergunb |
0:f1834a63f7c1
|
2063
|
if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
|
| Sergunb |
0:f1834a63f7c1
|
2064
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2065
|
tmp += (TIM_Channel>>1);
|
| Sergunb |
0:f1834a63f7c1
|
2066
|
|
| Sergunb |
0:f1834a63f7c1
|
2067
|
/* Reset the OCxM bits in the CCMRx register */
|
| Sergunb |
0:f1834a63f7c1
|
2068
|
*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
|
| Sergunb |
0:f1834a63f7c1
|
2069
|
|
| Sergunb |
0:f1834a63f7c1
|
2070
|
/* Configure the OCxM bits in the CCMRx register */
|
| Sergunb |
0:f1834a63f7c1
|
2071
|
*(__IO uint32_t *) tmp |= TIM_OCMode;
|
| Sergunb |
0:f1834a63f7c1
|
2072
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2073
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2074
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2075
|
tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
|
| Sergunb |
0:f1834a63f7c1
|
2076
|
|
| Sergunb |
0:f1834a63f7c1
|
2077
|
/* Reset the OCxM bits in the CCMRx register */
|
| Sergunb |
0:f1834a63f7c1
|
2078
|
*(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
|
| Sergunb |
0:f1834a63f7c1
|
2079
|
|
| Sergunb |
0:f1834a63f7c1
|
2080
|
/* Configure the OCxM bits in the CCMRx register */
|
| Sergunb |
0:f1834a63f7c1
|
2081
|
*(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
|
| Sergunb |
0:f1834a63f7c1
|
2082
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2083
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2084
|
|
| Sergunb |
0:f1834a63f7c1
|
2085
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2086
|
* @brief Enables or Disables the TIMx Update event.
|
| Sergunb |
0:f1834a63f7c1
|
2087
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2088
|
* @param NewState: new state of the TIMx UDIS bit
|
| Sergunb |
0:f1834a63f7c1
|
2089
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
2090
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2091
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2092
|
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
2093
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2094
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2095
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2096
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
2097
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
2098
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2099
|
/* Set the Update Disable Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2100
|
TIMx->CR1 |= TIM_CR1_UDIS;
|
| Sergunb |
0:f1834a63f7c1
|
2101
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2102
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2103
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2104
|
/* Reset the Update Disable Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2105
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
|
| Sergunb |
0:f1834a63f7c1
|
2106
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2107
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2108
|
|
| Sergunb |
0:f1834a63f7c1
|
2109
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2110
|
* @brief Configures the TIMx Update Request Interrupt source.
|
| Sergunb |
0:f1834a63f7c1
|
2111
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2112
|
* @param TIM_UpdateSource: specifies the Update source.
|
| Sergunb |
0:f1834a63f7c1
|
2113
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2114
|
* @arg TIM_UpdateSource_Regular: Source of update is the counter overflow/underflow
|
| Sergunb |
0:f1834a63f7c1
|
2115
|
or the setting of UG bit, or an update generation
|
| Sergunb |
0:f1834a63f7c1
|
2116
|
through the slave mode controller.
|
| Sergunb |
0:f1834a63f7c1
|
2117
|
* @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
|
| Sergunb |
0:f1834a63f7c1
|
2118
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2119
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2120
|
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
|
| Sergunb |
0:f1834a63f7c1
|
2121
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2122
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2123
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2124
|
assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
|
| Sergunb |
0:f1834a63f7c1
|
2125
|
if (TIM_UpdateSource != TIM_UpdateSource_Global)
|
| Sergunb |
0:f1834a63f7c1
|
2126
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2127
|
/* Set the URS Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2128
|
TIMx->CR1 |= TIM_CR1_URS;
|
| Sergunb |
0:f1834a63f7c1
|
2129
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2130
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2131
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2132
|
/* Reset the URS Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2133
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
|
| Sergunb |
0:f1834a63f7c1
|
2134
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2135
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2136
|
|
| Sergunb |
0:f1834a63f7c1
|
2137
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2138
|
* @brief Enables or disables the TIMx's Hall sensor interface.
|
| Sergunb |
0:f1834a63f7c1
|
2139
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2140
|
* @param NewState: new state of the TIMx Hall sensor interface.
|
| Sergunb |
0:f1834a63f7c1
|
2141
|
* This parameter can be: ENABLE or DISABLE.
|
| Sergunb |
0:f1834a63f7c1
|
2142
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2143
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2144
|
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
|
| Sergunb |
0:f1834a63f7c1
|
2145
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2146
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2147
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2148
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
| Sergunb |
0:f1834a63f7c1
|
2149
|
if (NewState != DISABLE)
|
| Sergunb |
0:f1834a63f7c1
|
2150
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2151
|
/* Set the TI1S Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2152
|
TIMx->CR2 |= TIM_CR2_TI1S;
|
| Sergunb |
0:f1834a63f7c1
|
2153
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2154
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2155
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2156
|
/* Reset the TI1S Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2157
|
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
|
| Sergunb |
0:f1834a63f7c1
|
2158
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2159
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2160
|
|
| Sergunb |
0:f1834a63f7c1
|
2161
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2162
|
* @brief Selects the TIMx's One Pulse Mode.
|
| Sergunb |
0:f1834a63f7c1
|
2163
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2164
|
* @param TIM_OPMode: specifies the OPM Mode to be used.
|
| Sergunb |
0:f1834a63f7c1
|
2165
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2166
|
* @arg TIM_OPMode_Single
|
| Sergunb |
0:f1834a63f7c1
|
2167
|
* @arg TIM_OPMode_Repetitive
|
| Sergunb |
0:f1834a63f7c1
|
2168
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2169
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2170
|
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
|
| Sergunb |
0:f1834a63f7c1
|
2171
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2172
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2173
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2174
|
assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
|
| Sergunb |
0:f1834a63f7c1
|
2175
|
/* Reset the OPM Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2176
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
|
| Sergunb |
0:f1834a63f7c1
|
2177
|
/* Configure the OPM Mode */
|
| Sergunb |
0:f1834a63f7c1
|
2178
|
TIMx->CR1 |= TIM_OPMode;
|
| Sergunb |
0:f1834a63f7c1
|
2179
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2180
|
|
| Sergunb |
0:f1834a63f7c1
|
2181
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2182
|
* @brief Selects the TIMx Trigger Output Mode.
|
| Sergunb |
0:f1834a63f7c1
|
2183
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2184
|
* @param TIM_TRGOSource: specifies the Trigger Output source.
|
| Sergunb |
0:f1834a63f7c1
|
2185
|
* This paramter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2186
|
*
|
| Sergunb |
0:f1834a63f7c1
|
2187
|
* - For all TIMx
|
| Sergunb |
0:f1834a63f7c1
|
2188
|
* @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
|
| Sergunb |
0:f1834a63f7c1
|
2189
|
* @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
|
| Sergunb |
0:f1834a63f7c1
|
2190
|
* @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
|
| Sergunb |
0:f1834a63f7c1
|
2191
|
*
|
| Sergunb |
0:f1834a63f7c1
|
2192
|
* - For all TIMx except TIM6 and TIM7
|
| Sergunb |
0:f1834a63f7c1
|
2193
|
* @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
|
| Sergunb |
0:f1834a63f7c1
|
2194
|
* is to be set, as soon as a capture or compare match occurs (TRGO).
|
| Sergunb |
0:f1834a63f7c1
|
2195
|
* @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
|
| Sergunb |
0:f1834a63f7c1
|
2196
|
* @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
|
| Sergunb |
0:f1834a63f7c1
|
2197
|
* @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
|
| Sergunb |
0:f1834a63f7c1
|
2198
|
* @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
|
| Sergunb |
0:f1834a63f7c1
|
2199
|
*
|
| Sergunb |
0:f1834a63f7c1
|
2200
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2201
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2202
|
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
|
| Sergunb |
0:f1834a63f7c1
|
2203
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2204
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2205
|
assert_param(IS_TIM_LIST7_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2206
|
assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
|
| Sergunb |
0:f1834a63f7c1
|
2207
|
/* Reset the MMS Bits */
|
| Sergunb |
0:f1834a63f7c1
|
2208
|
TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
|
| Sergunb |
0:f1834a63f7c1
|
2209
|
/* Select the TRGO source */
|
| Sergunb |
0:f1834a63f7c1
|
2210
|
TIMx->CR2 |= TIM_TRGOSource;
|
| Sergunb |
0:f1834a63f7c1
|
2211
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2212
|
|
| Sergunb |
0:f1834a63f7c1
|
2213
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2214
|
* @brief Selects the TIMx Slave Mode.
|
| Sergunb |
0:f1834a63f7c1
|
2215
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2216
|
* @param TIM_SlaveMode: specifies the Timer Slave Mode.
|
| Sergunb |
0:f1834a63f7c1
|
2217
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2218
|
* @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
|
| Sergunb |
0:f1834a63f7c1
|
2219
|
* the counter and triggers an update of the registers.
|
| Sergunb |
0:f1834a63f7c1
|
2220
|
* @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
|
| Sergunb |
0:f1834a63f7c1
|
2221
|
* @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
|
| Sergunb |
0:f1834a63f7c1
|
2222
|
* @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
|
| Sergunb |
0:f1834a63f7c1
|
2223
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2224
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2225
|
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
|
| Sergunb |
0:f1834a63f7c1
|
2226
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2227
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2228
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2229
|
assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
|
| Sergunb |
0:f1834a63f7c1
|
2230
|
/* Reset the SMS Bits */
|
| Sergunb |
0:f1834a63f7c1
|
2231
|
TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
|
| Sergunb |
0:f1834a63f7c1
|
2232
|
/* Select the Slave Mode */
|
| Sergunb |
0:f1834a63f7c1
|
2233
|
TIMx->SMCR |= TIM_SlaveMode;
|
| Sergunb |
0:f1834a63f7c1
|
2234
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2235
|
|
| Sergunb |
0:f1834a63f7c1
|
2236
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2237
|
* @brief Sets or Resets the TIMx Master/Slave Mode.
|
| Sergunb |
0:f1834a63f7c1
|
2238
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2239
|
* @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
|
| Sergunb |
0:f1834a63f7c1
|
2240
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2241
|
* @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
|
| Sergunb |
0:f1834a63f7c1
|
2242
|
* and its slaves (through TRGO).
|
| Sergunb |
0:f1834a63f7c1
|
2243
|
* @arg TIM_MasterSlaveMode_Disable: No action
|
| Sergunb |
0:f1834a63f7c1
|
2244
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2245
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2246
|
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
|
| Sergunb |
0:f1834a63f7c1
|
2247
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2248
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2249
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2250
|
assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
|
| Sergunb |
0:f1834a63f7c1
|
2251
|
/* Reset the MSM Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2252
|
TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
|
| Sergunb |
0:f1834a63f7c1
|
2253
|
|
| Sergunb |
0:f1834a63f7c1
|
2254
|
/* Set or Reset the MSM Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2255
|
TIMx->SMCR |= TIM_MasterSlaveMode;
|
| Sergunb |
0:f1834a63f7c1
|
2256
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2257
|
|
| Sergunb |
0:f1834a63f7c1
|
2258
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2259
|
* @brief Sets the TIMx Counter Register value
|
| Sergunb |
0:f1834a63f7c1
|
2260
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2261
|
* @param Counter: specifies the Counter register new value.
|
| Sergunb |
0:f1834a63f7c1
|
2262
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2263
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2264
|
void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter)
|
| Sergunb |
0:f1834a63f7c1
|
2265
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2266
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2267
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2268
|
/* Set the Counter Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2269
|
TIMx->CNT = Counter;
|
| Sergunb |
0:f1834a63f7c1
|
2270
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2271
|
|
| Sergunb |
0:f1834a63f7c1
|
2272
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2273
|
* @brief Sets the TIMx Autoreload Register value
|
| Sergunb |
0:f1834a63f7c1
|
2274
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2275
|
* @param Autoreload: specifies the Autoreload register new value.
|
| Sergunb |
0:f1834a63f7c1
|
2276
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2277
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2278
|
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload)
|
| Sergunb |
0:f1834a63f7c1
|
2279
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2280
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2281
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2282
|
/* Set the Autoreload Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2283
|
TIMx->ARR = Autoreload;
|
| Sergunb |
0:f1834a63f7c1
|
2284
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2285
|
|
| Sergunb |
0:f1834a63f7c1
|
2286
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2287
|
* @brief Sets the TIMx Capture Compare1 Register value
|
| Sergunb |
0:f1834a63f7c1
|
2288
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2289
|
* @param Compare1: specifies the Capture Compare1 register new value.
|
| Sergunb |
0:f1834a63f7c1
|
2290
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2291
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2292
|
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1)
|
| Sergunb |
0:f1834a63f7c1
|
2293
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2294
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2295
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2296
|
/* Set the Capture Compare1 Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2297
|
TIMx->CCR1 = Compare1;
|
| Sergunb |
0:f1834a63f7c1
|
2298
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2299
|
|
| Sergunb |
0:f1834a63f7c1
|
2300
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2301
|
* @brief Sets the TIMx Capture Compare2 Register value
|
| Sergunb |
0:f1834a63f7c1
|
2302
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2303
|
* @param Compare2: specifies the Capture Compare2 register new value.
|
| Sergunb |
0:f1834a63f7c1
|
2304
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2305
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2306
|
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2)
|
| Sergunb |
0:f1834a63f7c1
|
2307
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2308
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2309
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2310
|
/* Set the Capture Compare2 Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2311
|
TIMx->CCR2 = Compare2;
|
| Sergunb |
0:f1834a63f7c1
|
2312
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2313
|
|
| Sergunb |
0:f1834a63f7c1
|
2314
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2315
|
* @brief Sets the TIMx Capture Compare3 Register value
|
| Sergunb |
0:f1834a63f7c1
|
2316
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2317
|
* @param Compare3: specifies the Capture Compare3 register new value.
|
| Sergunb |
0:f1834a63f7c1
|
2318
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2319
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2320
|
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3)
|
| Sergunb |
0:f1834a63f7c1
|
2321
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2322
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2323
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2324
|
/* Set the Capture Compare3 Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2325
|
TIMx->CCR3 = Compare3;
|
| Sergunb |
0:f1834a63f7c1
|
2326
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2327
|
|
| Sergunb |
0:f1834a63f7c1
|
2328
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2329
|
* @brief Sets the TIMx Capture Compare4 Register value
|
| Sergunb |
0:f1834a63f7c1
|
2330
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2331
|
* @param Compare4: specifies the Capture Compare4 register new value.
|
| Sergunb |
0:f1834a63f7c1
|
2332
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2333
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2334
|
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4)
|
| Sergunb |
0:f1834a63f7c1
|
2335
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2336
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2337
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2338
|
/* Set the Capture Compare4 Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2339
|
TIMx->CCR4 = Compare4;
|
| Sergunb |
0:f1834a63f7c1
|
2340
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2341
|
|
| Sergunb |
0:f1834a63f7c1
|
2342
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2343
|
* @brief Sets the TIMx Input Capture 1 prescaler.
|
| Sergunb |
0:f1834a63f7c1
|
2344
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2345
|
* @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
|
| Sergunb |
0:f1834a63f7c1
|
2346
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2347
|
* @arg TIM_ICPSC_DIV1: no prescaler
|
| Sergunb |
0:f1834a63f7c1
|
2348
|
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
| Sergunb |
0:f1834a63f7c1
|
2349
|
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
| Sergunb |
0:f1834a63f7c1
|
2350
|
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
| Sergunb |
0:f1834a63f7c1
|
2351
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2352
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2353
|
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
|
| Sergunb |
0:f1834a63f7c1
|
2354
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2355
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2356
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2357
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
|
| Sergunb |
0:f1834a63f7c1
|
2358
|
/* Reset the IC1PSC Bits */
|
| Sergunb |
0:f1834a63f7c1
|
2359
|
TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
|
| Sergunb |
0:f1834a63f7c1
|
2360
|
/* Set the IC1PSC value */
|
| Sergunb |
0:f1834a63f7c1
|
2361
|
TIMx->CCMR1 |= TIM_ICPSC;
|
| Sergunb |
0:f1834a63f7c1
|
2362
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2363
|
|
| Sergunb |
0:f1834a63f7c1
|
2364
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2365
|
* @brief Sets the TIMx Input Capture 2 prescaler.
|
| Sergunb |
0:f1834a63f7c1
|
2366
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2367
|
* @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
|
| Sergunb |
0:f1834a63f7c1
|
2368
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2369
|
* @arg TIM_ICPSC_DIV1: no prescaler
|
| Sergunb |
0:f1834a63f7c1
|
2370
|
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
| Sergunb |
0:f1834a63f7c1
|
2371
|
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
| Sergunb |
0:f1834a63f7c1
|
2372
|
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
| Sergunb |
0:f1834a63f7c1
|
2373
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2374
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2375
|
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
|
| Sergunb |
0:f1834a63f7c1
|
2376
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2377
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2378
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2379
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
|
| Sergunb |
0:f1834a63f7c1
|
2380
|
/* Reset the IC2PSC Bits */
|
| Sergunb |
0:f1834a63f7c1
|
2381
|
TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
|
| Sergunb |
0:f1834a63f7c1
|
2382
|
/* Set the IC2PSC value */
|
| Sergunb |
0:f1834a63f7c1
|
2383
|
TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
|
| Sergunb |
0:f1834a63f7c1
|
2384
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2385
|
|
| Sergunb |
0:f1834a63f7c1
|
2386
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2387
|
* @brief Sets the TIMx Input Capture 3 prescaler.
|
| Sergunb |
0:f1834a63f7c1
|
2388
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2389
|
* @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
|
| Sergunb |
0:f1834a63f7c1
|
2390
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2391
|
* @arg TIM_ICPSC_DIV1: no prescaler
|
| Sergunb |
0:f1834a63f7c1
|
2392
|
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
| Sergunb |
0:f1834a63f7c1
|
2393
|
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
| Sergunb |
0:f1834a63f7c1
|
2394
|
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
| Sergunb |
0:f1834a63f7c1
|
2395
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2396
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2397
|
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
|
| Sergunb |
0:f1834a63f7c1
|
2398
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2399
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2400
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2401
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
|
| Sergunb |
0:f1834a63f7c1
|
2402
|
/* Reset the IC3PSC Bits */
|
| Sergunb |
0:f1834a63f7c1
|
2403
|
TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
|
| Sergunb |
0:f1834a63f7c1
|
2404
|
/* Set the IC3PSC value */
|
| Sergunb |
0:f1834a63f7c1
|
2405
|
TIMx->CCMR2 |= TIM_ICPSC;
|
| Sergunb |
0:f1834a63f7c1
|
2406
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2407
|
|
| Sergunb |
0:f1834a63f7c1
|
2408
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2409
|
* @brief Sets the TIMx Input Capture 4 prescaler.
|
| Sergunb |
0:f1834a63f7c1
|
2410
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2411
|
* @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
|
| Sergunb |
0:f1834a63f7c1
|
2412
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2413
|
* @arg TIM_ICPSC_DIV1: no prescaler
|
| Sergunb |
0:f1834a63f7c1
|
2414
|
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
|
| Sergunb |
0:f1834a63f7c1
|
2415
|
* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
|
| Sergunb |
0:f1834a63f7c1
|
2416
|
* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
|
| Sergunb |
0:f1834a63f7c1
|
2417
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2418
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2419
|
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
|
| Sergunb |
0:f1834a63f7c1
|
2420
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2421
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2422
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2423
|
assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
|
| Sergunb |
0:f1834a63f7c1
|
2424
|
/* Reset the IC4PSC Bits */
|
| Sergunb |
0:f1834a63f7c1
|
2425
|
TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
|
| Sergunb |
0:f1834a63f7c1
|
2426
|
/* Set the IC4PSC value */
|
| Sergunb |
0:f1834a63f7c1
|
2427
|
TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
|
| Sergunb |
0:f1834a63f7c1
|
2428
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2429
|
|
| Sergunb |
0:f1834a63f7c1
|
2430
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2431
|
* @brief Sets the TIMx Clock Division value.
|
| Sergunb |
0:f1834a63f7c1
|
2432
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select
|
| Sergunb |
0:f1834a63f7c1
|
2433
|
* the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2434
|
* @param TIM_CKD: specifies the clock division value.
|
| Sergunb |
0:f1834a63f7c1
|
2435
|
* This parameter can be one of the following value:
|
| Sergunb |
0:f1834a63f7c1
|
2436
|
* @arg TIM_CKD_DIV1: TDTS = Tck_tim
|
| Sergunb |
0:f1834a63f7c1
|
2437
|
* @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
|
| Sergunb |
0:f1834a63f7c1
|
2438
|
* @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
|
| Sergunb |
0:f1834a63f7c1
|
2439
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2440
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2441
|
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
|
| Sergunb |
0:f1834a63f7c1
|
2442
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2443
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2444
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2445
|
assert_param(IS_TIM_CKD_DIV(TIM_CKD));
|
| Sergunb |
0:f1834a63f7c1
|
2446
|
/* Reset the CKD Bits */
|
| Sergunb |
0:f1834a63f7c1
|
2447
|
TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
|
| Sergunb |
0:f1834a63f7c1
|
2448
|
/* Set the CKD value */
|
| Sergunb |
0:f1834a63f7c1
|
2449
|
TIMx->CR1 |= TIM_CKD;
|
| Sergunb |
0:f1834a63f7c1
|
2450
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2451
|
|
| Sergunb |
0:f1834a63f7c1
|
2452
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2453
|
* @brief Gets the TIMx Input Capture 1 value.
|
| Sergunb |
0:f1834a63f7c1
|
2454
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2455
|
* @retval Capture Compare 1 Register value.
|
| Sergunb |
0:f1834a63f7c1
|
2456
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2457
|
uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx)
|
| Sergunb |
0:f1834a63f7c1
|
2458
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2459
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2460
|
assert_param(IS_TIM_LIST8_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2461
|
/* Get the Capture 1 Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2462
|
return TIMx->CCR1;
|
| Sergunb |
0:f1834a63f7c1
|
2463
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2464
|
|
| Sergunb |
0:f1834a63f7c1
|
2465
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2466
|
* @brief Gets the TIMx Input Capture 2 value.
|
| Sergunb |
0:f1834a63f7c1
|
2467
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2468
|
* @retval Capture Compare 2 Register value.
|
| Sergunb |
0:f1834a63f7c1
|
2469
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2470
|
uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx)
|
| Sergunb |
0:f1834a63f7c1
|
2471
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2472
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2473
|
assert_param(IS_TIM_LIST6_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2474
|
/* Get the Capture 2 Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2475
|
return TIMx->CCR2;
|
| Sergunb |
0:f1834a63f7c1
|
2476
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2477
|
|
| Sergunb |
0:f1834a63f7c1
|
2478
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2479
|
* @brief Gets the TIMx Input Capture 3 value.
|
| Sergunb |
0:f1834a63f7c1
|
2480
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2481
|
* @retval Capture Compare 3 Register value.
|
| Sergunb |
0:f1834a63f7c1
|
2482
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2483
|
uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx)
|
| Sergunb |
0:f1834a63f7c1
|
2484
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2485
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2486
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2487
|
/* Get the Capture 3 Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2488
|
return TIMx->CCR3;
|
| Sergunb |
0:f1834a63f7c1
|
2489
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2490
|
|
| Sergunb |
0:f1834a63f7c1
|
2491
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2492
|
* @brief Gets the TIMx Input Capture 4 value.
|
| Sergunb |
0:f1834a63f7c1
|
2493
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2494
|
* @retval Capture Compare 4 Register value.
|
| Sergunb |
0:f1834a63f7c1
|
2495
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2496
|
uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx)
|
| Sergunb |
0:f1834a63f7c1
|
2497
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2498
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2499
|
assert_param(IS_TIM_LIST3_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2500
|
/* Get the Capture 4 Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2501
|
return TIMx->CCR4;
|
| Sergunb |
0:f1834a63f7c1
|
2502
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2503
|
|
| Sergunb |
0:f1834a63f7c1
|
2504
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2505
|
* @brief Gets the TIMx Counter value.
|
| Sergunb |
0:f1834a63f7c1
|
2506
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2507
|
* @retval Counter Register value.
|
| Sergunb |
0:f1834a63f7c1
|
2508
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2509
|
uint16_t TIM_GetCounter(TIM_TypeDef* TIMx)
|
| Sergunb |
0:f1834a63f7c1
|
2510
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2511
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2512
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2513
|
/* Get the Counter Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2514
|
return TIMx->CNT;
|
| Sergunb |
0:f1834a63f7c1
|
2515
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2516
|
|
| Sergunb |
0:f1834a63f7c1
|
2517
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2518
|
* @brief Gets the TIMx Prescaler value.
|
| Sergunb |
0:f1834a63f7c1
|
2519
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2520
|
* @retval Prescaler Register value.
|
| Sergunb |
0:f1834a63f7c1
|
2521
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2522
|
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
|
| Sergunb |
0:f1834a63f7c1
|
2523
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2524
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2525
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2526
|
/* Get the Prescaler Register value */
|
| Sergunb |
0:f1834a63f7c1
|
2527
|
return TIMx->PSC;
|
| Sergunb |
0:f1834a63f7c1
|
2528
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2529
|
|
| Sergunb |
0:f1834a63f7c1
|
2530
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2531
|
* @brief Checks whether the specified TIM flag is set or not.
|
| Sergunb |
0:f1834a63f7c1
|
2532
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2533
|
* @param TIM_FLAG: specifies the flag to check.
|
| Sergunb |
0:f1834a63f7c1
|
2534
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2535
|
* @arg TIM_FLAG_Update: TIM update Flag
|
| Sergunb |
0:f1834a63f7c1
|
2536
|
* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
|
| Sergunb |
0:f1834a63f7c1
|
2537
|
* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
|
| Sergunb |
0:f1834a63f7c1
|
2538
|
* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
|
| Sergunb |
0:f1834a63f7c1
|
2539
|
* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
|
| Sergunb |
0:f1834a63f7c1
|
2540
|
* @arg TIM_FLAG_COM: TIM Commutation Flag
|
| Sergunb |
0:f1834a63f7c1
|
2541
|
* @arg TIM_FLAG_Trigger: TIM Trigger Flag
|
| Sergunb |
0:f1834a63f7c1
|
2542
|
* @arg TIM_FLAG_Break: TIM Break Flag
|
| Sergunb |
0:f1834a63f7c1
|
2543
|
* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
|
| Sergunb |
0:f1834a63f7c1
|
2544
|
* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
|
| Sergunb |
0:f1834a63f7c1
|
2545
|
* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
|
| Sergunb |
0:f1834a63f7c1
|
2546
|
* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
|
| Sergunb |
0:f1834a63f7c1
|
2547
|
* @note
|
| Sergunb |
0:f1834a63f7c1
|
2548
|
* - TIM6 and TIM7 can have only one update flag.
|
| Sergunb |
0:f1834a63f7c1
|
2549
|
* - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
|
| Sergunb |
0:f1834a63f7c1
|
2550
|
* TIM_FLAG_CC2 or TIM_FLAG_Trigger.
|
| Sergunb |
0:f1834a63f7c1
|
2551
|
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
|
| Sergunb |
0:f1834a63f7c1
|
2552
|
* - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
|
| Sergunb |
0:f1834a63f7c1
|
2553
|
* - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
|
| Sergunb |
0:f1834a63f7c1
|
2554
|
* @retval The new state of TIM_FLAG (SET or RESET).
|
| Sergunb |
0:f1834a63f7c1
|
2555
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2556
|
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
|
| Sergunb |
0:f1834a63f7c1
|
2557
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2558
|
ITStatus bitstatus = RESET;
|
| Sergunb |
0:f1834a63f7c1
|
2559
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2560
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2561
|
assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
|
| Sergunb |
0:f1834a63f7c1
|
2562
|
|
| Sergunb |
0:f1834a63f7c1
|
2563
|
if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
|
| Sergunb |
0:f1834a63f7c1
|
2564
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2565
|
bitstatus = SET;
|
| Sergunb |
0:f1834a63f7c1
|
2566
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2567
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2568
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2569
|
bitstatus = RESET;
|
| Sergunb |
0:f1834a63f7c1
|
2570
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2571
|
return bitstatus;
|
| Sergunb |
0:f1834a63f7c1
|
2572
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2573
|
|
| Sergunb |
0:f1834a63f7c1
|
2574
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2575
|
* @brief Clears the TIMx's pending flags.
|
| Sergunb |
0:f1834a63f7c1
|
2576
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2577
|
* @param TIM_FLAG: specifies the flag bit to clear.
|
| Sergunb |
0:f1834a63f7c1
|
2578
|
* This parameter can be any combination of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2579
|
* @arg TIM_FLAG_Update: TIM update Flag
|
| Sergunb |
0:f1834a63f7c1
|
2580
|
* @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
|
| Sergunb |
0:f1834a63f7c1
|
2581
|
* @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
|
| Sergunb |
0:f1834a63f7c1
|
2582
|
* @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
|
| Sergunb |
0:f1834a63f7c1
|
2583
|
* @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
|
| Sergunb |
0:f1834a63f7c1
|
2584
|
* @arg TIM_FLAG_COM: TIM Commutation Flag
|
| Sergunb |
0:f1834a63f7c1
|
2585
|
* @arg TIM_FLAG_Trigger: TIM Trigger Flag
|
| Sergunb |
0:f1834a63f7c1
|
2586
|
* @arg TIM_FLAG_Break: TIM Break Flag
|
| Sergunb |
0:f1834a63f7c1
|
2587
|
* @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
|
| Sergunb |
0:f1834a63f7c1
|
2588
|
* @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
|
| Sergunb |
0:f1834a63f7c1
|
2589
|
* @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
|
| Sergunb |
0:f1834a63f7c1
|
2590
|
* @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
|
| Sergunb |
0:f1834a63f7c1
|
2591
|
* @note
|
| Sergunb |
0:f1834a63f7c1
|
2592
|
* - TIM6 and TIM7 can have only one update flag.
|
| Sergunb |
0:f1834a63f7c1
|
2593
|
* - TIM9, TIM12 and TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,
|
| Sergunb |
0:f1834a63f7c1
|
2594
|
* TIM_FLAG_CC2 or TIM_FLAG_Trigger.
|
| Sergunb |
0:f1834a63f7c1
|
2595
|
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
|
| Sergunb |
0:f1834a63f7c1
|
2596
|
* - TIM_FLAG_Break is used only with TIM1, TIM8 and TIM15.
|
| Sergunb |
0:f1834a63f7c1
|
2597
|
* - TIM_FLAG_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
|
| Sergunb |
0:f1834a63f7c1
|
2598
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2599
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2600
|
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
|
| Sergunb |
0:f1834a63f7c1
|
2601
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2602
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2603
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2604
|
assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
|
| Sergunb |
0:f1834a63f7c1
|
2605
|
|
| Sergunb |
0:f1834a63f7c1
|
2606
|
/* Clear the flags */
|
| Sergunb |
0:f1834a63f7c1
|
2607
|
TIMx->SR = (uint16_t)~TIM_FLAG;
|
| Sergunb |
0:f1834a63f7c1
|
2608
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2609
|
|
| Sergunb |
0:f1834a63f7c1
|
2610
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2611
|
* @brief Checks whether the TIM interrupt has occurred or not.
|
| Sergunb |
0:f1834a63f7c1
|
2612
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2613
|
* @param TIM_IT: specifies the TIM interrupt source to check.
|
| Sergunb |
0:f1834a63f7c1
|
2614
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2615
|
* @arg TIM_IT_Update: TIM update Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2616
|
* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2617
|
* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2618
|
* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2619
|
* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2620
|
* @arg TIM_IT_COM: TIM Commutation Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2621
|
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2622
|
* @arg TIM_IT_Break: TIM Break Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2623
|
* @note
|
| Sergunb |
0:f1834a63f7c1
|
2624
|
* - TIM6 and TIM7 can generate only an update interrupt.
|
| Sergunb |
0:f1834a63f7c1
|
2625
|
* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
|
| Sergunb |
0:f1834a63f7c1
|
2626
|
* TIM_IT_CC2 or TIM_IT_Trigger.
|
| Sergunb |
0:f1834a63f7c1
|
2627
|
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
|
| Sergunb |
0:f1834a63f7c1
|
2628
|
* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
|
| Sergunb |
0:f1834a63f7c1
|
2629
|
* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
|
| Sergunb |
0:f1834a63f7c1
|
2630
|
* @retval The new state of the TIM_IT(SET or RESET).
|
| Sergunb |
0:f1834a63f7c1
|
2631
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2632
|
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
|
| Sergunb |
0:f1834a63f7c1
|
2633
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2634
|
ITStatus bitstatus = RESET;
|
| Sergunb |
0:f1834a63f7c1
|
2635
|
uint16_t itstatus = 0x0, itenable = 0x0;
|
| Sergunb |
0:f1834a63f7c1
|
2636
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2637
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2638
|
assert_param(IS_TIM_GET_IT(TIM_IT));
|
| Sergunb |
0:f1834a63f7c1
|
2639
|
|
| Sergunb |
0:f1834a63f7c1
|
2640
|
itstatus = TIMx->SR & TIM_IT;
|
| Sergunb |
0:f1834a63f7c1
|
2641
|
|
| Sergunb |
0:f1834a63f7c1
|
2642
|
itenable = TIMx->DIER & TIM_IT;
|
| Sergunb |
0:f1834a63f7c1
|
2643
|
if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
|
| Sergunb |
0:f1834a63f7c1
|
2644
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2645
|
bitstatus = SET;
|
| Sergunb |
0:f1834a63f7c1
|
2646
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2647
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2648
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2649
|
bitstatus = RESET;
|
| Sergunb |
0:f1834a63f7c1
|
2650
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2651
|
return bitstatus;
|
| Sergunb |
0:f1834a63f7c1
|
2652
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2653
|
|
| Sergunb |
0:f1834a63f7c1
|
2654
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2655
|
* @brief Clears the TIMx's interrupt pending bits.
|
| Sergunb |
0:f1834a63f7c1
|
2656
|
* @param TIMx: where x can be 1 to 17 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2657
|
* @param TIM_IT: specifies the pending bit to clear.
|
| Sergunb |
0:f1834a63f7c1
|
2658
|
* This parameter can be any combination of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2659
|
* @arg TIM_IT_Update: TIM1 update Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2660
|
* @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2661
|
* @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2662
|
* @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2663
|
* @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2664
|
* @arg TIM_IT_COM: TIM Commutation Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2665
|
* @arg TIM_IT_Trigger: TIM Trigger Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2666
|
* @arg TIM_IT_Break: TIM Break Interrupt source
|
| Sergunb |
0:f1834a63f7c1
|
2667
|
* @note
|
| Sergunb |
0:f1834a63f7c1
|
2668
|
* - TIM6 and TIM7 can generate only an update interrupt.
|
| Sergunb |
0:f1834a63f7c1
|
2669
|
* - TIM9, TIM12 and TIM15 can have only TIM_IT_Update, TIM_IT_CC1,
|
| Sergunb |
0:f1834a63f7c1
|
2670
|
* TIM_IT_CC2 or TIM_IT_Trigger.
|
| Sergunb |
0:f1834a63f7c1
|
2671
|
* - TIM10, TIM11, TIM13, TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
|
| Sergunb |
0:f1834a63f7c1
|
2672
|
* - TIM_IT_Break is used only with TIM1, TIM8 and TIM15.
|
| Sergunb |
0:f1834a63f7c1
|
2673
|
* - TIM_IT_COM is used only with TIM1, TIM8, TIM15, TIM16 and TIM17.
|
| Sergunb |
0:f1834a63f7c1
|
2674
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2675
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2676
|
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
|
| Sergunb |
0:f1834a63f7c1
|
2677
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2678
|
/* Check the parameters */
|
| Sergunb |
0:f1834a63f7c1
|
2679
|
assert_param(IS_TIM_ALL_PERIPH(TIMx));
|
| Sergunb |
0:f1834a63f7c1
|
2680
|
assert_param(IS_TIM_IT(TIM_IT));
|
| Sergunb |
0:f1834a63f7c1
|
2681
|
/* Clear the IT pending Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2682
|
TIMx->SR = (uint16_t)~TIM_IT;
|
| Sergunb |
0:f1834a63f7c1
|
2683
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2684
|
|
| Sergunb |
0:f1834a63f7c1
|
2685
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2686
|
* @brief Configure the TI1 as Input.
|
| Sergunb |
0:f1834a63f7c1
|
2687
|
* @param TIMx: where x can be 1 to 17 except 6 and 7 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2688
|
* @param TIM_ICPolarity : The Input Polarity.
|
| Sergunb |
0:f1834a63f7c1
|
2689
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2690
|
* @arg TIM_ICPolarity_Rising
|
| Sergunb |
0:f1834a63f7c1
|
2691
|
* @arg TIM_ICPolarity_Falling
|
| Sergunb |
0:f1834a63f7c1
|
2692
|
* @param TIM_ICSelection: specifies the input to be used.
|
| Sergunb |
0:f1834a63f7c1
|
2693
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2694
|
* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
|
| Sergunb |
0:f1834a63f7c1
|
2695
|
* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
|
| Sergunb |
0:f1834a63f7c1
|
2696
|
* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
|
| Sergunb |
0:f1834a63f7c1
|
2697
|
* @param TIM_ICFilter: Specifies the Input Capture Filter.
|
| Sergunb |
0:f1834a63f7c1
|
2698
|
* This parameter must be a value between 0x00 and 0x0F.
|
| Sergunb |
0:f1834a63f7c1
|
2699
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2700
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2701
|
static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
2702
|
uint16_t TIM_ICFilter)
|
| Sergunb |
0:f1834a63f7c1
|
2703
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2704
|
uint16_t tmpccmr1 = 0, tmpccer = 0;
|
| Sergunb |
0:f1834a63f7c1
|
2705
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2706
|
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
|
| Sergunb |
0:f1834a63f7c1
|
2707
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
2708
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
2709
|
/* Select the Input and set the filter */
|
| Sergunb |
0:f1834a63f7c1
|
2710
|
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
|
| Sergunb |
0:f1834a63f7c1
|
2711
|
tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
|
| Sergunb |
0:f1834a63f7c1
|
2712
|
|
| Sergunb |
0:f1834a63f7c1
|
2713
|
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
|
| Sergunb |
0:f1834a63f7c1
|
2714
|
(TIMx == TIM4) ||(TIMx == TIM5))
|
| Sergunb |
0:f1834a63f7c1
|
2715
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2716
|
/* Select the Polarity and set the CC1E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2717
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P));
|
| Sergunb |
0:f1834a63f7c1
|
2718
|
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
|
| Sergunb |
0:f1834a63f7c1
|
2719
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2720
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2721
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2722
|
/* Select the Polarity and set the CC1E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2723
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
|
| Sergunb |
0:f1834a63f7c1
|
2724
|
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
|
| Sergunb |
0:f1834a63f7c1
|
2725
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2726
|
|
| Sergunb |
0:f1834a63f7c1
|
2727
|
/* Write to TIMx CCMR1 and CCER registers */
|
| Sergunb |
0:f1834a63f7c1
|
2728
|
TIMx->CCMR1 = tmpccmr1;
|
| Sergunb |
0:f1834a63f7c1
|
2729
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
2730
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2731
|
|
| Sergunb |
0:f1834a63f7c1
|
2732
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2733
|
* @brief Configure the TI2 as Input.
|
| Sergunb |
0:f1834a63f7c1
|
2734
|
* @param TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 12 or 15 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2735
|
* @param TIM_ICPolarity : The Input Polarity.
|
| Sergunb |
0:f1834a63f7c1
|
2736
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2737
|
* @arg TIM_ICPolarity_Rising
|
| Sergunb |
0:f1834a63f7c1
|
2738
|
* @arg TIM_ICPolarity_Falling
|
| Sergunb |
0:f1834a63f7c1
|
2739
|
* @param TIM_ICSelection: specifies the input to be used.
|
| Sergunb |
0:f1834a63f7c1
|
2740
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2741
|
* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
|
| Sergunb |
0:f1834a63f7c1
|
2742
|
* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
|
| Sergunb |
0:f1834a63f7c1
|
2743
|
* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
|
| Sergunb |
0:f1834a63f7c1
|
2744
|
* @param TIM_ICFilter: Specifies the Input Capture Filter.
|
| Sergunb |
0:f1834a63f7c1
|
2745
|
* This parameter must be a value between 0x00 and 0x0F.
|
| Sergunb |
0:f1834a63f7c1
|
2746
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2747
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2748
|
static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
2749
|
uint16_t TIM_ICFilter)
|
| Sergunb |
0:f1834a63f7c1
|
2750
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2751
|
uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
|
| Sergunb |
0:f1834a63f7c1
|
2752
|
/* Disable the Channel 2: Reset the CC2E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2753
|
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
|
| Sergunb |
0:f1834a63f7c1
|
2754
|
tmpccmr1 = TIMx->CCMR1;
|
| Sergunb |
0:f1834a63f7c1
|
2755
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
2756
|
tmp = (uint16_t)(TIM_ICPolarity << 4);
|
| Sergunb |
0:f1834a63f7c1
|
2757
|
/* Select the Input and set the filter */
|
| Sergunb |
0:f1834a63f7c1
|
2758
|
tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
|
| Sergunb |
0:f1834a63f7c1
|
2759
|
tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
|
| Sergunb |
0:f1834a63f7c1
|
2760
|
tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
|
| Sergunb |
0:f1834a63f7c1
|
2761
|
|
| Sergunb |
0:f1834a63f7c1
|
2762
|
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
|
| Sergunb |
0:f1834a63f7c1
|
2763
|
(TIMx == TIM4) ||(TIMx == TIM5))
|
| Sergunb |
0:f1834a63f7c1
|
2764
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2765
|
/* Select the Polarity and set the CC2E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2766
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P));
|
| Sergunb |
0:f1834a63f7c1
|
2767
|
tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
|
| Sergunb |
0:f1834a63f7c1
|
2768
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2769
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2770
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2771
|
/* Select the Polarity and set the CC2E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2772
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
|
| Sergunb |
0:f1834a63f7c1
|
2773
|
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC2E);
|
| Sergunb |
0:f1834a63f7c1
|
2774
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2775
|
|
| Sergunb |
0:f1834a63f7c1
|
2776
|
/* Write to TIMx CCMR1 and CCER registers */
|
| Sergunb |
0:f1834a63f7c1
|
2777
|
TIMx->CCMR1 = tmpccmr1 ;
|
| Sergunb |
0:f1834a63f7c1
|
2778
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
2779
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2780
|
|
| Sergunb |
0:f1834a63f7c1
|
2781
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2782
|
* @brief Configure the TI3 as Input.
|
| Sergunb |
0:f1834a63f7c1
|
2783
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2784
|
* @param TIM_ICPolarity : The Input Polarity.
|
| Sergunb |
0:f1834a63f7c1
|
2785
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2786
|
* @arg TIM_ICPolarity_Rising
|
| Sergunb |
0:f1834a63f7c1
|
2787
|
* @arg TIM_ICPolarity_Falling
|
| Sergunb |
0:f1834a63f7c1
|
2788
|
* @param TIM_ICSelection: specifies the input to be used.
|
| Sergunb |
0:f1834a63f7c1
|
2789
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2790
|
* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
|
| Sergunb |
0:f1834a63f7c1
|
2791
|
* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
|
| Sergunb |
0:f1834a63f7c1
|
2792
|
* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
|
| Sergunb |
0:f1834a63f7c1
|
2793
|
* @param TIM_ICFilter: Specifies the Input Capture Filter.
|
| Sergunb |
0:f1834a63f7c1
|
2794
|
* This parameter must be a value between 0x00 and 0x0F.
|
| Sergunb |
0:f1834a63f7c1
|
2795
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2796
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2797
|
static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
2798
|
uint16_t TIM_ICFilter)
|
| Sergunb |
0:f1834a63f7c1
|
2799
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2800
|
uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
|
| Sergunb |
0:f1834a63f7c1
|
2801
|
/* Disable the Channel 3: Reset the CC3E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2802
|
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
|
| Sergunb |
0:f1834a63f7c1
|
2803
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
2804
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
2805
|
tmp = (uint16_t)(TIM_ICPolarity << 8);
|
| Sergunb |
0:f1834a63f7c1
|
2806
|
/* Select the Input and set the filter */
|
| Sergunb |
0:f1834a63f7c1
|
2807
|
tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
|
| Sergunb |
0:f1834a63f7c1
|
2808
|
tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
|
| Sergunb |
0:f1834a63f7c1
|
2809
|
|
| Sergunb |
0:f1834a63f7c1
|
2810
|
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
|
| Sergunb |
0:f1834a63f7c1
|
2811
|
(TIMx == TIM4) ||(TIMx == TIM5))
|
| Sergunb |
0:f1834a63f7c1
|
2812
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2813
|
/* Select the Polarity and set the CC3E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2814
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P));
|
| Sergunb |
0:f1834a63f7c1
|
2815
|
tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
|
| Sergunb |
0:f1834a63f7c1
|
2816
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2817
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2818
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2819
|
/* Select the Polarity and set the CC3E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2820
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
|
| Sergunb |
0:f1834a63f7c1
|
2821
|
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC3E);
|
| Sergunb |
0:f1834a63f7c1
|
2822
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2823
|
|
| Sergunb |
0:f1834a63f7c1
|
2824
|
/* Write to TIMx CCMR2 and CCER registers */
|
| Sergunb |
0:f1834a63f7c1
|
2825
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
2826
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
2827
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2828
|
|
| Sergunb |
0:f1834a63f7c1
|
2829
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2830
|
* @brief Configure the TI4 as Input.
|
| Sergunb |
0:f1834a63f7c1
|
2831
|
* @param TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
|
| Sergunb |
0:f1834a63f7c1
|
2832
|
* @param TIM_ICPolarity : The Input Polarity.
|
| Sergunb |
0:f1834a63f7c1
|
2833
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2834
|
* @arg TIM_ICPolarity_Rising
|
| Sergunb |
0:f1834a63f7c1
|
2835
|
* @arg TIM_ICPolarity_Falling
|
| Sergunb |
0:f1834a63f7c1
|
2836
|
* @param TIM_ICSelection: specifies the input to be used.
|
| Sergunb |
0:f1834a63f7c1
|
2837
|
* This parameter can be one of the following values:
|
| Sergunb |
0:f1834a63f7c1
|
2838
|
* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
|
| Sergunb |
0:f1834a63f7c1
|
2839
|
* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
|
| Sergunb |
0:f1834a63f7c1
|
2840
|
* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
|
| Sergunb |
0:f1834a63f7c1
|
2841
|
* @param TIM_ICFilter: Specifies the Input Capture Filter.
|
| Sergunb |
0:f1834a63f7c1
|
2842
|
* This parameter must be a value between 0x00 and 0x0F.
|
| Sergunb |
0:f1834a63f7c1
|
2843
|
* @retval None
|
| Sergunb |
0:f1834a63f7c1
|
2844
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2845
|
static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
|
| Sergunb |
0:f1834a63f7c1
|
2846
|
uint16_t TIM_ICFilter)
|
| Sergunb |
0:f1834a63f7c1
|
2847
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2848
|
uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
|
| Sergunb |
0:f1834a63f7c1
|
2849
|
|
| Sergunb |
0:f1834a63f7c1
|
2850
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2851
|
TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
|
| Sergunb |
0:f1834a63f7c1
|
2852
|
tmpccmr2 = TIMx->CCMR2;
|
| Sergunb |
0:f1834a63f7c1
|
2853
|
tmpccer = TIMx->CCER;
|
| Sergunb |
0:f1834a63f7c1
|
2854
|
tmp = (uint16_t)(TIM_ICPolarity << 12);
|
| Sergunb |
0:f1834a63f7c1
|
2855
|
/* Select the Input and set the filter */
|
| Sergunb |
0:f1834a63f7c1
|
2856
|
tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
|
| Sergunb |
0:f1834a63f7c1
|
2857
|
tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
|
| Sergunb |
0:f1834a63f7c1
|
2858
|
tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
|
| Sergunb |
0:f1834a63f7c1
|
2859
|
|
| Sergunb |
0:f1834a63f7c1
|
2860
|
if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM2) || (TIMx == TIM3) ||
|
| Sergunb |
0:f1834a63f7c1
|
2861
|
(TIMx == TIM4) ||(TIMx == TIM5))
|
| Sergunb |
0:f1834a63f7c1
|
2862
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2863
|
/* Select the Polarity and set the CC4E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2864
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P));
|
| Sergunb |
0:f1834a63f7c1
|
2865
|
tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
|
| Sergunb |
0:f1834a63f7c1
|
2866
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2867
|
else
|
| Sergunb |
0:f1834a63f7c1
|
2868
|
{
|
| Sergunb |
0:f1834a63f7c1
|
2869
|
/* Select the Polarity and set the CC4E Bit */
|
| Sergunb |
0:f1834a63f7c1
|
2870
|
tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC4NP));
|
| Sergunb |
0:f1834a63f7c1
|
2871
|
tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC4E);
|
| Sergunb |
0:f1834a63f7c1
|
2872
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2873
|
/* Write to TIMx CCMR2 and CCER registers */
|
| Sergunb |
0:f1834a63f7c1
|
2874
|
TIMx->CCMR2 = tmpccmr2;
|
| Sergunb |
0:f1834a63f7c1
|
2875
|
TIMx->CCER = tmpccer;
|
| Sergunb |
0:f1834a63f7c1
|
2876
|
}
|
| Sergunb |
0:f1834a63f7c1
|
2877
|
|
| Sergunb |
0:f1834a63f7c1
|
2878
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2879
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
2880
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2881
|
|
| Sergunb |
0:f1834a63f7c1
|
2882
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2883
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
2884
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2885
|
|
| Sergunb |
0:f1834a63f7c1
|
2886
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
2887
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
2888
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
2889
|
|
| Sergunb |
0:f1834a63f7c1
|
2890
|
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
|