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/**
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******************************************************************************
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* @file stm32f10x_tim.h
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* @author MCD Application Team
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* @version V3.4.0
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* @date 10/15/2010
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* @brief This file contains all the functions prototypes for the TIM firmware
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* library.
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******************************************************************************
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* @copy
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
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* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F10x_TIM_H
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#define __STM32F10x_TIM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f10x.h"
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/** @addtogroup STM32F10x_StdPeriph_Driver
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* @{
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*/
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/** @addtogroup TIM
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* @{
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*/
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/** @defgroup TIM_Exported_Types
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* @{
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*/
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/**
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* @brief TIM Time Base Init structure definition
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* @note This sturcture is used with all TIMx except for TIM6 and TIM7.
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*/
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typedef struct
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{
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uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
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This parameter can be a value of @ref TIM_Counter_Mode */
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uint16_t TIM_Period; /*!< Specifies the period value to be loaded into the active
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Auto-Reload Register at the next update event.
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This parameter must be a number between 0x0000 and 0xFFFF. */
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uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
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This parameter can be a value of @ref TIM_Clock_Division_CKD */
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uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
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reaches zero, an update event is generated and counting restarts
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from the RCR value (N).
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This means in PWM mode that (N+1) corresponds to:
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- the number of PWM periods in edge-aligned mode
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- the number of half PWM period in center-aligned mode
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This parameter must be a number between 0x00 and 0xFF.
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@note This parameter is valid only for TIM1 and TIM8. */
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} TIM_TimeBaseInitTypeDef;
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/**
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* @brief TIM Output Compare Init structure definition
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*/
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typedef struct
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{
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uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
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This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
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uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
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This parameter can be a value of @ref TIM_Output_Compare_state */
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uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
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This parameter can be a value of @ref TIM_Output_Compare_N_state
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@note This parameter is valid only for TIM1 and TIM8. */
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uint16_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
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This parameter can be a value of @ref TIM_Output_Compare_Polarity */
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uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
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This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
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@note This parameter is valid only for TIM1 and TIM8. */
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uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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This parameter can be a value of @ref TIM_Output_Compare_Idle_State
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@note This parameter is valid only for TIM1 and TIM8. */
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uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
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This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
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@note This parameter is valid only for TIM1 and TIM8. */
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} TIM_OCInitTypeDef;
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/**
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* @brief TIM Input Capture Init structure definition
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*/
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typedef struct
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{
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uint16_t TIM_Channel; /*!< Specifies the TIM channel.
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This parameter can be a value of @ref TIM_Channel */
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uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
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This parameter can be a value of @ref TIM_Input_Capture_Polarity */
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uint16_t TIM_ICSelection; /*!< Specifies the input.
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This parameter can be a value of @ref TIM_Input_Capture_Selection */
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uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
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This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
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uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
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This parameter can be a number between 0x0 and 0xF */
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} TIM_ICInitTypeDef;
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/**
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* @brief BDTR structure definition
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* @note This sturcture is used only with TIM1 and TIM8.
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*/
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typedef struct
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{
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uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
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This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
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uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
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This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
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uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
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This parameter can be a value of @ref Lock_level */
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uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
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switching-on of the outputs.
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This parameter can be a number between 0x00 and 0xFF */
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uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
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This parameter can be a value of @ref Break_Input_enable_disable */
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uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
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This parameter can be a value of @ref Break_Polarity */
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uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
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This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
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} TIM_BDTRInitTypeDef;
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/** @defgroup TIM_Exported_constants
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* @{
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*/
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#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM6) || \
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((PERIPH) == TIM7) || \
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((PERIPH) == TIM8) || \
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((PERIPH) == TIM9) || \
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((PERIPH) == TIM10)|| \
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((PERIPH) == TIM11)|| \
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((PERIPH) == TIM12)|| \
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((PERIPH) == TIM13)|| \
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((PERIPH) == TIM14)|| \
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((PERIPH) == TIM15)|| \
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((PERIPH) == TIM16)|| \
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((PERIPH) == TIM17))
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/* LIST1: TIM 1 and 8 */
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#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM8))
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/* LIST2: TIM 1, 8, 15 16 and 17 */
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#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM8) || \
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((PERIPH) == TIM15)|| \
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((PERIPH) == TIM16)|| \
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((PERIPH) == TIM17))
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/* LIST3: TIM 1, 2, 3, 4, 5 and 8 */
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#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM8))
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/* LIST4: TIM 1, 2, 3, 4, 5, 8, 15, 16 and 17 */
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#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM8) || \
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((PERIPH) == TIM15)|| \
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((PERIPH) == TIM16)|| \
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((PERIPH) == TIM17))
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/* LIST5: TIM 1, 2, 3, 4, 5, 8 and 15 */
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#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM8) || \
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((PERIPH) == TIM15))
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/* LIST6: TIM 1, 2, 3, 4, 5, 8, 9, 12 and 15 */
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#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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((PERIPH) == TIM3) || \
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((PERIPH) == TIM4) || \
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((PERIPH) == TIM5) || \
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((PERIPH) == TIM8) || \
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((PERIPH) == TIM9) || \
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233
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((PERIPH) == TIM12)|| \
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|
((PERIPH) == TIM15))
|
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235
|
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|
/* LIST7: TIM 1, 2, 3, 4, 5, 6, 7, 8, 9, 12 and 15 */
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#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
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((PERIPH) == TIM2) || \
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|
239
|
((PERIPH) == TIM3) || \
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240
|
((PERIPH) == TIM4) || \
|
| Sergunb |
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241
|
((PERIPH) == TIM5) || \
|
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242
|
((PERIPH) == TIM6) || \
|
| Sergunb |
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|
243
|
((PERIPH) == TIM7) || \
|
| Sergunb |
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|
244
|
((PERIPH) == TIM8) || \
|
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|
245
|
((PERIPH) == TIM9) || \
|
| Sergunb |
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|
246
|
((PERIPH) == TIM12)|| \
|
| Sergunb |
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|
247
|
((PERIPH) == TIM15))
|
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|
248
|
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|
/* LIST8: TIM 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13, 14, 15, 16 and 17 */
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250
|
#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
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|
251
|
((PERIPH) == TIM2) || \
|
| Sergunb |
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|
252
|
((PERIPH) == TIM3) || \
|
| Sergunb |
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|
253
|
((PERIPH) == TIM4) || \
|
| Sergunb |
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|
254
|
((PERIPH) == TIM5) || \
|
| Sergunb |
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|
255
|
((PERIPH) == TIM8) || \
|
| Sergunb |
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|
256
|
((PERIPH) == TIM9) || \
|
| Sergunb |
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|
257
|
((PERIPH) == TIM10)|| \
|
| Sergunb |
0:f1834a63f7c1
|
258
|
((PERIPH) == TIM11)|| \
|
| Sergunb |
0:f1834a63f7c1
|
259
|
((PERIPH) == TIM12)|| \
|
| Sergunb |
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|
260
|
((PERIPH) == TIM13)|| \
|
| Sergunb |
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|
261
|
((PERIPH) == TIM14)|| \
|
| Sergunb |
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|
262
|
((PERIPH) == TIM15)|| \
|
| Sergunb |
0:f1834a63f7c1
|
263
|
((PERIPH) == TIM16)|| \
|
| Sergunb |
0:f1834a63f7c1
|
264
|
((PERIPH) == TIM17))
|
| Sergunb |
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|
265
|
|
| Sergunb |
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|
266
|
/* LIST9: TIM 1, 2, 3, 4, 5, 6, 7, 8, 15, 16, and 17 */
|
| Sergunb |
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|
267
|
#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
|
| Sergunb |
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|
268
|
((PERIPH) == TIM2) || \
|
| Sergunb |
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|
269
|
((PERIPH) == TIM3) || \
|
| Sergunb |
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|
270
|
((PERIPH) == TIM4) || \
|
| Sergunb |
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|
271
|
((PERIPH) == TIM5) || \
|
| Sergunb |
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|
272
|
((PERIPH) == TIM6) || \
|
| Sergunb |
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|
273
|
((PERIPH) == TIM7) || \
|
| Sergunb |
0:f1834a63f7c1
|
274
|
((PERIPH) == TIM8) || \
|
| Sergunb |
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|
275
|
((PERIPH) == TIM15)|| \
|
| Sergunb |
0:f1834a63f7c1
|
276
|
((PERIPH) == TIM16)|| \
|
| Sergunb |
0:f1834a63f7c1
|
277
|
((PERIPH) == TIM17))
|
| Sergunb |
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|
278
|
|
| Sergunb |
0:f1834a63f7c1
|
279
|
/**
|
| Sergunb |
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|
280
|
* @}
|
| Sergunb |
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|
281
|
*/
|
| Sergunb |
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|
282
|
|
| Sergunb |
0:f1834a63f7c1
|
283
|
/** @defgroup TIM_Output_Compare_and_PWM_modes
|
| Sergunb |
0:f1834a63f7c1
|
284
|
* @{
|
| Sergunb |
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|
285
|
*/
|
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|
286
|
|
| Sergunb |
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|
287
|
#define TIM_OCMode_Timing ((uint16_t)0x0000)
|
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288
|
#define TIM_OCMode_Active ((uint16_t)0x0010)
|
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289
|
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
|
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290
|
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
|
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|
291
|
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
|
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|
292
|
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
|
| Sergunb |
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|
293
|
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
|
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|
294
|
((MODE) == TIM_OCMode_Active) || \
|
| Sergunb |
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|
295
|
((MODE) == TIM_OCMode_Inactive) || \
|
| Sergunb |
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|
296
|
((MODE) == TIM_OCMode_Toggle)|| \
|
| Sergunb |
0:f1834a63f7c1
|
297
|
((MODE) == TIM_OCMode_PWM1) || \
|
| Sergunb |
0:f1834a63f7c1
|
298
|
((MODE) == TIM_OCMode_PWM2))
|
| Sergunb |
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|
299
|
#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
|
| Sergunb |
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|
300
|
((MODE) == TIM_OCMode_Active) || \
|
| Sergunb |
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|
301
|
((MODE) == TIM_OCMode_Inactive) || \
|
| Sergunb |
0:f1834a63f7c1
|
302
|
((MODE) == TIM_OCMode_Toggle)|| \
|
| Sergunb |
0:f1834a63f7c1
|
303
|
((MODE) == TIM_OCMode_PWM1) || \
|
| Sergunb |
0:f1834a63f7c1
|
304
|
((MODE) == TIM_OCMode_PWM2) || \
|
| Sergunb |
0:f1834a63f7c1
|
305
|
((MODE) == TIM_ForcedAction_Active) || \
|
| Sergunb |
0:f1834a63f7c1
|
306
|
((MODE) == TIM_ForcedAction_InActive))
|
| Sergunb |
0:f1834a63f7c1
|
307
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
308
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
309
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
310
|
|
| Sergunb |
0:f1834a63f7c1
|
311
|
/** @defgroup TIM_One_Pulse_Mode
|
| Sergunb |
0:f1834a63f7c1
|
312
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
313
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
314
|
|
| Sergunb |
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|
315
|
#define TIM_OPMode_Single ((uint16_t)0x0008)
|
| Sergunb |
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|
316
|
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
317
|
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
|
| Sergunb |
0:f1834a63f7c1
|
318
|
((MODE) == TIM_OPMode_Repetitive))
|
| Sergunb |
0:f1834a63f7c1
|
319
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
320
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
321
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
322
|
|
| Sergunb |
0:f1834a63f7c1
|
323
|
/** @defgroup TIM_Channel
|
| Sergunb |
0:f1834a63f7c1
|
324
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
325
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
326
|
|
| Sergunb |
0:f1834a63f7c1
|
327
|
#define TIM_Channel_1 ((uint16_t)0x0000)
|
| Sergunb |
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|
328
|
#define TIM_Channel_2 ((uint16_t)0x0004)
|
| Sergunb |
0:f1834a63f7c1
|
329
|
#define TIM_Channel_3 ((uint16_t)0x0008)
|
| Sergunb |
0:f1834a63f7c1
|
330
|
#define TIM_Channel_4 ((uint16_t)0x000C)
|
| Sergunb |
0:f1834a63f7c1
|
331
|
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
| Sergunb |
0:f1834a63f7c1
|
332
|
((CHANNEL) == TIM_Channel_2) || \
|
| Sergunb |
0:f1834a63f7c1
|
333
|
((CHANNEL) == TIM_Channel_3) || \
|
| Sergunb |
0:f1834a63f7c1
|
334
|
((CHANNEL) == TIM_Channel_4))
|
| Sergunb |
0:f1834a63f7c1
|
335
|
#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
| Sergunb |
0:f1834a63f7c1
|
336
|
((CHANNEL) == TIM_Channel_2))
|
| Sergunb |
0:f1834a63f7c1
|
337
|
#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
| Sergunb |
0:f1834a63f7c1
|
338
|
((CHANNEL) == TIM_Channel_2) || \
|
| Sergunb |
0:f1834a63f7c1
|
339
|
((CHANNEL) == TIM_Channel_3))
|
| Sergunb |
0:f1834a63f7c1
|
340
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
341
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
342
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
343
|
|
| Sergunb |
0:f1834a63f7c1
|
344
|
/** @defgroup TIM_Clock_Division_CKD
|
| Sergunb |
0:f1834a63f7c1
|
345
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
346
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
347
|
|
| Sergunb |
0:f1834a63f7c1
|
348
|
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
349
|
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
|
| Sergunb |
0:f1834a63f7c1
|
350
|
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
|
| Sergunb |
0:f1834a63f7c1
|
351
|
#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
|
| Sergunb |
0:f1834a63f7c1
|
352
|
((DIV) == TIM_CKD_DIV2) || \
|
| Sergunb |
0:f1834a63f7c1
|
353
|
((DIV) == TIM_CKD_DIV4))
|
| Sergunb |
0:f1834a63f7c1
|
354
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
355
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
356
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
357
|
|
| Sergunb |
0:f1834a63f7c1
|
358
|
/** @defgroup TIM_Counter_Mode
|
| Sergunb |
0:f1834a63f7c1
|
359
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
360
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
361
|
|
| Sergunb |
0:f1834a63f7c1
|
362
|
#define TIM_CounterMode_Up ((uint16_t)0x0000)
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| Sergunb |
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#define TIM_CounterMode_Down ((uint16_t)0x0010)
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#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
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#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
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#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
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#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
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((MODE) == TIM_CounterMode_Down) || \
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((MODE) == TIM_CounterMode_CenterAligned1) || \
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((MODE) == TIM_CounterMode_CenterAligned2) || \
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((MODE) == TIM_CounterMode_CenterAligned3))
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/**
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* @}
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*/
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/** @defgroup TIM_Output_Compare_Polarity
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377
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* @{
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*/
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#define TIM_OCPolarity_High ((uint16_t)0x0000)
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#define TIM_OCPolarity_Low ((uint16_t)0x0002)
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#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
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((POLARITY) == TIM_OCPolarity_Low))
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384
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/**
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385
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* @}
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386
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*/
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387
|
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| Sergunb |
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388
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/** @defgroup TIM_Output_Compare_N_Polarity
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* @{
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*/
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#define TIM_OCNPolarity_High ((uint16_t)0x0000)
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393
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#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
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#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
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((POLARITY) == TIM_OCNPolarity_Low))
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396
|
/**
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397
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* @}
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| Sergunb |
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398
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*/
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399
|
|
| Sergunb |
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400
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/** @defgroup TIM_Output_Compare_state
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401
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* @{
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| Sergunb |
0:f1834a63f7c1
|
402
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*/
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|
403
|
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404
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#define TIM_OutputState_Disable ((uint16_t)0x0000)
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405
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#define TIM_OutputState_Enable ((uint16_t)0x0001)
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406
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#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
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407
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((STATE) == TIM_OutputState_Enable))
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| Sergunb |
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|
408
|
/**
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| Sergunb |
0:f1834a63f7c1
|
409
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* @}
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| Sergunb |
0:f1834a63f7c1
|
410
|
*/
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| Sergunb |
0:f1834a63f7c1
|
411
|
|
| Sergunb |
0:f1834a63f7c1
|
412
|
/** @defgroup TIM_Output_Compare_N_state
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| Sergunb |
0:f1834a63f7c1
|
413
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
414
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*/
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0:f1834a63f7c1
|
415
|
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| Sergunb |
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416
|
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
|
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417
|
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
|
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0:f1834a63f7c1
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418
|
#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
|
| Sergunb |
0:f1834a63f7c1
|
419
|
((STATE) == TIM_OutputNState_Enable))
|
| Sergunb |
0:f1834a63f7c1
|
420
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
421
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
422
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
423
|
|
| Sergunb |
0:f1834a63f7c1
|
424
|
/** @defgroup TIM_Capture_Compare_state
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| Sergunb |
0:f1834a63f7c1
|
425
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
426
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
427
|
|
| Sergunb |
0:f1834a63f7c1
|
428
|
#define TIM_CCx_Enable ((uint16_t)0x0001)
|
| Sergunb |
0:f1834a63f7c1
|
429
|
#define TIM_CCx_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
430
|
#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
431
|
((CCX) == TIM_CCx_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
432
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
433
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
434
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
435
|
|
| Sergunb |
0:f1834a63f7c1
|
436
|
/** @defgroup TIM_Capture_Compare_N_state
|
| Sergunb |
0:f1834a63f7c1
|
437
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
438
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
439
|
|
| Sergunb |
0:f1834a63f7c1
|
440
|
#define TIM_CCxN_Enable ((uint16_t)0x0004)
|
| Sergunb |
0:f1834a63f7c1
|
441
|
#define TIM_CCxN_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
442
|
#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
443
|
((CCXN) == TIM_CCxN_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
444
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
445
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
446
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
447
|
|
| Sergunb |
0:f1834a63f7c1
|
448
|
/** @defgroup Break_Input_enable_disable
|
| Sergunb |
0:f1834a63f7c1
|
449
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
450
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
451
|
|
| Sergunb |
0:f1834a63f7c1
|
452
|
#define TIM_Break_Enable ((uint16_t)0x1000)
|
| Sergunb |
0:f1834a63f7c1
|
453
|
#define TIM_Break_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
454
|
#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
455
|
((STATE) == TIM_Break_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
456
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
457
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
458
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
459
|
|
| Sergunb |
0:f1834a63f7c1
|
460
|
/** @defgroup Break_Polarity
|
| Sergunb |
0:f1834a63f7c1
|
461
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
462
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
463
|
|
| Sergunb |
0:f1834a63f7c1
|
464
|
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
465
|
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
|
| Sergunb |
0:f1834a63f7c1
|
466
|
#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
|
| Sergunb |
0:f1834a63f7c1
|
467
|
((POLARITY) == TIM_BreakPolarity_High))
|
| Sergunb |
0:f1834a63f7c1
|
468
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
469
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
470
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
471
|
|
| Sergunb |
0:f1834a63f7c1
|
472
|
/** @defgroup TIM_AOE_Bit_Set_Reset
|
| Sergunb |
0:f1834a63f7c1
|
473
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
474
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
475
|
|
| Sergunb |
0:f1834a63f7c1
|
476
|
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
|
| Sergunb |
0:f1834a63f7c1
|
477
|
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
478
|
#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
479
|
((STATE) == TIM_AutomaticOutput_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
480
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
481
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
482
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
483
|
|
| Sergunb |
0:f1834a63f7c1
|
484
|
/** @defgroup Lock_level
|
| Sergunb |
0:f1834a63f7c1
|
485
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
486
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
487
|
|
| Sergunb |
0:f1834a63f7c1
|
488
|
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
489
|
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
|
| Sergunb |
0:f1834a63f7c1
|
490
|
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
|
| Sergunb |
0:f1834a63f7c1
|
491
|
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
|
| Sergunb |
0:f1834a63f7c1
|
492
|
#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
|
| Sergunb |
0:f1834a63f7c1
|
493
|
((LEVEL) == TIM_LOCKLevel_1) || \
|
| Sergunb |
0:f1834a63f7c1
|
494
|
((LEVEL) == TIM_LOCKLevel_2) || \
|
| Sergunb |
0:f1834a63f7c1
|
495
|
((LEVEL) == TIM_LOCKLevel_3))
|
| Sergunb |
0:f1834a63f7c1
|
496
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
497
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
498
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
499
|
|
| Sergunb |
0:f1834a63f7c1
|
500
|
/** @defgroup OSSI_Off_State_Selection_for_Idle_mode_state
|
| Sergunb |
0:f1834a63f7c1
|
501
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
502
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
503
|
|
| Sergunb |
0:f1834a63f7c1
|
504
|
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
|
| Sergunb |
0:f1834a63f7c1
|
505
|
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
506
|
#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
507
|
((STATE) == TIM_OSSIState_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
508
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
509
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
510
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
511
|
|
| Sergunb |
0:f1834a63f7c1
|
512
|
/** @defgroup OSSR_Off_State_Selection_for_Run_mode_state
|
| Sergunb |
0:f1834a63f7c1
|
513
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
514
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
515
|
|
| Sergunb |
0:f1834a63f7c1
|
516
|
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
|
| Sergunb |
0:f1834a63f7c1
|
517
|
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
518
|
#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
519
|
((STATE) == TIM_OSSRState_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
520
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
521
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
522
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
523
|
|
| Sergunb |
0:f1834a63f7c1
|
524
|
/** @defgroup TIM_Output_Compare_Idle_State
|
| Sergunb |
0:f1834a63f7c1
|
525
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
526
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
527
|
|
| Sergunb |
0:f1834a63f7c1
|
528
|
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
|
| Sergunb |
0:f1834a63f7c1
|
529
|
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
530
|
#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
|
| Sergunb |
0:f1834a63f7c1
|
531
|
((STATE) == TIM_OCIdleState_Reset))
|
| Sergunb |
0:f1834a63f7c1
|
532
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
533
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
534
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
535
|
|
| Sergunb |
0:f1834a63f7c1
|
536
|
/** @defgroup TIM_Output_Compare_N_Idle_State
|
| Sergunb |
0:f1834a63f7c1
|
537
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
538
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
539
|
|
| Sergunb |
0:f1834a63f7c1
|
540
|
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
|
| Sergunb |
0:f1834a63f7c1
|
541
|
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
542
|
#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
|
| Sergunb |
0:f1834a63f7c1
|
543
|
((STATE) == TIM_OCNIdleState_Reset))
|
| Sergunb |
0:f1834a63f7c1
|
544
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
545
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
546
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
547
|
|
| Sergunb |
0:f1834a63f7c1
|
548
|
/** @defgroup TIM_Input_Capture_Polarity
|
| Sergunb |
0:f1834a63f7c1
|
549
|
* @{
|
| Sergunb |
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|
*/
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551
|
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| Sergunb |
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|
552
|
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
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0:f1834a63f7c1
|
553
|
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
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0:f1834a63f7c1
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554
|
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
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0:f1834a63f7c1
|
555
|
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
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0:f1834a63f7c1
|
556
|
((POLARITY) == TIM_ICPolarity_Falling))
|
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0:f1834a63f7c1
|
557
|
#define IS_TIM_IC_POLARITY_LITE(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
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0:f1834a63f7c1
|
558
|
((POLARITY) == TIM_ICPolarity_Falling)|| \
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| Sergunb |
0:f1834a63f7c1
|
559
|
((POLARITY) == TIM_ICPolarity_BothEdge))
|
| Sergunb |
0:f1834a63f7c1
|
560
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
561
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
562
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
563
|
|
| Sergunb |
0:f1834a63f7c1
|
564
|
/** @defgroup TIM_Input_Capture_Selection
|
| Sergunb |
0:f1834a63f7c1
|
565
|
* @{
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| Sergunb |
0:f1834a63f7c1
|
566
|
*/
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| Sergunb |
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|
567
|
|
| Sergunb |
0:f1834a63f7c1
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568
|
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
| Sergunb |
0:f1834a63f7c1
|
569
|
connected to IC1, IC2, IC3 or IC4, respectively */
|
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0:f1834a63f7c1
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570
|
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
| Sergunb |
0:f1834a63f7c1
|
571
|
connected to IC2, IC1, IC4 or IC3, respectively. */
|
| Sergunb |
0:f1834a63f7c1
|
572
|
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
|
| Sergunb |
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|
573
|
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
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|
574
|
((SELECTION) == TIM_ICSelection_IndirectTI) || \
|
| Sergunb |
0:f1834a63f7c1
|
575
|
((SELECTION) == TIM_ICSelection_TRC))
|
| Sergunb |
0:f1834a63f7c1
|
576
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
577
|
* @}
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| Sergunb |
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|
578
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
579
|
|
| Sergunb |
0:f1834a63f7c1
|
580
|
/** @defgroup TIM_Input_Capture_Prescaler
|
| Sergunb |
0:f1834a63f7c1
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581
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
582
|
*/
|
| Sergunb |
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|
583
|
|
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0:f1834a63f7c1
|
584
|
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
|
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0:f1834a63f7c1
|
585
|
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
|
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0:f1834a63f7c1
|
586
|
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
|
| Sergunb |
0:f1834a63f7c1
|
587
|
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
|
| Sergunb |
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|
588
|
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
|
| Sergunb |
0:f1834a63f7c1
|
589
|
((PRESCALER) == TIM_ICPSC_DIV2) || \
|
| Sergunb |
0:f1834a63f7c1
|
590
|
((PRESCALER) == TIM_ICPSC_DIV4) || \
|
| Sergunb |
0:f1834a63f7c1
|
591
|
((PRESCALER) == TIM_ICPSC_DIV8))
|
| Sergunb |
0:f1834a63f7c1
|
592
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
593
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
594
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
595
|
|
| Sergunb |
0:f1834a63f7c1
|
596
|
/** @defgroup TIM_interrupt_sources
|
| Sergunb |
0:f1834a63f7c1
|
597
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
598
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
599
|
|
| Sergunb |
0:f1834a63f7c1
|
600
|
#define TIM_IT_Update ((uint16_t)0x0001)
|
| Sergunb |
0:f1834a63f7c1
|
601
|
#define TIM_IT_CC1 ((uint16_t)0x0002)
|
| Sergunb |
0:f1834a63f7c1
|
602
|
#define TIM_IT_CC2 ((uint16_t)0x0004)
|
| Sergunb |
0:f1834a63f7c1
|
603
|
#define TIM_IT_CC3 ((uint16_t)0x0008)
|
| Sergunb |
0:f1834a63f7c1
|
604
|
#define TIM_IT_CC4 ((uint16_t)0x0010)
|
| Sergunb |
0:f1834a63f7c1
|
605
|
#define TIM_IT_COM ((uint16_t)0x0020)
|
| Sergunb |
0:f1834a63f7c1
|
606
|
#define TIM_IT_Trigger ((uint16_t)0x0040)
|
| Sergunb |
0:f1834a63f7c1
|
607
|
#define TIM_IT_Break ((uint16_t)0x0080)
|
| Sergunb |
0:f1834a63f7c1
|
608
|
#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
|
| Sergunb |
0:f1834a63f7c1
|
609
|
|
| Sergunb |
0:f1834a63f7c1
|
610
|
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
|
| Sergunb |
0:f1834a63f7c1
|
611
|
((IT) == TIM_IT_CC1) || \
|
| Sergunb |
0:f1834a63f7c1
|
612
|
((IT) == TIM_IT_CC2) || \
|
| Sergunb |
0:f1834a63f7c1
|
613
|
((IT) == TIM_IT_CC3) || \
|
| Sergunb |
0:f1834a63f7c1
|
614
|
((IT) == TIM_IT_CC4) || \
|
| Sergunb |
0:f1834a63f7c1
|
615
|
((IT) == TIM_IT_COM) || \
|
| Sergunb |
0:f1834a63f7c1
|
616
|
((IT) == TIM_IT_Trigger) || \
|
| Sergunb |
0:f1834a63f7c1
|
617
|
((IT) == TIM_IT_Break))
|
| Sergunb |
0:f1834a63f7c1
|
618
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
619
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
620
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
621
|
|
| Sergunb |
0:f1834a63f7c1
|
622
|
/** @defgroup TIM_DMA_Base_address
|
| Sergunb |
0:f1834a63f7c1
|
623
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
624
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
625
|
|
| Sergunb |
0:f1834a63f7c1
|
626
|
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
627
|
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
|
| Sergunb |
0:f1834a63f7c1
|
628
|
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
|
| Sergunb |
0:f1834a63f7c1
|
629
|
#define TIM_DMABase_DIER ((uint16_t)0x0003)
|
| Sergunb |
0:f1834a63f7c1
|
630
|
#define TIM_DMABase_SR ((uint16_t)0x0004)
|
| Sergunb |
0:f1834a63f7c1
|
631
|
#define TIM_DMABase_EGR ((uint16_t)0x0005)
|
| Sergunb |
0:f1834a63f7c1
|
632
|
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
|
| Sergunb |
0:f1834a63f7c1
|
633
|
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
|
| Sergunb |
0:f1834a63f7c1
|
634
|
#define TIM_DMABase_CCER ((uint16_t)0x0008)
|
| Sergunb |
0:f1834a63f7c1
|
635
|
#define TIM_DMABase_CNT ((uint16_t)0x0009)
|
| Sergunb |
0:f1834a63f7c1
|
636
|
#define TIM_DMABase_PSC ((uint16_t)0x000A)
|
| Sergunb |
0:f1834a63f7c1
|
637
|
#define TIM_DMABase_ARR ((uint16_t)0x000B)
|
| Sergunb |
0:f1834a63f7c1
|
638
|
#define TIM_DMABase_RCR ((uint16_t)0x000C)
|
| Sergunb |
0:f1834a63f7c1
|
639
|
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
|
| Sergunb |
0:f1834a63f7c1
|
640
|
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
|
| Sergunb |
0:f1834a63f7c1
|
641
|
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
|
| Sergunb |
0:f1834a63f7c1
|
642
|
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
|
| Sergunb |
0:f1834a63f7c1
|
643
|
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
|
| Sergunb |
0:f1834a63f7c1
|
644
|
#define TIM_DMABase_DCR ((uint16_t)0x0012)
|
| Sergunb |
0:f1834a63f7c1
|
645
|
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
|
| Sergunb |
0:f1834a63f7c1
|
646
|
((BASE) == TIM_DMABase_CR2) || \
|
| Sergunb |
0:f1834a63f7c1
|
647
|
((BASE) == TIM_DMABase_SMCR) || \
|
| Sergunb |
0:f1834a63f7c1
|
648
|
((BASE) == TIM_DMABase_DIER) || \
|
| Sergunb |
0:f1834a63f7c1
|
649
|
((BASE) == TIM_DMABase_SR) || \
|
| Sergunb |
0:f1834a63f7c1
|
650
|
((BASE) == TIM_DMABase_EGR) || \
|
| Sergunb |
0:f1834a63f7c1
|
651
|
((BASE) == TIM_DMABase_CCMR1) || \
|
| Sergunb |
0:f1834a63f7c1
|
652
|
((BASE) == TIM_DMABase_CCMR2) || \
|
| Sergunb |
0:f1834a63f7c1
|
653
|
((BASE) == TIM_DMABase_CCER) || \
|
| Sergunb |
0:f1834a63f7c1
|
654
|
((BASE) == TIM_DMABase_CNT) || \
|
| Sergunb |
0:f1834a63f7c1
|
655
|
((BASE) == TIM_DMABase_PSC) || \
|
| Sergunb |
0:f1834a63f7c1
|
656
|
((BASE) == TIM_DMABase_ARR) || \
|
| Sergunb |
0:f1834a63f7c1
|
657
|
((BASE) == TIM_DMABase_RCR) || \
|
| Sergunb |
0:f1834a63f7c1
|
658
|
((BASE) == TIM_DMABase_CCR1) || \
|
| Sergunb |
0:f1834a63f7c1
|
659
|
((BASE) == TIM_DMABase_CCR2) || \
|
| Sergunb |
0:f1834a63f7c1
|
660
|
((BASE) == TIM_DMABase_CCR3) || \
|
| Sergunb |
0:f1834a63f7c1
|
661
|
((BASE) == TIM_DMABase_CCR4) || \
|
| Sergunb |
0:f1834a63f7c1
|
662
|
((BASE) == TIM_DMABase_BDTR) || \
|
| Sergunb |
0:f1834a63f7c1
|
663
|
((BASE) == TIM_DMABase_DCR))
|
| Sergunb |
0:f1834a63f7c1
|
664
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
665
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
666
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
667
|
|
| Sergunb |
0:f1834a63f7c1
|
668
|
/** @defgroup TIM_DMA_Burst_Length
|
| Sergunb |
0:f1834a63f7c1
|
669
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
670
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
671
|
|
| Sergunb |
0:f1834a63f7c1
|
672
|
#define TIM_DMABurstLength_1Byte ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
673
|
#define TIM_DMABurstLength_2Bytes ((uint16_t)0x0100)
|
| Sergunb |
0:f1834a63f7c1
|
674
|
#define TIM_DMABurstLength_3Bytes ((uint16_t)0x0200)
|
| Sergunb |
0:f1834a63f7c1
|
675
|
#define TIM_DMABurstLength_4Bytes ((uint16_t)0x0300)
|
| Sergunb |
0:f1834a63f7c1
|
676
|
#define TIM_DMABurstLength_5Bytes ((uint16_t)0x0400)
|
| Sergunb |
0:f1834a63f7c1
|
677
|
#define TIM_DMABurstLength_6Bytes ((uint16_t)0x0500)
|
| Sergunb |
0:f1834a63f7c1
|
678
|
#define TIM_DMABurstLength_7Bytes ((uint16_t)0x0600)
|
| Sergunb |
0:f1834a63f7c1
|
679
|
#define TIM_DMABurstLength_8Bytes ((uint16_t)0x0700)
|
| Sergunb |
0:f1834a63f7c1
|
680
|
#define TIM_DMABurstLength_9Bytes ((uint16_t)0x0800)
|
| Sergunb |
0:f1834a63f7c1
|
681
|
#define TIM_DMABurstLength_10Bytes ((uint16_t)0x0900)
|
| Sergunb |
0:f1834a63f7c1
|
682
|
#define TIM_DMABurstLength_11Bytes ((uint16_t)0x0A00)
|
| Sergunb |
0:f1834a63f7c1
|
683
|
#define TIM_DMABurstLength_12Bytes ((uint16_t)0x0B00)
|
| Sergunb |
0:f1834a63f7c1
|
684
|
#define TIM_DMABurstLength_13Bytes ((uint16_t)0x0C00)
|
| Sergunb |
0:f1834a63f7c1
|
685
|
#define TIM_DMABurstLength_14Bytes ((uint16_t)0x0D00)
|
| Sergunb |
0:f1834a63f7c1
|
686
|
#define TIM_DMABurstLength_15Bytes ((uint16_t)0x0E00)
|
| Sergunb |
0:f1834a63f7c1
|
687
|
#define TIM_DMABurstLength_16Bytes ((uint16_t)0x0F00)
|
| Sergunb |
0:f1834a63f7c1
|
688
|
#define TIM_DMABurstLength_17Bytes ((uint16_t)0x1000)
|
| Sergunb |
0:f1834a63f7c1
|
689
|
#define TIM_DMABurstLength_18Bytes ((uint16_t)0x1100)
|
| Sergunb |
0:f1834a63f7c1
|
690
|
#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Byte) || \
|
| Sergunb |
0:f1834a63f7c1
|
691
|
((LENGTH) == TIM_DMABurstLength_2Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
692
|
((LENGTH) == TIM_DMABurstLength_3Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
693
|
((LENGTH) == TIM_DMABurstLength_4Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
694
|
((LENGTH) == TIM_DMABurstLength_5Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
695
|
((LENGTH) == TIM_DMABurstLength_6Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
696
|
((LENGTH) == TIM_DMABurstLength_7Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
697
|
((LENGTH) == TIM_DMABurstLength_8Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
698
|
((LENGTH) == TIM_DMABurstLength_9Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
699
|
((LENGTH) == TIM_DMABurstLength_10Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
700
|
((LENGTH) == TIM_DMABurstLength_11Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
701
|
((LENGTH) == TIM_DMABurstLength_12Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
702
|
((LENGTH) == TIM_DMABurstLength_13Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
703
|
((LENGTH) == TIM_DMABurstLength_14Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
704
|
((LENGTH) == TIM_DMABurstLength_15Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
705
|
((LENGTH) == TIM_DMABurstLength_16Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
706
|
((LENGTH) == TIM_DMABurstLength_17Bytes) || \
|
| Sergunb |
0:f1834a63f7c1
|
707
|
((LENGTH) == TIM_DMABurstLength_18Bytes))
|
| Sergunb |
0:f1834a63f7c1
|
708
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
709
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
710
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
711
|
|
| Sergunb |
0:f1834a63f7c1
|
712
|
/** @defgroup TIM_DMA_sources
|
| Sergunb |
0:f1834a63f7c1
|
713
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
714
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
715
|
|
| Sergunb |
0:f1834a63f7c1
|
716
|
#define TIM_DMA_Update ((uint16_t)0x0100)
|
| Sergunb |
0:f1834a63f7c1
|
717
|
#define TIM_DMA_CC1 ((uint16_t)0x0200)
|
| Sergunb |
0:f1834a63f7c1
|
718
|
#define TIM_DMA_CC2 ((uint16_t)0x0400)
|
| Sergunb |
0:f1834a63f7c1
|
719
|
#define TIM_DMA_CC3 ((uint16_t)0x0800)
|
| Sergunb |
0:f1834a63f7c1
|
720
|
#define TIM_DMA_CC4 ((uint16_t)0x1000)
|
| Sergunb |
0:f1834a63f7c1
|
721
|
#define TIM_DMA_COM ((uint16_t)0x2000)
|
| Sergunb |
0:f1834a63f7c1
|
722
|
#define TIM_DMA_Trigger ((uint16_t)0x4000)
|
| Sergunb |
0:f1834a63f7c1
|
723
|
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
|
| Sergunb |
0:f1834a63f7c1
|
724
|
|
| Sergunb |
0:f1834a63f7c1
|
725
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
726
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
727
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
728
|
|
| Sergunb |
0:f1834a63f7c1
|
729
|
/** @defgroup TIM_External_Trigger_Prescaler
|
| Sergunb |
0:f1834a63f7c1
|
730
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
731
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
732
|
|
| Sergunb |
0:f1834a63f7c1
|
733
|
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
734
|
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
|
| Sergunb |
0:f1834a63f7c1
|
735
|
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
| Sergunb |
0:f1834a63f7c1
|
736
|
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
| Sergunb |
0:f1834a63f7c1
|
737
|
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
|
| Sergunb |
0:f1834a63f7c1
|
738
|
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
|
| Sergunb |
0:f1834a63f7c1
|
739
|
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
|
| Sergunb |
0:f1834a63f7c1
|
740
|
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
|
| Sergunb |
0:f1834a63f7c1
|
741
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
742
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
743
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
744
|
|
| Sergunb |
0:f1834a63f7c1
|
745
|
/** @defgroup TIM_Internal_Trigger_Selection
|
| Sergunb |
0:f1834a63f7c1
|
746
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
747
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
748
|
|
| Sergunb |
0:f1834a63f7c1
|
749
|
#define TIM_TS_ITR0 ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
750
|
#define TIM_TS_ITR1 ((uint16_t)0x0010)
|
| Sergunb |
0:f1834a63f7c1
|
751
|
#define TIM_TS_ITR2 ((uint16_t)0x0020)
|
| Sergunb |
0:f1834a63f7c1
|
752
|
#define TIM_TS_ITR3 ((uint16_t)0x0030)
|
| Sergunb |
0:f1834a63f7c1
|
753
|
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
|
| Sergunb |
0:f1834a63f7c1
|
754
|
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
|
| Sergunb |
0:f1834a63f7c1
|
755
|
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
|
| Sergunb |
0:f1834a63f7c1
|
756
|
#define TIM_TS_ETRF ((uint16_t)0x0070)
|
| Sergunb |
0:f1834a63f7c1
|
757
|
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
| Sergunb |
0:f1834a63f7c1
|
758
|
((SELECTION) == TIM_TS_ITR1) || \
|
| Sergunb |
0:f1834a63f7c1
|
759
|
((SELECTION) == TIM_TS_ITR2) || \
|
| Sergunb |
0:f1834a63f7c1
|
760
|
((SELECTION) == TIM_TS_ITR3) || \
|
| Sergunb |
0:f1834a63f7c1
|
761
|
((SELECTION) == TIM_TS_TI1F_ED) || \
|
| Sergunb |
0:f1834a63f7c1
|
762
|
((SELECTION) == TIM_TS_TI1FP1) || \
|
| Sergunb |
0:f1834a63f7c1
|
763
|
((SELECTION) == TIM_TS_TI2FP2) || \
|
| Sergunb |
0:f1834a63f7c1
|
764
|
((SELECTION) == TIM_TS_ETRF))
|
| Sergunb |
0:f1834a63f7c1
|
765
|
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
| Sergunb |
0:f1834a63f7c1
|
766
|
((SELECTION) == TIM_TS_ITR1) || \
|
| Sergunb |
0:f1834a63f7c1
|
767
|
((SELECTION) == TIM_TS_ITR2) || \
|
| Sergunb |
0:f1834a63f7c1
|
768
|
((SELECTION) == TIM_TS_ITR3))
|
| Sergunb |
0:f1834a63f7c1
|
769
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
770
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
771
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
772
|
|
| Sergunb |
0:f1834a63f7c1
|
773
|
/** @defgroup TIM_TIx_External_Clock_Source
|
| Sergunb |
0:f1834a63f7c1
|
774
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
775
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
776
|
|
| Sergunb |
0:f1834a63f7c1
|
777
|
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
|
| Sergunb |
0:f1834a63f7c1
|
778
|
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
|
| Sergunb |
0:f1834a63f7c1
|
779
|
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
|
| Sergunb |
0:f1834a63f7c1
|
780
|
#define IS_TIM_TIXCLK_SOURCE(SOURCE) (((SOURCE) == TIM_TIxExternalCLK1Source_TI1) || \
|
| Sergunb |
0:f1834a63f7c1
|
781
|
((SOURCE) == TIM_TIxExternalCLK1Source_TI2) || \
|
| Sergunb |
0:f1834a63f7c1
|
782
|
((SOURCE) == TIM_TIxExternalCLK1Source_TI1ED))
|
| Sergunb |
0:f1834a63f7c1
|
783
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
784
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
785
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
786
|
|
| Sergunb |
0:f1834a63f7c1
|
787
|
/** @defgroup TIM_External_Trigger_Polarity
|
| Sergunb |
0:f1834a63f7c1
|
788
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
789
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
790
|
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
| Sergunb |
0:f1834a63f7c1
|
791
|
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
792
|
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
|
| Sergunb |
0:f1834a63f7c1
|
793
|
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
|
| Sergunb |
0:f1834a63f7c1
|
794
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
795
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
796
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
797
|
|
| Sergunb |
0:f1834a63f7c1
|
798
|
/** @defgroup TIM_Prescaler_Reload_Mode
|
| Sergunb |
0:f1834a63f7c1
|
799
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
800
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
801
|
|
| Sergunb |
0:f1834a63f7c1
|
802
|
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
803
|
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
|
| Sergunb |
0:f1834a63f7c1
|
804
|
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
|
| Sergunb |
0:f1834a63f7c1
|
805
|
((RELOAD) == TIM_PSCReloadMode_Immediate))
|
| Sergunb |
0:f1834a63f7c1
|
806
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
807
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
808
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
809
|
|
| Sergunb |
0:f1834a63f7c1
|
810
|
/** @defgroup TIM_Forced_Action
|
| Sergunb |
0:f1834a63f7c1
|
811
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
812
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
813
|
|
| Sergunb |
0:f1834a63f7c1
|
814
|
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
|
| Sergunb |
0:f1834a63f7c1
|
815
|
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
|
| Sergunb |
0:f1834a63f7c1
|
816
|
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
|
| Sergunb |
0:f1834a63f7c1
|
817
|
((ACTION) == TIM_ForcedAction_InActive))
|
| Sergunb |
0:f1834a63f7c1
|
818
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
819
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
820
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
821
|
|
| Sergunb |
0:f1834a63f7c1
|
822
|
/** @defgroup TIM_Encoder_Mode
|
| Sergunb |
0:f1834a63f7c1
|
823
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
824
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
825
|
|
| Sergunb |
0:f1834a63f7c1
|
826
|
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
|
| Sergunb |
0:f1834a63f7c1
|
827
|
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
|
| Sergunb |
0:f1834a63f7c1
|
828
|
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
|
| Sergunb |
0:f1834a63f7c1
|
829
|
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
|
| Sergunb |
0:f1834a63f7c1
|
830
|
((MODE) == TIM_EncoderMode_TI2) || \
|
| Sergunb |
0:f1834a63f7c1
|
831
|
((MODE) == TIM_EncoderMode_TI12))
|
| Sergunb |
0:f1834a63f7c1
|
832
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
833
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
834
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
835
|
|
| Sergunb |
0:f1834a63f7c1
|
836
|
|
| Sergunb |
0:f1834a63f7c1
|
837
|
/** @defgroup TIM_Event_Source
|
| Sergunb |
0:f1834a63f7c1
|
838
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
839
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
840
|
|
| Sergunb |
0:f1834a63f7c1
|
841
|
#define TIM_EventSource_Update ((uint16_t)0x0001)
|
| Sergunb |
0:f1834a63f7c1
|
842
|
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
|
| Sergunb |
0:f1834a63f7c1
|
843
|
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
|
| Sergunb |
0:f1834a63f7c1
|
844
|
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
|
| Sergunb |
0:f1834a63f7c1
|
845
|
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
|
| Sergunb |
0:f1834a63f7c1
|
846
|
#define TIM_EventSource_COM ((uint16_t)0x0020)
|
| Sergunb |
0:f1834a63f7c1
|
847
|
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
|
| Sergunb |
0:f1834a63f7c1
|
848
|
#define TIM_EventSource_Break ((uint16_t)0x0080)
|
| Sergunb |
0:f1834a63f7c1
|
849
|
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
|
| Sergunb |
0:f1834a63f7c1
|
850
|
|
| Sergunb |
0:f1834a63f7c1
|
851
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
852
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
853
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
854
|
|
| Sergunb |
0:f1834a63f7c1
|
855
|
/** @defgroup TIM_Update_Source
|
| Sergunb |
0:f1834a63f7c1
|
856
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
857
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
858
|
|
| Sergunb |
0:f1834a63f7c1
|
859
|
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
|
| Sergunb |
0:f1834a63f7c1
|
860
|
or the setting of UG bit, or an update generation
|
| Sergunb |
0:f1834a63f7c1
|
861
|
through the slave mode controller. */
|
| Sergunb |
0:f1834a63f7c1
|
862
|
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
|
| Sergunb |
0:f1834a63f7c1
|
863
|
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
|
| Sergunb |
0:f1834a63f7c1
|
864
|
((SOURCE) == TIM_UpdateSource_Regular))
|
| Sergunb |
0:f1834a63f7c1
|
865
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
866
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
867
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
868
|
|
| Sergunb |
0:f1834a63f7c1
|
869
|
/** @defgroup TIM_Ouput_Compare_Preload_State
|
| Sergunb |
0:f1834a63f7c1
|
870
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
871
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
872
|
|
| Sergunb |
0:f1834a63f7c1
|
873
|
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
|
| Sergunb |
0:f1834a63f7c1
|
874
|
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
875
|
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
876
|
((STATE) == TIM_OCPreload_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
877
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
878
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
879
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
880
|
|
| Sergunb |
0:f1834a63f7c1
|
881
|
/** @defgroup TIM_Ouput_Compare_Fast_State
|
| Sergunb |
0:f1834a63f7c1
|
882
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
883
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
884
|
|
| Sergunb |
0:f1834a63f7c1
|
885
|
#define TIM_OCFast_Enable ((uint16_t)0x0004)
|
| Sergunb |
0:f1834a63f7c1
|
886
|
#define TIM_OCFast_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
887
|
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
888
|
((STATE) == TIM_OCFast_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
889
|
|
| Sergunb |
0:f1834a63f7c1
|
890
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
891
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
892
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
893
|
|
| Sergunb |
0:f1834a63f7c1
|
894
|
/** @defgroup TIM_Ouput_Compare_Clear_State
|
| Sergunb |
0:f1834a63f7c1
|
895
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
896
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
897
|
|
| Sergunb |
0:f1834a63f7c1
|
898
|
#define TIM_OCClear_Enable ((uint16_t)0x0080)
|
| Sergunb |
0:f1834a63f7c1
|
899
|
#define TIM_OCClear_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
900
|
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
901
|
((STATE) == TIM_OCClear_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
902
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
903
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
904
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
905
|
|
| Sergunb |
0:f1834a63f7c1
|
906
|
/** @defgroup TIM_Trigger_Output_Source
|
| Sergunb |
0:f1834a63f7c1
|
907
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
908
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
909
|
|
| Sergunb |
0:f1834a63f7c1
|
910
|
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
911
|
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
|
| Sergunb |
0:f1834a63f7c1
|
912
|
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
|
| Sergunb |
0:f1834a63f7c1
|
913
|
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
|
| Sergunb |
0:f1834a63f7c1
|
914
|
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
|
| Sergunb |
0:f1834a63f7c1
|
915
|
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
|
| Sergunb |
0:f1834a63f7c1
|
916
|
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
|
| Sergunb |
0:f1834a63f7c1
|
917
|
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
|
| Sergunb |
0:f1834a63f7c1
|
918
|
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
|
| Sergunb |
0:f1834a63f7c1
|
919
|
((SOURCE) == TIM_TRGOSource_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
920
|
((SOURCE) == TIM_TRGOSource_Update) || \
|
| Sergunb |
0:f1834a63f7c1
|
921
|
((SOURCE) == TIM_TRGOSource_OC1) || \
|
| Sergunb |
0:f1834a63f7c1
|
922
|
((SOURCE) == TIM_TRGOSource_OC1Ref) || \
|
| Sergunb |
0:f1834a63f7c1
|
923
|
((SOURCE) == TIM_TRGOSource_OC2Ref) || \
|
| Sergunb |
0:f1834a63f7c1
|
924
|
((SOURCE) == TIM_TRGOSource_OC3Ref) || \
|
| Sergunb |
0:f1834a63f7c1
|
925
|
((SOURCE) == TIM_TRGOSource_OC4Ref))
|
| Sergunb |
0:f1834a63f7c1
|
926
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
927
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
928
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
929
|
|
| Sergunb |
0:f1834a63f7c1
|
930
|
/** @defgroup TIM_Slave_Mode
|
| Sergunb |
0:f1834a63f7c1
|
931
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
932
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
933
|
|
| Sergunb |
0:f1834a63f7c1
|
934
|
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
|
| Sergunb |
0:f1834a63f7c1
|
935
|
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
|
| Sergunb |
0:f1834a63f7c1
|
936
|
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
|
| Sergunb |
0:f1834a63f7c1
|
937
|
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
|
| Sergunb |
0:f1834a63f7c1
|
938
|
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
|
| Sergunb |
0:f1834a63f7c1
|
939
|
((MODE) == TIM_SlaveMode_Gated) || \
|
| Sergunb |
0:f1834a63f7c1
|
940
|
((MODE) == TIM_SlaveMode_Trigger) || \
|
| Sergunb |
0:f1834a63f7c1
|
941
|
((MODE) == TIM_SlaveMode_External1))
|
| Sergunb |
0:f1834a63f7c1
|
942
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
943
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
944
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
945
|
|
| Sergunb |
0:f1834a63f7c1
|
946
|
/** @defgroup TIM_Master_Slave_Mode
|
| Sergunb |
0:f1834a63f7c1
|
947
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
948
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
949
|
|
| Sergunb |
0:f1834a63f7c1
|
950
|
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
|
| Sergunb |
0:f1834a63f7c1
|
951
|
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
|
| Sergunb |
0:f1834a63f7c1
|
952
|
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
|
| Sergunb |
0:f1834a63f7c1
|
953
|
((STATE) == TIM_MasterSlaveMode_Disable))
|
| Sergunb |
0:f1834a63f7c1
|
954
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
955
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
956
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
957
|
|
| Sergunb |
0:f1834a63f7c1
|
958
|
/** @defgroup TIM_Flags
|
| Sergunb |
0:f1834a63f7c1
|
959
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
960
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
961
|
|
| Sergunb |
0:f1834a63f7c1
|
962
|
#define TIM_FLAG_Update ((uint16_t)0x0001)
|
| Sergunb |
0:f1834a63f7c1
|
963
|
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
|
| Sergunb |
0:f1834a63f7c1
|
964
|
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
|
| Sergunb |
0:f1834a63f7c1
|
965
|
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
|
| Sergunb |
0:f1834a63f7c1
|
966
|
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
|
| Sergunb |
0:f1834a63f7c1
|
967
|
#define TIM_FLAG_COM ((uint16_t)0x0020)
|
| Sergunb |
0:f1834a63f7c1
|
968
|
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
|
| Sergunb |
0:f1834a63f7c1
|
969
|
#define TIM_FLAG_Break ((uint16_t)0x0080)
|
| Sergunb |
0:f1834a63f7c1
|
970
|
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
|
| Sergunb |
0:f1834a63f7c1
|
971
|
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
|
| Sergunb |
0:f1834a63f7c1
|
972
|
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
|
| Sergunb |
0:f1834a63f7c1
|
973
|
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
|
| Sergunb |
0:f1834a63f7c1
|
974
|
#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
|
| Sergunb |
0:f1834a63f7c1
|
975
|
((FLAG) == TIM_FLAG_CC1) || \
|
| Sergunb |
0:f1834a63f7c1
|
976
|
((FLAG) == TIM_FLAG_CC2) || \
|
| Sergunb |
0:f1834a63f7c1
|
977
|
((FLAG) == TIM_FLAG_CC3) || \
|
| Sergunb |
0:f1834a63f7c1
|
978
|
((FLAG) == TIM_FLAG_CC4) || \
|
| Sergunb |
0:f1834a63f7c1
|
979
|
((FLAG) == TIM_FLAG_COM) || \
|
| Sergunb |
0:f1834a63f7c1
|
980
|
((FLAG) == TIM_FLAG_Trigger) || \
|
| Sergunb |
0:f1834a63f7c1
|
981
|
((FLAG) == TIM_FLAG_Break) || \
|
| Sergunb |
0:f1834a63f7c1
|
982
|
((FLAG) == TIM_FLAG_CC1OF) || \
|
| Sergunb |
0:f1834a63f7c1
|
983
|
((FLAG) == TIM_FLAG_CC2OF) || \
|
| Sergunb |
0:f1834a63f7c1
|
984
|
((FLAG) == TIM_FLAG_CC3OF) || \
|
| Sergunb |
0:f1834a63f7c1
|
985
|
((FLAG) == TIM_FLAG_CC4OF))
|
| Sergunb |
0:f1834a63f7c1
|
986
|
|
| Sergunb |
0:f1834a63f7c1
|
987
|
|
| Sergunb |
0:f1834a63f7c1
|
988
|
#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
|
| Sergunb |
0:f1834a63f7c1
|
989
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
990
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
991
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
992
|
|
| Sergunb |
0:f1834a63f7c1
|
993
|
/** @defgroup TIM_Input_Capture_Filer_Value
|
| Sergunb |
0:f1834a63f7c1
|
994
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
995
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
996
|
|
| Sergunb |
0:f1834a63f7c1
|
997
|
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
|
| Sergunb |
0:f1834a63f7c1
|
998
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
999
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
1000
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1001
|
|
| Sergunb |
0:f1834a63f7c1
|
1002
|
/** @defgroup TIM_External_Trigger_Filter
|
| Sergunb |
0:f1834a63f7c1
|
1003
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
1004
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1005
|
|
| Sergunb |
0:f1834a63f7c1
|
1006
|
#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
|
| Sergunb |
0:f1834a63f7c1
|
1007
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1008
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
1009
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1010
|
|
| Sergunb |
0:f1834a63f7c1
|
1011
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1012
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
1013
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1014
|
|
| Sergunb |
0:f1834a63f7c1
|
1015
|
/** @defgroup TIM_Exported_Macros
|
| Sergunb |
0:f1834a63f7c1
|
1016
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
1017
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1018
|
|
| Sergunb |
0:f1834a63f7c1
|
1019
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1020
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
1021
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1022
|
|
| Sergunb |
0:f1834a63f7c1
|
1023
|
/** @defgroup TIM_Exported_Functions
|
| Sergunb |
0:f1834a63f7c1
|
1024
|
* @{
|
| Sergunb |
0:f1834a63f7c1
|
1025
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1026
|
|
| Sergunb |
0:f1834a63f7c1
|
1027
|
void TIM_DeInit(TIM_TypeDef* TIMx);
|
| Sergunb |
0:f1834a63f7c1
|
1028
|
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1029
|
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1030
|
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1031
|
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1032
|
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1033
|
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1034
|
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1035
|
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1036
|
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1037
|
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1038
|
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1039
|
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
|
| Sergunb |
0:f1834a63f7c1
|
1040
|
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1041
|
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1042
|
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1043
|
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
|
| Sergunb |
0:f1834a63f7c1
|
1044
|
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
|
| Sergunb |
0:f1834a63f7c1
|
1045
|
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1046
|
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
|
| Sergunb |
0:f1834a63f7c1
|
1047
|
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
| Sergunb |
0:f1834a63f7c1
|
1048
|
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
|
| Sergunb |
0:f1834a63f7c1
|
1049
|
uint16_t TIM_ICPolarity, uint16_t ICFilter);
|
| Sergunb |
0:f1834a63f7c1
|
1050
|
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
| Sergunb |
0:f1834a63f7c1
|
1051
|
uint16_t ExtTRGFilter);
|
| Sergunb |
0:f1834a63f7c1
|
1052
|
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
|
| Sergunb |
0:f1834a63f7c1
|
1053
|
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
| Sergunb |
0:f1834a63f7c1
|
1054
|
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
| Sergunb |
0:f1834a63f7c1
|
1055
|
uint16_t ExtTRGFilter);
|
| Sergunb |
0:f1834a63f7c1
|
1056
|
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
|
| Sergunb |
0:f1834a63f7c1
|
1057
|
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
|
| Sergunb |
0:f1834a63f7c1
|
1058
|
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
| Sergunb |
0:f1834a63f7c1
|
1059
|
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
|
| Sergunb |
0:f1834a63f7c1
|
1060
|
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
|
| Sergunb |
0:f1834a63f7c1
|
1061
|
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
| Sergunb |
0:f1834a63f7c1
|
1062
|
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
| Sergunb |
0:f1834a63f7c1
|
1063
|
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
| Sergunb |
0:f1834a63f7c1
|
1064
|
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
| Sergunb |
0:f1834a63f7c1
|
1065
|
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1066
|
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1067
|
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1068
|
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1069
|
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
| Sergunb |
0:f1834a63f7c1
|
1070
|
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
| Sergunb |
0:f1834a63f7c1
|
1071
|
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
| Sergunb |
0:f1834a63f7c1
|
1072
|
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
| Sergunb |
0:f1834a63f7c1
|
1073
|
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
| Sergunb |
0:f1834a63f7c1
|
1074
|
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
| Sergunb |
0:f1834a63f7c1
|
1075
|
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
| Sergunb |
0:f1834a63f7c1
|
1076
|
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
| Sergunb |
0:f1834a63f7c1
|
1077
|
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
| Sergunb |
0:f1834a63f7c1
|
1078
|
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
| Sergunb |
0:f1834a63f7c1
|
1079
|
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
| Sergunb |
0:f1834a63f7c1
|
1080
|
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
| Sergunb |
0:f1834a63f7c1
|
1081
|
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
| Sergunb |
0:f1834a63f7c1
|
1082
|
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
| Sergunb |
0:f1834a63f7c1
|
1083
|
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
| Sergunb |
0:f1834a63f7c1
|
1084
|
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
| Sergunb |
0:f1834a63f7c1
|
1085
|
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
| Sergunb |
0:f1834a63f7c1
|
1086
|
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
| Sergunb |
0:f1834a63f7c1
|
1087
|
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
| Sergunb |
0:f1834a63f7c1
|
1088
|
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
|
| Sergunb |
0:f1834a63f7c1
|
1089
|
void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
|
| Sergunb |
0:f1834a63f7c1
|
1090
|
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
|
| Sergunb |
0:f1834a63f7c1
|
1091
|
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1092
|
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
|
| Sergunb |
0:f1834a63f7c1
|
1093
|
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
|
| Sergunb |
0:f1834a63f7c1
|
1094
|
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
|
| Sergunb |
0:f1834a63f7c1
|
1095
|
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
|
| Sergunb |
0:f1834a63f7c1
|
1096
|
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
|
| Sergunb |
0:f1834a63f7c1
|
1097
|
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
|
| Sergunb |
0:f1834a63f7c1
|
1098
|
void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
|
| Sergunb |
0:f1834a63f7c1
|
1099
|
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
|
| Sergunb |
0:f1834a63f7c1
|
1100
|
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
|
| Sergunb |
0:f1834a63f7c1
|
1101
|
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
|
| Sergunb |
0:f1834a63f7c1
|
1102
|
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
|
| Sergunb |
0:f1834a63f7c1
|
1103
|
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
|
| Sergunb |
0:f1834a63f7c1
|
1104
|
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
| Sergunb |
0:f1834a63f7c1
|
1105
|
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
| Sergunb |
0:f1834a63f7c1
|
1106
|
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
| Sergunb |
0:f1834a63f7c1
|
1107
|
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
| Sergunb |
0:f1834a63f7c1
|
1108
|
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
|
| Sergunb |
0:f1834a63f7c1
|
1109
|
uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
|
| Sergunb |
0:f1834a63f7c1
|
1110
|
uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
|
| Sergunb |
0:f1834a63f7c1
|
1111
|
uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
|
| Sergunb |
0:f1834a63f7c1
|
1112
|
uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
|
| Sergunb |
0:f1834a63f7c1
|
1113
|
uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
|
| Sergunb |
0:f1834a63f7c1
|
1114
|
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
|
| Sergunb |
0:f1834a63f7c1
|
1115
|
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
| Sergunb |
0:f1834a63f7c1
|
1116
|
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
| Sergunb |
0:f1834a63f7c1
|
1117
|
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
| Sergunb |
0:f1834a63f7c1
|
1118
|
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
| Sergunb |
0:f1834a63f7c1
|
1119
|
|
| Sergunb |
0:f1834a63f7c1
|
1120
|
#ifdef __cplusplus
|
| Sergunb |
0:f1834a63f7c1
|
1121
|
}
|
| Sergunb |
0:f1834a63f7c1
|
1122
|
#endif
|
| Sergunb |
0:f1834a63f7c1
|
1123
|
|
| Sergunb |
0:f1834a63f7c1
|
1124
|
#endif /*__STM32F10x_TIM_H */
|
| Sergunb |
0:f1834a63f7c1
|
1125
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1126
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
1127
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1128
|
|
| Sergunb |
0:f1834a63f7c1
|
1129
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1130
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
1131
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1132
|
|
| Sergunb |
0:f1834a63f7c1
|
1133
|
/**
|
| Sergunb |
0:f1834a63f7c1
|
1134
|
* @}
|
| Sergunb |
0:f1834a63f7c1
|
1135
|
*/
|
| Sergunb |
0:f1834a63f7c1
|
1136
|
|
| Sergunb |
0:f1834a63f7c1
|
1137
|
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|