Sergey Pastor / grbl

I'm trying to port GRBL 1.1 to the STM32F746 chip. Tell me the solution, thanks.

cmsis_boot/system_stm32f10x.c@0:f1834a63f7c1, 2017-09-04 (annotated)

Committer:
Sergunb
Date:
Mon Sep 04 12:03:42 2017 +0000
Revision:
0:f1834a63f7c1
Initial commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:f1834a63f7c1 1 /**
Sergunb 0:f1834a63f7c1 2 ******************************************************************************
Sergunb 0:f1834a63f7c1 3 * @file system_stm32f10x.c
Sergunb 0:f1834a63f7c1 4 * @author MCD Application Team
Sergunb 0:f1834a63f7c1 5 * @version V3.5.0
Sergunb 0:f1834a63f7c1 6 * @date 11-March-2011
Sergunb 0:f1834a63f7c1 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
Sergunb 0:f1834a63f7c1 8 *
Sergunb 0:f1834a63f7c1 9 * 1. This file provides two functions and one global variable to be called from
Sergunb 0:f1834a63f7c1 10 * user application:
Sergunb 0:f1834a63f7c1 11 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
Sergunb 0:f1834a63f7c1 12 * factors, AHB/APBx prescalers and Flash settings).
Sergunb 0:f1834a63f7c1 13 * This function is called at startup just after reset and
Sergunb 0:f1834a63f7c1 14 * before branch to main program. This call is made inside
Sergunb 0:f1834a63f7c1 15 * the "startup_stm32f10x_xx.s" file.
Sergunb 0:f1834a63f7c1 16 *
Sergunb 0:f1834a63f7c1 17 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
Sergunb 0:f1834a63f7c1 18 * by the user application to setup the SysTick
Sergunb 0:f1834a63f7c1 19 * timer or configure other parameters.
Sergunb 0:f1834a63f7c1 20 *
Sergunb 0:f1834a63f7c1 21 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
Sergunb 0:f1834a63f7c1 22 * be called whenever the core clock is changed
Sergunb 0:f1834a63f7c1 23 * during program execution.
Sergunb 0:f1834a63f7c1 24 *
Sergunb 0:f1834a63f7c1 25 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
Sergunb 0:f1834a63f7c1 26 * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to
Sergunb 0:f1834a63f7c1 27 * configure the system clock before to branch to main program.
Sergunb 0:f1834a63f7c1 28 *
Sergunb 0:f1834a63f7c1 29 * 3. If the system clock source selected by user fails to startup, the SystemInit()
Sergunb 0:f1834a63f7c1 30 * function will do nothing and HSI still used as system clock source. User can
Sergunb 0:f1834a63f7c1 31 * add some code to deal with this issue inside the SetSysClock() function.
Sergunb 0:f1834a63f7c1 32 *
Sergunb 0:f1834a63f7c1 33 * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on
Sergunb 0:f1834a63f7c1 34 * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file.
Sergunb 0:f1834a63f7c1 35 * When HSE is used as system clock source, directly or through PLL, and you
Sergunb 0:f1834a63f7c1 36 * are using different crystal you have to adapt the HSE value to your own
Sergunb 0:f1834a63f7c1 37 * configuration.
Sergunb 0:f1834a63f7c1 38 *
Sergunb 0:f1834a63f7c1 39 ******************************************************************************
Sergunb 0:f1834a63f7c1 40 * @attention
Sergunb 0:f1834a63f7c1 41 *
Sergunb 0:f1834a63f7c1 42 * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
Sergunb 0:f1834a63f7c1 43 * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
Sergunb 0:f1834a63f7c1 44 * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
Sergunb 0:f1834a63f7c1 45 * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
Sergunb 0:f1834a63f7c1 46 * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
Sergunb 0:f1834a63f7c1 47 * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
Sergunb 0:f1834a63f7c1 48 *
Sergunb 0:f1834a63f7c1 49 * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
Sergunb 0:f1834a63f7c1 50 ******************************************************************************
Sergunb 0:f1834a63f7c1 51 */
Sergunb 0:f1834a63f7c1 52
Sergunb 0:f1834a63f7c1 53 /** @addtogroup CMSIS
Sergunb 0:f1834a63f7c1 54 * @{
Sergunb 0:f1834a63f7c1 55 */
Sergunb 0:f1834a63f7c1 56
Sergunb 0:f1834a63f7c1 57 /** @addtogroup stm32f10x_system
Sergunb 0:f1834a63f7c1 58 * @{
Sergunb 0:f1834a63f7c1 59 */
Sergunb 0:f1834a63f7c1 60
Sergunb 0:f1834a63f7c1 61 /** @addtogroup STM32F10x_System_Private_Includes
Sergunb 0:f1834a63f7c1 62 * @{
Sergunb 0:f1834a63f7c1 63 */
Sergunb 0:f1834a63f7c1 64
Sergunb 0:f1834a63f7c1 65 #include "stm32f10x.h"
Sergunb 0:f1834a63f7c1 66
Sergunb 0:f1834a63f7c1 67 /**
Sergunb 0:f1834a63f7c1 68 * @}
Sergunb 0:f1834a63f7c1 69 */
Sergunb 0:f1834a63f7c1 70
Sergunb 0:f1834a63f7c1 71 /** @addtogroup STM32F10x_System_Private_TypesDefinitions
Sergunb 0:f1834a63f7c1 72 * @{
Sergunb 0:f1834a63f7c1 73 */
Sergunb 0:f1834a63f7c1 74
Sergunb 0:f1834a63f7c1 75 /**
Sergunb 0:f1834a63f7c1 76 * @}
Sergunb 0:f1834a63f7c1 77 */
Sergunb 0:f1834a63f7c1 78
Sergunb 0:f1834a63f7c1 79 /** @addtogroup STM32F10x_System_Private_Defines
Sergunb 0:f1834a63f7c1 80 * @{
Sergunb 0:f1834a63f7c1 81 */
Sergunb 0:f1834a63f7c1 82
Sergunb 0:f1834a63f7c1 83 /*!< Uncomment the line corresponding to the desired System clock (SYSCLK)
Sergunb 0:f1834a63f7c1 84 frequency (after reset the HSI is used as SYSCLK source)
Sergunb 0:f1834a63f7c1 85
Sergunb 0:f1834a63f7c1 86 IMPORTANT NOTE:
Sergunb 0:f1834a63f7c1 87 ==============
Sergunb 0:f1834a63f7c1 88 1. After each device reset the HSI is used as System clock source.
Sergunb 0:f1834a63f7c1 89
Sergunb 0:f1834a63f7c1 90 2. Please make sure that the selected System clock doesn't exceed your device's
Sergunb 0:f1834a63f7c1 91 maximum frequency.
Sergunb 0:f1834a63f7c1 92
Sergunb 0:f1834a63f7c1 93 3. If none of the define below is enabled, the HSI is used as System clock
Sergunb 0:f1834a63f7c1 94 source.
Sergunb 0:f1834a63f7c1 95
Sergunb 0:f1834a63f7c1 96 4. The System clock configuration functions provided within this file assume that:
Sergunb 0:f1834a63f7c1 97 - For Low, Medium and High density Value line devices an external 8MHz
Sergunb 0:f1834a63f7c1 98 crystal is used to drive the System clock.
Sergunb 0:f1834a63f7c1 99 - For Low, Medium and High density devices an external 8MHz crystal is
Sergunb 0:f1834a63f7c1 100 used to drive the System clock.
Sergunb 0:f1834a63f7c1 101 - For Connectivity line devices an external 25MHz crystal is used to drive
Sergunb 0:f1834a63f7c1 102 the System clock.
Sergunb 0:f1834a63f7c1 103 If you are using different crystal you have to adapt those functions accordingly.
Sergunb 0:f1834a63f7c1 104 */
Sergunb 0:f1834a63f7c1 105
Sergunb 0:f1834a63f7c1 106 #if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
Sergunb 0:f1834a63f7c1 107 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
Sergunb 0:f1834a63f7c1 108 #define SYSCLK_FREQ_24MHz 24000000
Sergunb 0:f1834a63f7c1 109 #else
Sergunb 0:f1834a63f7c1 110 /* #define SYSCLK_FREQ_HSE HSE_VALUE */
Sergunb 0:f1834a63f7c1 111 /* #define SYSCLK_FREQ_24MHz 24000000 */
Sergunb 0:f1834a63f7c1 112 /* #define SYSCLK_FREQ_36MHz 36000000 */
Sergunb 0:f1834a63f7c1 113 /* #define SYSCLK_FREQ_48MHz 48000000 */
Sergunb 0:f1834a63f7c1 114 /* #define SYSCLK_FREQ_56MHz 56000000 */
Sergunb 0:f1834a63f7c1 115 #define SYSCLK_FREQ_72MHz 72000000
Sergunb 0:f1834a63f7c1 116 #endif
Sergunb 0:f1834a63f7c1 117
Sergunb 0:f1834a63f7c1 118 /*!< Uncomment the following line if you need to use external SRAM mounted
Sergunb 0:f1834a63f7c1 119 on STM3210E-EVAL board (STM32 High density and XL-density devices) or on
Sergunb 0:f1834a63f7c1 120 STM32100E-EVAL board (STM32 High-density value line devices) as data memory */
Sergunb 0:f1834a63f7c1 121 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
Sergunb 0:f1834a63f7c1 122 /* #define DATA_IN_ExtSRAM */
Sergunb 0:f1834a63f7c1 123 #endif
Sergunb 0:f1834a63f7c1 124
Sergunb 0:f1834a63f7c1 125 /*!< Uncomment the following line if you need to relocate your vector Table in
Sergunb 0:f1834a63f7c1 126 Internal SRAM. */
Sergunb 0:f1834a63f7c1 127 /* #define VECT_TAB_SRAM */
Sergunb 0:f1834a63f7c1 128 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
Sergunb 0:f1834a63f7c1 129 This value must be a multiple of 0x200. */
Sergunb 0:f1834a63f7c1 130
Sergunb 0:f1834a63f7c1 131
Sergunb 0:f1834a63f7c1 132 /**
Sergunb 0:f1834a63f7c1 133 * @}
Sergunb 0:f1834a63f7c1 134 */
Sergunb 0:f1834a63f7c1 135
Sergunb 0:f1834a63f7c1 136 /** @addtogroup STM32F10x_System_Private_Macros
Sergunb 0:f1834a63f7c1 137 * @{
Sergunb 0:f1834a63f7c1 138 */
Sergunb 0:f1834a63f7c1 139
Sergunb 0:f1834a63f7c1 140 /**
Sergunb 0:f1834a63f7c1 141 * @}
Sergunb 0:f1834a63f7c1 142 */
Sergunb 0:f1834a63f7c1 143
Sergunb 0:f1834a63f7c1 144 /** @addtogroup STM32F10x_System_Private_Variables
Sergunb 0:f1834a63f7c1 145 * @{
Sergunb 0:f1834a63f7c1 146 */
Sergunb 0:f1834a63f7c1 147
Sergunb 0:f1834a63f7c1 148 /*******************************************************************************
Sergunb 0:f1834a63f7c1 149 * Clock Definitions
Sergunb 0:f1834a63f7c1 150 *******************************************************************************/
Sergunb 0:f1834a63f7c1 151 #ifdef SYSCLK_FREQ_HSE
Sergunb 0:f1834a63f7c1 152 uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:f1834a63f7c1 153 #elif defined SYSCLK_FREQ_24MHz
Sergunb 0:f1834a63f7c1 154 uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:f1834a63f7c1 155 #elif defined SYSCLK_FREQ_36MHz
Sergunb 0:f1834a63f7c1 156 uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:f1834a63f7c1 157 #elif defined SYSCLK_FREQ_48MHz
Sergunb 0:f1834a63f7c1 158 uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:f1834a63f7c1 159 #elif defined SYSCLK_FREQ_56MHz
Sergunb 0:f1834a63f7c1 160 uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:f1834a63f7c1 161 #elif defined SYSCLK_FREQ_72MHz
Sergunb 0:f1834a63f7c1 162 uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:f1834a63f7c1 163 #else /*!< HSI Selected as System Clock source */
Sergunb 0:f1834a63f7c1 164 uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */
Sergunb 0:f1834a63f7c1 165 #endif
Sergunb 0:f1834a63f7c1 166
Sergunb 0:f1834a63f7c1 167 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
Sergunb 0:f1834a63f7c1 168 /**
Sergunb 0:f1834a63f7c1 169 * @}
Sergunb 0:f1834a63f7c1 170 */
Sergunb 0:f1834a63f7c1 171
Sergunb 0:f1834a63f7c1 172 /** @addtogroup STM32F10x_System_Private_FunctionPrototypes
Sergunb 0:f1834a63f7c1 173 * @{
Sergunb 0:f1834a63f7c1 174 */
Sergunb 0:f1834a63f7c1 175
Sergunb 0:f1834a63f7c1 176 static void SetSysClock(void);
Sergunb 0:f1834a63f7c1 177
Sergunb 0:f1834a63f7c1 178 #ifdef SYSCLK_FREQ_HSE
Sergunb 0:f1834a63f7c1 179 static void SetSysClockToHSE(void);
Sergunb 0:f1834a63f7c1 180 #elif defined SYSCLK_FREQ_24MHz
Sergunb 0:f1834a63f7c1 181 static void SetSysClockTo24(void);
Sergunb 0:f1834a63f7c1 182 #elif defined SYSCLK_FREQ_36MHz
Sergunb 0:f1834a63f7c1 183 static void SetSysClockTo36(void);
Sergunb 0:f1834a63f7c1 184 #elif defined SYSCLK_FREQ_48MHz
Sergunb 0:f1834a63f7c1 185 static void SetSysClockTo48(void);
Sergunb 0:f1834a63f7c1 186 #elif defined SYSCLK_FREQ_56MHz
Sergunb 0:f1834a63f7c1 187 static void SetSysClockTo56(void);
Sergunb 0:f1834a63f7c1 188 #elif defined SYSCLK_FREQ_72MHz
Sergunb 0:f1834a63f7c1 189 static void SetSysClockTo72(void);
Sergunb 0:f1834a63f7c1 190 #endif
Sergunb 0:f1834a63f7c1 191
Sergunb 0:f1834a63f7c1 192 #ifdef DATA_IN_ExtSRAM
Sergunb 0:f1834a63f7c1 193 static void SystemInit_ExtMemCtl(void);
Sergunb 0:f1834a63f7c1 194 #endif /* DATA_IN_ExtSRAM */
Sergunb 0:f1834a63f7c1 195
Sergunb 0:f1834a63f7c1 196 /**
Sergunb 0:f1834a63f7c1 197 * @}
Sergunb 0:f1834a63f7c1 198 */
Sergunb 0:f1834a63f7c1 199
Sergunb 0:f1834a63f7c1 200 /** @addtogroup STM32F10x_System_Private_Functions
Sergunb 0:f1834a63f7c1 201 * @{
Sergunb 0:f1834a63f7c1 202 */
Sergunb 0:f1834a63f7c1 203
Sergunb 0:f1834a63f7c1 204 /**
Sergunb 0:f1834a63f7c1 205 * @brief Setup the microcontroller system
Sergunb 0:f1834a63f7c1 206 * Initialize the Embedded Flash Interface, the PLL and update the
Sergunb 0:f1834a63f7c1 207 * SystemCoreClock variable.
Sergunb 0:f1834a63f7c1 208 * @note This function should be used only after reset.
Sergunb 0:f1834a63f7c1 209 * @param None
Sergunb 0:f1834a63f7c1 210 * @retval None
Sergunb 0:f1834a63f7c1 211 */
Sergunb 0:f1834a63f7c1 212 void SystemInit (void)
Sergunb 0:f1834a63f7c1 213 {
Sergunb 0:f1834a63f7c1 214 /* Reset the RCC clock configuration to the default reset state(for debug purpose) */
Sergunb 0:f1834a63f7c1 215 /* Set HSION bit */
Sergunb 0:f1834a63f7c1 216 RCC->CR |= (uint32_t)0x00000001;
Sergunb 0:f1834a63f7c1 217
Sergunb 0:f1834a63f7c1 218 /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
Sergunb 0:f1834a63f7c1 219 #ifndef STM32F10X_CL
Sergunb 0:f1834a63f7c1 220 RCC->CFGR &= (uint32_t)0xF8FF0000;
Sergunb 0:f1834a63f7c1 221 #else
Sergunb 0:f1834a63f7c1 222 RCC->CFGR &= (uint32_t)0xF0FF0000;
Sergunb 0:f1834a63f7c1 223 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 224
Sergunb 0:f1834a63f7c1 225 /* Reset HSEON, CSSON and PLLON bits */
Sergunb 0:f1834a63f7c1 226 RCC->CR &= (uint32_t)0xFEF6FFFF;
Sergunb 0:f1834a63f7c1 227
Sergunb 0:f1834a63f7c1 228 /* Reset HSEBYP bit */
Sergunb 0:f1834a63f7c1 229 RCC->CR &= (uint32_t)0xFFFBFFFF;
Sergunb 0:f1834a63f7c1 230
Sergunb 0:f1834a63f7c1 231 /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
Sergunb 0:f1834a63f7c1 232 RCC->CFGR &= (uint32_t)0xFF80FFFF;
Sergunb 0:f1834a63f7c1 233
Sergunb 0:f1834a63f7c1 234 #ifdef STM32F10X_CL
Sergunb 0:f1834a63f7c1 235 /* Reset PLL2ON and PLL3ON bits */
Sergunb 0:f1834a63f7c1 236 RCC->CR &= (uint32_t)0xEBFFFFFF;
Sergunb 0:f1834a63f7c1 237
Sergunb 0:f1834a63f7c1 238 /* Disable all interrupts and clear pending bits */
Sergunb 0:f1834a63f7c1 239 RCC->CIR = 0x00FF0000;
Sergunb 0:f1834a63f7c1 240
Sergunb 0:f1834a63f7c1 241 /* Reset CFGR2 register */
Sergunb 0:f1834a63f7c1 242 RCC->CFGR2 = 0x00000000;
Sergunb 0:f1834a63f7c1 243 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
Sergunb 0:f1834a63f7c1 244 /* Disable all interrupts and clear pending bits */
Sergunb 0:f1834a63f7c1 245 RCC->CIR = 0x009F0000;
Sergunb 0:f1834a63f7c1 246
Sergunb 0:f1834a63f7c1 247 /* Reset CFGR2 register */
Sergunb 0:f1834a63f7c1 248 RCC->CFGR2 = 0x00000000;
Sergunb 0:f1834a63f7c1 249 #else
Sergunb 0:f1834a63f7c1 250 /* Disable all interrupts and clear pending bits */
Sergunb 0:f1834a63f7c1 251 RCC->CIR = 0x009F0000;
Sergunb 0:f1834a63f7c1 252 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 253
Sergunb 0:f1834a63f7c1 254 #if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL)
Sergunb 0:f1834a63f7c1 255 #ifdef DATA_IN_ExtSRAM
Sergunb 0:f1834a63f7c1 256 SystemInit_ExtMemCtl();
Sergunb 0:f1834a63f7c1 257 #endif /* DATA_IN_ExtSRAM */
Sergunb 0:f1834a63f7c1 258 #endif
Sergunb 0:f1834a63f7c1 259
Sergunb 0:f1834a63f7c1 260 /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */
Sergunb 0:f1834a63f7c1 261 /* Configure the Flash Latency cycles and enable prefetch buffer */
Sergunb 0:f1834a63f7c1 262 SetSysClock();
Sergunb 0:f1834a63f7c1 263
Sergunb 0:f1834a63f7c1 264 #ifdef VECT_TAB_SRAM
Sergunb 0:f1834a63f7c1 265 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
Sergunb 0:f1834a63f7c1 266 #else
Sergunb 0:f1834a63f7c1 267 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
Sergunb 0:f1834a63f7c1 268 #endif
Sergunb 0:f1834a63f7c1 269 }
Sergunb 0:f1834a63f7c1 270
Sergunb 0:f1834a63f7c1 271 /**
Sergunb 0:f1834a63f7c1 272 * @brief Update SystemCoreClock variable according to Clock Register Values.
Sergunb 0:f1834a63f7c1 273 * The SystemCoreClock variable contains the core clock (HCLK), it can
Sergunb 0:f1834a63f7c1 274 * be used by the user application to setup the SysTick timer or configure
Sergunb 0:f1834a63f7c1 275 * other parameters.
Sergunb 0:f1834a63f7c1 276 *
Sergunb 0:f1834a63f7c1 277 * @note Each time the core clock (HCLK) changes, this function must be called
Sergunb 0:f1834a63f7c1 278 * to update SystemCoreClock variable value. Otherwise, any configuration
Sergunb 0:f1834a63f7c1 279 * based on this variable will be incorrect.
Sergunb 0:f1834a63f7c1 280 *
Sergunb 0:f1834a63f7c1 281 * @note - The system frequency computed by this function is not the real
Sergunb 0:f1834a63f7c1 282 * frequency in the chip. It is calculated based on the predefined
Sergunb 0:f1834a63f7c1 283 * constant and the selected clock source:
Sergunb 0:f1834a63f7c1 284 *
Sergunb 0:f1834a63f7c1 285 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
Sergunb 0:f1834a63f7c1 286 *
Sergunb 0:f1834a63f7c1 287 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
Sergunb 0:f1834a63f7c1 288 *
Sergunb 0:f1834a63f7c1 289 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
Sergunb 0:f1834a63f7c1 290 * or HSI_VALUE(*) multiplied by the PLL factors.
Sergunb 0:f1834a63f7c1 291 *
Sergunb 0:f1834a63f7c1 292 * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value
Sergunb 0:f1834a63f7c1 293 * 8 MHz) but the real value may vary depending on the variations
Sergunb 0:f1834a63f7c1 294 * in voltage and temperature.
Sergunb 0:f1834a63f7c1 295 *
Sergunb 0:f1834a63f7c1 296 * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value
Sergunb 0:f1834a63f7c1 297 * 8 MHz or 25 MHz, depedning on the product used), user has to ensure
Sergunb 0:f1834a63f7c1 298 * that HSE_VALUE is same as the real frequency of the crystal used.
Sergunb 0:f1834a63f7c1 299 * Otherwise, this function may have wrong result.
Sergunb 0:f1834a63f7c1 300 *
Sergunb 0:f1834a63f7c1 301 * - The result of this function could be not correct when using fractional
Sergunb 0:f1834a63f7c1 302 * value for HSE crystal.
Sergunb 0:f1834a63f7c1 303 * @param None
Sergunb 0:f1834a63f7c1 304 * @retval None
Sergunb 0:f1834a63f7c1 305 */
Sergunb 0:f1834a63f7c1 306 void SystemCoreClockUpdate (void)
Sergunb 0:f1834a63f7c1 307 {
Sergunb 0:f1834a63f7c1 308 uint32_t tmp = 0, pllmull = 0, pllsource = 0;
Sergunb 0:f1834a63f7c1 309
Sergunb 0:f1834a63f7c1 310 #ifdef STM32F10X_CL
Sergunb 0:f1834a63f7c1 311 uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0;
Sergunb 0:f1834a63f7c1 312 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 313
Sergunb 0:f1834a63f7c1 314 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
Sergunb 0:f1834a63f7c1 315 uint32_t prediv1factor = 0;
Sergunb 0:f1834a63f7c1 316 #endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */
Sergunb 0:f1834a63f7c1 317
Sergunb 0:f1834a63f7c1 318 /* Get SYSCLK source -------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 319 tmp = RCC->CFGR & RCC_CFGR_SWS;
Sergunb 0:f1834a63f7c1 320
Sergunb 0:f1834a63f7c1 321 switch (tmp)
Sergunb 0:f1834a63f7c1 322 {
Sergunb 0:f1834a63f7c1 323 case 0x00: /* HSI used as system clock */
Sergunb 0:f1834a63f7c1 324 SystemCoreClock = HSI_VALUE;
Sergunb 0:f1834a63f7c1 325 break;
Sergunb 0:f1834a63f7c1 326 case 0x04: /* HSE used as system clock */
Sergunb 0:f1834a63f7c1 327 SystemCoreClock = HSE_VALUE;
Sergunb 0:f1834a63f7c1 328 break;
Sergunb 0:f1834a63f7c1 329 case 0x08: /* PLL used as system clock */
Sergunb 0:f1834a63f7c1 330
Sergunb 0:f1834a63f7c1 331 /* Get PLL clock source and multiplication factor ----------------------*/
Sergunb 0:f1834a63f7c1 332 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
Sergunb 0:f1834a63f7c1 333 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
Sergunb 0:f1834a63f7c1 334
Sergunb 0:f1834a63f7c1 335 #ifndef STM32F10X_CL
Sergunb 0:f1834a63f7c1 336 pllmull = ( pllmull >> 18) + 2;
Sergunb 0:f1834a63f7c1 337
Sergunb 0:f1834a63f7c1 338 if (pllsource == 0x00)
Sergunb 0:f1834a63f7c1 339 {
Sergunb 0:f1834a63f7c1 340 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
Sergunb 0:f1834a63f7c1 341 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
Sergunb 0:f1834a63f7c1 342 }
Sergunb 0:f1834a63f7c1 343 else
Sergunb 0:f1834a63f7c1 344 {
Sergunb 0:f1834a63f7c1 345 #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL)
Sergunb 0:f1834a63f7c1 346 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
Sergunb 0:f1834a63f7c1 347 /* HSE oscillator clock selected as PREDIV1 clock entry */
Sergunb 0:f1834a63f7c1 348 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
Sergunb 0:f1834a63f7c1 349 #else
Sergunb 0:f1834a63f7c1 350 /* HSE selected as PLL clock entry */
Sergunb 0:f1834a63f7c1 351 if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET)
Sergunb 0:f1834a63f7c1 352 {/* HSE oscillator clock divided by 2 */
Sergunb 0:f1834a63f7c1 353 SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
Sergunb 0:f1834a63f7c1 354 }
Sergunb 0:f1834a63f7c1 355 else
Sergunb 0:f1834a63f7c1 356 {
Sergunb 0:f1834a63f7c1 357 SystemCoreClock = HSE_VALUE * pllmull;
Sergunb 0:f1834a63f7c1 358 }
Sergunb 0:f1834a63f7c1 359 #endif
Sergunb 0:f1834a63f7c1 360 }
Sergunb 0:f1834a63f7c1 361 #else
Sergunb 0:f1834a63f7c1 362 pllmull = pllmull >> 18;
Sergunb 0:f1834a63f7c1 363
Sergunb 0:f1834a63f7c1 364 if (pllmull != 0x0D)
Sergunb 0:f1834a63f7c1 365 {
Sergunb 0:f1834a63f7c1 366 pllmull += 2;
Sergunb 0:f1834a63f7c1 367 }
Sergunb 0:f1834a63f7c1 368 else
Sergunb 0:f1834a63f7c1 369 { /* PLL multiplication factor = PLL input clock * 6.5 */
Sergunb 0:f1834a63f7c1 370 pllmull = 13 / 2;
Sergunb 0:f1834a63f7c1 371 }
Sergunb 0:f1834a63f7c1 372
Sergunb 0:f1834a63f7c1 373 if (pllsource == 0x00)
Sergunb 0:f1834a63f7c1 374 {
Sergunb 0:f1834a63f7c1 375 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
Sergunb 0:f1834a63f7c1 376 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
Sergunb 0:f1834a63f7c1 377 }
Sergunb 0:f1834a63f7c1 378 else
Sergunb 0:f1834a63f7c1 379 {/* PREDIV1 selected as PLL clock entry */
Sergunb 0:f1834a63f7c1 380
Sergunb 0:f1834a63f7c1 381 /* Get PREDIV1 clock source and division factor */
Sergunb 0:f1834a63f7c1 382 prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC;
Sergunb 0:f1834a63f7c1 383 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
Sergunb 0:f1834a63f7c1 384
Sergunb 0:f1834a63f7c1 385 if (prediv1source == 0)
Sergunb 0:f1834a63f7c1 386 {
Sergunb 0:f1834a63f7c1 387 /* HSE oscillator clock selected as PREDIV1 clock entry */
Sergunb 0:f1834a63f7c1 388 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
Sergunb 0:f1834a63f7c1 389 }
Sergunb 0:f1834a63f7c1 390 else
Sergunb 0:f1834a63f7c1 391 {/* PLL2 clock selected as PREDIV1 clock entry */
Sergunb 0:f1834a63f7c1 392
Sergunb 0:f1834a63f7c1 393 /* Get PREDIV2 division factor and PLL2 multiplication factor */
Sergunb 0:f1834a63f7c1 394 prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1;
Sergunb 0:f1834a63f7c1 395 pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2;
Sergunb 0:f1834a63f7c1 396 SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull;
Sergunb 0:f1834a63f7c1 397 }
Sergunb 0:f1834a63f7c1 398 }
Sergunb 0:f1834a63f7c1 399 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 400 break;
Sergunb 0:f1834a63f7c1 401
Sergunb 0:f1834a63f7c1 402 default:
Sergunb 0:f1834a63f7c1 403 SystemCoreClock = HSI_VALUE;
Sergunb 0:f1834a63f7c1 404 break;
Sergunb 0:f1834a63f7c1 405 }
Sergunb 0:f1834a63f7c1 406
Sergunb 0:f1834a63f7c1 407 /* Compute HCLK clock frequency ----------------*/
Sergunb 0:f1834a63f7c1 408 /* Get HCLK prescaler */
Sergunb 0:f1834a63f7c1 409 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
Sergunb 0:f1834a63f7c1 410 /* HCLK clock frequency */
Sergunb 0:f1834a63f7c1 411 SystemCoreClock >>= tmp;
Sergunb 0:f1834a63f7c1 412 }
Sergunb 0:f1834a63f7c1 413
Sergunb 0:f1834a63f7c1 414 /**
Sergunb 0:f1834a63f7c1 415 * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
Sergunb 0:f1834a63f7c1 416 * @param None
Sergunb 0:f1834a63f7c1 417 * @retval None
Sergunb 0:f1834a63f7c1 418 */
Sergunb 0:f1834a63f7c1 419 static void SetSysClock(void)
Sergunb 0:f1834a63f7c1 420 {
Sergunb 0:f1834a63f7c1 421 #ifdef SYSCLK_FREQ_HSE
Sergunb 0:f1834a63f7c1 422 SetSysClockToHSE();
Sergunb 0:f1834a63f7c1 423 #elif defined SYSCLK_FREQ_24MHz
Sergunb 0:f1834a63f7c1 424 SetSysClockTo24();
Sergunb 0:f1834a63f7c1 425 #elif defined SYSCLK_FREQ_36MHz
Sergunb 0:f1834a63f7c1 426 SetSysClockTo36();
Sergunb 0:f1834a63f7c1 427 #elif defined SYSCLK_FREQ_48MHz
Sergunb 0:f1834a63f7c1 428 SetSysClockTo48();
Sergunb 0:f1834a63f7c1 429 #elif defined SYSCLK_FREQ_56MHz
Sergunb 0:f1834a63f7c1 430 SetSysClockTo56();
Sergunb 0:f1834a63f7c1 431 #elif defined SYSCLK_FREQ_72MHz
Sergunb 0:f1834a63f7c1 432 SetSysClockTo72();
Sergunb 0:f1834a63f7c1 433 #endif
Sergunb 0:f1834a63f7c1 434
Sergunb 0:f1834a63f7c1 435 /* If none of the define above is enabled, the HSI is used as System clock
Sergunb 0:f1834a63f7c1 436 source (default after reset) */
Sergunb 0:f1834a63f7c1 437 }
Sergunb 0:f1834a63f7c1 438
Sergunb 0:f1834a63f7c1 439 /**
Sergunb 0:f1834a63f7c1 440 * @brief Setup the external memory controller. Called in startup_stm32f10x.s
Sergunb 0:f1834a63f7c1 441 * before jump to __main
Sergunb 0:f1834a63f7c1 442 * @param None
Sergunb 0:f1834a63f7c1 443 * @retval None
Sergunb 0:f1834a63f7c1 444 */
Sergunb 0:f1834a63f7c1 445 #ifdef DATA_IN_ExtSRAM
Sergunb 0:f1834a63f7c1 446 /**
Sergunb 0:f1834a63f7c1 447 * @brief Setup the external memory controller.
Sergunb 0:f1834a63f7c1 448 * Called in startup_stm32f10x_xx.s/.c before jump to main.
Sergunb 0:f1834a63f7c1 449 * This function configures the external SRAM mounted on STM3210E-EVAL
Sergunb 0:f1834a63f7c1 450 * board (STM32 High density devices). This SRAM will be used as program
Sergunb 0:f1834a63f7c1 451 * data memory (including heap and stack).
Sergunb 0:f1834a63f7c1 452 * @param None
Sergunb 0:f1834a63f7c1 453 * @retval None
Sergunb 0:f1834a63f7c1 454 */
Sergunb 0:f1834a63f7c1 455 void SystemInit_ExtMemCtl(void)
Sergunb 0:f1834a63f7c1 456 {
Sergunb 0:f1834a63f7c1 457 /*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is
Sergunb 0:f1834a63f7c1 458 required, then adjust the Register Addresses */
Sergunb 0:f1834a63f7c1 459
Sergunb 0:f1834a63f7c1 460 /* Enable FSMC clock */
Sergunb 0:f1834a63f7c1 461 RCC->AHBENR = 0x00000114;
Sergunb 0:f1834a63f7c1 462
Sergunb 0:f1834a63f7c1 463 /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */
Sergunb 0:f1834a63f7c1 464 RCC->APB2ENR = 0x000001E0;
Sergunb 0:f1834a63f7c1 465
Sergunb 0:f1834a63f7c1 466 /* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/
Sergunb 0:f1834a63f7c1 467 /*---------------- SRAM Address lines configuration -------------------------*/
Sergunb 0:f1834a63f7c1 468 /*---------------- NOE and NWE configuration --------------------------------*/
Sergunb 0:f1834a63f7c1 469 /*---------------- NE3 configuration ----------------------------------------*/
Sergunb 0:f1834a63f7c1 470 /*---------------- NBL0, NBL1 configuration ---------------------------------*/
Sergunb 0:f1834a63f7c1 471
Sergunb 0:f1834a63f7c1 472 GPIOD->CRL = 0x44BB44BB;
Sergunb 0:f1834a63f7c1 473 GPIOD->CRH = 0xBBBBBBBB;
Sergunb 0:f1834a63f7c1 474
Sergunb 0:f1834a63f7c1 475 GPIOE->CRL = 0xB44444BB;
Sergunb 0:f1834a63f7c1 476 GPIOE->CRH = 0xBBBBBBBB;
Sergunb 0:f1834a63f7c1 477
Sergunb 0:f1834a63f7c1 478 GPIOF->CRL = 0x44BBBBBB;
Sergunb 0:f1834a63f7c1 479 GPIOF->CRH = 0xBBBB4444;
Sergunb 0:f1834a63f7c1 480
Sergunb 0:f1834a63f7c1 481 GPIOG->CRL = 0x44BBBBBB;
Sergunb 0:f1834a63f7c1 482 GPIOG->CRH = 0x44444B44;
Sergunb 0:f1834a63f7c1 483
Sergunb 0:f1834a63f7c1 484 /*---------------- FSMC Configuration ---------------------------------------*/
Sergunb 0:f1834a63f7c1 485 /*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/
Sergunb 0:f1834a63f7c1 486
Sergunb 0:f1834a63f7c1 487 FSMC_Bank1->BTCR[4] = 0x00001011;
Sergunb 0:f1834a63f7c1 488 FSMC_Bank1->BTCR[5] = 0x00000200;
Sergunb 0:f1834a63f7c1 489 }
Sergunb 0:f1834a63f7c1 490 #endif /* DATA_IN_ExtSRAM */
Sergunb 0:f1834a63f7c1 491
Sergunb 0:f1834a63f7c1 492 #ifdef SYSCLK_FREQ_HSE
Sergunb 0:f1834a63f7c1 493 /**
Sergunb 0:f1834a63f7c1 494 * @brief Selects HSE as System clock source and configure HCLK, PCLK2
Sergunb 0:f1834a63f7c1 495 * and PCLK1 prescalers.
Sergunb 0:f1834a63f7c1 496 * @note This function should be used only after reset.
Sergunb 0:f1834a63f7c1 497 * @param None
Sergunb 0:f1834a63f7c1 498 * @retval None
Sergunb 0:f1834a63f7c1 499 */
Sergunb 0:f1834a63f7c1 500 static void SetSysClockToHSE(void)
Sergunb 0:f1834a63f7c1 501 {
Sergunb 0:f1834a63f7c1 502 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:f1834a63f7c1 503
Sergunb 0:f1834a63f7c1 504 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:f1834a63f7c1 505 /* Enable HSE */
Sergunb 0:f1834a63f7c1 506 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:f1834a63f7c1 507
Sergunb 0:f1834a63f7c1 508 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:f1834a63f7c1 509 do
Sergunb 0:f1834a63f7c1 510 {
Sergunb 0:f1834a63f7c1 511 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:f1834a63f7c1 512 StartUpCounter++;
Sergunb 0:f1834a63f7c1 513 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:f1834a63f7c1 514
Sergunb 0:f1834a63f7c1 515 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:f1834a63f7c1 516 {
Sergunb 0:f1834a63f7c1 517 HSEStatus = (uint32_t)0x01;
Sergunb 0:f1834a63f7c1 518 }
Sergunb 0:f1834a63f7c1 519 else
Sergunb 0:f1834a63f7c1 520 {
Sergunb 0:f1834a63f7c1 521 HSEStatus = (uint32_t)0x00;
Sergunb 0:f1834a63f7c1 522 }
Sergunb 0:f1834a63f7c1 523
Sergunb 0:f1834a63f7c1 524 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:f1834a63f7c1 525 {
Sergunb 0:f1834a63f7c1 526
Sergunb 0:f1834a63f7c1 527 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
Sergunb 0:f1834a63f7c1 528 /* Enable Prefetch Buffer */
Sergunb 0:f1834a63f7c1 529 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:f1834a63f7c1 530
Sergunb 0:f1834a63f7c1 531 /* Flash 0 wait state */
Sergunb 0:f1834a63f7c1 532 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:f1834a63f7c1 533
Sergunb 0:f1834a63f7c1 534 #ifndef STM32F10X_CL
Sergunb 0:f1834a63f7c1 535 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
Sergunb 0:f1834a63f7c1 536 #else
Sergunb 0:f1834a63f7c1 537 if (HSE_VALUE <= 24000000)
Sergunb 0:f1834a63f7c1 538 {
Sergunb 0:f1834a63f7c1 539 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
Sergunb 0:f1834a63f7c1 540 }
Sergunb 0:f1834a63f7c1 541 else
Sergunb 0:f1834a63f7c1 542 {
Sergunb 0:f1834a63f7c1 543 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
Sergunb 0:f1834a63f7c1 544 }
Sergunb 0:f1834a63f7c1 545 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 546 #endif
Sergunb 0:f1834a63f7c1 547
Sergunb 0:f1834a63f7c1 548 /* HCLK = SYSCLK */
Sergunb 0:f1834a63f7c1 549 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:f1834a63f7c1 550
Sergunb 0:f1834a63f7c1 551 /* PCLK2 = HCLK */
Sergunb 0:f1834a63f7c1 552 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:f1834a63f7c1 553
Sergunb 0:f1834a63f7c1 554 /* PCLK1 = HCLK */
Sergunb 0:f1834a63f7c1 555 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
Sergunb 0:f1834a63f7c1 556
Sergunb 0:f1834a63f7c1 557 /* Select HSE as system clock source */
Sergunb 0:f1834a63f7c1 558 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:f1834a63f7c1 559 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE;
Sergunb 0:f1834a63f7c1 560
Sergunb 0:f1834a63f7c1 561 /* Wait till HSE is used as system clock source */
Sergunb 0:f1834a63f7c1 562 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04)
Sergunb 0:f1834a63f7c1 563 {
Sergunb 0:f1834a63f7c1 564 }
Sergunb 0:f1834a63f7c1 565 }
Sergunb 0:f1834a63f7c1 566 else
Sergunb 0:f1834a63f7c1 567 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:f1834a63f7c1 568 configuration. User can add here some code to deal with this error */
Sergunb 0:f1834a63f7c1 569 }
Sergunb 0:f1834a63f7c1 570 }
Sergunb 0:f1834a63f7c1 571 #elif defined SYSCLK_FREQ_24MHz
Sergunb 0:f1834a63f7c1 572 /**
Sergunb 0:f1834a63f7c1 573 * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2
Sergunb 0:f1834a63f7c1 574 * and PCLK1 prescalers.
Sergunb 0:f1834a63f7c1 575 * @note This function should be used only after reset.
Sergunb 0:f1834a63f7c1 576 * @param None
Sergunb 0:f1834a63f7c1 577 * @retval None
Sergunb 0:f1834a63f7c1 578 */
Sergunb 0:f1834a63f7c1 579 static void SetSysClockTo24(void)
Sergunb 0:f1834a63f7c1 580 {
Sergunb 0:f1834a63f7c1 581 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:f1834a63f7c1 582
Sergunb 0:f1834a63f7c1 583 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:f1834a63f7c1 584 /* Enable HSE */
Sergunb 0:f1834a63f7c1 585 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:f1834a63f7c1 586
Sergunb 0:f1834a63f7c1 587 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:f1834a63f7c1 588 do
Sergunb 0:f1834a63f7c1 589 {
Sergunb 0:f1834a63f7c1 590 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:f1834a63f7c1 591 StartUpCounter++;
Sergunb 0:f1834a63f7c1 592 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:f1834a63f7c1 593
Sergunb 0:f1834a63f7c1 594 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:f1834a63f7c1 595 {
Sergunb 0:f1834a63f7c1 596 HSEStatus = (uint32_t)0x01;
Sergunb 0:f1834a63f7c1 597 }
Sergunb 0:f1834a63f7c1 598 else
Sergunb 0:f1834a63f7c1 599 {
Sergunb 0:f1834a63f7c1 600 HSEStatus = (uint32_t)0x00;
Sergunb 0:f1834a63f7c1 601 }
Sergunb 0:f1834a63f7c1 602
Sergunb 0:f1834a63f7c1 603 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:f1834a63f7c1 604 {
Sergunb 0:f1834a63f7c1 605 #if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL
Sergunb 0:f1834a63f7c1 606 /* Enable Prefetch Buffer */
Sergunb 0:f1834a63f7c1 607 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:f1834a63f7c1 608
Sergunb 0:f1834a63f7c1 609 /* Flash 0 wait state */
Sergunb 0:f1834a63f7c1 610 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:f1834a63f7c1 611 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_0;
Sergunb 0:f1834a63f7c1 612 #endif
Sergunb 0:f1834a63f7c1 613
Sergunb 0:f1834a63f7c1 614 /* HCLK = SYSCLK */
Sergunb 0:f1834a63f7c1 615 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:f1834a63f7c1 616
Sergunb 0:f1834a63f7c1 617 /* PCLK2 = HCLK */
Sergunb 0:f1834a63f7c1 618 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:f1834a63f7c1 619
Sergunb 0:f1834a63f7c1 620 /* PCLK1 = HCLK */
Sergunb 0:f1834a63f7c1 621 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
Sergunb 0:f1834a63f7c1 622
Sergunb 0:f1834a63f7c1 623 #ifdef STM32F10X_CL
Sergunb 0:f1834a63f7c1 624 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 625 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */
Sergunb 0:f1834a63f7c1 626 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:f1834a63f7c1 627 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:f1834a63f7c1 628 RCC_CFGR_PLLMULL6);
Sergunb 0:f1834a63f7c1 629
Sergunb 0:f1834a63f7c1 630 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:f1834a63f7c1 631 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
Sergunb 0:f1834a63f7c1 632 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:f1834a63f7c1 633 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:f1834a63f7c1 634 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:f1834a63f7c1 635 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
Sergunb 0:f1834a63f7c1 636
Sergunb 0:f1834a63f7c1 637 /* Enable PLL2 */
Sergunb 0:f1834a63f7c1 638 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:f1834a63f7c1 639 /* Wait till PLL2 is ready */
Sergunb 0:f1834a63f7c1 640 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:f1834a63f7c1 641 {
Sergunb 0:f1834a63f7c1 642 }
Sergunb 0:f1834a63f7c1 643 #elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL)
Sergunb 0:f1834a63f7c1 644 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
Sergunb 0:f1834a63f7c1 645 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:f1834a63f7c1 646 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLMULL6);
Sergunb 0:f1834a63f7c1 647 #else
Sergunb 0:f1834a63f7c1 648 /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */
Sergunb 0:f1834a63f7c1 649 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:f1834a63f7c1 650 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL6);
Sergunb 0:f1834a63f7c1 651 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 652
Sergunb 0:f1834a63f7c1 653 /* Enable PLL */
Sergunb 0:f1834a63f7c1 654 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:f1834a63f7c1 655
Sergunb 0:f1834a63f7c1 656 /* Wait till PLL is ready */
Sergunb 0:f1834a63f7c1 657 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:f1834a63f7c1 658 {
Sergunb 0:f1834a63f7c1 659 }
Sergunb 0:f1834a63f7c1 660
Sergunb 0:f1834a63f7c1 661 /* Select PLL as system clock source */
Sergunb 0:f1834a63f7c1 662 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:f1834a63f7c1 663 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:f1834a63f7c1 664
Sergunb 0:f1834a63f7c1 665 /* Wait till PLL is used as system clock source */
Sergunb 0:f1834a63f7c1 666 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:f1834a63f7c1 667 {
Sergunb 0:f1834a63f7c1 668 }
Sergunb 0:f1834a63f7c1 669 }
Sergunb 0:f1834a63f7c1 670 else
Sergunb 0:f1834a63f7c1 671 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:f1834a63f7c1 672 configuration. User can add here some code to deal with this error */
Sergunb 0:f1834a63f7c1 673 }
Sergunb 0:f1834a63f7c1 674 }
Sergunb 0:f1834a63f7c1 675 #elif defined SYSCLK_FREQ_36MHz
Sergunb 0:f1834a63f7c1 676 /**
Sergunb 0:f1834a63f7c1 677 * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2
Sergunb 0:f1834a63f7c1 678 * and PCLK1 prescalers.
Sergunb 0:f1834a63f7c1 679 * @note This function should be used only after reset.
Sergunb 0:f1834a63f7c1 680 * @param None
Sergunb 0:f1834a63f7c1 681 * @retval None
Sergunb 0:f1834a63f7c1 682 */
Sergunb 0:f1834a63f7c1 683 static void SetSysClockTo36(void)
Sergunb 0:f1834a63f7c1 684 {
Sergunb 0:f1834a63f7c1 685 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:f1834a63f7c1 686
Sergunb 0:f1834a63f7c1 687 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:f1834a63f7c1 688 /* Enable HSE */
Sergunb 0:f1834a63f7c1 689 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:f1834a63f7c1 690
Sergunb 0:f1834a63f7c1 691 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:f1834a63f7c1 692 do
Sergunb 0:f1834a63f7c1 693 {
Sergunb 0:f1834a63f7c1 694 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:f1834a63f7c1 695 StartUpCounter++;
Sergunb 0:f1834a63f7c1 696 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:f1834a63f7c1 697
Sergunb 0:f1834a63f7c1 698 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:f1834a63f7c1 699 {
Sergunb 0:f1834a63f7c1 700 HSEStatus = (uint32_t)0x01;
Sergunb 0:f1834a63f7c1 701 }
Sergunb 0:f1834a63f7c1 702 else
Sergunb 0:f1834a63f7c1 703 {
Sergunb 0:f1834a63f7c1 704 HSEStatus = (uint32_t)0x00;
Sergunb 0:f1834a63f7c1 705 }
Sergunb 0:f1834a63f7c1 706
Sergunb 0:f1834a63f7c1 707 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:f1834a63f7c1 708 {
Sergunb 0:f1834a63f7c1 709 /* Enable Prefetch Buffer */
Sergunb 0:f1834a63f7c1 710 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:f1834a63f7c1 711
Sergunb 0:f1834a63f7c1 712 /* Flash 1 wait state */
Sergunb 0:f1834a63f7c1 713 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:f1834a63f7c1 714 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
Sergunb 0:f1834a63f7c1 715
Sergunb 0:f1834a63f7c1 716 /* HCLK = SYSCLK */
Sergunb 0:f1834a63f7c1 717 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:f1834a63f7c1 718
Sergunb 0:f1834a63f7c1 719 /* PCLK2 = HCLK */
Sergunb 0:f1834a63f7c1 720 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:f1834a63f7c1 721
Sergunb 0:f1834a63f7c1 722 /* PCLK1 = HCLK */
Sergunb 0:f1834a63f7c1 723 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
Sergunb 0:f1834a63f7c1 724
Sergunb 0:f1834a63f7c1 725 #ifdef STM32F10X_CL
Sergunb 0:f1834a63f7c1 726 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 727
Sergunb 0:f1834a63f7c1 728 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */
Sergunb 0:f1834a63f7c1 729 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:f1834a63f7c1 730 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:f1834a63f7c1 731 RCC_CFGR_PLLMULL9);
Sergunb 0:f1834a63f7c1 732
Sergunb 0:f1834a63f7c1 733 /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:f1834a63f7c1 734 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */
Sergunb 0:f1834a63f7c1 735
Sergunb 0:f1834a63f7c1 736 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:f1834a63f7c1 737 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:f1834a63f7c1 738 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:f1834a63f7c1 739 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10);
Sergunb 0:f1834a63f7c1 740
Sergunb 0:f1834a63f7c1 741 /* Enable PLL2 */
Sergunb 0:f1834a63f7c1 742 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:f1834a63f7c1 743 /* Wait till PLL2 is ready */
Sergunb 0:f1834a63f7c1 744 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:f1834a63f7c1 745 {
Sergunb 0:f1834a63f7c1 746 }
Sergunb 0:f1834a63f7c1 747
Sergunb 0:f1834a63f7c1 748 #else
Sergunb 0:f1834a63f7c1 749 /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */
Sergunb 0:f1834a63f7c1 750 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:f1834a63f7c1 751 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLXTPRE_HSE_Div2 | RCC_CFGR_PLLMULL9);
Sergunb 0:f1834a63f7c1 752 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 753
Sergunb 0:f1834a63f7c1 754 /* Enable PLL */
Sergunb 0:f1834a63f7c1 755 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:f1834a63f7c1 756
Sergunb 0:f1834a63f7c1 757 /* Wait till PLL is ready */
Sergunb 0:f1834a63f7c1 758 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:f1834a63f7c1 759 {
Sergunb 0:f1834a63f7c1 760 }
Sergunb 0:f1834a63f7c1 761
Sergunb 0:f1834a63f7c1 762 /* Select PLL as system clock source */
Sergunb 0:f1834a63f7c1 763 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:f1834a63f7c1 764 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:f1834a63f7c1 765
Sergunb 0:f1834a63f7c1 766 /* Wait till PLL is used as system clock source */
Sergunb 0:f1834a63f7c1 767 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:f1834a63f7c1 768 {
Sergunb 0:f1834a63f7c1 769 }
Sergunb 0:f1834a63f7c1 770 }
Sergunb 0:f1834a63f7c1 771 else
Sergunb 0:f1834a63f7c1 772 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:f1834a63f7c1 773 configuration. User can add here some code to deal with this error */
Sergunb 0:f1834a63f7c1 774 }
Sergunb 0:f1834a63f7c1 775 }
Sergunb 0:f1834a63f7c1 776 #elif defined SYSCLK_FREQ_48MHz
Sergunb 0:f1834a63f7c1 777 /**
Sergunb 0:f1834a63f7c1 778 * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2
Sergunb 0:f1834a63f7c1 779 * and PCLK1 prescalers.
Sergunb 0:f1834a63f7c1 780 * @note This function should be used only after reset.
Sergunb 0:f1834a63f7c1 781 * @param None
Sergunb 0:f1834a63f7c1 782 * @retval None
Sergunb 0:f1834a63f7c1 783 */
Sergunb 0:f1834a63f7c1 784 static void SetSysClockTo48(void)
Sergunb 0:f1834a63f7c1 785 {
Sergunb 0:f1834a63f7c1 786 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:f1834a63f7c1 787
Sergunb 0:f1834a63f7c1 788 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:f1834a63f7c1 789 /* Enable HSE */
Sergunb 0:f1834a63f7c1 790 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:f1834a63f7c1 791
Sergunb 0:f1834a63f7c1 792 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:f1834a63f7c1 793 do
Sergunb 0:f1834a63f7c1 794 {
Sergunb 0:f1834a63f7c1 795 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:f1834a63f7c1 796 StartUpCounter++;
Sergunb 0:f1834a63f7c1 797 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:f1834a63f7c1 798
Sergunb 0:f1834a63f7c1 799 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:f1834a63f7c1 800 {
Sergunb 0:f1834a63f7c1 801 HSEStatus = (uint32_t)0x01;
Sergunb 0:f1834a63f7c1 802 }
Sergunb 0:f1834a63f7c1 803 else
Sergunb 0:f1834a63f7c1 804 {
Sergunb 0:f1834a63f7c1 805 HSEStatus = (uint32_t)0x00;
Sergunb 0:f1834a63f7c1 806 }
Sergunb 0:f1834a63f7c1 807
Sergunb 0:f1834a63f7c1 808 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:f1834a63f7c1 809 {
Sergunb 0:f1834a63f7c1 810 /* Enable Prefetch Buffer */
Sergunb 0:f1834a63f7c1 811 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:f1834a63f7c1 812
Sergunb 0:f1834a63f7c1 813 /* Flash 1 wait state */
Sergunb 0:f1834a63f7c1 814 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:f1834a63f7c1 815 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1;
Sergunb 0:f1834a63f7c1 816
Sergunb 0:f1834a63f7c1 817 /* HCLK = SYSCLK */
Sergunb 0:f1834a63f7c1 818 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:f1834a63f7c1 819
Sergunb 0:f1834a63f7c1 820 /* PCLK2 = HCLK */
Sergunb 0:f1834a63f7c1 821 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:f1834a63f7c1 822
Sergunb 0:f1834a63f7c1 823 /* PCLK1 = HCLK */
Sergunb 0:f1834a63f7c1 824 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
Sergunb 0:f1834a63f7c1 825
Sergunb 0:f1834a63f7c1 826 #ifdef STM32F10X_CL
Sergunb 0:f1834a63f7c1 827 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 828 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:f1834a63f7c1 829 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
Sergunb 0:f1834a63f7c1 830
Sergunb 0:f1834a63f7c1 831 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:f1834a63f7c1 832 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:f1834a63f7c1 833 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:f1834a63f7c1 834 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
Sergunb 0:f1834a63f7c1 835
Sergunb 0:f1834a63f7c1 836 /* Enable PLL2 */
Sergunb 0:f1834a63f7c1 837 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:f1834a63f7c1 838 /* Wait till PLL2 is ready */
Sergunb 0:f1834a63f7c1 839 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:f1834a63f7c1 840 {
Sergunb 0:f1834a63f7c1 841 }
Sergunb 0:f1834a63f7c1 842
Sergunb 0:f1834a63f7c1 843
Sergunb 0:f1834a63f7c1 844 /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */
Sergunb 0:f1834a63f7c1 845 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:f1834a63f7c1 846 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:f1834a63f7c1 847 RCC_CFGR_PLLMULL6);
Sergunb 0:f1834a63f7c1 848 #else
Sergunb 0:f1834a63f7c1 849 /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
Sergunb 0:f1834a63f7c1 850 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:f1834a63f7c1 851 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL6);
Sergunb 0:f1834a63f7c1 852 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 853
Sergunb 0:f1834a63f7c1 854 /* Enable PLL */
Sergunb 0:f1834a63f7c1 855 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:f1834a63f7c1 856
Sergunb 0:f1834a63f7c1 857 /* Wait till PLL is ready */
Sergunb 0:f1834a63f7c1 858 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:f1834a63f7c1 859 {
Sergunb 0:f1834a63f7c1 860 }
Sergunb 0:f1834a63f7c1 861
Sergunb 0:f1834a63f7c1 862 /* Select PLL as system clock source */
Sergunb 0:f1834a63f7c1 863 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:f1834a63f7c1 864 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:f1834a63f7c1 865
Sergunb 0:f1834a63f7c1 866 /* Wait till PLL is used as system clock source */
Sergunb 0:f1834a63f7c1 867 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:f1834a63f7c1 868 {
Sergunb 0:f1834a63f7c1 869 }
Sergunb 0:f1834a63f7c1 870 }
Sergunb 0:f1834a63f7c1 871 else
Sergunb 0:f1834a63f7c1 872 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:f1834a63f7c1 873 configuration. User can add here some code to deal with this error */
Sergunb 0:f1834a63f7c1 874 }
Sergunb 0:f1834a63f7c1 875 }
Sergunb 0:f1834a63f7c1 876
Sergunb 0:f1834a63f7c1 877 #elif defined SYSCLK_FREQ_56MHz
Sergunb 0:f1834a63f7c1 878 /**
Sergunb 0:f1834a63f7c1 879 * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2
Sergunb 0:f1834a63f7c1 880 * and PCLK1 prescalers.
Sergunb 0:f1834a63f7c1 881 * @note This function should be used only after reset.
Sergunb 0:f1834a63f7c1 882 * @param None
Sergunb 0:f1834a63f7c1 883 * @retval None
Sergunb 0:f1834a63f7c1 884 */
Sergunb 0:f1834a63f7c1 885 static void SetSysClockTo56(void)
Sergunb 0:f1834a63f7c1 886 {
Sergunb 0:f1834a63f7c1 887 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:f1834a63f7c1 888
Sergunb 0:f1834a63f7c1 889 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:f1834a63f7c1 890 /* Enable HSE */
Sergunb 0:f1834a63f7c1 891 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:f1834a63f7c1 892
Sergunb 0:f1834a63f7c1 893 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:f1834a63f7c1 894 do
Sergunb 0:f1834a63f7c1 895 {
Sergunb 0:f1834a63f7c1 896 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:f1834a63f7c1 897 StartUpCounter++;
Sergunb 0:f1834a63f7c1 898 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:f1834a63f7c1 899
Sergunb 0:f1834a63f7c1 900 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:f1834a63f7c1 901 {
Sergunb 0:f1834a63f7c1 902 HSEStatus = (uint32_t)0x01;
Sergunb 0:f1834a63f7c1 903 }
Sergunb 0:f1834a63f7c1 904 else
Sergunb 0:f1834a63f7c1 905 {
Sergunb 0:f1834a63f7c1 906 HSEStatus = (uint32_t)0x00;
Sergunb 0:f1834a63f7c1 907 }
Sergunb 0:f1834a63f7c1 908
Sergunb 0:f1834a63f7c1 909 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:f1834a63f7c1 910 {
Sergunb 0:f1834a63f7c1 911 /* Enable Prefetch Buffer */
Sergunb 0:f1834a63f7c1 912 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:f1834a63f7c1 913
Sergunb 0:f1834a63f7c1 914 /* Flash 2 wait state */
Sergunb 0:f1834a63f7c1 915 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:f1834a63f7c1 916 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
Sergunb 0:f1834a63f7c1 917
Sergunb 0:f1834a63f7c1 918 /* HCLK = SYSCLK */
Sergunb 0:f1834a63f7c1 919 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:f1834a63f7c1 920
Sergunb 0:f1834a63f7c1 921 /* PCLK2 = HCLK */
Sergunb 0:f1834a63f7c1 922 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:f1834a63f7c1 923
Sergunb 0:f1834a63f7c1 924 /* PCLK1 = HCLK */
Sergunb 0:f1834a63f7c1 925 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
Sergunb 0:f1834a63f7c1 926
Sergunb 0:f1834a63f7c1 927 #ifdef STM32F10X_CL
Sergunb 0:f1834a63f7c1 928 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 929 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:f1834a63f7c1 930 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
Sergunb 0:f1834a63f7c1 931
Sergunb 0:f1834a63f7c1 932 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:f1834a63f7c1 933 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:f1834a63f7c1 934 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:f1834a63f7c1 935 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
Sergunb 0:f1834a63f7c1 936
Sergunb 0:f1834a63f7c1 937 /* Enable PLL2 */
Sergunb 0:f1834a63f7c1 938 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:f1834a63f7c1 939 /* Wait till PLL2 is ready */
Sergunb 0:f1834a63f7c1 940 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:f1834a63f7c1 941 {
Sergunb 0:f1834a63f7c1 942 }
Sergunb 0:f1834a63f7c1 943
Sergunb 0:f1834a63f7c1 944
Sergunb 0:f1834a63f7c1 945 /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */
Sergunb 0:f1834a63f7c1 946 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:f1834a63f7c1 947 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:f1834a63f7c1 948 RCC_CFGR_PLLMULL7);
Sergunb 0:f1834a63f7c1 949 #else
Sergunb 0:f1834a63f7c1 950 /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
Sergunb 0:f1834a63f7c1 951 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
Sergunb 0:f1834a63f7c1 952 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL7);
Sergunb 0:f1834a63f7c1 953
Sergunb 0:f1834a63f7c1 954 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 955
Sergunb 0:f1834a63f7c1 956 /* Enable PLL */
Sergunb 0:f1834a63f7c1 957 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:f1834a63f7c1 958
Sergunb 0:f1834a63f7c1 959 /* Wait till PLL is ready */
Sergunb 0:f1834a63f7c1 960 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:f1834a63f7c1 961 {
Sergunb 0:f1834a63f7c1 962 }
Sergunb 0:f1834a63f7c1 963
Sergunb 0:f1834a63f7c1 964 /* Select PLL as system clock source */
Sergunb 0:f1834a63f7c1 965 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:f1834a63f7c1 966 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:f1834a63f7c1 967
Sergunb 0:f1834a63f7c1 968 /* Wait till PLL is used as system clock source */
Sergunb 0:f1834a63f7c1 969 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:f1834a63f7c1 970 {
Sergunb 0:f1834a63f7c1 971 }
Sergunb 0:f1834a63f7c1 972 }
Sergunb 0:f1834a63f7c1 973 else
Sergunb 0:f1834a63f7c1 974 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:f1834a63f7c1 975 configuration. User can add here some code to deal with this error */
Sergunb 0:f1834a63f7c1 976 }
Sergunb 0:f1834a63f7c1 977 }
Sergunb 0:f1834a63f7c1 978
Sergunb 0:f1834a63f7c1 979 #elif defined SYSCLK_FREQ_72MHz
Sergunb 0:f1834a63f7c1 980 /**
Sergunb 0:f1834a63f7c1 981 * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2
Sergunb 0:f1834a63f7c1 982 * and PCLK1 prescalers.
Sergunb 0:f1834a63f7c1 983 * @note This function should be used only after reset.
Sergunb 0:f1834a63f7c1 984 * @param None
Sergunb 0:f1834a63f7c1 985 * @retval None
Sergunb 0:f1834a63f7c1 986 */
Sergunb 0:f1834a63f7c1 987 static void SetSysClockTo72(void)
Sergunb 0:f1834a63f7c1 988 {
Sergunb 0:f1834a63f7c1 989 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
Sergunb 0:f1834a63f7c1 990
Sergunb 0:f1834a63f7c1 991 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
Sergunb 0:f1834a63f7c1 992 /* Enable HSE */
Sergunb 0:f1834a63f7c1 993 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
Sergunb 0:f1834a63f7c1 994
Sergunb 0:f1834a63f7c1 995 /* Wait till HSE is ready and if Time out is reached exit */
Sergunb 0:f1834a63f7c1 996 do
Sergunb 0:f1834a63f7c1 997 {
Sergunb 0:f1834a63f7c1 998 HSEStatus = RCC->CR & RCC_CR_HSERDY;
Sergunb 0:f1834a63f7c1 999 StartUpCounter++;
Sergunb 0:f1834a63f7c1 1000 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
Sergunb 0:f1834a63f7c1 1001
Sergunb 0:f1834a63f7c1 1002 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
Sergunb 0:f1834a63f7c1 1003 {
Sergunb 0:f1834a63f7c1 1004 HSEStatus = (uint32_t)0x01;
Sergunb 0:f1834a63f7c1 1005 }
Sergunb 0:f1834a63f7c1 1006 else
Sergunb 0:f1834a63f7c1 1007 {
Sergunb 0:f1834a63f7c1 1008 HSEStatus = (uint32_t)0x00;
Sergunb 0:f1834a63f7c1 1009 }
Sergunb 0:f1834a63f7c1 1010
Sergunb 0:f1834a63f7c1 1011 if (HSEStatus == (uint32_t)0x01)
Sergunb 0:f1834a63f7c1 1012 {
Sergunb 0:f1834a63f7c1 1013 /* Enable Prefetch Buffer */
Sergunb 0:f1834a63f7c1 1014 FLASH->ACR |= FLASH_ACR_PRFTBE;
Sergunb 0:f1834a63f7c1 1015
Sergunb 0:f1834a63f7c1 1016 /* Flash 2 wait state */
Sergunb 0:f1834a63f7c1 1017 FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
Sergunb 0:f1834a63f7c1 1018 FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
Sergunb 0:f1834a63f7c1 1019
Sergunb 0:f1834a63f7c1 1020
Sergunb 0:f1834a63f7c1 1021 /* HCLK = SYSCLK */
Sergunb 0:f1834a63f7c1 1022 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
Sergunb 0:f1834a63f7c1 1023
Sergunb 0:f1834a63f7c1 1024 /* PCLK2 = HCLK */
Sergunb 0:f1834a63f7c1 1025 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
Sergunb 0:f1834a63f7c1 1026
Sergunb 0:f1834a63f7c1 1027 /* PCLK1 = HCLK */
Sergunb 0:f1834a63f7c1 1028 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
Sergunb 0:f1834a63f7c1 1029
Sergunb 0:f1834a63f7c1 1030 #ifdef STM32F10X_CL
Sergunb 0:f1834a63f7c1 1031 /* Configure PLLs ------------------------------------------------------*/
Sergunb 0:f1834a63f7c1 1032 /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */
Sergunb 0:f1834a63f7c1 1033 /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */
Sergunb 0:f1834a63f7c1 1034
Sergunb 0:f1834a63f7c1 1035 RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |
Sergunb 0:f1834a63f7c1 1036 RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);
Sergunb 0:f1834a63f7c1 1037 RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 |
Sergunb 0:f1834a63f7c1 1038 RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5);
Sergunb 0:f1834a63f7c1 1039
Sergunb 0:f1834a63f7c1 1040 /* Enable PLL2 */
Sergunb 0:f1834a63f7c1 1041 RCC->CR |= RCC_CR_PLL2ON;
Sergunb 0:f1834a63f7c1 1042 /* Wait till PLL2 is ready */
Sergunb 0:f1834a63f7c1 1043 while((RCC->CR & RCC_CR_PLL2RDY) == 0)
Sergunb 0:f1834a63f7c1 1044 {
Sergunb 0:f1834a63f7c1 1045 }
Sergunb 0:f1834a63f7c1 1046
Sergunb 0:f1834a63f7c1 1047
Sergunb 0:f1834a63f7c1 1048 /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */
Sergunb 0:f1834a63f7c1 1049 RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);
Sergunb 0:f1834a63f7c1 1050 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLSRC_PREDIV1 |
Sergunb 0:f1834a63f7c1 1051 RCC_CFGR_PLLMULL9);
Sergunb 0:f1834a63f7c1 1052 #else
Sergunb 0:f1834a63f7c1 1053 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
Sergunb 0:f1834a63f7c1 1054 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
Sergunb 0:f1834a63f7c1 1055 RCC_CFGR_PLLMULL));
Sergunb 0:f1834a63f7c1 1056 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL9);
Sergunb 0:f1834a63f7c1 1057 #endif /* STM32F10X_CL */
Sergunb 0:f1834a63f7c1 1058
Sergunb 0:f1834a63f7c1 1059 /* Enable PLL */
Sergunb 0:f1834a63f7c1 1060 RCC->CR |= RCC_CR_PLLON;
Sergunb 0:f1834a63f7c1 1061
Sergunb 0:f1834a63f7c1 1062 /* Wait till PLL is ready */
Sergunb 0:f1834a63f7c1 1063 while((RCC->CR & RCC_CR_PLLRDY) == 0)
Sergunb 0:f1834a63f7c1 1064 {
Sergunb 0:f1834a63f7c1 1065 }
Sergunb 0:f1834a63f7c1 1066
Sergunb 0:f1834a63f7c1 1067 /* Select PLL as system clock source */
Sergunb 0:f1834a63f7c1 1068 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
Sergunb 0:f1834a63f7c1 1069 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
Sergunb 0:f1834a63f7c1 1070
Sergunb 0:f1834a63f7c1 1071 /* Wait till PLL is used as system clock source */
Sergunb 0:f1834a63f7c1 1072 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
Sergunb 0:f1834a63f7c1 1073 {
Sergunb 0:f1834a63f7c1 1074 }
Sergunb 0:f1834a63f7c1 1075 }
Sergunb 0:f1834a63f7c1 1076 else
Sergunb 0:f1834a63f7c1 1077 { /* If HSE fails to start-up, the application will have wrong clock
Sergunb 0:f1834a63f7c1 1078 configuration. User can add here some code to deal with this error */
Sergunb 0:f1834a63f7c1 1079 }
Sergunb 0:f1834a63f7c1 1080 }
Sergunb 0:f1834a63f7c1 1081 #endif
Sergunb 0:f1834a63f7c1 1082
Sergunb 0:f1834a63f7c1 1083 /**
Sergunb 0:f1834a63f7c1 1084 * @}
Sergunb 0:f1834a63f7c1 1085 */
Sergunb 0:f1834a63f7c1 1086
Sergunb 0:f1834a63f7c1 1087 /**
Sergunb 0:f1834a63f7c1 1088 * @}
Sergunb 0:f1834a63f7c1 1089 */
Sergunb 0:f1834a63f7c1 1090
Sergunb 0:f1834a63f7c1 1091 /**
Sergunb 0:f1834a63f7c1 1092 * @}
Sergunb 0:f1834a63f7c1 1093 */
Sergunb 0:f1834a63f7c1 1094 /******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/