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cmsis_boot/stm32f10x.h@0:f1834a63f7c1, 2017-09-04 (annotated)

Committer:: Sergunb
Date:: Mon Sep 04 12:03:42 2017 +0000
Revision:: 0:f1834a63f7c1

Initial commit

Who changed what in which revision?

User	Revision	Line number	New contents of line
Sergunb	0:f1834a63f7c1	1	/**
Sergunb	0:f1834a63f7c1	2	******************************************************************************
Sergunb	0:f1834a63f7c1	3	* @file stm32f10x.h
Sergunb	0:f1834a63f7c1	4	* @author MCD Application Team
Sergunb	0:f1834a63f7c1	5	* @version V3.5.0
Sergunb	0:f1834a63f7c1	6	* @date 11-March-2011
Sergunb	0:f1834a63f7c1	7	* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
Sergunb	0:f1834a63f7c1	8	* This file contains all the peripheral register's definitions, bits
Sergunb	0:f1834a63f7c1	9	* definitions and memory mapping for STM32F10x Connectivity line,
Sergunb	0:f1834a63f7c1	10	* High density, High density value line, Medium density,
Sergunb	0:f1834a63f7c1	11	* Medium density Value line, Low density, Low density Value line
Sergunb	0:f1834a63f7c1	12	* and XL-density devices.
Sergunb	0:f1834a63f7c1	13	*
Sergunb	0:f1834a63f7c1	14	* The file is the unique include file that the application programmer
Sergunb	0:f1834a63f7c1	15	* is using in the C source code, usually in main.c. This file contains:
Sergunb	0:f1834a63f7c1	16	* - Configuration section that allows to select:
Sergunb	0:f1834a63f7c1	17	* - The device used in the target application
Sergunb	0:f1834a63f7c1	18	* - To use or not the peripherals drivers in application code(i.e.
Sergunb	0:f1834a63f7c1	19	* code will be based on direct access to peripherals registers
Sergunb	0:f1834a63f7c1	20	* rather than drivers API), this option is controlled by
Sergunb	0:f1834a63f7c1	21	* "#define USE_STDPERIPH_DRIVER"
Sergunb	0:f1834a63f7c1	22	* - To change few application-specific parameters such as the HSE
Sergunb	0:f1834a63f7c1	23	* crystal frequency
Sergunb	0:f1834a63f7c1	24	* - Data structures and the address mapping for all peripherals
Sergunb	0:f1834a63f7c1	25	* - Peripheral's registers declarations and bits definition
Sergunb	0:f1834a63f7c1	26	* - Macros to access peripherals registers hardware
Sergunb	0:f1834a63f7c1	27	*
Sergunb	0:f1834a63f7c1	28	******************************************************************************
Sergunb	0:f1834a63f7c1	29	* @attention
Sergunb	0:f1834a63f7c1	30	*
Sergunb	0:f1834a63f7c1	31	* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
Sergunb	0:f1834a63f7c1	32	* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
Sergunb	0:f1834a63f7c1	33	* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
Sergunb	0:f1834a63f7c1	34	* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
Sergunb	0:f1834a63f7c1	35	* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
Sergunb	0:f1834a63f7c1	36	* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
Sergunb	0:f1834a63f7c1	37	*
Sergunb	0:f1834a63f7c1	38	* <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
Sergunb	0:f1834a63f7c1	39	******************************************************************************
Sergunb	0:f1834a63f7c1	40	*/
Sergunb	0:f1834a63f7c1	41
Sergunb	0:f1834a63f7c1	42	/** @addtogroup CMSIS
Sergunb	0:f1834a63f7c1	43	* @{
Sergunb	0:f1834a63f7c1	44	*/
Sergunb	0:f1834a63f7c1	45
Sergunb	0:f1834a63f7c1	46	/** @addtogroup stm32f10x
Sergunb	0:f1834a63f7c1	47	* @{
Sergunb	0:f1834a63f7c1	48	*/
Sergunb	0:f1834a63f7c1	49
Sergunb	0:f1834a63f7c1	50	#ifndef __STM32F10x_H
Sergunb	0:f1834a63f7c1	51	#define __STM32F10x_H
Sergunb	0:f1834a63f7c1	52
Sergunb	0:f1834a63f7c1	53	#ifdef __cplusplus
Sergunb	0:f1834a63f7c1	54	extern "C" {
Sergunb	0:f1834a63f7c1	55	#endif
Sergunb	0:f1834a63f7c1	56
Sergunb	0:f1834a63f7c1	57	/** @addtogroup Library_configuration_section
Sergunb	0:f1834a63f7c1	58	* @{
Sergunb	0:f1834a63f7c1	59	*/
Sergunb	0:f1834a63f7c1	60
Sergunb	0:f1834a63f7c1	61	/* Uncomment the line below according to the target STM32 device used in your
Sergunb	0:f1834a63f7c1	62	application
Sergunb	0:f1834a63f7c1	63	*/
Sergunb	0:f1834a63f7c1	64
Sergunb	0:f1834a63f7c1	65	#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
Sergunb	0:f1834a63f7c1	66	/* #define STM32F10X_LD / /!< STM32F10X_LD: STM32 Low density devices */
Sergunb	0:f1834a63f7c1	67	/* #define STM32F10X_LD_VL / /!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
Sergunb	0:f1834a63f7c1	68	/* #define STM32F10X_MD / /!< STM32F10X_MD: STM32 Medium density devices */
Sergunb	0:f1834a63f7c1	69	/* #define STM32F10X_MD_VL / /!< STM32F10X_MD_VL: STM32 Medium density Value Line devices */
Sergunb	0:f1834a63f7c1	70	/* #define STM32F10X_HD / /!< STM32F10X_HD: STM32 High density devices */
Sergunb	0:f1834a63f7c1	71	/* #define STM32F10X_HD_VL / /!< STM32F10X_HD_VL: STM32 High density value line devices */
Sergunb	0:f1834a63f7c1	72	/* #define STM32F10X_XL / /!< STM32F10X_XL: STM32 XL-density devices */
Sergunb	0:f1834a63f7c1	73	/* #define STM32F10X_CL / /!< STM32F10X_CL: STM32 Connectivity line devices */
Sergunb	0:f1834a63f7c1	74	#endif
Sergunb	0:f1834a63f7c1	75	/* Tip: To avoid modifying this file each time you need to switch between these
Sergunb	0:f1834a63f7c1	76	devices, you can define the device in your toolchain compiler preprocessor.
Sergunb	0:f1834a63f7c1	77
Sergunb	0:f1834a63f7c1	78	- Low-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
Sergunb	0:f1834a63f7c1	79	where the Flash memory density ranges between 16 and 32 Kbytes.
Sergunb	0:f1834a63f7c1	80	- Low-density value line devices are STM32F100xx microcontrollers where the Flash
Sergunb	0:f1834a63f7c1	81	memory density ranges between 16 and 32 Kbytes.
Sergunb	0:f1834a63f7c1	82	- Medium-density devices are STM32F101xx, STM32F102xx and STM32F103xx microcontrollers
Sergunb	0:f1834a63f7c1	83	where the Flash memory density ranges between 64 and 128 Kbytes.
Sergunb	0:f1834a63f7c1	84	- Medium-density value line devices are STM32F100xx microcontrollers where the
Sergunb	0:f1834a63f7c1	85	Flash memory density ranges between 64 and 128 Kbytes.
Sergunb	0:f1834a63f7c1	86	- High-density devices are STM32F101xx and STM32F103xx microcontrollers where
Sergunb	0:f1834a63f7c1	87	the Flash memory density ranges between 256 and 512 Kbytes.
Sergunb	0:f1834a63f7c1	88	- High-density value line devices are STM32F100xx microcontrollers where the
Sergunb	0:f1834a63f7c1	89	Flash memory density ranges between 256 and 512 Kbytes.
Sergunb	0:f1834a63f7c1	90	- XL-density devices are STM32F101xx and STM32F103xx microcontrollers where
Sergunb	0:f1834a63f7c1	91	the Flash memory density ranges between 512 and 1024 Kbytes.
Sergunb	0:f1834a63f7c1	92	- Connectivity line devices are STM32F105xx and STM32F107xx microcontrollers.
Sergunb	0:f1834a63f7c1	93	*/
Sergunb	0:f1834a63f7c1	94
Sergunb	0:f1834a63f7c1	95	#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
Sergunb	0:f1834a63f7c1	96	#error "Please select first the target STM32F10x device used in your application (in stm32f10x.h file)"
Sergunb	0:f1834a63f7c1	97	#endif
Sergunb	0:f1834a63f7c1	98
Sergunb	0:f1834a63f7c1	99	#if !defined USE_STDPERIPH_DRIVER
Sergunb	0:f1834a63f7c1	100	/**
Sergunb	0:f1834a63f7c1	101	* @brief Comment the line below if you will not use the peripherals drivers.
Sergunb	0:f1834a63f7c1	102	In this case, these drivers will not be included and the application code will
Sergunb	0:f1834a63f7c1	103	be based on direct access to peripherals registers
Sergunb	0:f1834a63f7c1	104	*/
Sergunb	0:f1834a63f7c1	105	/#define USE_STDPERIPH_DRIVER/
Sergunb	0:f1834a63f7c1	106	#endif
Sergunb	0:f1834a63f7c1	107
Sergunb	0:f1834a63f7c1	108	/**
Sergunb	0:f1834a63f7c1	109	* @brief In the following line adjust the value of External High Speed oscillator (HSE)
Sergunb	0:f1834a63f7c1	110	used in your application
Sergunb	0:f1834a63f7c1	111
Sergunb	0:f1834a63f7c1	112	Tip: To avoid modifying this file each time you need to use different HSE, you
Sergunb	0:f1834a63f7c1	113	can define the HSE value in your toolchain compiler preprocessor.
Sergunb	0:f1834a63f7c1	114	*/
Sergunb	0:f1834a63f7c1	115	#if !defined HSE_VALUE
Sergunb	0:f1834a63f7c1	116	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	117	#define HSE_VALUE ((uint32_t)25000000) /!< Value of the External oscillator in Hz /
Sergunb	0:f1834a63f7c1	118	#else
Sergunb	0:f1834a63f7c1	119	#define HSE_VALUE ((uint32_t)8000000) /!< Value of the External oscillator in Hz /
Sergunb	0:f1834a63f7c1	120	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	121	#endif /* HSE_VALUE */
Sergunb	0:f1834a63f7c1	122
Sergunb	0:f1834a63f7c1	123
Sergunb	0:f1834a63f7c1	124	/**
Sergunb	0:f1834a63f7c1	125	* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
Sergunb	0:f1834a63f7c1	126	Timeout value
Sergunb	0:f1834a63f7c1	127	*/
Sergunb	0:f1834a63f7c1	128	#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /!< Time out for HSE start up /
Sergunb	0:f1834a63f7c1	129
Sergunb	0:f1834a63f7c1	130	#define HSI_VALUE ((uint32_t)8000000) /!< Value of the Internal oscillator in Hz/
Sergunb	0:f1834a63f7c1	131
Sergunb	0:f1834a63f7c1	132	/**
Sergunb	0:f1834a63f7c1	133	* @brief STM32F10x Standard Peripheral Library version number
Sergunb	0:f1834a63f7c1	134	*/
Sergunb	0:f1834a63f7c1	135	#define __STM32F10X_STDPERIPH_VERSION_MAIN (0x03) /!< [31:24] main version /
Sergunb	0:f1834a63f7c1	136	#define __STM32F10X_STDPERIPH_VERSION_SUB1 (0x05) /!< [23:16] sub1 version /
Sergunb	0:f1834a63f7c1	137	#define __STM32F10X_STDPERIPH_VERSION_SUB2 (0x00) /!< [15:8] sub2 version /
Sergunb	0:f1834a63f7c1	138	#define __STM32F10X_STDPERIPH_VERSION_RC (0x00) /!< [7:0] release candidate /
Sergunb	0:f1834a63f7c1	139	#define __STM32F10X_STDPERIPH_VERSION ( (__STM32F10X_STDPERIPH_VERSION_MAIN << 24)\
Sergunb	0:f1834a63f7c1	140	\|(__STM32F10X_STDPERIPH_VERSION_SUB1 << 16)\
Sergunb	0:f1834a63f7c1	141	\|(__STM32F10X_STDPERIPH_VERSION_SUB2 << 8)\
Sergunb	0:f1834a63f7c1	142	\|(__STM32F10X_STDPERIPH_VERSION_RC))
Sergunb	0:f1834a63f7c1	143
Sergunb	0:f1834a63f7c1	144	/**
Sergunb	0:f1834a63f7c1	145	* @}
Sergunb	0:f1834a63f7c1	146	*/
Sergunb	0:f1834a63f7c1	147
Sergunb	0:f1834a63f7c1	148	/** @addtogroup Configuration_section_for_CMSIS
Sergunb	0:f1834a63f7c1	149	* @{
Sergunb	0:f1834a63f7c1	150	*/
Sergunb	0:f1834a63f7c1	151
Sergunb	0:f1834a63f7c1	152	/**
Sergunb	0:f1834a63f7c1	153	* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
Sergunb	0:f1834a63f7c1	154	*/
Sergunb	0:f1834a63f7c1	155	#ifdef STM32F10X_XL
Sergunb	0:f1834a63f7c1	156	#define __MPU_PRESENT 1 /!< STM32 XL-density devices provide an MPU /
Sergunb	0:f1834a63f7c1	157	#else
Sergunb	0:f1834a63f7c1	158	#define __MPU_PRESENT 0 /!< Other STM32 devices does not provide an MPU /
Sergunb	0:f1834a63f7c1	159	#endif /* STM32F10X_XL */
Sergunb	0:f1834a63f7c1	160	#define __NVIC_PRIO_BITS 4 /!< STM32 uses 4 Bits for the Priority Levels /
Sergunb	0:f1834a63f7c1	161	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Sergunb	0:f1834a63f7c1	162
Sergunb	0:f1834a63f7c1	163	/**
Sergunb	0:f1834a63f7c1	164	* @brief STM32F10x Interrupt Number Definition, according to the selected device
Sergunb	0:f1834a63f7c1	165	* in @ref Library_configuration_section
Sergunb	0:f1834a63f7c1	166	*/
Sergunb	0:f1834a63f7c1	167	typedef enum IRQn
Sergunb	0:f1834a63f7c1	168	{
Sergunb	0:f1834a63f7c1	169	/**** Cortex-M3 Processor Exceptions Numbers *************************************************/
Sergunb	0:f1834a63f7c1	170	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
Sergunb	0:f1834a63f7c1	171	MemoryManagement_IRQn = -12, /!< 4 Cortex-M3 Memory Management Interrupt /
Sergunb	0:f1834a63f7c1	172	BusFault_IRQn = -11, /!< 5 Cortex-M3 Bus Fault Interrupt /
Sergunb	0:f1834a63f7c1	173	UsageFault_IRQn = -10, /!< 6 Cortex-M3 Usage Fault Interrupt /
Sergunb	0:f1834a63f7c1	174	SVCall_IRQn = -5, /!< 11 Cortex-M3 SV Call Interrupt /
Sergunb	0:f1834a63f7c1	175	DebugMonitor_IRQn = -4, /!< 12 Cortex-M3 Debug Monitor Interrupt /
Sergunb	0:f1834a63f7c1	176	PendSV_IRQn = -2, /!< 14 Cortex-M3 Pend SV Interrupt /
Sergunb	0:f1834a63f7c1	177	SysTick_IRQn = -1, /!< 15 Cortex-M3 System Tick Interrupt /
Sergunb	0:f1834a63f7c1	178
Sergunb	0:f1834a63f7c1	179	/**** STM32 specific Interrupt Numbers *******************************************************/
Sergunb	0:f1834a63f7c1	180	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
Sergunb	0:f1834a63f7c1	181	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
Sergunb	0:f1834a63f7c1	182	TAMPER_IRQn = 2, /!< Tamper Interrupt /
Sergunb	0:f1834a63f7c1	183	RTC_IRQn = 3, /!< RTC global Interrupt /
Sergunb	0:f1834a63f7c1	184	FLASH_IRQn = 4, /!< FLASH global Interrupt /
Sergunb	0:f1834a63f7c1	185	RCC_IRQn = 5, /!< RCC global Interrupt /
Sergunb	0:f1834a63f7c1	186	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
Sergunb	0:f1834a63f7c1	187	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
Sergunb	0:f1834a63f7c1	188	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
Sergunb	0:f1834a63f7c1	189	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
Sergunb	0:f1834a63f7c1	190	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
Sergunb	0:f1834a63f7c1	191	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 global Interrupt /
Sergunb	0:f1834a63f7c1	192	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 global Interrupt /
Sergunb	0:f1834a63f7c1	193	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 global Interrupt /
Sergunb	0:f1834a63f7c1	194	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 global Interrupt /
Sergunb	0:f1834a63f7c1	195	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 global Interrupt /
Sergunb	0:f1834a63f7c1	196	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 global Interrupt /
Sergunb	0:f1834a63f7c1	197	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 global Interrupt /
Sergunb	0:f1834a63f7c1	198
Sergunb	0:f1834a63f7c1	199	#ifdef STM32F10X_LD
Sergunb	0:f1834a63f7c1	200	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
Sergunb	0:f1834a63f7c1	201	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
Sergunb	0:f1834a63f7c1	202	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
Sergunb	0:f1834a63f7c1	203	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
Sergunb	0:f1834a63f7c1	204	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
Sergunb	0:f1834a63f7c1	205	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Sergunb	0:f1834a63f7c1	206	TIM1_BRK_IRQn = 24, /!< TIM1 Break Interrupt /
Sergunb	0:f1834a63f7c1	207	TIM1_UP_IRQn = 25, /!< TIM1 Update Interrupt /
Sergunb	0:f1834a63f7c1	208	TIM1_TRG_COM_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt /
Sergunb	0:f1834a63f7c1	209	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	210	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Sergunb	0:f1834a63f7c1	211	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Sergunb	0:f1834a63f7c1	212	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Sergunb	0:f1834a63f7c1	213	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Sergunb	0:f1834a63f7c1	214	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Sergunb	0:f1834a63f7c1	215	USART1_IRQn = 37, /!< USART1 global Interrupt /
Sergunb	0:f1834a63f7c1	216	USART2_IRQn = 38, /!< USART2 global Interrupt /
Sergunb	0:f1834a63f7c1	217	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Sergunb	0:f1834a63f7c1	218	RTCAlarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	219	USBWakeUp_IRQn = 42 /!< USB Device WakeUp from suspend through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	220	#endif /* STM32F10X_LD */
Sergunb	0:f1834a63f7c1	221
Sergunb	0:f1834a63f7c1	222	#ifdef STM32F10X_LD_VL
Sergunb	0:f1834a63f7c1	223	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
Sergunb	0:f1834a63f7c1	224	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Sergunb	0:f1834a63f7c1	225	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
Sergunb	0:f1834a63f7c1	226	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
Sergunb	0:f1834a63f7c1	227	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
Sergunb	0:f1834a63f7c1	228	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	229	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Sergunb	0:f1834a63f7c1	230	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Sergunb	0:f1834a63f7c1	231	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Sergunb	0:f1834a63f7c1	232	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Sergunb	0:f1834a63f7c1	233	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Sergunb	0:f1834a63f7c1	234	USART1_IRQn = 37, /!< USART1 global Interrupt /
Sergunb	0:f1834a63f7c1	235	USART2_IRQn = 38, /!< USART2 global Interrupt /
Sergunb	0:f1834a63f7c1	236	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Sergunb	0:f1834a63f7c1	237	RTCAlarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	238	CEC_IRQn = 42, /!< HDMI-CEC Interrupt /
Sergunb	0:f1834a63f7c1	239	TIM6_DAC_IRQn = 54, /!< TIM6 and DAC underrun Interrupt /
Sergunb	0:f1834a63f7c1	240	TIM7_IRQn = 55 /!< TIM7 Interrupt /
Sergunb	0:f1834a63f7c1	241	#endif /* STM32F10X_LD_VL */
Sergunb	0:f1834a63f7c1	242
Sergunb	0:f1834a63f7c1	243	#ifdef STM32F10X_MD
Sergunb	0:f1834a63f7c1	244	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
Sergunb	0:f1834a63f7c1	245	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
Sergunb	0:f1834a63f7c1	246	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
Sergunb	0:f1834a63f7c1	247	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
Sergunb	0:f1834a63f7c1	248	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
Sergunb	0:f1834a63f7c1	249	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Sergunb	0:f1834a63f7c1	250	TIM1_BRK_IRQn = 24, /!< TIM1 Break Interrupt /
Sergunb	0:f1834a63f7c1	251	TIM1_UP_IRQn = 25, /!< TIM1 Update Interrupt /
Sergunb	0:f1834a63f7c1	252	TIM1_TRG_COM_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt /
Sergunb	0:f1834a63f7c1	253	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	254	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Sergunb	0:f1834a63f7c1	255	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Sergunb	0:f1834a63f7c1	256	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Sergunb	0:f1834a63f7c1	257	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Sergunb	0:f1834a63f7c1	258	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Sergunb	0:f1834a63f7c1	259	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Sergunb	0:f1834a63f7c1	260	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Sergunb	0:f1834a63f7c1	261	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Sergunb	0:f1834a63f7c1	262	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Sergunb	0:f1834a63f7c1	263	USART1_IRQn = 37, /!< USART1 global Interrupt /
Sergunb	0:f1834a63f7c1	264	USART2_IRQn = 38, /!< USART2 global Interrupt /
Sergunb	0:f1834a63f7c1	265	USART3_IRQn = 39, /!< USART3 global Interrupt /
Sergunb	0:f1834a63f7c1	266	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Sergunb	0:f1834a63f7c1	267	RTCAlarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	268	USBWakeUp_IRQn = 42 /!< USB Device WakeUp from suspend through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	269	#endif /* STM32F10X_MD */
Sergunb	0:f1834a63f7c1	270
Sergunb	0:f1834a63f7c1	271	#ifdef STM32F10X_MD_VL
Sergunb	0:f1834a63f7c1	272	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
Sergunb	0:f1834a63f7c1	273	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Sergunb	0:f1834a63f7c1	274	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
Sergunb	0:f1834a63f7c1	275	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
Sergunb	0:f1834a63f7c1	276	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
Sergunb	0:f1834a63f7c1	277	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	278	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Sergunb	0:f1834a63f7c1	279	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Sergunb	0:f1834a63f7c1	280	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Sergunb	0:f1834a63f7c1	281	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Sergunb	0:f1834a63f7c1	282	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Sergunb	0:f1834a63f7c1	283	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Sergunb	0:f1834a63f7c1	284	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Sergunb	0:f1834a63f7c1	285	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Sergunb	0:f1834a63f7c1	286	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Sergunb	0:f1834a63f7c1	287	USART1_IRQn = 37, /!< USART1 global Interrupt /
Sergunb	0:f1834a63f7c1	288	USART2_IRQn = 38, /!< USART2 global Interrupt /
Sergunb	0:f1834a63f7c1	289	USART3_IRQn = 39, /!< USART3 global Interrupt /
Sergunb	0:f1834a63f7c1	290	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Sergunb	0:f1834a63f7c1	291	RTCAlarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	292	CEC_IRQn = 42, /!< HDMI-CEC Interrupt /
Sergunb	0:f1834a63f7c1	293	TIM6_DAC_IRQn = 54, /!< TIM6 and DAC underrun Interrupt /
Sergunb	0:f1834a63f7c1	294	TIM7_IRQn = 55 /!< TIM7 Interrupt /
Sergunb	0:f1834a63f7c1	295	#endif /* STM32F10X_MD_VL */
Sergunb	0:f1834a63f7c1	296
Sergunb	0:f1834a63f7c1	297	#ifdef STM32F10X_HD
Sergunb	0:f1834a63f7c1	298	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
Sergunb	0:f1834a63f7c1	299	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
Sergunb	0:f1834a63f7c1	300	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
Sergunb	0:f1834a63f7c1	301	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
Sergunb	0:f1834a63f7c1	302	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
Sergunb	0:f1834a63f7c1	303	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Sergunb	0:f1834a63f7c1	304	TIM1_BRK_IRQn = 24, /!< TIM1 Break Interrupt /
Sergunb	0:f1834a63f7c1	305	TIM1_UP_IRQn = 25, /!< TIM1 Update Interrupt /
Sergunb	0:f1834a63f7c1	306	TIM1_TRG_COM_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt /
Sergunb	0:f1834a63f7c1	307	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	308	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Sergunb	0:f1834a63f7c1	309	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Sergunb	0:f1834a63f7c1	310	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Sergunb	0:f1834a63f7c1	311	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Sergunb	0:f1834a63f7c1	312	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Sergunb	0:f1834a63f7c1	313	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Sergunb	0:f1834a63f7c1	314	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Sergunb	0:f1834a63f7c1	315	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Sergunb	0:f1834a63f7c1	316	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Sergunb	0:f1834a63f7c1	317	USART1_IRQn = 37, /!< USART1 global Interrupt /
Sergunb	0:f1834a63f7c1	318	USART2_IRQn = 38, /!< USART2 global Interrupt /
Sergunb	0:f1834a63f7c1	319	USART3_IRQn = 39, /!< USART3 global Interrupt /
Sergunb	0:f1834a63f7c1	320	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Sergunb	0:f1834a63f7c1	321	RTCAlarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	322	USBWakeUp_IRQn = 42, /!< USB Device WakeUp from suspend through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	323	TIM8_BRK_IRQn = 43, /!< TIM8 Break Interrupt /
Sergunb	0:f1834a63f7c1	324	TIM8_UP_IRQn = 44, /!< TIM8 Update Interrupt /
Sergunb	0:f1834a63f7c1	325	TIM8_TRG_COM_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt /
Sergunb	0:f1834a63f7c1	326	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	327	ADC3_IRQn = 47, /!< ADC3 global Interrupt /
Sergunb	0:f1834a63f7c1	328	FSMC_IRQn = 48, /!< FSMC global Interrupt /
Sergunb	0:f1834a63f7c1	329	SDIO_IRQn = 49, /!< SDIO global Interrupt /
Sergunb	0:f1834a63f7c1	330	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
Sergunb	0:f1834a63f7c1	331	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
Sergunb	0:f1834a63f7c1	332	UART4_IRQn = 52, /!< UART4 global Interrupt /
Sergunb	0:f1834a63f7c1	333	UART5_IRQn = 53, /!< UART5 global Interrupt /
Sergunb	0:f1834a63f7c1	334	TIM6_IRQn = 54, /!< TIM6 global Interrupt /
Sergunb	0:f1834a63f7c1	335	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
Sergunb	0:f1834a63f7c1	336	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
Sergunb	0:f1834a63f7c1	337	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
Sergunb	0:f1834a63f7c1	338	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
Sergunb	0:f1834a63f7c1	339	DMA2_Channel4_5_IRQn = 59 /!< DMA2 Channel 4 and Channel 5 global Interrupt /
Sergunb	0:f1834a63f7c1	340	#endif /* STM32F10X_HD */
Sergunb	0:f1834a63f7c1	341
Sergunb	0:f1834a63f7c1	342	#ifdef STM32F10X_HD_VL
Sergunb	0:f1834a63f7c1	343	ADC1_IRQn = 18, /!< ADC1 global Interrupt /
Sergunb	0:f1834a63f7c1	344	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Sergunb	0:f1834a63f7c1	345	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
Sergunb	0:f1834a63f7c1	346	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
Sergunb	0:f1834a63f7c1	347	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
Sergunb	0:f1834a63f7c1	348	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	349	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Sergunb	0:f1834a63f7c1	350	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Sergunb	0:f1834a63f7c1	351	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Sergunb	0:f1834a63f7c1	352	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Sergunb	0:f1834a63f7c1	353	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Sergunb	0:f1834a63f7c1	354	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Sergunb	0:f1834a63f7c1	355	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Sergunb	0:f1834a63f7c1	356	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Sergunb	0:f1834a63f7c1	357	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Sergunb	0:f1834a63f7c1	358	USART1_IRQn = 37, /!< USART1 global Interrupt /
Sergunb	0:f1834a63f7c1	359	USART2_IRQn = 38, /!< USART2 global Interrupt /
Sergunb	0:f1834a63f7c1	360	USART3_IRQn = 39, /!< USART3 global Interrupt /
Sergunb	0:f1834a63f7c1	361	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Sergunb	0:f1834a63f7c1	362	RTCAlarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	363	CEC_IRQn = 42, /!< HDMI-CEC Interrupt /
Sergunb	0:f1834a63f7c1	364	TIM12_IRQn = 43, /!< TIM12 global Interrupt /
Sergunb	0:f1834a63f7c1	365	TIM13_IRQn = 44, /!< TIM13 global Interrupt /
Sergunb	0:f1834a63f7c1	366	TIM14_IRQn = 45, /!< TIM14 global Interrupt /
Sergunb	0:f1834a63f7c1	367	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
Sergunb	0:f1834a63f7c1	368	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
Sergunb	0:f1834a63f7c1	369	UART4_IRQn = 52, /!< UART4 global Interrupt /
Sergunb	0:f1834a63f7c1	370	UART5_IRQn = 53, /!< UART5 global Interrupt /
Sergunb	0:f1834a63f7c1	371	TIM6_DAC_IRQn = 54, /!< TIM6 and DAC underrun Interrupt /
Sergunb	0:f1834a63f7c1	372	TIM7_IRQn = 55, /!< TIM7 Interrupt /
Sergunb	0:f1834a63f7c1	373	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
Sergunb	0:f1834a63f7c1	374	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
Sergunb	0:f1834a63f7c1	375	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
Sergunb	0:f1834a63f7c1	376	DMA2_Channel4_5_IRQn = 59, /!< DMA2 Channel 4 and Channel 5 global Interrupt /
Sergunb	0:f1834a63f7c1	377	DMA2_Channel5_IRQn = 60 /*!< DMA2 Channel 5 global Interrupt (DMA2 Channel 5 is
Sergunb	0:f1834a63f7c1	378	mapped at position 60 only if the MISC_REMAP bit in
Sergunb	0:f1834a63f7c1	379	the AFIO_MAPR2 register is set) */
Sergunb	0:f1834a63f7c1	380	#endif /* STM32F10X_HD_VL */
Sergunb	0:f1834a63f7c1	381
Sergunb	0:f1834a63f7c1	382	#ifdef STM32F10X_XL
Sergunb	0:f1834a63f7c1	383	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
Sergunb	0:f1834a63f7c1	384	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
Sergunb	0:f1834a63f7c1	385	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
Sergunb	0:f1834a63f7c1	386	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
Sergunb	0:f1834a63f7c1	387	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
Sergunb	0:f1834a63f7c1	388	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Sergunb	0:f1834a63f7c1	389	TIM1_BRK_TIM9_IRQn = 24, /!< TIM1 Break Interrupt and TIM9 global Interrupt /
Sergunb	0:f1834a63f7c1	390	TIM1_UP_TIM10_IRQn = 25, /!< TIM1 Update Interrupt and TIM10 global Interrupt /
Sergunb	0:f1834a63f7c1	391	TIM1_TRG_COM_TIM11_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt /
Sergunb	0:f1834a63f7c1	392	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	393	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Sergunb	0:f1834a63f7c1	394	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Sergunb	0:f1834a63f7c1	395	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Sergunb	0:f1834a63f7c1	396	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Sergunb	0:f1834a63f7c1	397	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Sergunb	0:f1834a63f7c1	398	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Sergunb	0:f1834a63f7c1	399	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Sergunb	0:f1834a63f7c1	400	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Sergunb	0:f1834a63f7c1	401	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Sergunb	0:f1834a63f7c1	402	USART1_IRQn = 37, /!< USART1 global Interrupt /
Sergunb	0:f1834a63f7c1	403	USART2_IRQn = 38, /!< USART2 global Interrupt /
Sergunb	0:f1834a63f7c1	404	USART3_IRQn = 39, /!< USART3 global Interrupt /
Sergunb	0:f1834a63f7c1	405	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Sergunb	0:f1834a63f7c1	406	RTCAlarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	407	USBWakeUp_IRQn = 42, /!< USB Device WakeUp from suspend through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	408	TIM8_BRK_TIM12_IRQn = 43, /!< TIM8 Break Interrupt and TIM12 global Interrupt /
Sergunb	0:f1834a63f7c1	409	TIM8_UP_TIM13_IRQn = 44, /!< TIM8 Update Interrupt and TIM13 global Interrupt /
Sergunb	0:f1834a63f7c1	410	TIM8_TRG_COM_TIM14_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt /
Sergunb	0:f1834a63f7c1	411	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	412	ADC3_IRQn = 47, /!< ADC3 global Interrupt /
Sergunb	0:f1834a63f7c1	413	FSMC_IRQn = 48, /!< FSMC global Interrupt /
Sergunb	0:f1834a63f7c1	414	SDIO_IRQn = 49, /!< SDIO global Interrupt /
Sergunb	0:f1834a63f7c1	415	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
Sergunb	0:f1834a63f7c1	416	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
Sergunb	0:f1834a63f7c1	417	UART4_IRQn = 52, /!< UART4 global Interrupt /
Sergunb	0:f1834a63f7c1	418	UART5_IRQn = 53, /!< UART5 global Interrupt /
Sergunb	0:f1834a63f7c1	419	TIM6_IRQn = 54, /!< TIM6 global Interrupt /
Sergunb	0:f1834a63f7c1	420	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
Sergunb	0:f1834a63f7c1	421	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
Sergunb	0:f1834a63f7c1	422	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
Sergunb	0:f1834a63f7c1	423	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
Sergunb	0:f1834a63f7c1	424	DMA2_Channel4_5_IRQn = 59 /!< DMA2 Channel 4 and Channel 5 global Interrupt /
Sergunb	0:f1834a63f7c1	425	#endif /* STM32F10X_XL */
Sergunb	0:f1834a63f7c1	426
Sergunb	0:f1834a63f7c1	427	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	428	ADC1_2_IRQn = 18, /!< ADC1 and ADC2 global Interrupt /
Sergunb	0:f1834a63f7c1	429	CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
Sergunb	0:f1834a63f7c1	430	CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
Sergunb	0:f1834a63f7c1	431	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
Sergunb	0:f1834a63f7c1	432	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
Sergunb	0:f1834a63f7c1	433	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Sergunb	0:f1834a63f7c1	434	TIM1_BRK_IRQn = 24, /!< TIM1 Break Interrupt /
Sergunb	0:f1834a63f7c1	435	TIM1_UP_IRQn = 25, /!< TIM1 Update Interrupt /
Sergunb	0:f1834a63f7c1	436	TIM1_TRG_COM_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt /
Sergunb	0:f1834a63f7c1	437	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Sergunb	0:f1834a63f7c1	438	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Sergunb	0:f1834a63f7c1	439	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Sergunb	0:f1834a63f7c1	440	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Sergunb	0:f1834a63f7c1	441	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Sergunb	0:f1834a63f7c1	442	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Sergunb	0:f1834a63f7c1	443	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Sergunb	0:f1834a63f7c1	444	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Sergunb	0:f1834a63f7c1	445	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Sergunb	0:f1834a63f7c1	446	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Sergunb	0:f1834a63f7c1	447	USART1_IRQn = 37, /!< USART1 global Interrupt /
Sergunb	0:f1834a63f7c1	448	USART2_IRQn = 38, /!< USART2 global Interrupt /
Sergunb	0:f1834a63f7c1	449	USART3_IRQn = 39, /!< USART3 global Interrupt /
Sergunb	0:f1834a63f7c1	450	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Sergunb	0:f1834a63f7c1	451	RTCAlarm_IRQn = 41, /!< RTC Alarm through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	452	OTG_FS_WKUP_IRQn = 42, /!< USB OTG FS WakeUp from suspend through EXTI Line Interrupt /
Sergunb	0:f1834a63f7c1	453	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
Sergunb	0:f1834a63f7c1	454	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
Sergunb	0:f1834a63f7c1	455	UART4_IRQn = 52, /!< UART4 global Interrupt /
Sergunb	0:f1834a63f7c1	456	UART5_IRQn = 53, /!< UART5 global Interrupt /
Sergunb	0:f1834a63f7c1	457	TIM6_IRQn = 54, /!< TIM6 global Interrupt /
Sergunb	0:f1834a63f7c1	458	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
Sergunb	0:f1834a63f7c1	459	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
Sergunb	0:f1834a63f7c1	460	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
Sergunb	0:f1834a63f7c1	461	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
Sergunb	0:f1834a63f7c1	462	DMA2_Channel4_IRQn = 59, /!< DMA2 Channel 4 global Interrupt /
Sergunb	0:f1834a63f7c1	463	DMA2_Channel5_IRQn = 60, /!< DMA2 Channel 5 global Interrupt /
Sergunb	0:f1834a63f7c1	464	ETH_IRQn = 61, /!< Ethernet global Interrupt /
Sergunb	0:f1834a63f7c1	465	ETH_WKUP_IRQn = 62, /!< Ethernet Wakeup through EXTI line Interrupt /
Sergunb	0:f1834a63f7c1	466	CAN2_TX_IRQn = 63, /!< CAN2 TX Interrupt /
Sergunb	0:f1834a63f7c1	467	CAN2_RX0_IRQn = 64, /!< CAN2 RX0 Interrupt /
Sergunb	0:f1834a63f7c1	468	CAN2_RX1_IRQn = 65, /!< CAN2 RX1 Interrupt /
Sergunb	0:f1834a63f7c1	469	CAN2_SCE_IRQn = 66, /!< CAN2 SCE Interrupt /
Sergunb	0:f1834a63f7c1	470	OTG_FS_IRQn = 67 /!< USB OTG FS global Interrupt /
Sergunb	0:f1834a63f7c1	471	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	472	} IRQn_Type;
Sergunb	0:f1834a63f7c1	473
Sergunb	0:f1834a63f7c1	474	/**
Sergunb	0:f1834a63f7c1	475	* @}
Sergunb	0:f1834a63f7c1	476	*/
Sergunb	0:f1834a63f7c1	477
Sergunb	0:f1834a63f7c1	478	#include "core_cm3.h"
Sergunb	0:f1834a63f7c1	479	#include "system_stm32f10x.h"
Sergunb	0:f1834a63f7c1	480	#include <stdint.h>
Sergunb	0:f1834a63f7c1	481
Sergunb	0:f1834a63f7c1	482	/** @addtogroup Exported_types
Sergunb	0:f1834a63f7c1	483	* @{
Sergunb	0:f1834a63f7c1	484	*/
Sergunb	0:f1834a63f7c1	485
Sergunb	0:f1834a63f7c1	486	/!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) /
Sergunb	0:f1834a63f7c1	487	typedef int32_t s32;
Sergunb	0:f1834a63f7c1	488	typedef int16_t s16;
Sergunb	0:f1834a63f7c1	489	typedef int8_t s8;
Sergunb	0:f1834a63f7c1	490
Sergunb	0:f1834a63f7c1	491	typedef const int32_t sc32; /!< Read Only /
Sergunb	0:f1834a63f7c1	492	typedef const int16_t sc16; /!< Read Only /
Sergunb	0:f1834a63f7c1	493	typedef const int8_t sc8; /!< Read Only /
Sergunb	0:f1834a63f7c1	494
Sergunb	0:f1834a63f7c1	495	typedef __IO int32_t vs32;
Sergunb	0:f1834a63f7c1	496	typedef __IO int16_t vs16;
Sergunb	0:f1834a63f7c1	497	typedef __IO int8_t vs8;
Sergunb	0:f1834a63f7c1	498
Sergunb	0:f1834a63f7c1	499	typedef __I int32_t vsc32; /!< Read Only /
Sergunb	0:f1834a63f7c1	500	typedef __I int16_t vsc16; /!< Read Only /
Sergunb	0:f1834a63f7c1	501	typedef __I int8_t vsc8; /!< Read Only /
Sergunb	0:f1834a63f7c1	502
Sergunb	0:f1834a63f7c1	503	typedef uint32_t u32;
Sergunb	0:f1834a63f7c1	504	typedef uint16_t u16;
Sergunb	0:f1834a63f7c1	505	typedef uint8_t u8;
Sergunb	0:f1834a63f7c1	506
Sergunb	0:f1834a63f7c1	507	typedef const uint32_t uc32; /!< Read Only /
Sergunb	0:f1834a63f7c1	508	typedef const uint16_t uc16; /!< Read Only /
Sergunb	0:f1834a63f7c1	509	typedef const uint8_t uc8; /!< Read Only /
Sergunb	0:f1834a63f7c1	510
Sergunb	0:f1834a63f7c1	511	typedef __IO uint32_t vu32;
Sergunb	0:f1834a63f7c1	512	typedef __IO uint16_t vu16;
Sergunb	0:f1834a63f7c1	513	typedef __IO uint8_t vu8;
Sergunb	0:f1834a63f7c1	514
Sergunb	0:f1834a63f7c1	515	typedef __I uint32_t vuc32; /!< Read Only /
Sergunb	0:f1834a63f7c1	516	typedef __I uint16_t vuc16; /!< Read Only /
Sergunb	0:f1834a63f7c1	517	typedef __I uint8_t vuc8; /!< Read Only /
Sergunb	0:f1834a63f7c1	518
Sergunb	0:f1834a63f7c1	519	typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
Sergunb	0:f1834a63f7c1	520
Sergunb	0:f1834a63f7c1	521	typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
Sergunb	0:f1834a63f7c1	522	#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) \|\| ((STATE) == ENABLE))
Sergunb	0:f1834a63f7c1	523
Sergunb	0:f1834a63f7c1	524	typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
Sergunb	0:f1834a63f7c1	525
Sergunb	0:f1834a63f7c1	526	/!< STM32F10x Standard Peripheral Library old definitions (maintained for legacy purpose) /
Sergunb	0:f1834a63f7c1	527	#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
Sergunb	0:f1834a63f7c1	528	#define HSE_Value HSE_VALUE
Sergunb	0:f1834a63f7c1	529	#define HSI_Value HSI_VALUE
Sergunb	0:f1834a63f7c1	530	/**
Sergunb	0:f1834a63f7c1	531	* @}
Sergunb	0:f1834a63f7c1	532	*/
Sergunb	0:f1834a63f7c1	533
Sergunb	0:f1834a63f7c1	534	/** @addtogroup Peripheral_registers_structures
Sergunb	0:f1834a63f7c1	535	* @{
Sergunb	0:f1834a63f7c1	536	*/
Sergunb	0:f1834a63f7c1	537
Sergunb	0:f1834a63f7c1	538	/**
Sergunb	0:f1834a63f7c1	539	* @brief Analog to Digital Converter
Sergunb	0:f1834a63f7c1	540	*/
Sergunb	0:f1834a63f7c1	541
Sergunb	0:f1834a63f7c1	542	typedef struct
Sergunb	0:f1834a63f7c1	543	{
Sergunb	0:f1834a63f7c1	544	__IO uint32_t SR;
Sergunb	0:f1834a63f7c1	545	__IO uint32_t CR1;
Sergunb	0:f1834a63f7c1	546	__IO uint32_t CR2;
Sergunb	0:f1834a63f7c1	547	__IO uint32_t SMPR1;
Sergunb	0:f1834a63f7c1	548	__IO uint32_t SMPR2;
Sergunb	0:f1834a63f7c1	549	__IO uint32_t JOFR1;
Sergunb	0:f1834a63f7c1	550	__IO uint32_t JOFR2;
Sergunb	0:f1834a63f7c1	551	__IO uint32_t JOFR3;
Sergunb	0:f1834a63f7c1	552	__IO uint32_t JOFR4;
Sergunb	0:f1834a63f7c1	553	__IO uint32_t HTR;
Sergunb	0:f1834a63f7c1	554	__IO uint32_t LTR;
Sergunb	0:f1834a63f7c1	555	__IO uint32_t SQR1;
Sergunb	0:f1834a63f7c1	556	__IO uint32_t SQR2;
Sergunb	0:f1834a63f7c1	557	__IO uint32_t SQR3;
Sergunb	0:f1834a63f7c1	558	__IO uint32_t JSQR;
Sergunb	0:f1834a63f7c1	559	__IO uint32_t JDR1;
Sergunb	0:f1834a63f7c1	560	__IO uint32_t JDR2;
Sergunb	0:f1834a63f7c1	561	__IO uint32_t JDR3;
Sergunb	0:f1834a63f7c1	562	__IO uint32_t JDR4;
Sergunb	0:f1834a63f7c1	563	__IO uint32_t DR;
Sergunb	0:f1834a63f7c1	564	} ADC_TypeDef;
Sergunb	0:f1834a63f7c1	565
Sergunb	0:f1834a63f7c1	566	/**
Sergunb	0:f1834a63f7c1	567	* @brief Backup Registers
Sergunb	0:f1834a63f7c1	568	*/
Sergunb	0:f1834a63f7c1	569
Sergunb	0:f1834a63f7c1	570	typedef struct
Sergunb	0:f1834a63f7c1	571	{
Sergunb	0:f1834a63f7c1	572	uint32_t RESERVED0;
Sergunb	0:f1834a63f7c1	573	__IO uint16_t DR1;
Sergunb	0:f1834a63f7c1	574	uint16_t RESERVED1;
Sergunb	0:f1834a63f7c1	575	__IO uint16_t DR2;
Sergunb	0:f1834a63f7c1	576	uint16_t RESERVED2;
Sergunb	0:f1834a63f7c1	577	__IO uint16_t DR3;
Sergunb	0:f1834a63f7c1	578	uint16_t RESERVED3;
Sergunb	0:f1834a63f7c1	579	__IO uint16_t DR4;
Sergunb	0:f1834a63f7c1	580	uint16_t RESERVED4;
Sergunb	0:f1834a63f7c1	581	__IO uint16_t DR5;
Sergunb	0:f1834a63f7c1	582	uint16_t RESERVED5;
Sergunb	0:f1834a63f7c1	583	__IO uint16_t DR6;
Sergunb	0:f1834a63f7c1	584	uint16_t RESERVED6;
Sergunb	0:f1834a63f7c1	585	__IO uint16_t DR7;
Sergunb	0:f1834a63f7c1	586	uint16_t RESERVED7;
Sergunb	0:f1834a63f7c1	587	__IO uint16_t DR8;
Sergunb	0:f1834a63f7c1	588	uint16_t RESERVED8;
Sergunb	0:f1834a63f7c1	589	__IO uint16_t DR9;
Sergunb	0:f1834a63f7c1	590	uint16_t RESERVED9;
Sergunb	0:f1834a63f7c1	591	__IO uint16_t DR10;
Sergunb	0:f1834a63f7c1	592	uint16_t RESERVED10;
Sergunb	0:f1834a63f7c1	593	__IO uint16_t RTCCR;
Sergunb	0:f1834a63f7c1	594	uint16_t RESERVED11;
Sergunb	0:f1834a63f7c1	595	__IO uint16_t CR;
Sergunb	0:f1834a63f7c1	596	uint16_t RESERVED12;
Sergunb	0:f1834a63f7c1	597	__IO uint16_t CSR;
Sergunb	0:f1834a63f7c1	598	uint16_t RESERVED13[5];
Sergunb	0:f1834a63f7c1	599	__IO uint16_t DR11;
Sergunb	0:f1834a63f7c1	600	uint16_t RESERVED14;
Sergunb	0:f1834a63f7c1	601	__IO uint16_t DR12;
Sergunb	0:f1834a63f7c1	602	uint16_t RESERVED15;
Sergunb	0:f1834a63f7c1	603	__IO uint16_t DR13;
Sergunb	0:f1834a63f7c1	604	uint16_t RESERVED16;
Sergunb	0:f1834a63f7c1	605	__IO uint16_t DR14;
Sergunb	0:f1834a63f7c1	606	uint16_t RESERVED17;
Sergunb	0:f1834a63f7c1	607	__IO uint16_t DR15;
Sergunb	0:f1834a63f7c1	608	uint16_t RESERVED18;
Sergunb	0:f1834a63f7c1	609	__IO uint16_t DR16;
Sergunb	0:f1834a63f7c1	610	uint16_t RESERVED19;
Sergunb	0:f1834a63f7c1	611	__IO uint16_t DR17;
Sergunb	0:f1834a63f7c1	612	uint16_t RESERVED20;
Sergunb	0:f1834a63f7c1	613	__IO uint16_t DR18;
Sergunb	0:f1834a63f7c1	614	uint16_t RESERVED21;
Sergunb	0:f1834a63f7c1	615	__IO uint16_t DR19;
Sergunb	0:f1834a63f7c1	616	uint16_t RESERVED22;
Sergunb	0:f1834a63f7c1	617	__IO uint16_t DR20;
Sergunb	0:f1834a63f7c1	618	uint16_t RESERVED23;
Sergunb	0:f1834a63f7c1	619	__IO uint16_t DR21;
Sergunb	0:f1834a63f7c1	620	uint16_t RESERVED24;
Sergunb	0:f1834a63f7c1	621	__IO uint16_t DR22;
Sergunb	0:f1834a63f7c1	622	uint16_t RESERVED25;
Sergunb	0:f1834a63f7c1	623	__IO uint16_t DR23;
Sergunb	0:f1834a63f7c1	624	uint16_t RESERVED26;
Sergunb	0:f1834a63f7c1	625	__IO uint16_t DR24;
Sergunb	0:f1834a63f7c1	626	uint16_t RESERVED27;
Sergunb	0:f1834a63f7c1	627	__IO uint16_t DR25;
Sergunb	0:f1834a63f7c1	628	uint16_t RESERVED28;
Sergunb	0:f1834a63f7c1	629	__IO uint16_t DR26;
Sergunb	0:f1834a63f7c1	630	uint16_t RESERVED29;
Sergunb	0:f1834a63f7c1	631	__IO uint16_t DR27;
Sergunb	0:f1834a63f7c1	632	uint16_t RESERVED30;
Sergunb	0:f1834a63f7c1	633	__IO uint16_t DR28;
Sergunb	0:f1834a63f7c1	634	uint16_t RESERVED31;
Sergunb	0:f1834a63f7c1	635	__IO uint16_t DR29;
Sergunb	0:f1834a63f7c1	636	uint16_t RESERVED32;
Sergunb	0:f1834a63f7c1	637	__IO uint16_t DR30;
Sergunb	0:f1834a63f7c1	638	uint16_t RESERVED33;
Sergunb	0:f1834a63f7c1	639	__IO uint16_t DR31;
Sergunb	0:f1834a63f7c1	640	uint16_t RESERVED34;
Sergunb	0:f1834a63f7c1	641	__IO uint16_t DR32;
Sergunb	0:f1834a63f7c1	642	uint16_t RESERVED35;
Sergunb	0:f1834a63f7c1	643	__IO uint16_t DR33;
Sergunb	0:f1834a63f7c1	644	uint16_t RESERVED36;
Sergunb	0:f1834a63f7c1	645	__IO uint16_t DR34;
Sergunb	0:f1834a63f7c1	646	uint16_t RESERVED37;
Sergunb	0:f1834a63f7c1	647	__IO uint16_t DR35;
Sergunb	0:f1834a63f7c1	648	uint16_t RESERVED38;
Sergunb	0:f1834a63f7c1	649	__IO uint16_t DR36;
Sergunb	0:f1834a63f7c1	650	uint16_t RESERVED39;
Sergunb	0:f1834a63f7c1	651	__IO uint16_t DR37;
Sergunb	0:f1834a63f7c1	652	uint16_t RESERVED40;
Sergunb	0:f1834a63f7c1	653	__IO uint16_t DR38;
Sergunb	0:f1834a63f7c1	654	uint16_t RESERVED41;
Sergunb	0:f1834a63f7c1	655	__IO uint16_t DR39;
Sergunb	0:f1834a63f7c1	656	uint16_t RESERVED42;
Sergunb	0:f1834a63f7c1	657	__IO uint16_t DR40;
Sergunb	0:f1834a63f7c1	658	uint16_t RESERVED43;
Sergunb	0:f1834a63f7c1	659	__IO uint16_t DR41;
Sergunb	0:f1834a63f7c1	660	uint16_t RESERVED44;
Sergunb	0:f1834a63f7c1	661	__IO uint16_t DR42;
Sergunb	0:f1834a63f7c1	662	uint16_t RESERVED45;
Sergunb	0:f1834a63f7c1	663	} BKP_TypeDef;
Sergunb	0:f1834a63f7c1	664
Sergunb	0:f1834a63f7c1	665	/**
Sergunb	0:f1834a63f7c1	666	* @brief Controller Area Network TxMailBox
Sergunb	0:f1834a63f7c1	667	*/
Sergunb	0:f1834a63f7c1	668
Sergunb	0:f1834a63f7c1	669	typedef struct
Sergunb	0:f1834a63f7c1	670	{
Sergunb	0:f1834a63f7c1	671	__IO uint32_t TIR;
Sergunb	0:f1834a63f7c1	672	__IO uint32_t TDTR;
Sergunb	0:f1834a63f7c1	673	__IO uint32_t TDLR;
Sergunb	0:f1834a63f7c1	674	__IO uint32_t TDHR;
Sergunb	0:f1834a63f7c1	675	} CAN_TxMailBox_TypeDef;
Sergunb	0:f1834a63f7c1	676
Sergunb	0:f1834a63f7c1	677	/**
Sergunb	0:f1834a63f7c1	678	* @brief Controller Area Network FIFOMailBox
Sergunb	0:f1834a63f7c1	679	*/
Sergunb	0:f1834a63f7c1	680
Sergunb	0:f1834a63f7c1	681	typedef struct
Sergunb	0:f1834a63f7c1	682	{
Sergunb	0:f1834a63f7c1	683	__IO uint32_t RIR;
Sergunb	0:f1834a63f7c1	684	__IO uint32_t RDTR;
Sergunb	0:f1834a63f7c1	685	__IO uint32_t RDLR;
Sergunb	0:f1834a63f7c1	686	__IO uint32_t RDHR;
Sergunb	0:f1834a63f7c1	687	} CAN_FIFOMailBox_TypeDef;
Sergunb	0:f1834a63f7c1	688
Sergunb	0:f1834a63f7c1	689	/**
Sergunb	0:f1834a63f7c1	690	* @brief Controller Area Network FilterRegister
Sergunb	0:f1834a63f7c1	691	*/
Sergunb	0:f1834a63f7c1	692
Sergunb	0:f1834a63f7c1	693	typedef struct
Sergunb	0:f1834a63f7c1	694	{
Sergunb	0:f1834a63f7c1	695	__IO uint32_t FR1;
Sergunb	0:f1834a63f7c1	696	__IO uint32_t FR2;
Sergunb	0:f1834a63f7c1	697	} CAN_FilterRegister_TypeDef;
Sergunb	0:f1834a63f7c1	698
Sergunb	0:f1834a63f7c1	699	/**
Sergunb	0:f1834a63f7c1	700	* @brief Controller Area Network
Sergunb	0:f1834a63f7c1	701	*/
Sergunb	0:f1834a63f7c1	702
Sergunb	0:f1834a63f7c1	703	typedef struct
Sergunb	0:f1834a63f7c1	704	{
Sergunb	0:f1834a63f7c1	705	__IO uint32_t MCR;
Sergunb	0:f1834a63f7c1	706	__IO uint32_t MSR;
Sergunb	0:f1834a63f7c1	707	__IO uint32_t TSR;
Sergunb	0:f1834a63f7c1	708	__IO uint32_t RF0R;
Sergunb	0:f1834a63f7c1	709	__IO uint32_t RF1R;
Sergunb	0:f1834a63f7c1	710	__IO uint32_t IER;
Sergunb	0:f1834a63f7c1	711	__IO uint32_t ESR;
Sergunb	0:f1834a63f7c1	712	__IO uint32_t BTR;
Sergunb	0:f1834a63f7c1	713	uint32_t RESERVED0[88];
Sergunb	0:f1834a63f7c1	714	CAN_TxMailBox_TypeDef sTxMailBox[3];
Sergunb	0:f1834a63f7c1	715	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2];
Sergunb	0:f1834a63f7c1	716	uint32_t RESERVED1[12];
Sergunb	0:f1834a63f7c1	717	__IO uint32_t FMR;
Sergunb	0:f1834a63f7c1	718	__IO uint32_t FM1R;
Sergunb	0:f1834a63f7c1	719	uint32_t RESERVED2;
Sergunb	0:f1834a63f7c1	720	__IO uint32_t FS1R;
Sergunb	0:f1834a63f7c1	721	uint32_t RESERVED3;
Sergunb	0:f1834a63f7c1	722	__IO uint32_t FFA1R;
Sergunb	0:f1834a63f7c1	723	uint32_t RESERVED4;
Sergunb	0:f1834a63f7c1	724	__IO uint32_t FA1R;
Sergunb	0:f1834a63f7c1	725	uint32_t RESERVED5[8];
Sergunb	0:f1834a63f7c1	726	#ifndef STM32F10X_CL
Sergunb	0:f1834a63f7c1	727	CAN_FilterRegister_TypeDef sFilterRegister[14];
Sergunb	0:f1834a63f7c1	728	#else
Sergunb	0:f1834a63f7c1	729	CAN_FilterRegister_TypeDef sFilterRegister[28];
Sergunb	0:f1834a63f7c1	730	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	731	} CAN_TypeDef;
Sergunb	0:f1834a63f7c1	732
Sergunb	0:f1834a63f7c1	733	/**
Sergunb	0:f1834a63f7c1	734	* @brief Consumer Electronics Control (CEC)
Sergunb	0:f1834a63f7c1	735	*/
Sergunb	0:f1834a63f7c1	736	typedef struct
Sergunb	0:f1834a63f7c1	737	{
Sergunb	0:f1834a63f7c1	738	__IO uint32_t CFGR;
Sergunb	0:f1834a63f7c1	739	__IO uint32_t OAR;
Sergunb	0:f1834a63f7c1	740	__IO uint32_t PRES;
Sergunb	0:f1834a63f7c1	741	__IO uint32_t ESR;
Sergunb	0:f1834a63f7c1	742	__IO uint32_t CSR;
Sergunb	0:f1834a63f7c1	743	__IO uint32_t TXD;
Sergunb	0:f1834a63f7c1	744	__IO uint32_t RXD;
Sergunb	0:f1834a63f7c1	745	} CEC_TypeDef;
Sergunb	0:f1834a63f7c1	746
Sergunb	0:f1834a63f7c1	747	/**
Sergunb	0:f1834a63f7c1	748	* @brief CRC calculation unit
Sergunb	0:f1834a63f7c1	749	*/
Sergunb	0:f1834a63f7c1	750
Sergunb	0:f1834a63f7c1	751	typedef struct
Sergunb	0:f1834a63f7c1	752	{
Sergunb	0:f1834a63f7c1	753	__IO uint32_t DR;
Sergunb	0:f1834a63f7c1	754	__IO uint8_t IDR;
Sergunb	0:f1834a63f7c1	755	uint8_t RESERVED0;
Sergunb	0:f1834a63f7c1	756	uint16_t RESERVED1;
Sergunb	0:f1834a63f7c1	757	__IO uint32_t CR;
Sergunb	0:f1834a63f7c1	758	} CRC_TypeDef;
Sergunb	0:f1834a63f7c1	759
Sergunb	0:f1834a63f7c1	760	/**
Sergunb	0:f1834a63f7c1	761	* @brief Digital to Analog Converter
Sergunb	0:f1834a63f7c1	762	*/
Sergunb	0:f1834a63f7c1	763
Sergunb	0:f1834a63f7c1	764	typedef struct
Sergunb	0:f1834a63f7c1	765	{
Sergunb	0:f1834a63f7c1	766	__IO uint32_t CR;
Sergunb	0:f1834a63f7c1	767	__IO uint32_t SWTRIGR;
Sergunb	0:f1834a63f7c1	768	__IO uint32_t DHR12R1;
Sergunb	0:f1834a63f7c1	769	__IO uint32_t DHR12L1;
Sergunb	0:f1834a63f7c1	770	__IO uint32_t DHR8R1;
Sergunb	0:f1834a63f7c1	771	__IO uint32_t DHR12R2;
Sergunb	0:f1834a63f7c1	772	__IO uint32_t DHR12L2;
Sergunb	0:f1834a63f7c1	773	__IO uint32_t DHR8R2;
Sergunb	0:f1834a63f7c1	774	__IO uint32_t DHR12RD;
Sergunb	0:f1834a63f7c1	775	__IO uint32_t DHR12LD;
Sergunb	0:f1834a63f7c1	776	__IO uint32_t DHR8RD;
Sergunb	0:f1834a63f7c1	777	__IO uint32_t DOR1;
Sergunb	0:f1834a63f7c1	778	__IO uint32_t DOR2;
Sergunb	0:f1834a63f7c1	779	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	780	__IO uint32_t SR;
Sergunb	0:f1834a63f7c1	781	#endif
Sergunb	0:f1834a63f7c1	782	} DAC_TypeDef;
Sergunb	0:f1834a63f7c1	783
Sergunb	0:f1834a63f7c1	784	/**
Sergunb	0:f1834a63f7c1	785	* @brief Debug MCU
Sergunb	0:f1834a63f7c1	786	*/
Sergunb	0:f1834a63f7c1	787
Sergunb	0:f1834a63f7c1	788	typedef struct
Sergunb	0:f1834a63f7c1	789	{
Sergunb	0:f1834a63f7c1	790	__IO uint32_t IDCODE;
Sergunb	0:f1834a63f7c1	791	__IO uint32_t CR;
Sergunb	0:f1834a63f7c1	792	}DBGMCU_TypeDef;
Sergunb	0:f1834a63f7c1	793
Sergunb	0:f1834a63f7c1	794	/**
Sergunb	0:f1834a63f7c1	795	* @brief DMA Controller
Sergunb	0:f1834a63f7c1	796	*/
Sergunb	0:f1834a63f7c1	797
Sergunb	0:f1834a63f7c1	798	typedef struct
Sergunb	0:f1834a63f7c1	799	{
Sergunb	0:f1834a63f7c1	800	__IO uint32_t CCR;
Sergunb	0:f1834a63f7c1	801	__IO uint32_t CNDTR;
Sergunb	0:f1834a63f7c1	802	__IO uint32_t CPAR;
Sergunb	0:f1834a63f7c1	803	__IO uint32_t CMAR;
Sergunb	0:f1834a63f7c1	804	} DMA_Channel_TypeDef;
Sergunb	0:f1834a63f7c1	805
Sergunb	0:f1834a63f7c1	806	typedef struct
Sergunb	0:f1834a63f7c1	807	{
Sergunb	0:f1834a63f7c1	808	__IO uint32_t ISR;
Sergunb	0:f1834a63f7c1	809	__IO uint32_t IFCR;
Sergunb	0:f1834a63f7c1	810	} DMA_TypeDef;
Sergunb	0:f1834a63f7c1	811
Sergunb	0:f1834a63f7c1	812	/**
Sergunb	0:f1834a63f7c1	813	* @brief Ethernet MAC
Sergunb	0:f1834a63f7c1	814	*/
Sergunb	0:f1834a63f7c1	815
Sergunb	0:f1834a63f7c1	816	typedef struct
Sergunb	0:f1834a63f7c1	817	{
Sergunb	0:f1834a63f7c1	818	__IO uint32_t MACCR;
Sergunb	0:f1834a63f7c1	819	__IO uint32_t MACFFR;
Sergunb	0:f1834a63f7c1	820	__IO uint32_t MACHTHR;
Sergunb	0:f1834a63f7c1	821	__IO uint32_t MACHTLR;
Sergunb	0:f1834a63f7c1	822	__IO uint32_t MACMIIAR;
Sergunb	0:f1834a63f7c1	823	__IO uint32_t MACMIIDR;
Sergunb	0:f1834a63f7c1	824	__IO uint32_t MACFCR;
Sergunb	0:f1834a63f7c1	825	__IO uint32_t MACVLANTR; /* 8 */
Sergunb	0:f1834a63f7c1	826	uint32_t RESERVED0[2];
Sergunb	0:f1834a63f7c1	827	__IO uint32_t MACRWUFFR; /* 11 */
Sergunb	0:f1834a63f7c1	828	__IO uint32_t MACPMTCSR;
Sergunb	0:f1834a63f7c1	829	uint32_t RESERVED1[2];
Sergunb	0:f1834a63f7c1	830	__IO uint32_t MACSR; /* 15 */
Sergunb	0:f1834a63f7c1	831	__IO uint32_t MACIMR;
Sergunb	0:f1834a63f7c1	832	__IO uint32_t MACA0HR;
Sergunb	0:f1834a63f7c1	833	__IO uint32_t MACA0LR;
Sergunb	0:f1834a63f7c1	834	__IO uint32_t MACA1HR;
Sergunb	0:f1834a63f7c1	835	__IO uint32_t MACA1LR;
Sergunb	0:f1834a63f7c1	836	__IO uint32_t MACA2HR;
Sergunb	0:f1834a63f7c1	837	__IO uint32_t MACA2LR;
Sergunb	0:f1834a63f7c1	838	__IO uint32_t MACA3HR;
Sergunb	0:f1834a63f7c1	839	__IO uint32_t MACA3LR; /* 24 */
Sergunb	0:f1834a63f7c1	840	uint32_t RESERVED2[40];
Sergunb	0:f1834a63f7c1	841	__IO uint32_t MMCCR; /* 65 */
Sergunb	0:f1834a63f7c1	842	__IO uint32_t MMCRIR;
Sergunb	0:f1834a63f7c1	843	__IO uint32_t MMCTIR;
Sergunb	0:f1834a63f7c1	844	__IO uint32_t MMCRIMR;
Sergunb	0:f1834a63f7c1	845	__IO uint32_t MMCTIMR; /* 69 */
Sergunb	0:f1834a63f7c1	846	uint32_t RESERVED3[14];
Sergunb	0:f1834a63f7c1	847	__IO uint32_t MMCTGFSCCR; /* 84 */
Sergunb	0:f1834a63f7c1	848	__IO uint32_t MMCTGFMSCCR;
Sergunb	0:f1834a63f7c1	849	uint32_t RESERVED4[5];
Sergunb	0:f1834a63f7c1	850	__IO uint32_t MMCTGFCR;
Sergunb	0:f1834a63f7c1	851	uint32_t RESERVED5[10];
Sergunb	0:f1834a63f7c1	852	__IO uint32_t MMCRFCECR;
Sergunb	0:f1834a63f7c1	853	__IO uint32_t MMCRFAECR;
Sergunb	0:f1834a63f7c1	854	uint32_t RESERVED6[10];
Sergunb	0:f1834a63f7c1	855	__IO uint32_t MMCRGUFCR;
Sergunb	0:f1834a63f7c1	856	uint32_t RESERVED7[334];
Sergunb	0:f1834a63f7c1	857	__IO uint32_t PTPTSCR;
Sergunb	0:f1834a63f7c1	858	__IO uint32_t PTPSSIR;
Sergunb	0:f1834a63f7c1	859	__IO uint32_t PTPTSHR;
Sergunb	0:f1834a63f7c1	860	__IO uint32_t PTPTSLR;
Sergunb	0:f1834a63f7c1	861	__IO uint32_t PTPTSHUR;
Sergunb	0:f1834a63f7c1	862	__IO uint32_t PTPTSLUR;
Sergunb	0:f1834a63f7c1	863	__IO uint32_t PTPTSAR;
Sergunb	0:f1834a63f7c1	864	__IO uint32_t PTPTTHR;
Sergunb	0:f1834a63f7c1	865	__IO uint32_t PTPTTLR;
Sergunb	0:f1834a63f7c1	866	uint32_t RESERVED8[567];
Sergunb	0:f1834a63f7c1	867	__IO uint32_t DMABMR;
Sergunb	0:f1834a63f7c1	868	__IO uint32_t DMATPDR;
Sergunb	0:f1834a63f7c1	869	__IO uint32_t DMARPDR;
Sergunb	0:f1834a63f7c1	870	__IO uint32_t DMARDLAR;
Sergunb	0:f1834a63f7c1	871	__IO uint32_t DMATDLAR;
Sergunb	0:f1834a63f7c1	872	__IO uint32_t DMASR;
Sergunb	0:f1834a63f7c1	873	__IO uint32_t DMAOMR;
Sergunb	0:f1834a63f7c1	874	__IO uint32_t DMAIER;
Sergunb	0:f1834a63f7c1	875	__IO uint32_t DMAMFBOCR;
Sergunb	0:f1834a63f7c1	876	uint32_t RESERVED9[9];
Sergunb	0:f1834a63f7c1	877	__IO uint32_t DMACHTDR;
Sergunb	0:f1834a63f7c1	878	__IO uint32_t DMACHRDR;
Sergunb	0:f1834a63f7c1	879	__IO uint32_t DMACHTBAR;
Sergunb	0:f1834a63f7c1	880	__IO uint32_t DMACHRBAR;
Sergunb	0:f1834a63f7c1	881	} ETH_TypeDef;
Sergunb	0:f1834a63f7c1	882
Sergunb	0:f1834a63f7c1	883	/**
Sergunb	0:f1834a63f7c1	884	* @brief External Interrupt/Event Controller
Sergunb	0:f1834a63f7c1	885	*/
Sergunb	0:f1834a63f7c1	886
Sergunb	0:f1834a63f7c1	887	typedef struct
Sergunb	0:f1834a63f7c1	888	{
Sergunb	0:f1834a63f7c1	889	__IO uint32_t IMR;
Sergunb	0:f1834a63f7c1	890	__IO uint32_t EMR;
Sergunb	0:f1834a63f7c1	891	__IO uint32_t RTSR;
Sergunb	0:f1834a63f7c1	892	__IO uint32_t FTSR;
Sergunb	0:f1834a63f7c1	893	__IO uint32_t SWIER;
Sergunb	0:f1834a63f7c1	894	__IO uint32_t PR;
Sergunb	0:f1834a63f7c1	895	} EXTI_TypeDef;
Sergunb	0:f1834a63f7c1	896
Sergunb	0:f1834a63f7c1	897	/**
Sergunb	0:f1834a63f7c1	898	* @brief FLASH Registers
Sergunb	0:f1834a63f7c1	899	*/
Sergunb	0:f1834a63f7c1	900
Sergunb	0:f1834a63f7c1	901	typedef struct
Sergunb	0:f1834a63f7c1	902	{
Sergunb	0:f1834a63f7c1	903	__IO uint32_t ACR;
Sergunb	0:f1834a63f7c1	904	__IO uint32_t KEYR;
Sergunb	0:f1834a63f7c1	905	__IO uint32_t OPTKEYR;
Sergunb	0:f1834a63f7c1	906	__IO uint32_t SR;
Sergunb	0:f1834a63f7c1	907	__IO uint32_t CR;
Sergunb	0:f1834a63f7c1	908	__IO uint32_t AR;
Sergunb	0:f1834a63f7c1	909	__IO uint32_t RESERVED;
Sergunb	0:f1834a63f7c1	910	__IO uint32_t OBR;
Sergunb	0:f1834a63f7c1	911	__IO uint32_t WRPR;
Sergunb	0:f1834a63f7c1	912	#ifdef STM32F10X_XL
Sergunb	0:f1834a63f7c1	913	uint32_t RESERVED1[8];
Sergunb	0:f1834a63f7c1	914	__IO uint32_t KEYR2;
Sergunb	0:f1834a63f7c1	915	uint32_t RESERVED2;
Sergunb	0:f1834a63f7c1	916	__IO uint32_t SR2;
Sergunb	0:f1834a63f7c1	917	__IO uint32_t CR2;
Sergunb	0:f1834a63f7c1	918	__IO uint32_t AR2;
Sergunb	0:f1834a63f7c1	919	#endif /* STM32F10X_XL */
Sergunb	0:f1834a63f7c1	920	} FLASH_TypeDef;
Sergunb	0:f1834a63f7c1	921
Sergunb	0:f1834a63f7c1	922	/**
Sergunb	0:f1834a63f7c1	923	* @brief Option Bytes Registers
Sergunb	0:f1834a63f7c1	924	*/
Sergunb	0:f1834a63f7c1	925
Sergunb	0:f1834a63f7c1	926	typedef struct
Sergunb	0:f1834a63f7c1	927	{
Sergunb	0:f1834a63f7c1	928	__IO uint16_t RDP;
Sergunb	0:f1834a63f7c1	929	__IO uint16_t USER;
Sergunb	0:f1834a63f7c1	930	__IO uint16_t Data0;
Sergunb	0:f1834a63f7c1	931	__IO uint16_t Data1;
Sergunb	0:f1834a63f7c1	932	__IO uint16_t WRP0;
Sergunb	0:f1834a63f7c1	933	__IO uint16_t WRP1;
Sergunb	0:f1834a63f7c1	934	__IO uint16_t WRP2;
Sergunb	0:f1834a63f7c1	935	__IO uint16_t WRP3;
Sergunb	0:f1834a63f7c1	936	} OB_TypeDef;
Sergunb	0:f1834a63f7c1	937
Sergunb	0:f1834a63f7c1	938	/**
Sergunb	0:f1834a63f7c1	939	* @brief Flexible Static Memory Controller
Sergunb	0:f1834a63f7c1	940	*/
Sergunb	0:f1834a63f7c1	941
Sergunb	0:f1834a63f7c1	942	typedef struct
Sergunb	0:f1834a63f7c1	943	{
Sergunb	0:f1834a63f7c1	944	__IO uint32_t BTCR[8];
Sergunb	0:f1834a63f7c1	945	} FSMC_Bank1_TypeDef;
Sergunb	0:f1834a63f7c1	946
Sergunb	0:f1834a63f7c1	947	/**
Sergunb	0:f1834a63f7c1	948	* @brief Flexible Static Memory Controller Bank1E
Sergunb	0:f1834a63f7c1	949	*/
Sergunb	0:f1834a63f7c1	950
Sergunb	0:f1834a63f7c1	951	typedef struct
Sergunb	0:f1834a63f7c1	952	{
Sergunb	0:f1834a63f7c1	953	__IO uint32_t BWTR[7];
Sergunb	0:f1834a63f7c1	954	} FSMC_Bank1E_TypeDef;
Sergunb	0:f1834a63f7c1	955
Sergunb	0:f1834a63f7c1	956	/**
Sergunb	0:f1834a63f7c1	957	* @brief Flexible Static Memory Controller Bank2
Sergunb	0:f1834a63f7c1	958	*/
Sergunb	0:f1834a63f7c1	959
Sergunb	0:f1834a63f7c1	960	typedef struct
Sergunb	0:f1834a63f7c1	961	{
Sergunb	0:f1834a63f7c1	962	__IO uint32_t PCR2;
Sergunb	0:f1834a63f7c1	963	__IO uint32_t SR2;
Sergunb	0:f1834a63f7c1	964	__IO uint32_t PMEM2;
Sergunb	0:f1834a63f7c1	965	__IO uint32_t PATT2;
Sergunb	0:f1834a63f7c1	966	uint32_t RESERVED0;
Sergunb	0:f1834a63f7c1	967	__IO uint32_t ECCR2;
Sergunb	0:f1834a63f7c1	968	} FSMC_Bank2_TypeDef;
Sergunb	0:f1834a63f7c1	969
Sergunb	0:f1834a63f7c1	970	/**
Sergunb	0:f1834a63f7c1	971	* @brief Flexible Static Memory Controller Bank3
Sergunb	0:f1834a63f7c1	972	*/
Sergunb	0:f1834a63f7c1	973
Sergunb	0:f1834a63f7c1	974	typedef struct
Sergunb	0:f1834a63f7c1	975	{
Sergunb	0:f1834a63f7c1	976	__IO uint32_t PCR3;
Sergunb	0:f1834a63f7c1	977	__IO uint32_t SR3;
Sergunb	0:f1834a63f7c1	978	__IO uint32_t PMEM3;
Sergunb	0:f1834a63f7c1	979	__IO uint32_t PATT3;
Sergunb	0:f1834a63f7c1	980	uint32_t RESERVED0;
Sergunb	0:f1834a63f7c1	981	__IO uint32_t ECCR3;
Sergunb	0:f1834a63f7c1	982	} FSMC_Bank3_TypeDef;
Sergunb	0:f1834a63f7c1	983
Sergunb	0:f1834a63f7c1	984	/**
Sergunb	0:f1834a63f7c1	985	* @brief Flexible Static Memory Controller Bank4
Sergunb	0:f1834a63f7c1	986	*/
Sergunb	0:f1834a63f7c1	987
Sergunb	0:f1834a63f7c1	988	typedef struct
Sergunb	0:f1834a63f7c1	989	{
Sergunb	0:f1834a63f7c1	990	__IO uint32_t PCR4;
Sergunb	0:f1834a63f7c1	991	__IO uint32_t SR4;
Sergunb	0:f1834a63f7c1	992	__IO uint32_t PMEM4;
Sergunb	0:f1834a63f7c1	993	__IO uint32_t PATT4;
Sergunb	0:f1834a63f7c1	994	__IO uint32_t PIO4;
Sergunb	0:f1834a63f7c1	995	} FSMC_Bank4_TypeDef;
Sergunb	0:f1834a63f7c1	996
Sergunb	0:f1834a63f7c1	997	/**
Sergunb	0:f1834a63f7c1	998	* @brief General Purpose I/O
Sergunb	0:f1834a63f7c1	999	*/
Sergunb	0:f1834a63f7c1	1000
Sergunb	0:f1834a63f7c1	1001	typedef struct
Sergunb	0:f1834a63f7c1	1002	{
Sergunb	0:f1834a63f7c1	1003	__IO uint32_t CRL;
Sergunb	0:f1834a63f7c1	1004	__IO uint32_t CRH;
Sergunb	0:f1834a63f7c1	1005	__IO uint32_t IDR;
Sergunb	0:f1834a63f7c1	1006	__IO uint32_t ODR;
Sergunb	0:f1834a63f7c1	1007	__IO uint32_t BSRR;
Sergunb	0:f1834a63f7c1	1008	__IO uint32_t BRR;
Sergunb	0:f1834a63f7c1	1009	__IO uint32_t LCKR;
Sergunb	0:f1834a63f7c1	1010	} GPIO_TypeDef;
Sergunb	0:f1834a63f7c1	1011
Sergunb	0:f1834a63f7c1	1012	/**
Sergunb	0:f1834a63f7c1	1013	* @brief Alternate Function I/O
Sergunb	0:f1834a63f7c1	1014	*/
Sergunb	0:f1834a63f7c1	1015
Sergunb	0:f1834a63f7c1	1016	typedef struct
Sergunb	0:f1834a63f7c1	1017	{
Sergunb	0:f1834a63f7c1	1018	__IO uint32_t EVCR;
Sergunb	0:f1834a63f7c1	1019	__IO uint32_t MAPR;
Sergunb	0:f1834a63f7c1	1020	__IO uint32_t EXTICR[4];
Sergunb	0:f1834a63f7c1	1021	uint32_t RESERVED0;
Sergunb	0:f1834a63f7c1	1022	__IO uint32_t MAPR2;
Sergunb	0:f1834a63f7c1	1023	} AFIO_TypeDef;
Sergunb	0:f1834a63f7c1	1024	/**
Sergunb	0:f1834a63f7c1	1025	* @brief Inter Integrated Circuit Interface
Sergunb	0:f1834a63f7c1	1026	*/
Sergunb	0:f1834a63f7c1	1027
Sergunb	0:f1834a63f7c1	1028	typedef struct
Sergunb	0:f1834a63f7c1	1029	{
Sergunb	0:f1834a63f7c1	1030	__IO uint16_t CR1;
Sergunb	0:f1834a63f7c1	1031	uint16_t RESERVED0;
Sergunb	0:f1834a63f7c1	1032	__IO uint16_t CR2;
Sergunb	0:f1834a63f7c1	1033	uint16_t RESERVED1;
Sergunb	0:f1834a63f7c1	1034	__IO uint16_t OAR1;
Sergunb	0:f1834a63f7c1	1035	uint16_t RESERVED2;
Sergunb	0:f1834a63f7c1	1036	__IO uint16_t OAR2;
Sergunb	0:f1834a63f7c1	1037	uint16_t RESERVED3;
Sergunb	0:f1834a63f7c1	1038	__IO uint16_t DR;
Sergunb	0:f1834a63f7c1	1039	uint16_t RESERVED4;
Sergunb	0:f1834a63f7c1	1040	__IO uint16_t SR1;
Sergunb	0:f1834a63f7c1	1041	uint16_t RESERVED5;
Sergunb	0:f1834a63f7c1	1042	__IO uint16_t SR2;
Sergunb	0:f1834a63f7c1	1043	uint16_t RESERVED6;
Sergunb	0:f1834a63f7c1	1044	__IO uint16_t CCR;
Sergunb	0:f1834a63f7c1	1045	uint16_t RESERVED7;
Sergunb	0:f1834a63f7c1	1046	__IO uint16_t TRISE;
Sergunb	0:f1834a63f7c1	1047	uint16_t RESERVED8;
Sergunb	0:f1834a63f7c1	1048	} I2C_TypeDef;
Sergunb	0:f1834a63f7c1	1049
Sergunb	0:f1834a63f7c1	1050	/**
Sergunb	0:f1834a63f7c1	1051	* @brief Independent WATCHDOG
Sergunb	0:f1834a63f7c1	1052	*/
Sergunb	0:f1834a63f7c1	1053
Sergunb	0:f1834a63f7c1	1054	typedef struct
Sergunb	0:f1834a63f7c1	1055	{
Sergunb	0:f1834a63f7c1	1056	__IO uint32_t KR;
Sergunb	0:f1834a63f7c1	1057	__IO uint32_t PR;
Sergunb	0:f1834a63f7c1	1058	__IO uint32_t RLR;
Sergunb	0:f1834a63f7c1	1059	__IO uint32_t SR;
Sergunb	0:f1834a63f7c1	1060	} IWDG_TypeDef;
Sergunb	0:f1834a63f7c1	1061
Sergunb	0:f1834a63f7c1	1062	/**
Sergunb	0:f1834a63f7c1	1063	* @brief Power Control
Sergunb	0:f1834a63f7c1	1064	*/
Sergunb	0:f1834a63f7c1	1065
Sergunb	0:f1834a63f7c1	1066	typedef struct
Sergunb	0:f1834a63f7c1	1067	{
Sergunb	0:f1834a63f7c1	1068	__IO uint32_t CR;
Sergunb	0:f1834a63f7c1	1069	__IO uint32_t CSR;
Sergunb	0:f1834a63f7c1	1070	} PWR_TypeDef;
Sergunb	0:f1834a63f7c1	1071
Sergunb	0:f1834a63f7c1	1072	/**
Sergunb	0:f1834a63f7c1	1073	* @brief Reset and Clock Control
Sergunb	0:f1834a63f7c1	1074	*/
Sergunb	0:f1834a63f7c1	1075
Sergunb	0:f1834a63f7c1	1076	typedef struct
Sergunb	0:f1834a63f7c1	1077	{
Sergunb	0:f1834a63f7c1	1078	__IO uint32_t CR;
Sergunb	0:f1834a63f7c1	1079	__IO uint32_t CFGR;
Sergunb	0:f1834a63f7c1	1080	__IO uint32_t CIR;
Sergunb	0:f1834a63f7c1	1081	__IO uint32_t APB2RSTR;
Sergunb	0:f1834a63f7c1	1082	__IO uint32_t APB1RSTR;
Sergunb	0:f1834a63f7c1	1083	__IO uint32_t AHBENR;
Sergunb	0:f1834a63f7c1	1084	__IO uint32_t APB2ENR;
Sergunb	0:f1834a63f7c1	1085	__IO uint32_t APB1ENR;
Sergunb	0:f1834a63f7c1	1086	__IO uint32_t BDCR;
Sergunb	0:f1834a63f7c1	1087	__IO uint32_t CSR;
Sergunb	0:f1834a63f7c1	1088
Sergunb	0:f1834a63f7c1	1089	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	1090	__IO uint32_t AHBRSTR;
Sergunb	0:f1834a63f7c1	1091	__IO uint32_t CFGR2;
Sergunb	0:f1834a63f7c1	1092	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	1093
Sergunb	0:f1834a63f7c1	1094	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	1095	uint32_t RESERVED0;
Sergunb	0:f1834a63f7c1	1096	__IO uint32_t CFGR2;
Sergunb	0:f1834a63f7c1	1097	#endif /* STM32F10X_LD_VL \|\| STM32F10X_MD_VL \|\| STM32F10X_HD_VL */
Sergunb	0:f1834a63f7c1	1098	} RCC_TypeDef;
Sergunb	0:f1834a63f7c1	1099
Sergunb	0:f1834a63f7c1	1100	/**
Sergunb	0:f1834a63f7c1	1101	* @brief Real-Time Clock
Sergunb	0:f1834a63f7c1	1102	*/
Sergunb	0:f1834a63f7c1	1103
Sergunb	0:f1834a63f7c1	1104	typedef struct
Sergunb	0:f1834a63f7c1	1105	{
Sergunb	0:f1834a63f7c1	1106	__IO uint16_t CRH;
Sergunb	0:f1834a63f7c1	1107	uint16_t RESERVED0;
Sergunb	0:f1834a63f7c1	1108	__IO uint16_t CRL;
Sergunb	0:f1834a63f7c1	1109	uint16_t RESERVED1;
Sergunb	0:f1834a63f7c1	1110	__IO uint16_t PRLH;
Sergunb	0:f1834a63f7c1	1111	uint16_t RESERVED2;
Sergunb	0:f1834a63f7c1	1112	__IO uint16_t PRLL;
Sergunb	0:f1834a63f7c1	1113	uint16_t RESERVED3;
Sergunb	0:f1834a63f7c1	1114	__IO uint16_t DIVH;
Sergunb	0:f1834a63f7c1	1115	uint16_t RESERVED4;
Sergunb	0:f1834a63f7c1	1116	__IO uint16_t DIVL;
Sergunb	0:f1834a63f7c1	1117	uint16_t RESERVED5;
Sergunb	0:f1834a63f7c1	1118	__IO uint16_t CNTH;
Sergunb	0:f1834a63f7c1	1119	uint16_t RESERVED6;
Sergunb	0:f1834a63f7c1	1120	__IO uint16_t CNTL;
Sergunb	0:f1834a63f7c1	1121	uint16_t RESERVED7;
Sergunb	0:f1834a63f7c1	1122	__IO uint16_t ALRH;
Sergunb	0:f1834a63f7c1	1123	uint16_t RESERVED8;
Sergunb	0:f1834a63f7c1	1124	__IO uint16_t ALRL;
Sergunb	0:f1834a63f7c1	1125	uint16_t RESERVED9;
Sergunb	0:f1834a63f7c1	1126	} RTC_TypeDef;
Sergunb	0:f1834a63f7c1	1127
Sergunb	0:f1834a63f7c1	1128	/**
Sergunb	0:f1834a63f7c1	1129	* @brief SD host Interface
Sergunb	0:f1834a63f7c1	1130	*/
Sergunb	0:f1834a63f7c1	1131
Sergunb	0:f1834a63f7c1	1132	typedef struct
Sergunb	0:f1834a63f7c1	1133	{
Sergunb	0:f1834a63f7c1	1134	__IO uint32_t POWER;
Sergunb	0:f1834a63f7c1	1135	__IO uint32_t CLKCR;
Sergunb	0:f1834a63f7c1	1136	__IO uint32_t ARG;
Sergunb	0:f1834a63f7c1	1137	__IO uint32_t CMD;
Sergunb	0:f1834a63f7c1	1138	__I uint32_t RESPCMD;
Sergunb	0:f1834a63f7c1	1139	__I uint32_t RESP1;
Sergunb	0:f1834a63f7c1	1140	__I uint32_t RESP2;
Sergunb	0:f1834a63f7c1	1141	__I uint32_t RESP3;
Sergunb	0:f1834a63f7c1	1142	__I uint32_t RESP4;
Sergunb	0:f1834a63f7c1	1143	__IO uint32_t DTIMER;
Sergunb	0:f1834a63f7c1	1144	__IO uint32_t DLEN;
Sergunb	0:f1834a63f7c1	1145	__IO uint32_t DCTRL;
Sergunb	0:f1834a63f7c1	1146	__I uint32_t DCOUNT;
Sergunb	0:f1834a63f7c1	1147	__I uint32_t STA;
Sergunb	0:f1834a63f7c1	1148	__IO uint32_t ICR;
Sergunb	0:f1834a63f7c1	1149	__IO uint32_t MASK;
Sergunb	0:f1834a63f7c1	1150	uint32_t RESERVED0[2];
Sergunb	0:f1834a63f7c1	1151	__I uint32_t FIFOCNT;
Sergunb	0:f1834a63f7c1	1152	uint32_t RESERVED1[13];
Sergunb	0:f1834a63f7c1	1153	__IO uint32_t FIFO;
Sergunb	0:f1834a63f7c1	1154	} SDIO_TypeDef;
Sergunb	0:f1834a63f7c1	1155
Sergunb	0:f1834a63f7c1	1156	/**
Sergunb	0:f1834a63f7c1	1157	* @brief Serial Peripheral Interface
Sergunb	0:f1834a63f7c1	1158	*/
Sergunb	0:f1834a63f7c1	1159
Sergunb	0:f1834a63f7c1	1160	typedef struct
Sergunb	0:f1834a63f7c1	1161	{
Sergunb	0:f1834a63f7c1	1162	__IO uint16_t CR1;
Sergunb	0:f1834a63f7c1	1163	uint16_t RESERVED0;
Sergunb	0:f1834a63f7c1	1164	__IO uint16_t CR2;
Sergunb	0:f1834a63f7c1	1165	uint16_t RESERVED1;
Sergunb	0:f1834a63f7c1	1166	__IO uint16_t SR;
Sergunb	0:f1834a63f7c1	1167	uint16_t RESERVED2;
Sergunb	0:f1834a63f7c1	1168	__IO uint16_t DR;
Sergunb	0:f1834a63f7c1	1169	uint16_t RESERVED3;
Sergunb	0:f1834a63f7c1	1170	__IO uint16_t CRCPR;
Sergunb	0:f1834a63f7c1	1171	uint16_t RESERVED4;
Sergunb	0:f1834a63f7c1	1172	__IO uint16_t RXCRCR;
Sergunb	0:f1834a63f7c1	1173	uint16_t RESERVED5;
Sergunb	0:f1834a63f7c1	1174	__IO uint16_t TXCRCR;
Sergunb	0:f1834a63f7c1	1175	uint16_t RESERVED6;
Sergunb	0:f1834a63f7c1	1176	__IO uint16_t I2SCFGR;
Sergunb	0:f1834a63f7c1	1177	uint16_t RESERVED7;
Sergunb	0:f1834a63f7c1	1178	__IO uint16_t I2SPR;
Sergunb	0:f1834a63f7c1	1179	uint16_t RESERVED8;
Sergunb	0:f1834a63f7c1	1180	} SPI_TypeDef;
Sergunb	0:f1834a63f7c1	1181
Sergunb	0:f1834a63f7c1	1182	/**
Sergunb	0:f1834a63f7c1	1183	* @brief TIM
Sergunb	0:f1834a63f7c1	1184	*/
Sergunb	0:f1834a63f7c1	1185
Sergunb	0:f1834a63f7c1	1186	typedef struct
Sergunb	0:f1834a63f7c1	1187	{
Sergunb	0:f1834a63f7c1	1188	__IO uint16_t CR1;
Sergunb	0:f1834a63f7c1	1189	uint16_t RESERVED0;
Sergunb	0:f1834a63f7c1	1190	__IO uint16_t CR2;
Sergunb	0:f1834a63f7c1	1191	uint16_t RESERVED1;
Sergunb	0:f1834a63f7c1	1192	__IO uint16_t SMCR;
Sergunb	0:f1834a63f7c1	1193	uint16_t RESERVED2;
Sergunb	0:f1834a63f7c1	1194	__IO uint16_t DIER;
Sergunb	0:f1834a63f7c1	1195	uint16_t RESERVED3;
Sergunb	0:f1834a63f7c1	1196	__IO uint16_t SR;
Sergunb	0:f1834a63f7c1	1197	uint16_t RESERVED4;
Sergunb	0:f1834a63f7c1	1198	__IO uint16_t EGR;
Sergunb	0:f1834a63f7c1	1199	uint16_t RESERVED5;
Sergunb	0:f1834a63f7c1	1200	__IO uint16_t CCMR1;
Sergunb	0:f1834a63f7c1	1201	uint16_t RESERVED6;
Sergunb	0:f1834a63f7c1	1202	__IO uint16_t CCMR2;
Sergunb	0:f1834a63f7c1	1203	uint16_t RESERVED7;
Sergunb	0:f1834a63f7c1	1204	__IO uint16_t CCER;
Sergunb	0:f1834a63f7c1	1205	uint16_t RESERVED8;
Sergunb	0:f1834a63f7c1	1206	__IO uint16_t CNT;
Sergunb	0:f1834a63f7c1	1207	uint16_t RESERVED9;
Sergunb	0:f1834a63f7c1	1208	__IO uint16_t PSC;
Sergunb	0:f1834a63f7c1	1209	uint16_t RESERVED10;
Sergunb	0:f1834a63f7c1	1210	__IO uint16_t ARR;
Sergunb	0:f1834a63f7c1	1211	uint16_t RESERVED11;
Sergunb	0:f1834a63f7c1	1212	__IO uint16_t RCR;
Sergunb	0:f1834a63f7c1	1213	uint16_t RESERVED12;
Sergunb	0:f1834a63f7c1	1214	__IO uint16_t CCR1;
Sergunb	0:f1834a63f7c1	1215	uint16_t RESERVED13;
Sergunb	0:f1834a63f7c1	1216	__IO uint16_t CCR2;
Sergunb	0:f1834a63f7c1	1217	uint16_t RESERVED14;
Sergunb	0:f1834a63f7c1	1218	__IO uint16_t CCR3;
Sergunb	0:f1834a63f7c1	1219	uint16_t RESERVED15;
Sergunb	0:f1834a63f7c1	1220	__IO uint16_t CCR4;
Sergunb	0:f1834a63f7c1	1221	uint16_t RESERVED16;
Sergunb	0:f1834a63f7c1	1222	__IO uint16_t BDTR;
Sergunb	0:f1834a63f7c1	1223	uint16_t RESERVED17;
Sergunb	0:f1834a63f7c1	1224	__IO uint16_t DCR;
Sergunb	0:f1834a63f7c1	1225	uint16_t RESERVED18;
Sergunb	0:f1834a63f7c1	1226	__IO uint16_t DMAR;
Sergunb	0:f1834a63f7c1	1227	uint16_t RESERVED19;
Sergunb	0:f1834a63f7c1	1228	} TIM_TypeDef;
Sergunb	0:f1834a63f7c1	1229
Sergunb	0:f1834a63f7c1	1230	/**
Sergunb	0:f1834a63f7c1	1231	* @brief Universal Synchronous Asynchronous Receiver Transmitter
Sergunb	0:f1834a63f7c1	1232	*/
Sergunb	0:f1834a63f7c1	1233
Sergunb	0:f1834a63f7c1	1234	typedef struct
Sergunb	0:f1834a63f7c1	1235	{
Sergunb	0:f1834a63f7c1	1236	__IO uint16_t SR;
Sergunb	0:f1834a63f7c1	1237	uint16_t RESERVED0;
Sergunb	0:f1834a63f7c1	1238	__IO uint16_t DR;
Sergunb	0:f1834a63f7c1	1239	uint16_t RESERVED1;
Sergunb	0:f1834a63f7c1	1240	__IO uint16_t BRR;
Sergunb	0:f1834a63f7c1	1241	uint16_t RESERVED2;
Sergunb	0:f1834a63f7c1	1242	__IO uint16_t CR1;
Sergunb	0:f1834a63f7c1	1243	uint16_t RESERVED3;
Sergunb	0:f1834a63f7c1	1244	__IO uint16_t CR2;
Sergunb	0:f1834a63f7c1	1245	uint16_t RESERVED4;
Sergunb	0:f1834a63f7c1	1246	__IO uint16_t CR3;
Sergunb	0:f1834a63f7c1	1247	uint16_t RESERVED5;
Sergunb	0:f1834a63f7c1	1248	__IO uint16_t GTPR;
Sergunb	0:f1834a63f7c1	1249	uint16_t RESERVED6;
Sergunb	0:f1834a63f7c1	1250	} USART_TypeDef;
Sergunb	0:f1834a63f7c1	1251
Sergunb	0:f1834a63f7c1	1252	/**
Sergunb	0:f1834a63f7c1	1253	* @brief Window WATCHDOG
Sergunb	0:f1834a63f7c1	1254	*/
Sergunb	0:f1834a63f7c1	1255
Sergunb	0:f1834a63f7c1	1256	typedef struct
Sergunb	0:f1834a63f7c1	1257	{
Sergunb	0:f1834a63f7c1	1258	__IO uint32_t CR;
Sergunb	0:f1834a63f7c1	1259	__IO uint32_t CFR;
Sergunb	0:f1834a63f7c1	1260	__IO uint32_t SR;
Sergunb	0:f1834a63f7c1	1261	} WWDG_TypeDef;
Sergunb	0:f1834a63f7c1	1262
Sergunb	0:f1834a63f7c1	1263	/**
Sergunb	0:f1834a63f7c1	1264	* @}
Sergunb	0:f1834a63f7c1	1265	*/
Sergunb	0:f1834a63f7c1	1266
Sergunb	0:f1834a63f7c1	1267	/** @addtogroup Peripheral_memory_map
Sergunb	0:f1834a63f7c1	1268	* @{
Sergunb	0:f1834a63f7c1	1269	*/
Sergunb	0:f1834a63f7c1	1270
Sergunb	0:f1834a63f7c1	1271
Sergunb	0:f1834a63f7c1	1272	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
Sergunb	0:f1834a63f7c1	1273	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
Sergunb	0:f1834a63f7c1	1274	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
Sergunb	0:f1834a63f7c1	1275
Sergunb	0:f1834a63f7c1	1276	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
Sergunb	0:f1834a63f7c1	1277	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
Sergunb	0:f1834a63f7c1	1278
Sergunb	0:f1834a63f7c1	1279	#define FSMC_R_BASE ((uint32_t)0xA0000000) /!< FSMC registers base address /
Sergunb	0:f1834a63f7c1	1280
Sergunb	0:f1834a63f7c1	1281	/!< Peripheral memory map /
Sergunb	0:f1834a63f7c1	1282	#define APB1PERIPH_BASE PERIPH_BASE
Sergunb	0:f1834a63f7c1	1283	#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
Sergunb	0:f1834a63f7c1	1284	#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
Sergunb	0:f1834a63f7c1	1285
Sergunb	0:f1834a63f7c1	1286	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
Sergunb	0:f1834a63f7c1	1287	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
Sergunb	0:f1834a63f7c1	1288	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
Sergunb	0:f1834a63f7c1	1289	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
Sergunb	0:f1834a63f7c1	1290	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
Sergunb	0:f1834a63f7c1	1291	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
Sergunb	0:f1834a63f7c1	1292	#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
Sergunb	0:f1834a63f7c1	1293	#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
Sergunb	0:f1834a63f7c1	1294	#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
Sergunb	0:f1834a63f7c1	1295	#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
Sergunb	0:f1834a63f7c1	1296	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
Sergunb	0:f1834a63f7c1	1297	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
Sergunb	0:f1834a63f7c1	1298	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
Sergunb	0:f1834a63f7c1	1299	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
Sergunb	0:f1834a63f7c1	1300	#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
Sergunb	0:f1834a63f7c1	1301	#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
Sergunb	0:f1834a63f7c1	1302	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
Sergunb	0:f1834a63f7c1	1303	#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
Sergunb	0:f1834a63f7c1	1304	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
Sergunb	0:f1834a63f7c1	1305	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
Sergunb	0:f1834a63f7c1	1306	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
Sergunb	0:f1834a63f7c1	1307	#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
Sergunb	0:f1834a63f7c1	1308	#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
Sergunb	0:f1834a63f7c1	1309	#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
Sergunb	0:f1834a63f7c1	1310	#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
Sergunb	0:f1834a63f7c1	1311	#define CEC_BASE (APB1PERIPH_BASE + 0x7800)
Sergunb	0:f1834a63f7c1	1312
Sergunb	0:f1834a63f7c1	1313	#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
Sergunb	0:f1834a63f7c1	1314	#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
Sergunb	0:f1834a63f7c1	1315	#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
Sergunb	0:f1834a63f7c1	1316	#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00)
Sergunb	0:f1834a63f7c1	1317	#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
Sergunb	0:f1834a63f7c1	1318	#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
Sergunb	0:f1834a63f7c1	1319	#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
Sergunb	0:f1834a63f7c1	1320	#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
Sergunb	0:f1834a63f7c1	1321	#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
Sergunb	0:f1834a63f7c1	1322	#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
Sergunb	0:f1834a63f7c1	1323	#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
Sergunb	0:f1834a63f7c1	1324	#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
Sergunb	0:f1834a63f7c1	1325	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
Sergunb	0:f1834a63f7c1	1326	#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
Sergunb	0:f1834a63f7c1	1327	#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
Sergunb	0:f1834a63f7c1	1328	#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
Sergunb	0:f1834a63f7c1	1329	#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
Sergunb	0:f1834a63f7c1	1330	#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
Sergunb	0:f1834a63f7c1	1331	#define TIM17_BASE (APB2PERIPH_BASE + 0x4800)
Sergunb	0:f1834a63f7c1	1332	#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
Sergunb	0:f1834a63f7c1	1333	#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
Sergunb	0:f1834a63f7c1	1334	#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
Sergunb	0:f1834a63f7c1	1335
Sergunb	0:f1834a63f7c1	1336	#define SDIO_BASE (PERIPH_BASE + 0x18000)
Sergunb	0:f1834a63f7c1	1337
Sergunb	0:f1834a63f7c1	1338	#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
Sergunb	0:f1834a63f7c1	1339	#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
Sergunb	0:f1834a63f7c1	1340	#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
Sergunb	0:f1834a63f7c1	1341	#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
Sergunb	0:f1834a63f7c1	1342	#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
Sergunb	0:f1834a63f7c1	1343	#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
Sergunb	0:f1834a63f7c1	1344	#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
Sergunb	0:f1834a63f7c1	1345	#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
Sergunb	0:f1834a63f7c1	1346	#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
Sergunb	0:f1834a63f7c1	1347	#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
Sergunb	0:f1834a63f7c1	1348	#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
Sergunb	0:f1834a63f7c1	1349	#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
Sergunb	0:f1834a63f7c1	1350	#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
Sergunb	0:f1834a63f7c1	1351	#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
Sergunb	0:f1834a63f7c1	1352	#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
Sergunb	0:f1834a63f7c1	1353	#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
Sergunb	0:f1834a63f7c1	1354
Sergunb	0:f1834a63f7c1	1355	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /!< Flash registers base address /
Sergunb	0:f1834a63f7c1	1356	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
Sergunb	0:f1834a63f7c1	1357
Sergunb	0:f1834a63f7c1	1358	#define ETH_BASE (AHBPERIPH_BASE + 0x8000)
Sergunb	0:f1834a63f7c1	1359	#define ETH_MAC_BASE (ETH_BASE)
Sergunb	0:f1834a63f7c1	1360	#define ETH_MMC_BASE (ETH_BASE + 0x0100)
Sergunb	0:f1834a63f7c1	1361	#define ETH_PTP_BASE (ETH_BASE + 0x0700)
Sergunb	0:f1834a63f7c1	1362	#define ETH_DMA_BASE (ETH_BASE + 0x1000)
Sergunb	0:f1834a63f7c1	1363
Sergunb	0:f1834a63f7c1	1364	#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /!< FSMC Bank1 registers base address /
Sergunb	0:f1834a63f7c1	1365	#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /!< FSMC Bank1E registers base address /
Sergunb	0:f1834a63f7c1	1366	#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) /!< FSMC Bank2 registers base address /
Sergunb	0:f1834a63f7c1	1367	#define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) /!< FSMC Bank3 registers base address /
Sergunb	0:f1834a63f7c1	1368	#define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) /!< FSMC Bank4 registers base address /
Sergunb	0:f1834a63f7c1	1369
Sergunb	0:f1834a63f7c1	1370	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
Sergunb	0:f1834a63f7c1	1371
Sergunb	0:f1834a63f7c1	1372	/**
Sergunb	0:f1834a63f7c1	1373	* @}
Sergunb	0:f1834a63f7c1	1374	*/
Sergunb	0:f1834a63f7c1	1375
Sergunb	0:f1834a63f7c1	1376	/** @addtogroup Peripheral_declaration
Sergunb	0:f1834a63f7c1	1377	* @{
Sergunb	0:f1834a63f7c1	1378	*/
Sergunb	0:f1834a63f7c1	1379
Sergunb	0:f1834a63f7c1	1380	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Sergunb	0:f1834a63f7c1	1381	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Sergunb	0:f1834a63f7c1	1382	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Sergunb	0:f1834a63f7c1	1383	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Sergunb	0:f1834a63f7c1	1384	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Sergunb	0:f1834a63f7c1	1385	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Sergunb	0:f1834a63f7c1	1386	#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
Sergunb	0:f1834a63f7c1	1387	#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
Sergunb	0:f1834a63f7c1	1388	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Sergunb	0:f1834a63f7c1	1389	#define RTC ((RTC_TypeDef *) RTC_BASE)
Sergunb	0:f1834a63f7c1	1390	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Sergunb	0:f1834a63f7c1	1391	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Sergunb	0:f1834a63f7c1	1392	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Sergunb	0:f1834a63f7c1	1393	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Sergunb	0:f1834a63f7c1	1394	#define USART2 ((USART_TypeDef *) USART2_BASE)
Sergunb	0:f1834a63f7c1	1395	#define USART3 ((USART_TypeDef *) USART3_BASE)
Sergunb	0:f1834a63f7c1	1396	#define UART4 ((USART_TypeDef *) UART4_BASE)
Sergunb	0:f1834a63f7c1	1397	#define UART5 ((USART_TypeDef *) UART5_BASE)
Sergunb	0:f1834a63f7c1	1398	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Sergunb	0:f1834a63f7c1	1399	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Sergunb	0:f1834a63f7c1	1400	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Sergunb	0:f1834a63f7c1	1401	#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
Sergunb	0:f1834a63f7c1	1402	#define BKP ((BKP_TypeDef *) BKP_BASE)
Sergunb	0:f1834a63f7c1	1403	#define PWR ((PWR_TypeDef *) PWR_BASE)
Sergunb	0:f1834a63f7c1	1404	#define DAC ((DAC_TypeDef *) DAC_BASE)
Sergunb	0:f1834a63f7c1	1405	#define CEC ((CEC_TypeDef *) CEC_BASE)
Sergunb	0:f1834a63f7c1	1406	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
Sergunb	0:f1834a63f7c1	1407	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Sergunb	0:f1834a63f7c1	1408	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Sergunb	0:f1834a63f7c1	1409	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Sergunb	0:f1834a63f7c1	1410	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Sergunb	0:f1834a63f7c1	1411	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Sergunb	0:f1834a63f7c1	1412	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Sergunb	0:f1834a63f7c1	1413	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Sergunb	0:f1834a63f7c1	1414	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Sergunb	0:f1834a63f7c1	1415	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Sergunb	0:f1834a63f7c1	1416	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Sergunb	0:f1834a63f7c1	1417	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Sergunb	0:f1834a63f7c1	1418	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Sergunb	0:f1834a63f7c1	1419	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
Sergunb	0:f1834a63f7c1	1420	#define USART1 ((USART_TypeDef *) USART1_BASE)
Sergunb	0:f1834a63f7c1	1421	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
Sergunb	0:f1834a63f7c1	1422	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
Sergunb	0:f1834a63f7c1	1423	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Sergunb	0:f1834a63f7c1	1424	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Sergunb	0:f1834a63f7c1	1425	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Sergunb	0:f1834a63f7c1	1426	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Sergunb	0:f1834a63f7c1	1427	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Sergunb	0:f1834a63f7c1	1428	#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
Sergunb	0:f1834a63f7c1	1429	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Sergunb	0:f1834a63f7c1	1430	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Sergunb	0:f1834a63f7c1	1431	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Sergunb	0:f1834a63f7c1	1432	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Sergunb	0:f1834a63f7c1	1433	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Sergunb	0:f1834a63f7c1	1434	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Sergunb	0:f1834a63f7c1	1435	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Sergunb	0:f1834a63f7c1	1436	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Sergunb	0:f1834a63f7c1	1437	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Sergunb	0:f1834a63f7c1	1438	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
Sergunb	0:f1834a63f7c1	1439	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
Sergunb	0:f1834a63f7c1	1440	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
Sergunb	0:f1834a63f7c1	1441	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
Sergunb	0:f1834a63f7c1	1442	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
Sergunb	0:f1834a63f7c1	1443	#define RCC ((RCC_TypeDef *) RCC_BASE)
Sergunb	0:f1834a63f7c1	1444	#define CRC ((CRC_TypeDef *) CRC_BASE)
Sergunb	0:f1834a63f7c1	1445	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Sergunb	0:f1834a63f7c1	1446	#define OB ((OB_TypeDef *) OB_BASE)
Sergunb	0:f1834a63f7c1	1447	#define ETH ((ETH_TypeDef *) ETH_BASE)
Sergunb	0:f1834a63f7c1	1448	#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
Sergunb	0:f1834a63f7c1	1449	#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
Sergunb	0:f1834a63f7c1	1450	#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
Sergunb	0:f1834a63f7c1	1451	#define FSMC_Bank3 ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
Sergunb	0:f1834a63f7c1	1452	#define FSMC_Bank4 ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
Sergunb	0:f1834a63f7c1	1453	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Sergunb	0:f1834a63f7c1	1454
Sergunb	0:f1834a63f7c1	1455	/**
Sergunb	0:f1834a63f7c1	1456	* @}
Sergunb	0:f1834a63f7c1	1457	*/
Sergunb	0:f1834a63f7c1	1458
Sergunb	0:f1834a63f7c1	1459	/** @addtogroup Exported_constants
Sergunb	0:f1834a63f7c1	1460	* @{
Sergunb	0:f1834a63f7c1	1461	*/
Sergunb	0:f1834a63f7c1	1462
Sergunb	0:f1834a63f7c1	1463	/** @addtogroup Peripheral_Registers_Bits_Definition
Sergunb	0:f1834a63f7c1	1464	* @{
Sergunb	0:f1834a63f7c1	1465	*/
Sergunb	0:f1834a63f7c1	1466
Sergunb	0:f1834a63f7c1	1467	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1468	/* Peripheral Registers_Bits_Definition */
Sergunb	0:f1834a63f7c1	1469	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1470
Sergunb	0:f1834a63f7c1	1471	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1472	/* */
Sergunb	0:f1834a63f7c1	1473	/* CRC calculation unit */
Sergunb	0:f1834a63f7c1	1474	/* */
Sergunb	0:f1834a63f7c1	1475	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1476
Sergunb	0:f1834a63f7c1	1477	/***************** Bit definition for CRC_DR register *******************/
Sergunb	0:f1834a63f7c1	1478	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
Sergunb	0:f1834a63f7c1	1479
Sergunb	0:f1834a63f7c1	1480
Sergunb	0:f1834a63f7c1	1481	/***************** Bit definition for CRC_IDR register ******************/
Sergunb	0:f1834a63f7c1	1482	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
Sergunb	0:f1834a63f7c1	1483
Sergunb	0:f1834a63f7c1	1484
Sergunb	0:f1834a63f7c1	1485	/****************** Bit definition for CRC_CR register ******************/
Sergunb	0:f1834a63f7c1	1486	#define CRC_CR_RESET ((uint8_t)0x01) /!< RESET bit /
Sergunb	0:f1834a63f7c1	1487
Sergunb	0:f1834a63f7c1	1488	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1489	/* */
Sergunb	0:f1834a63f7c1	1490	/* Power Control */
Sergunb	0:f1834a63f7c1	1491	/* */
Sergunb	0:f1834a63f7c1	1492	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1493
Sergunb	0:f1834a63f7c1	1494	/****************** Bit definition for PWR_CR register ******************/
Sergunb	0:f1834a63f7c1	1495	#define PWR_CR_LPDS ((uint16_t)0x0001) /!< Low-Power Deepsleep /
Sergunb	0:f1834a63f7c1	1496	#define PWR_CR_PDDS ((uint16_t)0x0002) /!< Power Down Deepsleep /
Sergunb	0:f1834a63f7c1	1497	#define PWR_CR_CWUF ((uint16_t)0x0004) /!< Clear Wakeup Flag /
Sergunb	0:f1834a63f7c1	1498	#define PWR_CR_CSBF ((uint16_t)0x0008) /!< Clear Standby Flag /
Sergunb	0:f1834a63f7c1	1499	#define PWR_CR_PVDE ((uint16_t)0x0010) /!< Power Voltage Detector Enable /
Sergunb	0:f1834a63f7c1	1500
Sergunb	0:f1834a63f7c1	1501	#define PWR_CR_PLS ((uint16_t)0x00E0) /!< PLS[2:0] bits (PVD Level Selection) /
Sergunb	0:f1834a63f7c1	1502	#define PWR_CR_PLS_0 ((uint16_t)0x0020) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1503	#define PWR_CR_PLS_1 ((uint16_t)0x0040) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1504	#define PWR_CR_PLS_2 ((uint16_t)0x0080) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	1505
Sergunb	0:f1834a63f7c1	1506	/!< PVD level configuration /
Sergunb	0:f1834a63f7c1	1507	#define PWR_CR_PLS_2V2 ((uint16_t)0x0000) /!< PVD level 2.2V /
Sergunb	0:f1834a63f7c1	1508	#define PWR_CR_PLS_2V3 ((uint16_t)0x0020) /!< PVD level 2.3V /
Sergunb	0:f1834a63f7c1	1509	#define PWR_CR_PLS_2V4 ((uint16_t)0x0040) /!< PVD level 2.4V /
Sergunb	0:f1834a63f7c1	1510	#define PWR_CR_PLS_2V5 ((uint16_t)0x0060) /!< PVD level 2.5V /
Sergunb	0:f1834a63f7c1	1511	#define PWR_CR_PLS_2V6 ((uint16_t)0x0080) /!< PVD level 2.6V /
Sergunb	0:f1834a63f7c1	1512	#define PWR_CR_PLS_2V7 ((uint16_t)0x00A0) /!< PVD level 2.7V /
Sergunb	0:f1834a63f7c1	1513	#define PWR_CR_PLS_2V8 ((uint16_t)0x00C0) /!< PVD level 2.8V /
Sergunb	0:f1834a63f7c1	1514	#define PWR_CR_PLS_2V9 ((uint16_t)0x00E0) /!< PVD level 2.9V /
Sergunb	0:f1834a63f7c1	1515
Sergunb	0:f1834a63f7c1	1516	#define PWR_CR_DBP ((uint16_t)0x0100) /!< Disable Backup Domain write protection /
Sergunb	0:f1834a63f7c1	1517
Sergunb	0:f1834a63f7c1	1518
Sergunb	0:f1834a63f7c1	1519	/***************** Bit definition for PWR_CSR register ******************/
Sergunb	0:f1834a63f7c1	1520	#define PWR_CSR_WUF ((uint16_t)0x0001) /!< Wakeup Flag /
Sergunb	0:f1834a63f7c1	1521	#define PWR_CSR_SBF ((uint16_t)0x0002) /!< Standby Flag /
Sergunb	0:f1834a63f7c1	1522	#define PWR_CSR_PVDO ((uint16_t)0x0004) /!< PVD Output /
Sergunb	0:f1834a63f7c1	1523	#define PWR_CSR_EWUP ((uint16_t)0x0100) /!< Enable WKUP pin /
Sergunb	0:f1834a63f7c1	1524
Sergunb	0:f1834a63f7c1	1525	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1526	/* */
Sergunb	0:f1834a63f7c1	1527	/* Backup registers */
Sergunb	0:f1834a63f7c1	1528	/* */
Sergunb	0:f1834a63f7c1	1529	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1530
Sergunb	0:f1834a63f7c1	1531	/***************** Bit definition for BKP_DR1 register ******************/
Sergunb	0:f1834a63f7c1	1532	#define BKP_DR1_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1533
Sergunb	0:f1834a63f7c1	1534	/***************** Bit definition for BKP_DR2 register ******************/
Sergunb	0:f1834a63f7c1	1535	#define BKP_DR2_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1536
Sergunb	0:f1834a63f7c1	1537	/***************** Bit definition for BKP_DR3 register ******************/
Sergunb	0:f1834a63f7c1	1538	#define BKP_DR3_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1539
Sergunb	0:f1834a63f7c1	1540	/***************** Bit definition for BKP_DR4 register ******************/
Sergunb	0:f1834a63f7c1	1541	#define BKP_DR4_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1542
Sergunb	0:f1834a63f7c1	1543	/***************** Bit definition for BKP_DR5 register ******************/
Sergunb	0:f1834a63f7c1	1544	#define BKP_DR5_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1545
Sergunb	0:f1834a63f7c1	1546	/***************** Bit definition for BKP_DR6 register ******************/
Sergunb	0:f1834a63f7c1	1547	#define BKP_DR6_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1548
Sergunb	0:f1834a63f7c1	1549	/***************** Bit definition for BKP_DR7 register ******************/
Sergunb	0:f1834a63f7c1	1550	#define BKP_DR7_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1551
Sergunb	0:f1834a63f7c1	1552	/***************** Bit definition for BKP_DR8 register ******************/
Sergunb	0:f1834a63f7c1	1553	#define BKP_DR8_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1554
Sergunb	0:f1834a63f7c1	1555	/***************** Bit definition for BKP_DR9 register ******************/
Sergunb	0:f1834a63f7c1	1556	#define BKP_DR9_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1557
Sergunb	0:f1834a63f7c1	1558	/***************** Bit definition for BKP_DR10 register *****************/
Sergunb	0:f1834a63f7c1	1559	#define BKP_DR10_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1560
Sergunb	0:f1834a63f7c1	1561	/***************** Bit definition for BKP_DR11 register *****************/
Sergunb	0:f1834a63f7c1	1562	#define BKP_DR11_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1563
Sergunb	0:f1834a63f7c1	1564	/***************** Bit definition for BKP_DR12 register *****************/
Sergunb	0:f1834a63f7c1	1565	#define BKP_DR12_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1566
Sergunb	0:f1834a63f7c1	1567	/***************** Bit definition for BKP_DR13 register *****************/
Sergunb	0:f1834a63f7c1	1568	#define BKP_DR13_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1569
Sergunb	0:f1834a63f7c1	1570	/***************** Bit definition for BKP_DR14 register *****************/
Sergunb	0:f1834a63f7c1	1571	#define BKP_DR14_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1572
Sergunb	0:f1834a63f7c1	1573	/***************** Bit definition for BKP_DR15 register *****************/
Sergunb	0:f1834a63f7c1	1574	#define BKP_DR15_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1575
Sergunb	0:f1834a63f7c1	1576	/***************** Bit definition for BKP_DR16 register *****************/
Sergunb	0:f1834a63f7c1	1577	#define BKP_DR16_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1578
Sergunb	0:f1834a63f7c1	1579	/***************** Bit definition for BKP_DR17 register *****************/
Sergunb	0:f1834a63f7c1	1580	#define BKP_DR17_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1581
Sergunb	0:f1834a63f7c1	1582	/**************** Bit definition for BKP_DR18 register ******************/
Sergunb	0:f1834a63f7c1	1583	#define BKP_DR18_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1584
Sergunb	0:f1834a63f7c1	1585	/***************** Bit definition for BKP_DR19 register *****************/
Sergunb	0:f1834a63f7c1	1586	#define BKP_DR19_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1587
Sergunb	0:f1834a63f7c1	1588	/***************** Bit definition for BKP_DR20 register *****************/
Sergunb	0:f1834a63f7c1	1589	#define BKP_DR20_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1590
Sergunb	0:f1834a63f7c1	1591	/***************** Bit definition for BKP_DR21 register *****************/
Sergunb	0:f1834a63f7c1	1592	#define BKP_DR21_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1593
Sergunb	0:f1834a63f7c1	1594	/***************** Bit definition for BKP_DR22 register *****************/
Sergunb	0:f1834a63f7c1	1595	#define BKP_DR22_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1596
Sergunb	0:f1834a63f7c1	1597	/***************** Bit definition for BKP_DR23 register *****************/
Sergunb	0:f1834a63f7c1	1598	#define BKP_DR23_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1599
Sergunb	0:f1834a63f7c1	1600	/***************** Bit definition for BKP_DR24 register *****************/
Sergunb	0:f1834a63f7c1	1601	#define BKP_DR24_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1602
Sergunb	0:f1834a63f7c1	1603	/***************** Bit definition for BKP_DR25 register *****************/
Sergunb	0:f1834a63f7c1	1604	#define BKP_DR25_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1605
Sergunb	0:f1834a63f7c1	1606	/***************** Bit definition for BKP_DR26 register *****************/
Sergunb	0:f1834a63f7c1	1607	#define BKP_DR26_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1608
Sergunb	0:f1834a63f7c1	1609	/***************** Bit definition for BKP_DR27 register *****************/
Sergunb	0:f1834a63f7c1	1610	#define BKP_DR27_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1611
Sergunb	0:f1834a63f7c1	1612	/***************** Bit definition for BKP_DR28 register *****************/
Sergunb	0:f1834a63f7c1	1613	#define BKP_DR28_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1614
Sergunb	0:f1834a63f7c1	1615	/***************** Bit definition for BKP_DR29 register *****************/
Sergunb	0:f1834a63f7c1	1616	#define BKP_DR29_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1617
Sergunb	0:f1834a63f7c1	1618	/***************** Bit definition for BKP_DR30 register *****************/
Sergunb	0:f1834a63f7c1	1619	#define BKP_DR30_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1620
Sergunb	0:f1834a63f7c1	1621	/***************** Bit definition for BKP_DR31 register *****************/
Sergunb	0:f1834a63f7c1	1622	#define BKP_DR31_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1623
Sergunb	0:f1834a63f7c1	1624	/***************** Bit definition for BKP_DR32 register *****************/
Sergunb	0:f1834a63f7c1	1625	#define BKP_DR32_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1626
Sergunb	0:f1834a63f7c1	1627	/***************** Bit definition for BKP_DR33 register *****************/
Sergunb	0:f1834a63f7c1	1628	#define BKP_DR33_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1629
Sergunb	0:f1834a63f7c1	1630	/***************** Bit definition for BKP_DR34 register *****************/
Sergunb	0:f1834a63f7c1	1631	#define BKP_DR34_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1632
Sergunb	0:f1834a63f7c1	1633	/***************** Bit definition for BKP_DR35 register *****************/
Sergunb	0:f1834a63f7c1	1634	#define BKP_DR35_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1635
Sergunb	0:f1834a63f7c1	1636	/***************** Bit definition for BKP_DR36 register *****************/
Sergunb	0:f1834a63f7c1	1637	#define BKP_DR36_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1638
Sergunb	0:f1834a63f7c1	1639	/***************** Bit definition for BKP_DR37 register *****************/
Sergunb	0:f1834a63f7c1	1640	#define BKP_DR37_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1641
Sergunb	0:f1834a63f7c1	1642	/***************** Bit definition for BKP_DR38 register *****************/
Sergunb	0:f1834a63f7c1	1643	#define BKP_DR38_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1644
Sergunb	0:f1834a63f7c1	1645	/***************** Bit definition for BKP_DR39 register *****************/
Sergunb	0:f1834a63f7c1	1646	#define BKP_DR39_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1647
Sergunb	0:f1834a63f7c1	1648	/***************** Bit definition for BKP_DR40 register *****************/
Sergunb	0:f1834a63f7c1	1649	#define BKP_DR40_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1650
Sergunb	0:f1834a63f7c1	1651	/***************** Bit definition for BKP_DR41 register *****************/
Sergunb	0:f1834a63f7c1	1652	#define BKP_DR41_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1653
Sergunb	0:f1834a63f7c1	1654	/***************** Bit definition for BKP_DR42 register *****************/
Sergunb	0:f1834a63f7c1	1655	#define BKP_DR42_D ((uint16_t)0xFFFF) /!< Backup data /
Sergunb	0:f1834a63f7c1	1656
Sergunb	0:f1834a63f7c1	1657	/**************** Bit definition for BKP_RTCCR register *****************/
Sergunb	0:f1834a63f7c1	1658	#define BKP_RTCCR_CAL ((uint16_t)0x007F) /!< Calibration value /
Sergunb	0:f1834a63f7c1	1659	#define BKP_RTCCR_CCO ((uint16_t)0x0080) /!< Calibration Clock Output /
Sergunb	0:f1834a63f7c1	1660	#define BKP_RTCCR_ASOE ((uint16_t)0x0100) /!< Alarm or Second Output Enable /
Sergunb	0:f1834a63f7c1	1661	#define BKP_RTCCR_ASOS ((uint16_t)0x0200) /!< Alarm or Second Output Selection /
Sergunb	0:f1834a63f7c1	1662
Sergunb	0:f1834a63f7c1	1663	/****************** Bit definition for BKP_CR register ******************/
Sergunb	0:f1834a63f7c1	1664	#define BKP_CR_TPE ((uint8_t)0x01) /!< TAMPER pin enable /
Sergunb	0:f1834a63f7c1	1665	#define BKP_CR_TPAL ((uint8_t)0x02) /!< TAMPER pin active level /
Sergunb	0:f1834a63f7c1	1666
Sergunb	0:f1834a63f7c1	1667	/***************** Bit definition for BKP_CSR register ******************/
Sergunb	0:f1834a63f7c1	1668	#define BKP_CSR_CTE ((uint16_t)0x0001) /!< Clear Tamper event /
Sergunb	0:f1834a63f7c1	1669	#define BKP_CSR_CTI ((uint16_t)0x0002) /!< Clear Tamper Interrupt /
Sergunb	0:f1834a63f7c1	1670	#define BKP_CSR_TPIE ((uint16_t)0x0004) /!< TAMPER Pin interrupt enable /
Sergunb	0:f1834a63f7c1	1671	#define BKP_CSR_TEF ((uint16_t)0x0100) /!< Tamper Event Flag /
Sergunb	0:f1834a63f7c1	1672	#define BKP_CSR_TIF ((uint16_t)0x0200) /!< Tamper Interrupt Flag /
Sergunb	0:f1834a63f7c1	1673
Sergunb	0:f1834a63f7c1	1674	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1675	/* */
Sergunb	0:f1834a63f7c1	1676	/* Reset and Clock Control */
Sergunb	0:f1834a63f7c1	1677	/* */
Sergunb	0:f1834a63f7c1	1678	/******************************************************************************/
Sergunb	0:f1834a63f7c1	1679
Sergunb	0:f1834a63f7c1	1680	/****************** Bit definition for RCC_CR register ******************/
Sergunb	0:f1834a63f7c1	1681	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
Sergunb	0:f1834a63f7c1	1682	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
Sergunb	0:f1834a63f7c1	1683	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
Sergunb	0:f1834a63f7c1	1684	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
Sergunb	0:f1834a63f7c1	1685	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
Sergunb	0:f1834a63f7c1	1686	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
Sergunb	0:f1834a63f7c1	1687	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
Sergunb	0:f1834a63f7c1	1688	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
Sergunb	0:f1834a63f7c1	1689	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
Sergunb	0:f1834a63f7c1	1690	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
Sergunb	0:f1834a63f7c1	1691
Sergunb	0:f1834a63f7c1	1692	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	1693	#define RCC_CR_PLL2ON ((uint32_t)0x04000000) /!< PLL2 enable /
Sergunb	0:f1834a63f7c1	1694	#define RCC_CR_PLL2RDY ((uint32_t)0x08000000) /!< PLL2 clock ready flag /
Sergunb	0:f1834a63f7c1	1695	#define RCC_CR_PLL3ON ((uint32_t)0x10000000) /!< PLL3 enable /
Sergunb	0:f1834a63f7c1	1696	#define RCC_CR_PLL3RDY ((uint32_t)0x20000000) /!< PLL3 clock ready flag /
Sergunb	0:f1834a63f7c1	1697	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	1698
Sergunb	0:f1834a63f7c1	1699	/***************** Bit definition for RCC_CFGR register *****************/
Sergunb	0:f1834a63f7c1	1700	/!< SW configuration /
Sergunb	0:f1834a63f7c1	1701	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
Sergunb	0:f1834a63f7c1	1702	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1703	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1704
Sergunb	0:f1834a63f7c1	1705	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
Sergunb	0:f1834a63f7c1	1706	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
Sergunb	0:f1834a63f7c1	1707	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
Sergunb	0:f1834a63f7c1	1708
Sergunb	0:f1834a63f7c1	1709	/!< SWS configuration /
Sergunb	0:f1834a63f7c1	1710	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
Sergunb	0:f1834a63f7c1	1711	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1712	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1713
Sergunb	0:f1834a63f7c1	1714	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
Sergunb	0:f1834a63f7c1	1715	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
Sergunb	0:f1834a63f7c1	1716	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
Sergunb	0:f1834a63f7c1	1717
Sergunb	0:f1834a63f7c1	1718	/!< HPRE configuration /
Sergunb	0:f1834a63f7c1	1719	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
Sergunb	0:f1834a63f7c1	1720	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1721	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1722	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	1723	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	1724
Sergunb	0:f1834a63f7c1	1725	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
Sergunb	0:f1834a63f7c1	1726	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
Sergunb	0:f1834a63f7c1	1727	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
Sergunb	0:f1834a63f7c1	1728	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
Sergunb	0:f1834a63f7c1	1729	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
Sergunb	0:f1834a63f7c1	1730	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
Sergunb	0:f1834a63f7c1	1731	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
Sergunb	0:f1834a63f7c1	1732	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
Sergunb	0:f1834a63f7c1	1733	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
Sergunb	0:f1834a63f7c1	1734
Sergunb	0:f1834a63f7c1	1735	/!< PPRE1 configuration /
Sergunb	0:f1834a63f7c1	1736	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
Sergunb	0:f1834a63f7c1	1737	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1738	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1739	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	1740
Sergunb	0:f1834a63f7c1	1741	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
Sergunb	0:f1834a63f7c1	1742	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
Sergunb	0:f1834a63f7c1	1743	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
Sergunb	0:f1834a63f7c1	1744	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
Sergunb	0:f1834a63f7c1	1745	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
Sergunb	0:f1834a63f7c1	1746
Sergunb	0:f1834a63f7c1	1747	/!< PPRE2 configuration /
Sergunb	0:f1834a63f7c1	1748	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
Sergunb	0:f1834a63f7c1	1749	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1750	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1751	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	1752
Sergunb	0:f1834a63f7c1	1753	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
Sergunb	0:f1834a63f7c1	1754	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
Sergunb	0:f1834a63f7c1	1755	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
Sergunb	0:f1834a63f7c1	1756	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
Sergunb	0:f1834a63f7c1	1757	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
Sergunb	0:f1834a63f7c1	1758
Sergunb	0:f1834a63f7c1	1759	/!< ADCPPRE configuration /
Sergunb	0:f1834a63f7c1	1760	#define RCC_CFGR_ADCPRE ((uint32_t)0x0000C000) /!< ADCPRE[1:0] bits (ADC prescaler) /
Sergunb	0:f1834a63f7c1	1761	#define RCC_CFGR_ADCPRE_0 ((uint32_t)0x00004000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1762	#define RCC_CFGR_ADCPRE_1 ((uint32_t)0x00008000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1763
Sergunb	0:f1834a63f7c1	1764	#define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /!< PCLK2 divided by 2 /
Sergunb	0:f1834a63f7c1	1765	#define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /!< PCLK2 divided by 4 /
Sergunb	0:f1834a63f7c1	1766	#define RCC_CFGR_ADCPRE_DIV6 ((uint32_t)0x00008000) /!< PCLK2 divided by 6 /
Sergunb	0:f1834a63f7c1	1767	#define RCC_CFGR_ADCPRE_DIV8 ((uint32_t)0x0000C000) /!< PCLK2 divided by 8 /
Sergunb	0:f1834a63f7c1	1768
Sergunb	0:f1834a63f7c1	1769	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
Sergunb	0:f1834a63f7c1	1770
Sergunb	0:f1834a63f7c1	1771	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
Sergunb	0:f1834a63f7c1	1772
Sergunb	0:f1834a63f7c1	1773	/!< PLLMUL configuration /
Sergunb	0:f1834a63f7c1	1774	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
Sergunb	0:f1834a63f7c1	1775	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1776	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1777	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	1778	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	1779
Sergunb	0:f1834a63f7c1	1780	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	1781	#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
Sergunb	0:f1834a63f7c1	1782	#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /!< PREDIV1 clock selected as PLL entry clock source /
Sergunb	0:f1834a63f7c1	1783
Sergunb	0:f1834a63f7c1	1784	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
Sergunb	0:f1834a63f7c1	1785	#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
Sergunb	0:f1834a63f7c1	1786
Sergunb	0:f1834a63f7c1	1787	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock 4 */
Sergunb	0:f1834a63f7c1	1788	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock 5 */
Sergunb	0:f1834a63f7c1	1789	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock 6 */
Sergunb	0:f1834a63f7c1	1790	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock 7 */
Sergunb	0:f1834a63f7c1	1791	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock 8 */
Sergunb	0:f1834a63f7c1	1792	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock 9 */
Sergunb	0:f1834a63f7c1	1793	#define RCC_CFGR_PLLMULL6_5 ((uint32_t)0x00340000) /!< PLL input clock 6.5 */
Sergunb	0:f1834a63f7c1	1794
Sergunb	0:f1834a63f7c1	1795	#define RCC_CFGR_OTGFSPRE ((uint32_t)0x00400000) /!< USB OTG FS prescaler /
Sergunb	0:f1834a63f7c1	1796
Sergunb	0:f1834a63f7c1	1797	/!< MCO configuration /
Sergunb	0:f1834a63f7c1	1798	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[3:0] bits (Microcontroller Clock Output) /
Sergunb	0:f1834a63f7c1	1799	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1800	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1801	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	1802	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	1803
Sergunb	0:f1834a63f7c1	1804	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Sergunb	0:f1834a63f7c1	1805	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1806	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1807	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1808	#define RCC_CFGR_MCO_PLLCLK_Div2 ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
Sergunb	0:f1834a63f7c1	1809	#define RCC_CFGR_MCO_PLL2CLK ((uint32_t)0x08000000) /!< PLL2 clock selected as MCO source/
Sergunb	0:f1834a63f7c1	1810	#define RCC_CFGR_MCO_PLL3CLK_Div2 ((uint32_t)0x09000000) /!< PLL3 clock divided by 2 selected as MCO source/
Sergunb	0:f1834a63f7c1	1811	#define RCC_CFGR_MCO_Ext_HSE ((uint32_t)0x0A000000) /!< XT1 external 3-25 MHz oscillator clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1812	#define RCC_CFGR_MCO_PLL3CLK ((uint32_t)0x0B000000) /!< PLL3 clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1813	#elif defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	1814	#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
Sergunb	0:f1834a63f7c1	1815	#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /!< PREDIV1 clock selected as PLL entry clock source /
Sergunb	0:f1834a63f7c1	1816
Sergunb	0:f1834a63f7c1	1817	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
Sergunb	0:f1834a63f7c1	1818	#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
Sergunb	0:f1834a63f7c1	1819
Sergunb	0:f1834a63f7c1	1820	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
Sergunb	0:f1834a63f7c1	1821	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
Sergunb	0:f1834a63f7c1	1822	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
Sergunb	0:f1834a63f7c1	1823	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
Sergunb	0:f1834a63f7c1	1824	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
Sergunb	0:f1834a63f7c1	1825	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
Sergunb	0:f1834a63f7c1	1826	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
Sergunb	0:f1834a63f7c1	1827	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
Sergunb	0:f1834a63f7c1	1828	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
Sergunb	0:f1834a63f7c1	1829	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
Sergunb	0:f1834a63f7c1	1830	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
Sergunb	0:f1834a63f7c1	1831	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
Sergunb	0:f1834a63f7c1	1832	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
Sergunb	0:f1834a63f7c1	1833	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
Sergunb	0:f1834a63f7c1	1834	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
Sergunb	0:f1834a63f7c1	1835
Sergunb	0:f1834a63f7c1	1836	/!< MCO configuration /
Sergunb	0:f1834a63f7c1	1837	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
Sergunb	0:f1834a63f7c1	1838	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1839	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1840	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	1841
Sergunb	0:f1834a63f7c1	1842	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Sergunb	0:f1834a63f7c1	1843	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1844	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1845	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1846	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
Sergunb	0:f1834a63f7c1	1847	#else
Sergunb	0:f1834a63f7c1	1848	#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
Sergunb	0:f1834a63f7c1	1849	#define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /!< HSE clock selected as PLL entry clock source /
Sergunb	0:f1834a63f7c1	1850
Sergunb	0:f1834a63f7c1	1851	#define RCC_CFGR_PLLXTPRE_HSE ((uint32_t)0x00000000) /!< HSE clock not divided for PLL entry /
Sergunb	0:f1834a63f7c1	1852	#define RCC_CFGR_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /!< HSE clock divided by 2 for PLL entry /
Sergunb	0:f1834a63f7c1	1853
Sergunb	0:f1834a63f7c1	1854	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
Sergunb	0:f1834a63f7c1	1855	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
Sergunb	0:f1834a63f7c1	1856	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
Sergunb	0:f1834a63f7c1	1857	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
Sergunb	0:f1834a63f7c1	1858	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
Sergunb	0:f1834a63f7c1	1859	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
Sergunb	0:f1834a63f7c1	1860	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
Sergunb	0:f1834a63f7c1	1861	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
Sergunb	0:f1834a63f7c1	1862	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
Sergunb	0:f1834a63f7c1	1863	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
Sergunb	0:f1834a63f7c1	1864	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
Sergunb	0:f1834a63f7c1	1865	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
Sergunb	0:f1834a63f7c1	1866	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
Sergunb	0:f1834a63f7c1	1867	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
Sergunb	0:f1834a63f7c1	1868	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
Sergunb	0:f1834a63f7c1	1869	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB Device prescaler /
Sergunb	0:f1834a63f7c1	1870
Sergunb	0:f1834a63f7c1	1871	/!< MCO configuration /
Sergunb	0:f1834a63f7c1	1872	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
Sergunb	0:f1834a63f7c1	1873	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	1874	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	1875	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	1876
Sergunb	0:f1834a63f7c1	1877	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Sergunb	0:f1834a63f7c1	1878	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1879	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1880	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
Sergunb	0:f1834a63f7c1	1881	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
Sergunb	0:f1834a63f7c1	1882	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	1883
Sergunb	0:f1834a63f7c1	1884	/!<*************** Bit definition for RCC_CIR register ******************/
Sergunb	0:f1834a63f7c1	1885	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
Sergunb	0:f1834a63f7c1	1886	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
Sergunb	0:f1834a63f7c1	1887	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
Sergunb	0:f1834a63f7c1	1888	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
Sergunb	0:f1834a63f7c1	1889	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
Sergunb	0:f1834a63f7c1	1890	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
Sergunb	0:f1834a63f7c1	1891	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
Sergunb	0:f1834a63f7c1	1892	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
Sergunb	0:f1834a63f7c1	1893	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
Sergunb	0:f1834a63f7c1	1894	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
Sergunb	0:f1834a63f7c1	1895	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
Sergunb	0:f1834a63f7c1	1896	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
Sergunb	0:f1834a63f7c1	1897	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
Sergunb	0:f1834a63f7c1	1898	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
Sergunb	0:f1834a63f7c1	1899	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
Sergunb	0:f1834a63f7c1	1900	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
Sergunb	0:f1834a63f7c1	1901	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
Sergunb	0:f1834a63f7c1	1902
Sergunb	0:f1834a63f7c1	1903	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	1904	#define RCC_CIR_PLL2RDYF ((uint32_t)0x00000020) /!< PLL2 Ready Interrupt flag /
Sergunb	0:f1834a63f7c1	1905	#define RCC_CIR_PLL3RDYF ((uint32_t)0x00000040) /!< PLL3 Ready Interrupt flag /
Sergunb	0:f1834a63f7c1	1906	#define RCC_CIR_PLL2RDYIE ((uint32_t)0x00002000) /!< PLL2 Ready Interrupt Enable /
Sergunb	0:f1834a63f7c1	1907	#define RCC_CIR_PLL3RDYIE ((uint32_t)0x00004000) /!< PLL3 Ready Interrupt Enable /
Sergunb	0:f1834a63f7c1	1908	#define RCC_CIR_PLL2RDYC ((uint32_t)0x00200000) /!< PLL2 Ready Interrupt Clear /
Sergunb	0:f1834a63f7c1	1909	#define RCC_CIR_PLL3RDYC ((uint32_t)0x00400000) /!< PLL3 Ready Interrupt Clear /
Sergunb	0:f1834a63f7c1	1910	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	1911
Sergunb	0:f1834a63f7c1	1912	/*************** Bit definition for RCC_APB2RSTR register ***************/
Sergunb	0:f1834a63f7c1	1913	#define RCC_APB2RSTR_AFIORST ((uint32_t)0x00000001) /!< Alternate Function I/O reset /
Sergunb	0:f1834a63f7c1	1914	#define RCC_APB2RSTR_IOPARST ((uint32_t)0x00000004) /!< I/O port A reset /
Sergunb	0:f1834a63f7c1	1915	#define RCC_APB2RSTR_IOPBRST ((uint32_t)0x00000008) /!< I/O port B reset /
Sergunb	0:f1834a63f7c1	1916	#define RCC_APB2RSTR_IOPCRST ((uint32_t)0x00000010) /!< I/O port C reset /
Sergunb	0:f1834a63f7c1	1917	#define RCC_APB2RSTR_IOPDRST ((uint32_t)0x00000020) /!< I/O port D reset /
Sergunb	0:f1834a63f7c1	1918	#define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /!< ADC 1 interface reset /
Sergunb	0:f1834a63f7c1	1919
Sergunb	0:f1834a63f7c1	1920	#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	1921	#define RCC_APB2RSTR_ADC2RST ((uint32_t)0x00000400) /!< ADC 2 interface reset /
Sergunb	0:f1834a63f7c1	1922	#endif
Sergunb	0:f1834a63f7c1	1923
Sergunb	0:f1834a63f7c1	1924	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 Timer reset /
Sergunb	0:f1834a63f7c1	1925	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI 1 reset /
Sergunb	0:f1834a63f7c1	1926	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
Sergunb	0:f1834a63f7c1	1927
Sergunb	0:f1834a63f7c1	1928	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	1929	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 Timer reset /
Sergunb	0:f1834a63f7c1	1930	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 Timer reset /
Sergunb	0:f1834a63f7c1	1931	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 Timer reset /
Sergunb	0:f1834a63f7c1	1932	#endif
Sergunb	0:f1834a63f7c1	1933
Sergunb	0:f1834a63f7c1	1934	#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
Sergunb	0:f1834a63f7c1	1935	#define RCC_APB2RSTR_IOPERST ((uint32_t)0x00000040) /!< I/O port E reset /
Sergunb	0:f1834a63f7c1	1936	#endif /* STM32F10X_LD && STM32F10X_LD_VL */
Sergunb	0:f1834a63f7c1	1937
Sergunb	0:f1834a63f7c1	1938	#if defined (STM32F10X_HD) \|\| defined (STM32F10X_XL)
Sergunb	0:f1834a63f7c1	1939	#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /!< I/O port F reset /
Sergunb	0:f1834a63f7c1	1940	#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /!< I/O port G reset /
Sergunb	0:f1834a63f7c1	1941	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00002000) /!< TIM8 Timer reset /
Sergunb	0:f1834a63f7c1	1942	#define RCC_APB2RSTR_ADC3RST ((uint32_t)0x00008000) /!< ADC3 interface reset /
Sergunb	0:f1834a63f7c1	1943	#endif
Sergunb	0:f1834a63f7c1	1944
Sergunb	0:f1834a63f7c1	1945	#if defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	1946	#define RCC_APB2RSTR_IOPFRST ((uint32_t)0x00000080) /!< I/O port F reset /
Sergunb	0:f1834a63f7c1	1947	#define RCC_APB2RSTR_IOPGRST ((uint32_t)0x00000100) /!< I/O port G reset /
Sergunb	0:f1834a63f7c1	1948	#endif
Sergunb	0:f1834a63f7c1	1949
Sergunb	0:f1834a63f7c1	1950	#ifdef STM32F10X_XL
Sergunb	0:f1834a63f7c1	1951	#define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00080000) /!< TIM9 Timer reset /
Sergunb	0:f1834a63f7c1	1952	#define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00100000) /!< TIM10 Timer reset /
Sergunb	0:f1834a63f7c1	1953	#define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00200000) /!< TIM11 Timer reset /
Sergunb	0:f1834a63f7c1	1954	#endif /* STM32F10X_XL */
Sergunb	0:f1834a63f7c1	1955
Sergunb	0:f1834a63f7c1	1956	/*************** Bit definition for RCC_APB1RSTR register ***************/
Sergunb	0:f1834a63f7c1	1957	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
Sergunb	0:f1834a63f7c1	1958	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
Sergunb	0:f1834a63f7c1	1959	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
Sergunb	0:f1834a63f7c1	1960	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
Sergunb	0:f1834a63f7c1	1961	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
Sergunb	0:f1834a63f7c1	1962
Sergunb	0:f1834a63f7c1	1963	#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	1964	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /!< CAN1 reset /
Sergunb	0:f1834a63f7c1	1965	#endif
Sergunb	0:f1834a63f7c1	1966
Sergunb	0:f1834a63f7c1	1967	#define RCC_APB1RSTR_BKPRST ((uint32_t)0x08000000) /!< Backup interface reset /
Sergunb	0:f1834a63f7c1	1968	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< Power interface reset /
Sergunb	0:f1834a63f7c1	1969
Sergunb	0:f1834a63f7c1	1970	#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
Sergunb	0:f1834a63f7c1	1971	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
Sergunb	0:f1834a63f7c1	1972	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI 2 reset /
Sergunb	0:f1834a63f7c1	1973	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
Sergunb	0:f1834a63f7c1	1974	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
Sergunb	0:f1834a63f7c1	1975	#endif /* STM32F10X_LD && STM32F10X_LD_VL */
Sergunb	0:f1834a63f7c1	1976
Sergunb	0:f1834a63f7c1	1977	#if defined (STM32F10X_HD) \|\| defined (STM32F10X_MD) \|\| defined (STM32F10X_LD) \|\| defined (STM32F10X_XL)
Sergunb	0:f1834a63f7c1	1978	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB Device reset /
Sergunb	0:f1834a63f7c1	1979	#endif
Sergunb	0:f1834a63f7c1	1980
Sergunb	0:f1834a63f7c1	1981	#if defined (STM32F10X_HD) \|\| defined (STM32F10X_CL) \|\| defined (STM32F10X_XL)
Sergunb	0:f1834a63f7c1	1982	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /!< Timer 5 reset /
Sergunb	0:f1834a63f7c1	1983	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
Sergunb	0:f1834a63f7c1	1984	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
Sergunb	0:f1834a63f7c1	1985	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI 3 reset /
Sergunb	0:f1834a63f7c1	1986	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /!< UART 4 reset /
Sergunb	0:f1834a63f7c1	1987	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /!< UART 5 reset /
Sergunb	0:f1834a63f7c1	1988	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC interface reset /
Sergunb	0:f1834a63f7c1	1989	#endif
Sergunb	0:f1834a63f7c1	1990
Sergunb	0:f1834a63f7c1	1991	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	1992	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
Sergunb	0:f1834a63f7c1	1993	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
Sergunb	0:f1834a63f7c1	1994	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC interface reset /
Sergunb	0:f1834a63f7c1	1995	#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /!< CEC interface reset /
Sergunb	0:f1834a63f7c1	1996	#endif
Sergunb	0:f1834a63f7c1	1997
Sergunb	0:f1834a63f7c1	1998	#if defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	1999	#define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /!< Timer 5 reset /
Sergunb	0:f1834a63f7c1	2000	#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /!< TIM12 Timer reset /
Sergunb	0:f1834a63f7c1	2001	#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /!< TIM13 Timer reset /
Sergunb	0:f1834a63f7c1	2002	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< TIM14 Timer reset /
Sergunb	0:f1834a63f7c1	2003	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI 3 reset /
Sergunb	0:f1834a63f7c1	2004	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /!< UART 4 reset /
Sergunb	0:f1834a63f7c1	2005	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /!< UART 5 reset /
Sergunb	0:f1834a63f7c1	2006	#endif
Sergunb	0:f1834a63f7c1	2007
Sergunb	0:f1834a63f7c1	2008	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	2009	#define RCC_APB1RSTR_CAN2RST ((uint32_t)0x04000000) /!< CAN2 reset /
Sergunb	0:f1834a63f7c1	2010	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	2011
Sergunb	0:f1834a63f7c1	2012	#ifdef STM32F10X_XL
Sergunb	0:f1834a63f7c1	2013	#define RCC_APB1RSTR_TIM12RST ((uint32_t)0x00000040) /!< TIM12 Timer reset /
Sergunb	0:f1834a63f7c1	2014	#define RCC_APB1RSTR_TIM13RST ((uint32_t)0x00000080) /!< TIM13 Timer reset /
Sergunb	0:f1834a63f7c1	2015	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< TIM14 Timer reset /
Sergunb	0:f1834a63f7c1	2016	#endif /* STM32F10X_XL */
Sergunb	0:f1834a63f7c1	2017
Sergunb	0:f1834a63f7c1	2018	/**************** Bit definition for RCC_AHBENR register ****************/
Sergunb	0:f1834a63f7c1	2019	#define RCC_AHBENR_DMA1EN ((uint16_t)0x0001) /!< DMA1 clock enable /
Sergunb	0:f1834a63f7c1	2020	#define RCC_AHBENR_SRAMEN ((uint16_t)0x0004) /!< SRAM interface clock enable /
Sergunb	0:f1834a63f7c1	2021	#define RCC_AHBENR_FLITFEN ((uint16_t)0x0010) /!< FLITF clock enable /
Sergunb	0:f1834a63f7c1	2022	#define RCC_AHBENR_CRCEN ((uint16_t)0x0040) /!< CRC clock enable /
Sergunb	0:f1834a63f7c1	2023
Sergunb	0:f1834a63f7c1	2024	#if defined (STM32F10X_HD) \|\| defined (STM32F10X_CL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	2025	#define RCC_AHBENR_DMA2EN ((uint16_t)0x0002) /!< DMA2 clock enable /
Sergunb	0:f1834a63f7c1	2026	#endif
Sergunb	0:f1834a63f7c1	2027
Sergunb	0:f1834a63f7c1	2028	#if defined (STM32F10X_HD) \|\| defined (STM32F10X_XL)
Sergunb	0:f1834a63f7c1	2029	#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /!< FSMC clock enable /
Sergunb	0:f1834a63f7c1	2030	#define RCC_AHBENR_SDIOEN ((uint16_t)0x0400) /!< SDIO clock enable /
Sergunb	0:f1834a63f7c1	2031	#endif
Sergunb	0:f1834a63f7c1	2032
Sergunb	0:f1834a63f7c1	2033	#if defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	2034	#define RCC_AHBENR_FSMCEN ((uint16_t)0x0100) /!< FSMC clock enable /
Sergunb	0:f1834a63f7c1	2035	#endif
Sergunb	0:f1834a63f7c1	2036
Sergunb	0:f1834a63f7c1	2037	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	2038	#define RCC_AHBENR_OTGFSEN ((uint32_t)0x00001000) /!< USB OTG FS clock enable /
Sergunb	0:f1834a63f7c1	2039	#define RCC_AHBENR_ETHMACEN ((uint32_t)0x00004000) /!< ETHERNET MAC clock enable /
Sergunb	0:f1834a63f7c1	2040	#define RCC_AHBENR_ETHMACTXEN ((uint32_t)0x00008000) /!< ETHERNET MAC Tx clock enable /
Sergunb	0:f1834a63f7c1	2041	#define RCC_AHBENR_ETHMACRXEN ((uint32_t)0x00010000) /!< ETHERNET MAC Rx clock enable /
Sergunb	0:f1834a63f7c1	2042	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	2043
Sergunb	0:f1834a63f7c1	2044	/**************** Bit definition for RCC_APB2ENR register ***************/
Sergunb	0:f1834a63f7c1	2045	#define RCC_APB2ENR_AFIOEN ((uint32_t)0x00000001) /!< Alternate Function I/O clock enable /
Sergunb	0:f1834a63f7c1	2046	#define RCC_APB2ENR_IOPAEN ((uint32_t)0x00000004) /!< I/O port A clock enable /
Sergunb	0:f1834a63f7c1	2047	#define RCC_APB2ENR_IOPBEN ((uint32_t)0x00000008) /!< I/O port B clock enable /
Sergunb	0:f1834a63f7c1	2048	#define RCC_APB2ENR_IOPCEN ((uint32_t)0x00000010) /!< I/O port C clock enable /
Sergunb	0:f1834a63f7c1	2049	#define RCC_APB2ENR_IOPDEN ((uint32_t)0x00000020) /!< I/O port D clock enable /
Sergunb	0:f1834a63f7c1	2050	#define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /!< ADC 1 interface clock enable /
Sergunb	0:f1834a63f7c1	2051
Sergunb	0:f1834a63f7c1	2052	#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	2053	#define RCC_APB2ENR_ADC2EN ((uint32_t)0x00000400) /!< ADC 2 interface clock enable /
Sergunb	0:f1834a63f7c1	2054	#endif
Sergunb	0:f1834a63f7c1	2055
Sergunb	0:f1834a63f7c1	2056	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 Timer clock enable /
Sergunb	0:f1834a63f7c1	2057	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI 1 clock enable /
Sergunb	0:f1834a63f7c1	2058	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
Sergunb	0:f1834a63f7c1	2059
Sergunb	0:f1834a63f7c1	2060	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	2061	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 Timer clock enable /
Sergunb	0:f1834a63f7c1	2062	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 Timer clock enable /
Sergunb	0:f1834a63f7c1	2063	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 Timer clock enable /
Sergunb	0:f1834a63f7c1	2064	#endif
Sergunb	0:f1834a63f7c1	2065
Sergunb	0:f1834a63f7c1	2066	#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
Sergunb	0:f1834a63f7c1	2067	#define RCC_APB2ENR_IOPEEN ((uint32_t)0x00000040) /!< I/O port E clock enable /
Sergunb	0:f1834a63f7c1	2068	#endif /* STM32F10X_LD && STM32F10X_LD_VL */
Sergunb	0:f1834a63f7c1	2069
Sergunb	0:f1834a63f7c1	2070	#if defined (STM32F10X_HD) \|\| defined (STM32F10X_XL)
Sergunb	0:f1834a63f7c1	2071	#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /!< I/O port F clock enable /
Sergunb	0:f1834a63f7c1	2072	#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /!< I/O port G clock enable /
Sergunb	0:f1834a63f7c1	2073	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /!< TIM8 Timer clock enable /
Sergunb	0:f1834a63f7c1	2074	#define RCC_APB2ENR_ADC3EN ((uint32_t)0x00008000) /!< DMA1 clock enable /
Sergunb	0:f1834a63f7c1	2075	#endif
Sergunb	0:f1834a63f7c1	2076
Sergunb	0:f1834a63f7c1	2077	#if defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	2078	#define RCC_APB2ENR_IOPFEN ((uint32_t)0x00000080) /!< I/O port F clock enable /
Sergunb	0:f1834a63f7c1	2079	#define RCC_APB2ENR_IOPGEN ((uint32_t)0x00000100) /!< I/O port G clock enable /
Sergunb	0:f1834a63f7c1	2080	#endif
Sergunb	0:f1834a63f7c1	2081
Sergunb	0:f1834a63f7c1	2082	#ifdef STM32F10X_XL
Sergunb	0:f1834a63f7c1	2083	#define RCC_APB2ENR_TIM9EN ((uint32_t)0x00080000) /!< TIM9 Timer clock enable /
Sergunb	0:f1834a63f7c1	2084	#define RCC_APB2ENR_TIM10EN ((uint32_t)0x00100000) /!< TIM10 Timer clock enable /
Sergunb	0:f1834a63f7c1	2085	#define RCC_APB2ENR_TIM11EN ((uint32_t)0x00200000) /!< TIM11 Timer clock enable /
Sergunb	0:f1834a63f7c1	2086	#endif
Sergunb	0:f1834a63f7c1	2087
Sergunb	0:f1834a63f7c1	2088	/*************** Bit definition for RCC_APB1ENR register ****************/
Sergunb	0:f1834a63f7c1	2089	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enabled/
Sergunb	0:f1834a63f7c1	2090	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
Sergunb	0:f1834a63f7c1	2091	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
Sergunb	0:f1834a63f7c1	2092	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
Sergunb	0:f1834a63f7c1	2093	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
Sergunb	0:f1834a63f7c1	2094
Sergunb	0:f1834a63f7c1	2095	#if !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	2096	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /!< CAN1 clock enable /
Sergunb	0:f1834a63f7c1	2097	#endif
Sergunb	0:f1834a63f7c1	2098
Sergunb	0:f1834a63f7c1	2099	#define RCC_APB1ENR_BKPEN ((uint32_t)0x08000000) /!< Backup interface clock enable /
Sergunb	0:f1834a63f7c1	2100	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< Power interface clock enable /
Sergunb	0:f1834a63f7c1	2101
Sergunb	0:f1834a63f7c1	2102	#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL)
Sergunb	0:f1834a63f7c1	2103	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
Sergunb	0:f1834a63f7c1	2104	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI 2 clock enable /
Sergunb	0:f1834a63f7c1	2105	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
Sergunb	0:f1834a63f7c1	2106	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
Sergunb	0:f1834a63f7c1	2107	#endif /* STM32F10X_LD && STM32F10X_LD_VL */
Sergunb	0:f1834a63f7c1	2108
Sergunb	0:f1834a63f7c1	2109	#if defined (STM32F10X_HD) \|\| defined (STM32F10X_MD) \|\| defined (STM32F10X_LD)
Sergunb	0:f1834a63f7c1	2110	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB Device clock enable /
Sergunb	0:f1834a63f7c1	2111	#endif
Sergunb	0:f1834a63f7c1	2112
Sergunb	0:f1834a63f7c1	2113	#if defined (STM32F10X_HD) \|\| defined (STM32F10X_CL)
Sergunb	0:f1834a63f7c1	2114	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /!< Timer 5 clock enable /
Sergunb	0:f1834a63f7c1	2115	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
Sergunb	0:f1834a63f7c1	2116	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
Sergunb	0:f1834a63f7c1	2117	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI 3 clock enable /
Sergunb	0:f1834a63f7c1	2118	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /!< UART 4 clock enable /
Sergunb	0:f1834a63f7c1	2119	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /!< UART 5 clock enable /
Sergunb	0:f1834a63f7c1	2120	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC interface clock enable /
Sergunb	0:f1834a63f7c1	2121	#endif
Sergunb	0:f1834a63f7c1	2122
Sergunb	0:f1834a63f7c1	2123	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	2124	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
Sergunb	0:f1834a63f7c1	2125	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
Sergunb	0:f1834a63f7c1	2126	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC interface clock enable /
Sergunb	0:f1834a63f7c1	2127	#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /!< CEC interface clock enable /
Sergunb	0:f1834a63f7c1	2128	#endif
Sergunb	0:f1834a63f7c1	2129
Sergunb	0:f1834a63f7c1	2130	#ifdef STM32F10X_HD_VL
Sergunb	0:f1834a63f7c1	2131	#define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /!< Timer 5 clock enable /
Sergunb	0:f1834a63f7c1	2132	#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /!< TIM12 Timer clock enable /
Sergunb	0:f1834a63f7c1	2133	#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /!< TIM13 Timer clock enable /
Sergunb	0:f1834a63f7c1	2134	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< TIM14 Timer clock enable /
Sergunb	0:f1834a63f7c1	2135	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI 3 clock enable /
Sergunb	0:f1834a63f7c1	2136	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /!< UART 4 clock enable /
Sergunb	0:f1834a63f7c1	2137	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /!< UART 5 clock enable /
Sergunb	0:f1834a63f7c1	2138	#endif /* STM32F10X_HD_VL */
Sergunb	0:f1834a63f7c1	2139
Sergunb	0:f1834a63f7c1	2140	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	2141	#define RCC_APB1ENR_CAN2EN ((uint32_t)0x04000000) /!< CAN2 clock enable /
Sergunb	0:f1834a63f7c1	2142	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	2143
Sergunb	0:f1834a63f7c1	2144	#ifdef STM32F10X_XL
Sergunb	0:f1834a63f7c1	2145	#define RCC_APB1ENR_TIM12EN ((uint32_t)0x00000040) /!< TIM12 Timer clock enable /
Sergunb	0:f1834a63f7c1	2146	#define RCC_APB1ENR_TIM13EN ((uint32_t)0x00000080) /!< TIM13 Timer clock enable /
Sergunb	0:f1834a63f7c1	2147	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< TIM14 Timer clock enable /
Sergunb	0:f1834a63f7c1	2148	#endif /* STM32F10X_XL */
Sergunb	0:f1834a63f7c1	2149
Sergunb	0:f1834a63f7c1	2150	/***************** Bit definition for RCC_BDCR register *****************/
Sergunb	0:f1834a63f7c1	2151	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
Sergunb	0:f1834a63f7c1	2152	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
Sergunb	0:f1834a63f7c1	2153	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
Sergunb	0:f1834a63f7c1	2154
Sergunb	0:f1834a63f7c1	2155	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
Sergunb	0:f1834a63f7c1	2156	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2157	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2158
Sergunb	0:f1834a63f7c1	2159	/!< RTC congiguration /
Sergunb	0:f1834a63f7c1	2160	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
Sergunb	0:f1834a63f7c1	2161	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
Sergunb	0:f1834a63f7c1	2162	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
Sergunb	0:f1834a63f7c1	2163	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 128 used as RTC clock /
Sergunb	0:f1834a63f7c1	2164
Sergunb	0:f1834a63f7c1	2165	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
Sergunb	0:f1834a63f7c1	2166	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
Sergunb	0:f1834a63f7c1	2167
Sergunb	0:f1834a63f7c1	2168	/***************** Bit definition for RCC_CSR register ******************/
Sergunb	0:f1834a63f7c1	2169	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
Sergunb	0:f1834a63f7c1	2170	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
Sergunb	0:f1834a63f7c1	2171	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
Sergunb	0:f1834a63f7c1	2172	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
Sergunb	0:f1834a63f7c1	2173	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
Sergunb	0:f1834a63f7c1	2174	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
Sergunb	0:f1834a63f7c1	2175	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
Sergunb	0:f1834a63f7c1	2176	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
Sergunb	0:f1834a63f7c1	2177	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
Sergunb	0:f1834a63f7c1	2178
Sergunb	0:f1834a63f7c1	2179	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	2180	/***************** Bit definition for RCC_AHBRSTR register **************/
Sergunb	0:f1834a63f7c1	2181	#define RCC_AHBRSTR_OTGFSRST ((uint32_t)0x00001000) /!< USB OTG FS reset /
Sergunb	0:f1834a63f7c1	2182	#define RCC_AHBRSTR_ETHMACRST ((uint32_t)0x00004000) /!< ETHERNET MAC reset /
Sergunb	0:f1834a63f7c1	2183
Sergunb	0:f1834a63f7c1	2184	/***************** Bit definition for RCC_CFGR2 register ****************/
Sergunb	0:f1834a63f7c1	2185	/!< PREDIV1 configuration /
Sergunb	0:f1834a63f7c1	2186	#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /!< PREDIV1[3:0] bits /
Sergunb	0:f1834a63f7c1	2187	#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2188	#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2189	#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	2190	#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	2191
Sergunb	0:f1834a63f7c1	2192	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
Sergunb	0:f1834a63f7c1	2193	#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /!< PREDIV1 input clock divided by 2 /
Sergunb	0:f1834a63f7c1	2194	#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /!< PREDIV1 input clock divided by 3 /
Sergunb	0:f1834a63f7c1	2195	#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /!< PREDIV1 input clock divided by 4 /
Sergunb	0:f1834a63f7c1	2196	#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /!< PREDIV1 input clock divided by 5 /
Sergunb	0:f1834a63f7c1	2197	#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /!< PREDIV1 input clock divided by 6 /
Sergunb	0:f1834a63f7c1	2198	#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /!< PREDIV1 input clock divided by 7 /
Sergunb	0:f1834a63f7c1	2199	#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /!< PREDIV1 input clock divided by 8 /
Sergunb	0:f1834a63f7c1	2200	#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /!< PREDIV1 input clock divided by 9 /
Sergunb	0:f1834a63f7c1	2201	#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /!< PREDIV1 input clock divided by 10 /
Sergunb	0:f1834a63f7c1	2202	#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /!< PREDIV1 input clock divided by 11 /
Sergunb	0:f1834a63f7c1	2203	#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /!< PREDIV1 input clock divided by 12 /
Sergunb	0:f1834a63f7c1	2204	#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /!< PREDIV1 input clock divided by 13 /
Sergunb	0:f1834a63f7c1	2205	#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /!< PREDIV1 input clock divided by 14 /
Sergunb	0:f1834a63f7c1	2206	#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /!< PREDIV1 input clock divided by 15 /
Sergunb	0:f1834a63f7c1	2207	#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /!< PREDIV1 input clock divided by 16 /
Sergunb	0:f1834a63f7c1	2208
Sergunb	0:f1834a63f7c1	2209	/!< PREDIV2 configuration /
Sergunb	0:f1834a63f7c1	2210	#define RCC_CFGR2_PREDIV2 ((uint32_t)0x000000F0) /!< PREDIV2[3:0] bits /
Sergunb	0:f1834a63f7c1	2211	#define RCC_CFGR2_PREDIV2_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2212	#define RCC_CFGR2_PREDIV2_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2213	#define RCC_CFGR2_PREDIV2_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	2214	#define RCC_CFGR2_PREDIV2_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	2215
Sergunb	0:f1834a63f7c1	2216	#define RCC_CFGR2_PREDIV2_DIV1 ((uint32_t)0x00000000) /!< PREDIV2 input clock not divided /
Sergunb	0:f1834a63f7c1	2217	#define RCC_CFGR2_PREDIV2_DIV2 ((uint32_t)0x00000010) /!< PREDIV2 input clock divided by 2 /
Sergunb	0:f1834a63f7c1	2218	#define RCC_CFGR2_PREDIV2_DIV3 ((uint32_t)0x00000020) /!< PREDIV2 input clock divided by 3 /
Sergunb	0:f1834a63f7c1	2219	#define RCC_CFGR2_PREDIV2_DIV4 ((uint32_t)0x00000030) /!< PREDIV2 input clock divided by 4 /
Sergunb	0:f1834a63f7c1	2220	#define RCC_CFGR2_PREDIV2_DIV5 ((uint32_t)0x00000040) /!< PREDIV2 input clock divided by 5 /
Sergunb	0:f1834a63f7c1	2221	#define RCC_CFGR2_PREDIV2_DIV6 ((uint32_t)0x00000050) /!< PREDIV2 input clock divided by 6 /
Sergunb	0:f1834a63f7c1	2222	#define RCC_CFGR2_PREDIV2_DIV7 ((uint32_t)0x00000060) /!< PREDIV2 input clock divided by 7 /
Sergunb	0:f1834a63f7c1	2223	#define RCC_CFGR2_PREDIV2_DIV8 ((uint32_t)0x00000070) /!< PREDIV2 input clock divided by 8 /
Sergunb	0:f1834a63f7c1	2224	#define RCC_CFGR2_PREDIV2_DIV9 ((uint32_t)0x00000080) /!< PREDIV2 input clock divided by 9 /
Sergunb	0:f1834a63f7c1	2225	#define RCC_CFGR2_PREDIV2_DIV10 ((uint32_t)0x00000090) /!< PREDIV2 input clock divided by 10 /
Sergunb	0:f1834a63f7c1	2226	#define RCC_CFGR2_PREDIV2_DIV11 ((uint32_t)0x000000A0) /!< PREDIV2 input clock divided by 11 /
Sergunb	0:f1834a63f7c1	2227	#define RCC_CFGR2_PREDIV2_DIV12 ((uint32_t)0x000000B0) /!< PREDIV2 input clock divided by 12 /
Sergunb	0:f1834a63f7c1	2228	#define RCC_CFGR2_PREDIV2_DIV13 ((uint32_t)0x000000C0) /!< PREDIV2 input clock divided by 13 /
Sergunb	0:f1834a63f7c1	2229	#define RCC_CFGR2_PREDIV2_DIV14 ((uint32_t)0x000000D0) /!< PREDIV2 input clock divided by 14 /
Sergunb	0:f1834a63f7c1	2230	#define RCC_CFGR2_PREDIV2_DIV15 ((uint32_t)0x000000E0) /!< PREDIV2 input clock divided by 15 /
Sergunb	0:f1834a63f7c1	2231	#define RCC_CFGR2_PREDIV2_DIV16 ((uint32_t)0x000000F0) /!< PREDIV2 input clock divided by 16 /
Sergunb	0:f1834a63f7c1	2232
Sergunb	0:f1834a63f7c1	2233	/!< PLL2MUL configuration /
Sergunb	0:f1834a63f7c1	2234	#define RCC_CFGR2_PLL2MUL ((uint32_t)0x00000F00) /!< PLL2MUL[3:0] bits /
Sergunb	0:f1834a63f7c1	2235	#define RCC_CFGR2_PLL2MUL_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2236	#define RCC_CFGR2_PLL2MUL_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2237	#define RCC_CFGR2_PLL2MUL_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	2238	#define RCC_CFGR2_PLL2MUL_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	2239
Sergunb	0:f1834a63f7c1	2240	#define RCC_CFGR2_PLL2MUL8 ((uint32_t)0x00000600) /!< PLL2 input clock 8 */
Sergunb	0:f1834a63f7c1	2241	#define RCC_CFGR2_PLL2MUL9 ((uint32_t)0x00000700) /!< PLL2 input clock 9 */
Sergunb	0:f1834a63f7c1	2242	#define RCC_CFGR2_PLL2MUL10 ((uint32_t)0x00000800) /!< PLL2 input clock 10 */
Sergunb	0:f1834a63f7c1	2243	#define RCC_CFGR2_PLL2MUL11 ((uint32_t)0x00000900) /!< PLL2 input clock 11 */
Sergunb	0:f1834a63f7c1	2244	#define RCC_CFGR2_PLL2MUL12 ((uint32_t)0x00000A00) /!< PLL2 input clock 12 */
Sergunb	0:f1834a63f7c1	2245	#define RCC_CFGR2_PLL2MUL13 ((uint32_t)0x00000B00) /!< PLL2 input clock 13 */
Sergunb	0:f1834a63f7c1	2246	#define RCC_CFGR2_PLL2MUL14 ((uint32_t)0x00000C00) /!< PLL2 input clock 14 */
Sergunb	0:f1834a63f7c1	2247	#define RCC_CFGR2_PLL2MUL16 ((uint32_t)0x00000E00) /!< PLL2 input clock 16 */
Sergunb	0:f1834a63f7c1	2248	#define RCC_CFGR2_PLL2MUL20 ((uint32_t)0x00000F00) /!< PLL2 input clock 20 */
Sergunb	0:f1834a63f7c1	2249
Sergunb	0:f1834a63f7c1	2250	/!< PLL3MUL configuration /
Sergunb	0:f1834a63f7c1	2251	#define RCC_CFGR2_PLL3MUL ((uint32_t)0x0000F000) /!< PLL3MUL[3:0] bits /
Sergunb	0:f1834a63f7c1	2252	#define RCC_CFGR2_PLL3MUL_0 ((uint32_t)0x00001000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2253	#define RCC_CFGR2_PLL3MUL_1 ((uint32_t)0x00002000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2254	#define RCC_CFGR2_PLL3MUL_2 ((uint32_t)0x00004000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	2255	#define RCC_CFGR2_PLL3MUL_3 ((uint32_t)0x00008000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	2256
Sergunb	0:f1834a63f7c1	2257	#define RCC_CFGR2_PLL3MUL8 ((uint32_t)0x00006000) /!< PLL3 input clock 8 */
Sergunb	0:f1834a63f7c1	2258	#define RCC_CFGR2_PLL3MUL9 ((uint32_t)0x00007000) /!< PLL3 input clock 9 */
Sergunb	0:f1834a63f7c1	2259	#define RCC_CFGR2_PLL3MUL10 ((uint32_t)0x00008000) /!< PLL3 input clock 10 */
Sergunb	0:f1834a63f7c1	2260	#define RCC_CFGR2_PLL3MUL11 ((uint32_t)0x00009000) /!< PLL3 input clock 11 */
Sergunb	0:f1834a63f7c1	2261	#define RCC_CFGR2_PLL3MUL12 ((uint32_t)0x0000A000) /!< PLL3 input clock 12 */
Sergunb	0:f1834a63f7c1	2262	#define RCC_CFGR2_PLL3MUL13 ((uint32_t)0x0000B000) /!< PLL3 input clock 13 */
Sergunb	0:f1834a63f7c1	2263	#define RCC_CFGR2_PLL3MUL14 ((uint32_t)0x0000C000) /!< PLL3 input clock 14 */
Sergunb	0:f1834a63f7c1	2264	#define RCC_CFGR2_PLL3MUL16 ((uint32_t)0x0000E000) /!< PLL3 input clock 16 */
Sergunb	0:f1834a63f7c1	2265	#define RCC_CFGR2_PLL3MUL20 ((uint32_t)0x0000F000) /!< PLL3 input clock 20 */
Sergunb	0:f1834a63f7c1	2266
Sergunb	0:f1834a63f7c1	2267	#define RCC_CFGR2_PREDIV1SRC ((uint32_t)0x00010000) /!< PREDIV1 entry clock source /
Sergunb	0:f1834a63f7c1	2268	#define RCC_CFGR2_PREDIV1SRC_PLL2 ((uint32_t)0x00010000) /!< PLL2 selected as PREDIV1 entry clock source /
Sergunb	0:f1834a63f7c1	2269	#define RCC_CFGR2_PREDIV1SRC_HSE ((uint32_t)0x00000000) /!< HSE selected as PREDIV1 entry clock source /
Sergunb	0:f1834a63f7c1	2270	#define RCC_CFGR2_I2S2SRC ((uint32_t)0x00020000) /!< I2S2 entry clock source /
Sergunb	0:f1834a63f7c1	2271	#define RCC_CFGR2_I2S3SRC ((uint32_t)0x00040000) /!< I2S3 clock source /
Sergunb	0:f1834a63f7c1	2272	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	2273
Sergunb	0:f1834a63f7c1	2274	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	2275	/***************** Bit definition for RCC_CFGR2 register ****************/
Sergunb	0:f1834a63f7c1	2276	/!< PREDIV1 configuration /
Sergunb	0:f1834a63f7c1	2277	#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /!< PREDIV1[3:0] bits /
Sergunb	0:f1834a63f7c1	2278	#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2279	#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2280	#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	2281	#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	2282
Sergunb	0:f1834a63f7c1	2283	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
Sergunb	0:f1834a63f7c1	2284	#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /!< PREDIV1 input clock divided by 2 /
Sergunb	0:f1834a63f7c1	2285	#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /!< PREDIV1 input clock divided by 3 /
Sergunb	0:f1834a63f7c1	2286	#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /!< PREDIV1 input clock divided by 4 /
Sergunb	0:f1834a63f7c1	2287	#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /!< PREDIV1 input clock divided by 5 /
Sergunb	0:f1834a63f7c1	2288	#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /!< PREDIV1 input clock divided by 6 /
Sergunb	0:f1834a63f7c1	2289	#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /!< PREDIV1 input clock divided by 7 /
Sergunb	0:f1834a63f7c1	2290	#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /!< PREDIV1 input clock divided by 8 /
Sergunb	0:f1834a63f7c1	2291	#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /!< PREDIV1 input clock divided by 9 /
Sergunb	0:f1834a63f7c1	2292	#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /!< PREDIV1 input clock divided by 10 /
Sergunb	0:f1834a63f7c1	2293	#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /!< PREDIV1 input clock divided by 11 /
Sergunb	0:f1834a63f7c1	2294	#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /!< PREDIV1 input clock divided by 12 /
Sergunb	0:f1834a63f7c1	2295	#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /!< PREDIV1 input clock divided by 13 /
Sergunb	0:f1834a63f7c1	2296	#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /!< PREDIV1 input clock divided by 14 /
Sergunb	0:f1834a63f7c1	2297	#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /!< PREDIV1 input clock divided by 15 /
Sergunb	0:f1834a63f7c1	2298	#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /!< PREDIV1 input clock divided by 16 /
Sergunb	0:f1834a63f7c1	2299	#endif
Sergunb	0:f1834a63f7c1	2300
Sergunb	0:f1834a63f7c1	2301	/******************************************************************************/
Sergunb	0:f1834a63f7c1	2302	/* */
Sergunb	0:f1834a63f7c1	2303	/* General Purpose and Alternate Function I/O */
Sergunb	0:f1834a63f7c1	2304	/* */
Sergunb	0:f1834a63f7c1	2305	/******************************************************************************/
Sergunb	0:f1834a63f7c1	2306
Sergunb	0:f1834a63f7c1	2307	/***************** Bit definition for GPIO_CRL register *****************/
Sergunb	0:f1834a63f7c1	2308	#define GPIO_CRL_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
Sergunb	0:f1834a63f7c1	2309
Sergunb	0:f1834a63f7c1	2310	#define GPIO_CRL_MODE0 ((uint32_t)0x00000003) /!< MODE0[1:0] bits (Port x mode bits, pin 0) /
Sergunb	0:f1834a63f7c1	2311	#define GPIO_CRL_MODE0_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2312	#define GPIO_CRL_MODE0_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2313
Sergunb	0:f1834a63f7c1	2314	#define GPIO_CRL_MODE1 ((uint32_t)0x00000030) /!< MODE1[1:0] bits (Port x mode bits, pin 1) /
Sergunb	0:f1834a63f7c1	2315	#define GPIO_CRL_MODE1_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2316	#define GPIO_CRL_MODE1_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2317
Sergunb	0:f1834a63f7c1	2318	#define GPIO_CRL_MODE2 ((uint32_t)0x00000300) /!< MODE2[1:0] bits (Port x mode bits, pin 2) /
Sergunb	0:f1834a63f7c1	2319	#define GPIO_CRL_MODE2_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2320	#define GPIO_CRL_MODE2_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2321
Sergunb	0:f1834a63f7c1	2322	#define GPIO_CRL_MODE3 ((uint32_t)0x00003000) /!< MODE3[1:0] bits (Port x mode bits, pin 3) /
Sergunb	0:f1834a63f7c1	2323	#define GPIO_CRL_MODE3_0 ((uint32_t)0x00001000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2324	#define GPIO_CRL_MODE3_1 ((uint32_t)0x00002000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2325
Sergunb	0:f1834a63f7c1	2326	#define GPIO_CRL_MODE4 ((uint32_t)0x00030000) /!< MODE4[1:0] bits (Port x mode bits, pin 4) /
Sergunb	0:f1834a63f7c1	2327	#define GPIO_CRL_MODE4_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2328	#define GPIO_CRL_MODE4_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2329
Sergunb	0:f1834a63f7c1	2330	#define GPIO_CRL_MODE5 ((uint32_t)0x00300000) /!< MODE5[1:0] bits (Port x mode bits, pin 5) /
Sergunb	0:f1834a63f7c1	2331	#define GPIO_CRL_MODE5_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2332	#define GPIO_CRL_MODE5_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2333
Sergunb	0:f1834a63f7c1	2334	#define GPIO_CRL_MODE6 ((uint32_t)0x03000000) /!< MODE6[1:0] bits (Port x mode bits, pin 6) /
Sergunb	0:f1834a63f7c1	2335	#define GPIO_CRL_MODE6_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2336	#define GPIO_CRL_MODE6_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2337
Sergunb	0:f1834a63f7c1	2338	#define GPIO_CRL_MODE7 ((uint32_t)0x30000000) /!< MODE7[1:0] bits (Port x mode bits, pin 7) /
Sergunb	0:f1834a63f7c1	2339	#define GPIO_CRL_MODE7_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2340	#define GPIO_CRL_MODE7_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2341
Sergunb	0:f1834a63f7c1	2342	#define GPIO_CRL_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
Sergunb	0:f1834a63f7c1	2343
Sergunb	0:f1834a63f7c1	2344	#define GPIO_CRL_CNF0 ((uint32_t)0x0000000C) /!< CNF0[1:0] bits (Port x configuration bits, pin 0) /
Sergunb	0:f1834a63f7c1	2345	#define GPIO_CRL_CNF0_0 ((uint32_t)0x00000004) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2346	#define GPIO_CRL_CNF0_1 ((uint32_t)0x00000008) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2347
Sergunb	0:f1834a63f7c1	2348	#define GPIO_CRL_CNF1 ((uint32_t)0x000000C0) /!< CNF1[1:0] bits (Port x configuration bits, pin 1) /
Sergunb	0:f1834a63f7c1	2349	#define GPIO_CRL_CNF1_0 ((uint32_t)0x00000040) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2350	#define GPIO_CRL_CNF1_1 ((uint32_t)0x00000080) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2351
Sergunb	0:f1834a63f7c1	2352	#define GPIO_CRL_CNF2 ((uint32_t)0x00000C00) /!< CNF2[1:0] bits (Port x configuration bits, pin 2) /
Sergunb	0:f1834a63f7c1	2353	#define GPIO_CRL_CNF2_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2354	#define GPIO_CRL_CNF2_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2355
Sergunb	0:f1834a63f7c1	2356	#define GPIO_CRL_CNF3 ((uint32_t)0x0000C000) /!< CNF3[1:0] bits (Port x configuration bits, pin 3) /
Sergunb	0:f1834a63f7c1	2357	#define GPIO_CRL_CNF3_0 ((uint32_t)0x00004000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2358	#define GPIO_CRL_CNF3_1 ((uint32_t)0x00008000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2359
Sergunb	0:f1834a63f7c1	2360	#define GPIO_CRL_CNF4 ((uint32_t)0x000C0000) /!< CNF4[1:0] bits (Port x configuration bits, pin 4) /
Sergunb	0:f1834a63f7c1	2361	#define GPIO_CRL_CNF4_0 ((uint32_t)0x00040000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2362	#define GPIO_CRL_CNF4_1 ((uint32_t)0x00080000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2363
Sergunb	0:f1834a63f7c1	2364	#define GPIO_CRL_CNF5 ((uint32_t)0x00C00000) /!< CNF5[1:0] bits (Port x configuration bits, pin 5) /
Sergunb	0:f1834a63f7c1	2365	#define GPIO_CRL_CNF5_0 ((uint32_t)0x00400000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2366	#define GPIO_CRL_CNF5_1 ((uint32_t)0x00800000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2367
Sergunb	0:f1834a63f7c1	2368	#define GPIO_CRL_CNF6 ((uint32_t)0x0C000000) /!< CNF6[1:0] bits (Port x configuration bits, pin 6) /
Sergunb	0:f1834a63f7c1	2369	#define GPIO_CRL_CNF6_0 ((uint32_t)0x04000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2370	#define GPIO_CRL_CNF6_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2371
Sergunb	0:f1834a63f7c1	2372	#define GPIO_CRL_CNF7 ((uint32_t)0xC0000000) /!< CNF7[1:0] bits (Port x configuration bits, pin 7) /
Sergunb	0:f1834a63f7c1	2373	#define GPIO_CRL_CNF7_0 ((uint32_t)0x40000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2374	#define GPIO_CRL_CNF7_1 ((uint32_t)0x80000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2375
Sergunb	0:f1834a63f7c1	2376	/***************** Bit definition for GPIO_CRH register *****************/
Sergunb	0:f1834a63f7c1	2377	#define GPIO_CRH_MODE ((uint32_t)0x33333333) /!< Port x mode bits /
Sergunb	0:f1834a63f7c1	2378
Sergunb	0:f1834a63f7c1	2379	#define GPIO_CRH_MODE8 ((uint32_t)0x00000003) /!< MODE8[1:0] bits (Port x mode bits, pin 8) /
Sergunb	0:f1834a63f7c1	2380	#define GPIO_CRH_MODE8_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2381	#define GPIO_CRH_MODE8_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2382
Sergunb	0:f1834a63f7c1	2383	#define GPIO_CRH_MODE9 ((uint32_t)0x00000030) /!< MODE9[1:0] bits (Port x mode bits, pin 9) /
Sergunb	0:f1834a63f7c1	2384	#define GPIO_CRH_MODE9_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2385	#define GPIO_CRH_MODE9_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2386
Sergunb	0:f1834a63f7c1	2387	#define GPIO_CRH_MODE10 ((uint32_t)0x00000300) /!< MODE10[1:0] bits (Port x mode bits, pin 10) /
Sergunb	0:f1834a63f7c1	2388	#define GPIO_CRH_MODE10_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2389	#define GPIO_CRH_MODE10_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2390
Sergunb	0:f1834a63f7c1	2391	#define GPIO_CRH_MODE11 ((uint32_t)0x00003000) /!< MODE11[1:0] bits (Port x mode bits, pin 11) /
Sergunb	0:f1834a63f7c1	2392	#define GPIO_CRH_MODE11_0 ((uint32_t)0x00001000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2393	#define GPIO_CRH_MODE11_1 ((uint32_t)0x00002000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2394
Sergunb	0:f1834a63f7c1	2395	#define GPIO_CRH_MODE12 ((uint32_t)0x00030000) /!< MODE12[1:0] bits (Port x mode bits, pin 12) /
Sergunb	0:f1834a63f7c1	2396	#define GPIO_CRH_MODE12_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2397	#define GPIO_CRH_MODE12_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2398
Sergunb	0:f1834a63f7c1	2399	#define GPIO_CRH_MODE13 ((uint32_t)0x00300000) /!< MODE13[1:0] bits (Port x mode bits, pin 13) /
Sergunb	0:f1834a63f7c1	2400	#define GPIO_CRH_MODE13_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2401	#define GPIO_CRH_MODE13_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2402
Sergunb	0:f1834a63f7c1	2403	#define GPIO_CRH_MODE14 ((uint32_t)0x03000000) /!< MODE14[1:0] bits (Port x mode bits, pin 14) /
Sergunb	0:f1834a63f7c1	2404	#define GPIO_CRH_MODE14_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2405	#define GPIO_CRH_MODE14_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2406
Sergunb	0:f1834a63f7c1	2407	#define GPIO_CRH_MODE15 ((uint32_t)0x30000000) /!< MODE15[1:0] bits (Port x mode bits, pin 15) /
Sergunb	0:f1834a63f7c1	2408	#define GPIO_CRH_MODE15_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2409	#define GPIO_CRH_MODE15_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2410
Sergunb	0:f1834a63f7c1	2411	#define GPIO_CRH_CNF ((uint32_t)0xCCCCCCCC) /!< Port x configuration bits /
Sergunb	0:f1834a63f7c1	2412
Sergunb	0:f1834a63f7c1	2413	#define GPIO_CRH_CNF8 ((uint32_t)0x0000000C) /!< CNF8[1:0] bits (Port x configuration bits, pin 8) /
Sergunb	0:f1834a63f7c1	2414	#define GPIO_CRH_CNF8_0 ((uint32_t)0x00000004) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2415	#define GPIO_CRH_CNF8_1 ((uint32_t)0x00000008) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2416
Sergunb	0:f1834a63f7c1	2417	#define GPIO_CRH_CNF9 ((uint32_t)0x000000C0) /!< CNF9[1:0] bits (Port x configuration bits, pin 9) /
Sergunb	0:f1834a63f7c1	2418	#define GPIO_CRH_CNF9_0 ((uint32_t)0x00000040) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2419	#define GPIO_CRH_CNF9_1 ((uint32_t)0x00000080) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2420
Sergunb	0:f1834a63f7c1	2421	#define GPIO_CRH_CNF10 ((uint32_t)0x00000C00) /!< CNF10[1:0] bits (Port x configuration bits, pin 10) /
Sergunb	0:f1834a63f7c1	2422	#define GPIO_CRH_CNF10_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2423	#define GPIO_CRH_CNF10_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2424
Sergunb	0:f1834a63f7c1	2425	#define GPIO_CRH_CNF11 ((uint32_t)0x0000C000) /!< CNF11[1:0] bits (Port x configuration bits, pin 11) /
Sergunb	0:f1834a63f7c1	2426	#define GPIO_CRH_CNF11_0 ((uint32_t)0x00004000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2427	#define GPIO_CRH_CNF11_1 ((uint32_t)0x00008000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2428
Sergunb	0:f1834a63f7c1	2429	#define GPIO_CRH_CNF12 ((uint32_t)0x000C0000) /!< CNF12[1:0] bits (Port x configuration bits, pin 12) /
Sergunb	0:f1834a63f7c1	2430	#define GPIO_CRH_CNF12_0 ((uint32_t)0x00040000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2431	#define GPIO_CRH_CNF12_1 ((uint32_t)0x00080000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2432
Sergunb	0:f1834a63f7c1	2433	#define GPIO_CRH_CNF13 ((uint32_t)0x00C00000) /!< CNF13[1:0] bits (Port x configuration bits, pin 13) /
Sergunb	0:f1834a63f7c1	2434	#define GPIO_CRH_CNF13_0 ((uint32_t)0x00400000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2435	#define GPIO_CRH_CNF13_1 ((uint32_t)0x00800000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2436
Sergunb	0:f1834a63f7c1	2437	#define GPIO_CRH_CNF14 ((uint32_t)0x0C000000) /!< CNF14[1:0] bits (Port x configuration bits, pin 14) /
Sergunb	0:f1834a63f7c1	2438	#define GPIO_CRH_CNF14_0 ((uint32_t)0x04000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2439	#define GPIO_CRH_CNF14_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2440
Sergunb	0:f1834a63f7c1	2441	#define GPIO_CRH_CNF15 ((uint32_t)0xC0000000) /!< CNF15[1:0] bits (Port x configuration bits, pin 15) /
Sergunb	0:f1834a63f7c1	2442	#define GPIO_CRH_CNF15_0 ((uint32_t)0x40000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2443	#define GPIO_CRH_CNF15_1 ((uint32_t)0x80000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2444
Sergunb	0:f1834a63f7c1	2445	/!<*************** Bit definition for GPIO_IDR register *****************/
Sergunb	0:f1834a63f7c1	2446	#define GPIO_IDR_IDR0 ((uint16_t)0x0001) /!< Port input data, bit 0 /
Sergunb	0:f1834a63f7c1	2447	#define GPIO_IDR_IDR1 ((uint16_t)0x0002) /!< Port input data, bit 1 /
Sergunb	0:f1834a63f7c1	2448	#define GPIO_IDR_IDR2 ((uint16_t)0x0004) /!< Port input data, bit 2 /
Sergunb	0:f1834a63f7c1	2449	#define GPIO_IDR_IDR3 ((uint16_t)0x0008) /!< Port input data, bit 3 /
Sergunb	0:f1834a63f7c1	2450	#define GPIO_IDR_IDR4 ((uint16_t)0x0010) /!< Port input data, bit 4 /
Sergunb	0:f1834a63f7c1	2451	#define GPIO_IDR_IDR5 ((uint16_t)0x0020) /!< Port input data, bit 5 /
Sergunb	0:f1834a63f7c1	2452	#define GPIO_IDR_IDR6 ((uint16_t)0x0040) /!< Port input data, bit 6 /
Sergunb	0:f1834a63f7c1	2453	#define GPIO_IDR_IDR7 ((uint16_t)0x0080) /!< Port input data, bit 7 /
Sergunb	0:f1834a63f7c1	2454	#define GPIO_IDR_IDR8 ((uint16_t)0x0100) /!< Port input data, bit 8 /
Sergunb	0:f1834a63f7c1	2455	#define GPIO_IDR_IDR9 ((uint16_t)0x0200) /!< Port input data, bit 9 /
Sergunb	0:f1834a63f7c1	2456	#define GPIO_IDR_IDR10 ((uint16_t)0x0400) /!< Port input data, bit 10 /
Sergunb	0:f1834a63f7c1	2457	#define GPIO_IDR_IDR11 ((uint16_t)0x0800) /!< Port input data, bit 11 /
Sergunb	0:f1834a63f7c1	2458	#define GPIO_IDR_IDR12 ((uint16_t)0x1000) /!< Port input data, bit 12 /
Sergunb	0:f1834a63f7c1	2459	#define GPIO_IDR_IDR13 ((uint16_t)0x2000) /!< Port input data, bit 13 /
Sergunb	0:f1834a63f7c1	2460	#define GPIO_IDR_IDR14 ((uint16_t)0x4000) /!< Port input data, bit 14 /
Sergunb	0:f1834a63f7c1	2461	#define GPIO_IDR_IDR15 ((uint16_t)0x8000) /!< Port input data, bit 15 /
Sergunb	0:f1834a63f7c1	2462
Sergunb	0:f1834a63f7c1	2463	/***************** Bit definition for GPIO_ODR register *****************/
Sergunb	0:f1834a63f7c1	2464	#define GPIO_ODR_ODR0 ((uint16_t)0x0001) /!< Port output data, bit 0 /
Sergunb	0:f1834a63f7c1	2465	#define GPIO_ODR_ODR1 ((uint16_t)0x0002) /!< Port output data, bit 1 /
Sergunb	0:f1834a63f7c1	2466	#define GPIO_ODR_ODR2 ((uint16_t)0x0004) /!< Port output data, bit 2 /
Sergunb	0:f1834a63f7c1	2467	#define GPIO_ODR_ODR3 ((uint16_t)0x0008) /!< Port output data, bit 3 /
Sergunb	0:f1834a63f7c1	2468	#define GPIO_ODR_ODR4 ((uint16_t)0x0010) /!< Port output data, bit 4 /
Sergunb	0:f1834a63f7c1	2469	#define GPIO_ODR_ODR5 ((uint16_t)0x0020) /!< Port output data, bit 5 /
Sergunb	0:f1834a63f7c1	2470	#define GPIO_ODR_ODR6 ((uint16_t)0x0040) /!< Port output data, bit 6 /
Sergunb	0:f1834a63f7c1	2471	#define GPIO_ODR_ODR7 ((uint16_t)0x0080) /!< Port output data, bit 7 /
Sergunb	0:f1834a63f7c1	2472	#define GPIO_ODR_ODR8 ((uint16_t)0x0100) /!< Port output data, bit 8 /
Sergunb	0:f1834a63f7c1	2473	#define GPIO_ODR_ODR9 ((uint16_t)0x0200) /!< Port output data, bit 9 /
Sergunb	0:f1834a63f7c1	2474	#define GPIO_ODR_ODR10 ((uint16_t)0x0400) /!< Port output data, bit 10 /
Sergunb	0:f1834a63f7c1	2475	#define GPIO_ODR_ODR11 ((uint16_t)0x0800) /!< Port output data, bit 11 /
Sergunb	0:f1834a63f7c1	2476	#define GPIO_ODR_ODR12 ((uint16_t)0x1000) /!< Port output data, bit 12 /
Sergunb	0:f1834a63f7c1	2477	#define GPIO_ODR_ODR13 ((uint16_t)0x2000) /!< Port output data, bit 13 /
Sergunb	0:f1834a63f7c1	2478	#define GPIO_ODR_ODR14 ((uint16_t)0x4000) /!< Port output data, bit 14 /
Sergunb	0:f1834a63f7c1	2479	#define GPIO_ODR_ODR15 ((uint16_t)0x8000) /!< Port output data, bit 15 /
Sergunb	0:f1834a63f7c1	2480
Sergunb	0:f1834a63f7c1	2481	/**************** Bit definition for GPIO_BSRR register *****************/
Sergunb	0:f1834a63f7c1	2482	#define GPIO_BSRR_BS0 ((uint32_t)0x00000001) /!< Port x Set bit 0 /
Sergunb	0:f1834a63f7c1	2483	#define GPIO_BSRR_BS1 ((uint32_t)0x00000002) /!< Port x Set bit 1 /
Sergunb	0:f1834a63f7c1	2484	#define GPIO_BSRR_BS2 ((uint32_t)0x00000004) /!< Port x Set bit 2 /
Sergunb	0:f1834a63f7c1	2485	#define GPIO_BSRR_BS3 ((uint32_t)0x00000008) /!< Port x Set bit 3 /
Sergunb	0:f1834a63f7c1	2486	#define GPIO_BSRR_BS4 ((uint32_t)0x00000010) /!< Port x Set bit 4 /
Sergunb	0:f1834a63f7c1	2487	#define GPIO_BSRR_BS5 ((uint32_t)0x00000020) /!< Port x Set bit 5 /
Sergunb	0:f1834a63f7c1	2488	#define GPIO_BSRR_BS6 ((uint32_t)0x00000040) /!< Port x Set bit 6 /
Sergunb	0:f1834a63f7c1	2489	#define GPIO_BSRR_BS7 ((uint32_t)0x00000080) /!< Port x Set bit 7 /
Sergunb	0:f1834a63f7c1	2490	#define GPIO_BSRR_BS8 ((uint32_t)0x00000100) /!< Port x Set bit 8 /
Sergunb	0:f1834a63f7c1	2491	#define GPIO_BSRR_BS9 ((uint32_t)0x00000200) /!< Port x Set bit 9 /
Sergunb	0:f1834a63f7c1	2492	#define GPIO_BSRR_BS10 ((uint32_t)0x00000400) /!< Port x Set bit 10 /
Sergunb	0:f1834a63f7c1	2493	#define GPIO_BSRR_BS11 ((uint32_t)0x00000800) /!< Port x Set bit 11 /
Sergunb	0:f1834a63f7c1	2494	#define GPIO_BSRR_BS12 ((uint32_t)0x00001000) /!< Port x Set bit 12 /
Sergunb	0:f1834a63f7c1	2495	#define GPIO_BSRR_BS13 ((uint32_t)0x00002000) /!< Port x Set bit 13 /
Sergunb	0:f1834a63f7c1	2496	#define GPIO_BSRR_BS14 ((uint32_t)0x00004000) /!< Port x Set bit 14 /
Sergunb	0:f1834a63f7c1	2497	#define GPIO_BSRR_BS15 ((uint32_t)0x00008000) /!< Port x Set bit 15 /
Sergunb	0:f1834a63f7c1	2498
Sergunb	0:f1834a63f7c1	2499	#define GPIO_BSRR_BR0 ((uint32_t)0x00010000) /!< Port x Reset bit 0 /
Sergunb	0:f1834a63f7c1	2500	#define GPIO_BSRR_BR1 ((uint32_t)0x00020000) /!< Port x Reset bit 1 /
Sergunb	0:f1834a63f7c1	2501	#define GPIO_BSRR_BR2 ((uint32_t)0x00040000) /!< Port x Reset bit 2 /
Sergunb	0:f1834a63f7c1	2502	#define GPIO_BSRR_BR3 ((uint32_t)0x00080000) /!< Port x Reset bit 3 /
Sergunb	0:f1834a63f7c1	2503	#define GPIO_BSRR_BR4 ((uint32_t)0x00100000) /!< Port x Reset bit 4 /
Sergunb	0:f1834a63f7c1	2504	#define GPIO_BSRR_BR5 ((uint32_t)0x00200000) /!< Port x Reset bit 5 /
Sergunb	0:f1834a63f7c1	2505	#define GPIO_BSRR_BR6 ((uint32_t)0x00400000) /!< Port x Reset bit 6 /
Sergunb	0:f1834a63f7c1	2506	#define GPIO_BSRR_BR7 ((uint32_t)0x00800000) /!< Port x Reset bit 7 /
Sergunb	0:f1834a63f7c1	2507	#define GPIO_BSRR_BR8 ((uint32_t)0x01000000) /!< Port x Reset bit 8 /
Sergunb	0:f1834a63f7c1	2508	#define GPIO_BSRR_BR9 ((uint32_t)0x02000000) /!< Port x Reset bit 9 /
Sergunb	0:f1834a63f7c1	2509	#define GPIO_BSRR_BR10 ((uint32_t)0x04000000) /!< Port x Reset bit 10 /
Sergunb	0:f1834a63f7c1	2510	#define GPIO_BSRR_BR11 ((uint32_t)0x08000000) /!< Port x Reset bit 11 /
Sergunb	0:f1834a63f7c1	2511	#define GPIO_BSRR_BR12 ((uint32_t)0x10000000) /!< Port x Reset bit 12 /
Sergunb	0:f1834a63f7c1	2512	#define GPIO_BSRR_BR13 ((uint32_t)0x20000000) /!< Port x Reset bit 13 /
Sergunb	0:f1834a63f7c1	2513	#define GPIO_BSRR_BR14 ((uint32_t)0x40000000) /!< Port x Reset bit 14 /
Sergunb	0:f1834a63f7c1	2514	#define GPIO_BSRR_BR15 ((uint32_t)0x80000000) /!< Port x Reset bit 15 /
Sergunb	0:f1834a63f7c1	2515
Sergunb	0:f1834a63f7c1	2516	/***************** Bit definition for GPIO_BRR register *****************/
Sergunb	0:f1834a63f7c1	2517	#define GPIO_BRR_BR0 ((uint16_t)0x0001) /!< Port x Reset bit 0 /
Sergunb	0:f1834a63f7c1	2518	#define GPIO_BRR_BR1 ((uint16_t)0x0002) /!< Port x Reset bit 1 /
Sergunb	0:f1834a63f7c1	2519	#define GPIO_BRR_BR2 ((uint16_t)0x0004) /!< Port x Reset bit 2 /
Sergunb	0:f1834a63f7c1	2520	#define GPIO_BRR_BR3 ((uint16_t)0x0008) /!< Port x Reset bit 3 /
Sergunb	0:f1834a63f7c1	2521	#define GPIO_BRR_BR4 ((uint16_t)0x0010) /!< Port x Reset bit 4 /
Sergunb	0:f1834a63f7c1	2522	#define GPIO_BRR_BR5 ((uint16_t)0x0020) /!< Port x Reset bit 5 /
Sergunb	0:f1834a63f7c1	2523	#define GPIO_BRR_BR6 ((uint16_t)0x0040) /!< Port x Reset bit 6 /
Sergunb	0:f1834a63f7c1	2524	#define GPIO_BRR_BR7 ((uint16_t)0x0080) /!< Port x Reset bit 7 /
Sergunb	0:f1834a63f7c1	2525	#define GPIO_BRR_BR8 ((uint16_t)0x0100) /!< Port x Reset bit 8 /
Sergunb	0:f1834a63f7c1	2526	#define GPIO_BRR_BR9 ((uint16_t)0x0200) /!< Port x Reset bit 9 /
Sergunb	0:f1834a63f7c1	2527	#define GPIO_BRR_BR10 ((uint16_t)0x0400) /!< Port x Reset bit 10 /
Sergunb	0:f1834a63f7c1	2528	#define GPIO_BRR_BR11 ((uint16_t)0x0800) /!< Port x Reset bit 11 /
Sergunb	0:f1834a63f7c1	2529	#define GPIO_BRR_BR12 ((uint16_t)0x1000) /!< Port x Reset bit 12 /
Sergunb	0:f1834a63f7c1	2530	#define GPIO_BRR_BR13 ((uint16_t)0x2000) /!< Port x Reset bit 13 /
Sergunb	0:f1834a63f7c1	2531	#define GPIO_BRR_BR14 ((uint16_t)0x4000) /!< Port x Reset bit 14 /
Sergunb	0:f1834a63f7c1	2532	#define GPIO_BRR_BR15 ((uint16_t)0x8000) /!< Port x Reset bit 15 /
Sergunb	0:f1834a63f7c1	2533
Sergunb	0:f1834a63f7c1	2534	/**************** Bit definition for GPIO_LCKR register *****************/
Sergunb	0:f1834a63f7c1	2535	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001) /!< Port x Lock bit 0 /
Sergunb	0:f1834a63f7c1	2536	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002) /!< Port x Lock bit 1 /
Sergunb	0:f1834a63f7c1	2537	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004) /!< Port x Lock bit 2 /
Sergunb	0:f1834a63f7c1	2538	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008) /!< Port x Lock bit 3 /
Sergunb	0:f1834a63f7c1	2539	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010) /!< Port x Lock bit 4 /
Sergunb	0:f1834a63f7c1	2540	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020) /!< Port x Lock bit 5 /
Sergunb	0:f1834a63f7c1	2541	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040) /!< Port x Lock bit 6 /
Sergunb	0:f1834a63f7c1	2542	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080) /!< Port x Lock bit 7 /
Sergunb	0:f1834a63f7c1	2543	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100) /!< Port x Lock bit 8 /
Sergunb	0:f1834a63f7c1	2544	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200) /!< Port x Lock bit 9 /
Sergunb	0:f1834a63f7c1	2545	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400) /!< Port x Lock bit 10 /
Sergunb	0:f1834a63f7c1	2546	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800) /!< Port x Lock bit 11 /
Sergunb	0:f1834a63f7c1	2547	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000) /!< Port x Lock bit 12 /
Sergunb	0:f1834a63f7c1	2548	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000) /!< Port x Lock bit 13 /
Sergunb	0:f1834a63f7c1	2549	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000) /!< Port x Lock bit 14 /
Sergunb	0:f1834a63f7c1	2550	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000) /!< Port x Lock bit 15 /
Sergunb	0:f1834a63f7c1	2551	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000) /!< Lock key /
Sergunb	0:f1834a63f7c1	2552
Sergunb	0:f1834a63f7c1	2553	/----------------------------------------------------------------------------/
Sergunb	0:f1834a63f7c1	2554
Sergunb	0:f1834a63f7c1	2555	/**************** Bit definition for AFIO_EVCR register *****************/
Sergunb	0:f1834a63f7c1	2556	#define AFIO_EVCR_PIN ((uint8_t)0x0F) /!< PIN[3:0] bits (Pin selection) /
Sergunb	0:f1834a63f7c1	2557	#define AFIO_EVCR_PIN_0 ((uint8_t)0x01) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2558	#define AFIO_EVCR_PIN_1 ((uint8_t)0x02) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2559	#define AFIO_EVCR_PIN_2 ((uint8_t)0x04) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	2560	#define AFIO_EVCR_PIN_3 ((uint8_t)0x08) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	2561
Sergunb	0:f1834a63f7c1	2562	/!< PIN configuration /
Sergunb	0:f1834a63f7c1	2563	#define AFIO_EVCR_PIN_PX0 ((uint8_t)0x00) /!< Pin 0 selected /
Sergunb	0:f1834a63f7c1	2564	#define AFIO_EVCR_PIN_PX1 ((uint8_t)0x01) /!< Pin 1 selected /
Sergunb	0:f1834a63f7c1	2565	#define AFIO_EVCR_PIN_PX2 ((uint8_t)0x02) /!< Pin 2 selected /
Sergunb	0:f1834a63f7c1	2566	#define AFIO_EVCR_PIN_PX3 ((uint8_t)0x03) /!< Pin 3 selected /
Sergunb	0:f1834a63f7c1	2567	#define AFIO_EVCR_PIN_PX4 ((uint8_t)0x04) /!< Pin 4 selected /
Sergunb	0:f1834a63f7c1	2568	#define AFIO_EVCR_PIN_PX5 ((uint8_t)0x05) /!< Pin 5 selected /
Sergunb	0:f1834a63f7c1	2569	#define AFIO_EVCR_PIN_PX6 ((uint8_t)0x06) /!< Pin 6 selected /
Sergunb	0:f1834a63f7c1	2570	#define AFIO_EVCR_PIN_PX7 ((uint8_t)0x07) /!< Pin 7 selected /
Sergunb	0:f1834a63f7c1	2571	#define AFIO_EVCR_PIN_PX8 ((uint8_t)0x08) /!< Pin 8 selected /
Sergunb	0:f1834a63f7c1	2572	#define AFIO_EVCR_PIN_PX9 ((uint8_t)0x09) /!< Pin 9 selected /
Sergunb	0:f1834a63f7c1	2573	#define AFIO_EVCR_PIN_PX10 ((uint8_t)0x0A) /!< Pin 10 selected /
Sergunb	0:f1834a63f7c1	2574	#define AFIO_EVCR_PIN_PX11 ((uint8_t)0x0B) /!< Pin 11 selected /
Sergunb	0:f1834a63f7c1	2575	#define AFIO_EVCR_PIN_PX12 ((uint8_t)0x0C) /!< Pin 12 selected /
Sergunb	0:f1834a63f7c1	2576	#define AFIO_EVCR_PIN_PX13 ((uint8_t)0x0D) /!< Pin 13 selected /
Sergunb	0:f1834a63f7c1	2577	#define AFIO_EVCR_PIN_PX14 ((uint8_t)0x0E) /!< Pin 14 selected /
Sergunb	0:f1834a63f7c1	2578	#define AFIO_EVCR_PIN_PX15 ((uint8_t)0x0F) /!< Pin 15 selected /
Sergunb	0:f1834a63f7c1	2579
Sergunb	0:f1834a63f7c1	2580	#define AFIO_EVCR_PORT ((uint8_t)0x70) /!< PORT[2:0] bits (Port selection) /
Sergunb	0:f1834a63f7c1	2581	#define AFIO_EVCR_PORT_0 ((uint8_t)0x10) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2582	#define AFIO_EVCR_PORT_1 ((uint8_t)0x20) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2583	#define AFIO_EVCR_PORT_2 ((uint8_t)0x40) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	2584
Sergunb	0:f1834a63f7c1	2585	/!< PORT configuration /
Sergunb	0:f1834a63f7c1	2586	#define AFIO_EVCR_PORT_PA ((uint8_t)0x00) /!< Port A selected /
Sergunb	0:f1834a63f7c1	2587	#define AFIO_EVCR_PORT_PB ((uint8_t)0x10) /!< Port B selected /
Sergunb	0:f1834a63f7c1	2588	#define AFIO_EVCR_PORT_PC ((uint8_t)0x20) /!< Port C selected /
Sergunb	0:f1834a63f7c1	2589	#define AFIO_EVCR_PORT_PD ((uint8_t)0x30) /!< Port D selected /
Sergunb	0:f1834a63f7c1	2590	#define AFIO_EVCR_PORT_PE ((uint8_t)0x40) /!< Port E selected /
Sergunb	0:f1834a63f7c1	2591
Sergunb	0:f1834a63f7c1	2592	#define AFIO_EVCR_EVOE ((uint8_t)0x80) /!< Event Output Enable /
Sergunb	0:f1834a63f7c1	2593
Sergunb	0:f1834a63f7c1	2594	/**************** Bit definition for AFIO_MAPR register *****************/
Sergunb	0:f1834a63f7c1	2595	#define AFIO_MAPR_SPI1_REMAP ((uint32_t)0x00000001) /!< SPI1 remapping /
Sergunb	0:f1834a63f7c1	2596	#define AFIO_MAPR_I2C1_REMAP ((uint32_t)0x00000002) /!< I2C1 remapping /
Sergunb	0:f1834a63f7c1	2597	#define AFIO_MAPR_USART1_REMAP ((uint32_t)0x00000004) /!< USART1 remapping /
Sergunb	0:f1834a63f7c1	2598	#define AFIO_MAPR_USART2_REMAP ((uint32_t)0x00000008) /!< USART2 remapping /
Sergunb	0:f1834a63f7c1	2599
Sergunb	0:f1834a63f7c1	2600	#define AFIO_MAPR_USART3_REMAP ((uint32_t)0x00000030) /!< USART3_REMAP[1:0] bits (USART3 remapping) /
Sergunb	0:f1834a63f7c1	2601	#define AFIO_MAPR_USART3_REMAP_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2602	#define AFIO_MAPR_USART3_REMAP_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2603
Sergunb	0:f1834a63f7c1	2604	/* USART3_REMAP configuration */
Sergunb	0:f1834a63f7c1	2605	#define AFIO_MAPR_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) /
Sergunb	0:f1834a63f7c1	2606	#define AFIO_MAPR_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /!< Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) /
Sergunb	0:f1834a63f7c1	2607	#define AFIO_MAPR_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /!< Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) /
Sergunb	0:f1834a63f7c1	2608
Sergunb	0:f1834a63f7c1	2609	#define AFIO_MAPR_TIM1_REMAP ((uint32_t)0x000000C0) /!< TIM1_REMAP[1:0] bits (TIM1 remapping) /
Sergunb	0:f1834a63f7c1	2610	#define AFIO_MAPR_TIM1_REMAP_0 ((uint32_t)0x00000040) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2611	#define AFIO_MAPR_TIM1_REMAP_1 ((uint32_t)0x00000080) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2612
Sergunb	0:f1834a63f7c1	2613	/!< TIM1_REMAP configuration /
Sergunb	0:f1834a63f7c1	2614	#define AFIO_MAPR_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) /
Sergunb	0:f1834a63f7c1	2615	#define AFIO_MAPR_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /!< Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) /
Sergunb	0:f1834a63f7c1	2616	#define AFIO_MAPR_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /!< Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) /
Sergunb	0:f1834a63f7c1	2617
Sergunb	0:f1834a63f7c1	2618	#define AFIO_MAPR_TIM2_REMAP ((uint32_t)0x00000300) /!< TIM2_REMAP[1:0] bits (TIM2 remapping) /
Sergunb	0:f1834a63f7c1	2619	#define AFIO_MAPR_TIM2_REMAP_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2620	#define AFIO_MAPR_TIM2_REMAP_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2621
Sergunb	0:f1834a63f7c1	2622	/!< TIM2_REMAP configuration /
Sergunb	0:f1834a63f7c1	2623	#define AFIO_MAPR_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) /
Sergunb	0:f1834a63f7c1	2624	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /!< Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) /
Sergunb	0:f1834a63f7c1	2625	#define AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /!< Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) /
Sergunb	0:f1834a63f7c1	2626	#define AFIO_MAPR_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /!< Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) /
Sergunb	0:f1834a63f7c1	2627
Sergunb	0:f1834a63f7c1	2628	#define AFIO_MAPR_TIM3_REMAP ((uint32_t)0x00000C00) /!< TIM3_REMAP[1:0] bits (TIM3 remapping) /
Sergunb	0:f1834a63f7c1	2629	#define AFIO_MAPR_TIM3_REMAP_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2630	#define AFIO_MAPR_TIM3_REMAP_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2631
Sergunb	0:f1834a63f7c1	2632	/!< TIM3_REMAP configuration /
Sergunb	0:f1834a63f7c1	2633	#define AFIO_MAPR_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /!< No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) /
Sergunb	0:f1834a63f7c1	2634	#define AFIO_MAPR_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /!< Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) /
Sergunb	0:f1834a63f7c1	2635	#define AFIO_MAPR_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /!< Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) /
Sergunb	0:f1834a63f7c1	2636
Sergunb	0:f1834a63f7c1	2637	#define AFIO_MAPR_TIM4_REMAP ((uint32_t)0x00001000) /!< TIM4_REMAP bit (TIM4 remapping) /
Sergunb	0:f1834a63f7c1	2638
Sergunb	0:f1834a63f7c1	2639	#define AFIO_MAPR_CAN_REMAP ((uint32_t)0x00006000) /!< CAN_REMAP[1:0] bits (CAN Alternate function remapping) /
Sergunb	0:f1834a63f7c1	2640	#define AFIO_MAPR_CAN_REMAP_0 ((uint32_t)0x00002000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2641	#define AFIO_MAPR_CAN_REMAP_1 ((uint32_t)0x00004000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2642
Sergunb	0:f1834a63f7c1	2643	/!< CAN_REMAP configuration /
Sergunb	0:f1834a63f7c1	2644	#define AFIO_MAPR_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /!< CANRX mapped to PA11, CANTX mapped to PA12 /
Sergunb	0:f1834a63f7c1	2645	#define AFIO_MAPR_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /!< CANRX mapped to PB8, CANTX mapped to PB9 /
Sergunb	0:f1834a63f7c1	2646	#define AFIO_MAPR_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /!< CANRX mapped to PD0, CANTX mapped to PD1 /
Sergunb	0:f1834a63f7c1	2647
Sergunb	0:f1834a63f7c1	2648	#define AFIO_MAPR_PD01_REMAP ((uint32_t)0x00008000) /!< Port D0/Port D1 mapping on OSC_IN/OSC_OUT /
Sergunb	0:f1834a63f7c1	2649	#define AFIO_MAPR_TIM5CH4_IREMAP ((uint32_t)0x00010000) /!< TIM5 Channel4 Internal Remap /
Sergunb	0:f1834a63f7c1	2650	#define AFIO_MAPR_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /!< ADC 1 External Trigger Injected Conversion remapping /
Sergunb	0:f1834a63f7c1	2651	#define AFIO_MAPR_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /!< ADC 1 External Trigger Regular Conversion remapping /
Sergunb	0:f1834a63f7c1	2652	#define AFIO_MAPR_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /!< ADC 2 External Trigger Injected Conversion remapping /
Sergunb	0:f1834a63f7c1	2653	#define AFIO_MAPR_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /!< ADC 2 External Trigger Regular Conversion remapping /
Sergunb	0:f1834a63f7c1	2654
Sergunb	0:f1834a63f7c1	2655	/!< SWJ_CFG configuration /
Sergunb	0:f1834a63f7c1	2656	#define AFIO_MAPR_SWJ_CFG ((uint32_t)0x07000000) /!< SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) /
Sergunb	0:f1834a63f7c1	2657	#define AFIO_MAPR_SWJ_CFG_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	2658	#define AFIO_MAPR_SWJ_CFG_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	2659	#define AFIO_MAPR_SWJ_CFG_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	2660
Sergunb	0:f1834a63f7c1	2661	#define AFIO_MAPR_SWJ_CFG_RESET ((uint32_t)0x00000000) /!< Full SWJ (JTAG-DP + SW-DP) : Reset State /
Sergunb	0:f1834a63f7c1	2662	#define AFIO_MAPR_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /!< Full SWJ (JTAG-DP + SW-DP) but without JNTRST /
Sergunb	0:f1834a63f7c1	2663	#define AFIO_MAPR_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /!< JTAG-DP Disabled and SW-DP Enabled /
Sergunb	0:f1834a63f7c1	2664	#define AFIO_MAPR_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /!< JTAG-DP Disabled and SW-DP Disabled /
Sergunb	0:f1834a63f7c1	2665
Sergunb	0:f1834a63f7c1	2666	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	2667	/!< ETH_REMAP configuration /
Sergunb	0:f1834a63f7c1	2668	#define AFIO_MAPR_ETH_REMAP ((uint32_t)0x00200000) /!< SPI3_REMAP bit (Ethernet MAC I/O remapping) /
Sergunb	0:f1834a63f7c1	2669
Sergunb	0:f1834a63f7c1	2670	/!< CAN2_REMAP configuration /
Sergunb	0:f1834a63f7c1	2671	#define AFIO_MAPR_CAN2_REMAP ((uint32_t)0x00400000) /!< CAN2_REMAP bit (CAN2 I/O remapping) /
Sergunb	0:f1834a63f7c1	2672
Sergunb	0:f1834a63f7c1	2673	/!< MII_RMII_SEL configuration /
Sergunb	0:f1834a63f7c1	2674	#define AFIO_MAPR_MII_RMII_SEL ((uint32_t)0x00800000) /!< MII_RMII_SEL bit (Ethernet MII or RMII selection) /
Sergunb	0:f1834a63f7c1	2675
Sergunb	0:f1834a63f7c1	2676	/!< SPI3_REMAP configuration /
Sergunb	0:f1834a63f7c1	2677	#define AFIO_MAPR_SPI3_REMAP ((uint32_t)0x10000000) /!< SPI3_REMAP bit (SPI3 remapping) /
Sergunb	0:f1834a63f7c1	2678
Sergunb	0:f1834a63f7c1	2679	/!< TIM2ITR1_IREMAP configuration /
Sergunb	0:f1834a63f7c1	2680	#define AFIO_MAPR_TIM2ITR1_IREMAP ((uint32_t)0x20000000) /!< TIM2ITR1_IREMAP bit (TIM2 internal trigger 1 remapping) /
Sergunb	0:f1834a63f7c1	2681
Sergunb	0:f1834a63f7c1	2682	/!< PTP_PPS_REMAP configuration /
Sergunb	0:f1834a63f7c1	2683	#define AFIO_MAPR_PTP_PPS_REMAP ((uint32_t)0x40000000) /!< PTP_PPS_REMAP bit (Ethernet PTP PPS remapping) /
Sergunb	0:f1834a63f7c1	2684	#endif
Sergunb	0:f1834a63f7c1	2685
Sergunb	0:f1834a63f7c1	2686	/*************** Bit definition for AFIO_EXTICR1 register ***************/
Sergunb	0:f1834a63f7c1	2687	#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
Sergunb	0:f1834a63f7c1	2688	#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
Sergunb	0:f1834a63f7c1	2689	#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
Sergunb	0:f1834a63f7c1	2690	#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
Sergunb	0:f1834a63f7c1	2691
Sergunb	0:f1834a63f7c1	2692	/!< EXTI0 configuration /
Sergunb	0:f1834a63f7c1	2693	#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
Sergunb	0:f1834a63f7c1	2694	#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
Sergunb	0:f1834a63f7c1	2695	#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
Sergunb	0:f1834a63f7c1	2696	#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
Sergunb	0:f1834a63f7c1	2697	#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /!< PE[0] pin /
Sergunb	0:f1834a63f7c1	2698	#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!< PF[0] pin /
Sergunb	0:f1834a63f7c1	2699	#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /!< PG[0] pin /
Sergunb	0:f1834a63f7c1	2700
Sergunb	0:f1834a63f7c1	2701	/!< EXTI1 configuration /
Sergunb	0:f1834a63f7c1	2702	#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
Sergunb	0:f1834a63f7c1	2703	#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
Sergunb	0:f1834a63f7c1	2704	#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
Sergunb	0:f1834a63f7c1	2705	#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
Sergunb	0:f1834a63f7c1	2706	#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /!< PE[1] pin /
Sergunb	0:f1834a63f7c1	2707	#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!< PF[1] pin /
Sergunb	0:f1834a63f7c1	2708	#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /!< PG[1] pin /
Sergunb	0:f1834a63f7c1	2709
Sergunb	0:f1834a63f7c1	2710	/!< EXTI2 configuration /
Sergunb	0:f1834a63f7c1	2711	#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
Sergunb	0:f1834a63f7c1	2712	#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
Sergunb	0:f1834a63f7c1	2713	#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
Sergunb	0:f1834a63f7c1	2714	#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
Sergunb	0:f1834a63f7c1	2715	#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /!< PE[2] pin /
Sergunb	0:f1834a63f7c1	2716	#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!< PF[2] pin /
Sergunb	0:f1834a63f7c1	2717	#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /!< PG[2] pin /
Sergunb	0:f1834a63f7c1	2718
Sergunb	0:f1834a63f7c1	2719	/!< EXTI3 configuration /
Sergunb	0:f1834a63f7c1	2720	#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
Sergunb	0:f1834a63f7c1	2721	#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
Sergunb	0:f1834a63f7c1	2722	#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
Sergunb	0:f1834a63f7c1	2723	#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
Sergunb	0:f1834a63f7c1	2724	#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /!< PE[3] pin /
Sergunb	0:f1834a63f7c1	2725	#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /!< PF[3] pin /
Sergunb	0:f1834a63f7c1	2726	#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /!< PG[3] pin /
Sergunb	0:f1834a63f7c1	2727
Sergunb	0:f1834a63f7c1	2728	/*************** Bit definition for AFIO_EXTICR2 register ***************/
Sergunb	0:f1834a63f7c1	2729	#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
Sergunb	0:f1834a63f7c1	2730	#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
Sergunb	0:f1834a63f7c1	2731	#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
Sergunb	0:f1834a63f7c1	2732	#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
Sergunb	0:f1834a63f7c1	2733
Sergunb	0:f1834a63f7c1	2734	/!< EXTI4 configuration /
Sergunb	0:f1834a63f7c1	2735	#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
Sergunb	0:f1834a63f7c1	2736	#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
Sergunb	0:f1834a63f7c1	2737	#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
Sergunb	0:f1834a63f7c1	2738	#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
Sergunb	0:f1834a63f7c1	2739	#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /!< PE[4] pin /
Sergunb	0:f1834a63f7c1	2740	#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /!< PF[4] pin /
Sergunb	0:f1834a63f7c1	2741	#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /!< PG[4] pin /
Sergunb	0:f1834a63f7c1	2742
Sergunb	0:f1834a63f7c1	2743	/* EXTI5 configuration */
Sergunb	0:f1834a63f7c1	2744	#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
Sergunb	0:f1834a63f7c1	2745	#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
Sergunb	0:f1834a63f7c1	2746	#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
Sergunb	0:f1834a63f7c1	2747	#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
Sergunb	0:f1834a63f7c1	2748	#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /!< PE[5] pin /
Sergunb	0:f1834a63f7c1	2749	#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /!< PF[5] pin /
Sergunb	0:f1834a63f7c1	2750	#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /!< PG[5] pin /
Sergunb	0:f1834a63f7c1	2751
Sergunb	0:f1834a63f7c1	2752	/!< EXTI6 configuration /
Sergunb	0:f1834a63f7c1	2753	#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
Sergunb	0:f1834a63f7c1	2754	#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
Sergunb	0:f1834a63f7c1	2755	#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
Sergunb	0:f1834a63f7c1	2756	#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
Sergunb	0:f1834a63f7c1	2757	#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /!< PE[6] pin /
Sergunb	0:f1834a63f7c1	2758	#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /!< PF[6] pin /
Sergunb	0:f1834a63f7c1	2759	#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /!< PG[6] pin /
Sergunb	0:f1834a63f7c1	2760
Sergunb	0:f1834a63f7c1	2761	/!< EXTI7 configuration /
Sergunb	0:f1834a63f7c1	2762	#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
Sergunb	0:f1834a63f7c1	2763	#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
Sergunb	0:f1834a63f7c1	2764	#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
Sergunb	0:f1834a63f7c1	2765	#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
Sergunb	0:f1834a63f7c1	2766	#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /!< PE[7] pin /
Sergunb	0:f1834a63f7c1	2767	#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /!< PF[7] pin /
Sergunb	0:f1834a63f7c1	2768	#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /!< PG[7] pin /
Sergunb	0:f1834a63f7c1	2769
Sergunb	0:f1834a63f7c1	2770	/*************** Bit definition for AFIO_EXTICR3 register ***************/
Sergunb	0:f1834a63f7c1	2771	#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
Sergunb	0:f1834a63f7c1	2772	#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
Sergunb	0:f1834a63f7c1	2773	#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
Sergunb	0:f1834a63f7c1	2774	#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
Sergunb	0:f1834a63f7c1	2775
Sergunb	0:f1834a63f7c1	2776	/!< EXTI8 configuration /
Sergunb	0:f1834a63f7c1	2777	#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
Sergunb	0:f1834a63f7c1	2778	#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
Sergunb	0:f1834a63f7c1	2779	#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
Sergunb	0:f1834a63f7c1	2780	#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
Sergunb	0:f1834a63f7c1	2781	#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /!< PE[8] pin /
Sergunb	0:f1834a63f7c1	2782	#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /!< PF[8] pin /
Sergunb	0:f1834a63f7c1	2783	#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /!< PG[8] pin /
Sergunb	0:f1834a63f7c1	2784
Sergunb	0:f1834a63f7c1	2785	/!< EXTI9 configuration /
Sergunb	0:f1834a63f7c1	2786	#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
Sergunb	0:f1834a63f7c1	2787	#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
Sergunb	0:f1834a63f7c1	2788	#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
Sergunb	0:f1834a63f7c1	2789	#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
Sergunb	0:f1834a63f7c1	2790	#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /!< PE[9] pin /
Sergunb	0:f1834a63f7c1	2791	#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!< PF[9] pin /
Sergunb	0:f1834a63f7c1	2792	#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /!< PG[9] pin /
Sergunb	0:f1834a63f7c1	2793
Sergunb	0:f1834a63f7c1	2794	/!< EXTI10 configuration /
Sergunb	0:f1834a63f7c1	2795	#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
Sergunb	0:f1834a63f7c1	2796	#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
Sergunb	0:f1834a63f7c1	2797	#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
Sergunb	0:f1834a63f7c1	2798	#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PD[10] pin /
Sergunb	0:f1834a63f7c1	2799	#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /!< PE[10] pin /
Sergunb	0:f1834a63f7c1	2800	#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!< PF[10] pin /
Sergunb	0:f1834a63f7c1	2801	#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /!< PG[10] pin /
Sergunb	0:f1834a63f7c1	2802
Sergunb	0:f1834a63f7c1	2803	/!< EXTI11 configuration /
Sergunb	0:f1834a63f7c1	2804	#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
Sergunb	0:f1834a63f7c1	2805	#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
Sergunb	0:f1834a63f7c1	2806	#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
Sergunb	0:f1834a63f7c1	2807	#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
Sergunb	0:f1834a63f7c1	2808	#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /!< PE[11] pin /
Sergunb	0:f1834a63f7c1	2809	#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /!< PF[11] pin /
Sergunb	0:f1834a63f7c1	2810	#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /!< PG[11] pin /
Sergunb	0:f1834a63f7c1	2811
Sergunb	0:f1834a63f7c1	2812	/*************** Bit definition for AFIO_EXTICR4 register ***************/
Sergunb	0:f1834a63f7c1	2813	#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
Sergunb	0:f1834a63f7c1	2814	#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
Sergunb	0:f1834a63f7c1	2815	#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
Sergunb	0:f1834a63f7c1	2816	#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
Sergunb	0:f1834a63f7c1	2817
Sergunb	0:f1834a63f7c1	2818	/* EXTI12 configuration */
Sergunb	0:f1834a63f7c1	2819	#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
Sergunb	0:f1834a63f7c1	2820	#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
Sergunb	0:f1834a63f7c1	2821	#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
Sergunb	0:f1834a63f7c1	2822	#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
Sergunb	0:f1834a63f7c1	2823	#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /!< PE[12] pin /
Sergunb	0:f1834a63f7c1	2824	#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /!< PF[12] pin /
Sergunb	0:f1834a63f7c1	2825	#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /!< PG[12] pin /
Sergunb	0:f1834a63f7c1	2826
Sergunb	0:f1834a63f7c1	2827	/* EXTI13 configuration */
Sergunb	0:f1834a63f7c1	2828	#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
Sergunb	0:f1834a63f7c1	2829	#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
Sergunb	0:f1834a63f7c1	2830	#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
Sergunb	0:f1834a63f7c1	2831	#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
Sergunb	0:f1834a63f7c1	2832	#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /!< PE[13] pin /
Sergunb	0:f1834a63f7c1	2833	#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /!< PF[13] pin /
Sergunb	0:f1834a63f7c1	2834	#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /!< PG[13] pin /
Sergunb	0:f1834a63f7c1	2835
Sergunb	0:f1834a63f7c1	2836	/!< EXTI14 configuration /
Sergunb	0:f1834a63f7c1	2837	#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
Sergunb	0:f1834a63f7c1	2838	#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
Sergunb	0:f1834a63f7c1	2839	#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
Sergunb	0:f1834a63f7c1	2840	#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
Sergunb	0:f1834a63f7c1	2841	#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /!< PE[14] pin /
Sergunb	0:f1834a63f7c1	2842	#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /!< PF[14] pin /
Sergunb	0:f1834a63f7c1	2843	#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /!< PG[14] pin /
Sergunb	0:f1834a63f7c1	2844
Sergunb	0:f1834a63f7c1	2845	/!< EXTI15 configuration /
Sergunb	0:f1834a63f7c1	2846	#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
Sergunb	0:f1834a63f7c1	2847	#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
Sergunb	0:f1834a63f7c1	2848	#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
Sergunb	0:f1834a63f7c1	2849	#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
Sergunb	0:f1834a63f7c1	2850	#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /!< PE[15] pin /
Sergunb	0:f1834a63f7c1	2851	#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /!< PF[15] pin /
Sergunb	0:f1834a63f7c1	2852	#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /!< PG[15] pin /
Sergunb	0:f1834a63f7c1	2853
Sergunb	0:f1834a63f7c1	2854	#if defined (STM32F10X_LD_VL) \|\| defined (STM32F10X_MD_VL) \|\| defined (STM32F10X_HD_VL)
Sergunb	0:f1834a63f7c1	2855	/**************** Bit definition for AFIO_MAPR2 register ****************/
Sergunb	0:f1834a63f7c1	2856	#define AFIO_MAPR2_TIM15_REMAP ((uint32_t)0x00000001) /!< TIM15 remapping /
Sergunb	0:f1834a63f7c1	2857	#define AFIO_MAPR2_TIM16_REMAP ((uint32_t)0x00000002) /!< TIM16 remapping /
Sergunb	0:f1834a63f7c1	2858	#define AFIO_MAPR2_TIM17_REMAP ((uint32_t)0x00000004) /!< TIM17 remapping /
Sergunb	0:f1834a63f7c1	2859	#define AFIO_MAPR2_CEC_REMAP ((uint32_t)0x00000008) /!< CEC remapping /
Sergunb	0:f1834a63f7c1	2860	#define AFIO_MAPR2_TIM1_DMA_REMAP ((uint32_t)0x00000010) /!< TIM1_DMA remapping /
Sergunb	0:f1834a63f7c1	2861	#endif
Sergunb	0:f1834a63f7c1	2862
Sergunb	0:f1834a63f7c1	2863	#ifdef STM32F10X_HD_VL
Sergunb	0:f1834a63f7c1	2864	#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /!< TIM13 remapping /
Sergunb	0:f1834a63f7c1	2865	#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /!< TIM14 remapping /
Sergunb	0:f1834a63f7c1	2866	#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /!< FSMC NADV remapping /
Sergunb	0:f1834a63f7c1	2867	#define AFIO_MAPR2_TIM67_DAC_DMA_REMAP ((uint32_t)0x00000800) /!< TIM6/TIM7 and DAC DMA remapping /
Sergunb	0:f1834a63f7c1	2868	#define AFIO_MAPR2_TIM12_REMAP ((uint32_t)0x00001000) /!< TIM12 remapping /
Sergunb	0:f1834a63f7c1	2869	#define AFIO_MAPR2_MISC_REMAP ((uint32_t)0x00002000) /!< Miscellaneous remapping /
Sergunb	0:f1834a63f7c1	2870	#endif
Sergunb	0:f1834a63f7c1	2871
Sergunb	0:f1834a63f7c1	2872	#ifdef STM32F10X_XL
Sergunb	0:f1834a63f7c1	2873	/**************** Bit definition for AFIO_MAPR2 register ****************/
Sergunb	0:f1834a63f7c1	2874	#define AFIO_MAPR2_TIM9_REMAP ((uint32_t)0x00000020) /!< TIM9 remapping /
Sergunb	0:f1834a63f7c1	2875	#define AFIO_MAPR2_TIM10_REMAP ((uint32_t)0x00000040) /!< TIM10 remapping /
Sergunb	0:f1834a63f7c1	2876	#define AFIO_MAPR2_TIM11_REMAP ((uint32_t)0x00000080) /!< TIM11 remapping /
Sergunb	0:f1834a63f7c1	2877	#define AFIO_MAPR2_TIM13_REMAP ((uint32_t)0x00000100) /!< TIM13 remapping /
Sergunb	0:f1834a63f7c1	2878	#define AFIO_MAPR2_TIM14_REMAP ((uint32_t)0x00000200) /!< TIM14 remapping /
Sergunb	0:f1834a63f7c1	2879	#define AFIO_MAPR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) /!< FSMC NADV remapping /
Sergunb	0:f1834a63f7c1	2880	#endif
Sergunb	0:f1834a63f7c1	2881
Sergunb	0:f1834a63f7c1	2882	/******************************************************************************/
Sergunb	0:f1834a63f7c1	2883	/* */
Sergunb	0:f1834a63f7c1	2884	/* SystemTick */
Sergunb	0:f1834a63f7c1	2885	/* */
Sergunb	0:f1834a63f7c1	2886	/******************************************************************************/
Sergunb	0:f1834a63f7c1	2887
Sergunb	0:f1834a63f7c1	2888	/*************** Bit definition for SysTick_CTRL register ***************/
Sergunb	0:f1834a63f7c1	2889	#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /!< Counter enable /
Sergunb	0:f1834a63f7c1	2890	#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /!< Counting down to 0 pends the SysTick handler /
Sergunb	0:f1834a63f7c1	2891	#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /!< Clock source /
Sergunb	0:f1834a63f7c1	2892	#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /!< Count Flag /
Sergunb	0:f1834a63f7c1	2893
Sergunb	0:f1834a63f7c1	2894	/*************** Bit definition for SysTick_LOAD register ***************/
Sergunb	0:f1834a63f7c1	2895	#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /!< Value to load into the SysTick Current Value Register when the counter reaches 0 /
Sergunb	0:f1834a63f7c1	2896
Sergunb	0:f1834a63f7c1	2897	/*************** Bit definition for SysTick_VAL register ****************/
Sergunb	0:f1834a63f7c1	2898	#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /!< Current value at the time the register is accessed /
Sergunb	0:f1834a63f7c1	2899
Sergunb	0:f1834a63f7c1	2900	/*************** Bit definition for SysTick_CALIB register **************/
Sergunb	0:f1834a63f7c1	2901	#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /!< Reload value to use for 10ms timing /
Sergunb	0:f1834a63f7c1	2902	#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /!< Calibration value is not exactly 10 ms /
Sergunb	0:f1834a63f7c1	2903	#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /!< The reference clock is not provided /
Sergunb	0:f1834a63f7c1	2904
Sergunb	0:f1834a63f7c1	2905	/******************************************************************************/
Sergunb	0:f1834a63f7c1	2906	/* */
Sergunb	0:f1834a63f7c1	2907	/* Nested Vectored Interrupt Controller */
Sergunb	0:f1834a63f7c1	2908	/* */
Sergunb	0:f1834a63f7c1	2909	/******************************************************************************/
Sergunb	0:f1834a63f7c1	2910
Sergunb	0:f1834a63f7c1	2911	/**************** Bit definition for NVIC_ISER register *****************/
Sergunb	0:f1834a63f7c1	2912	#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /!< Interrupt set enable bits /
Sergunb	0:f1834a63f7c1	2913	#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /!< bit 0 /
Sergunb	0:f1834a63f7c1	2914	#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /!< bit 1 /
Sergunb	0:f1834a63f7c1	2915	#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /!< bit 2 /
Sergunb	0:f1834a63f7c1	2916	#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /!< bit 3 /
Sergunb	0:f1834a63f7c1	2917	#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /!< bit 4 /
Sergunb	0:f1834a63f7c1	2918	#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /!< bit 5 /
Sergunb	0:f1834a63f7c1	2919	#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /!< bit 6 /
Sergunb	0:f1834a63f7c1	2920	#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /!< bit 7 /
Sergunb	0:f1834a63f7c1	2921	#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /!< bit 8 /
Sergunb	0:f1834a63f7c1	2922	#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /!< bit 9 /
Sergunb	0:f1834a63f7c1	2923	#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /!< bit 10 /
Sergunb	0:f1834a63f7c1	2924	#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /!< bit 11 /
Sergunb	0:f1834a63f7c1	2925	#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /!< bit 12 /
Sergunb	0:f1834a63f7c1	2926	#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /!< bit 13 /
Sergunb	0:f1834a63f7c1	2927	#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /!< bit 14 /
Sergunb	0:f1834a63f7c1	2928	#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /!< bit 15 /
Sergunb	0:f1834a63f7c1	2929	#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /!< bit 16 /
Sergunb	0:f1834a63f7c1	2930	#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /!< bit 17 /
Sergunb	0:f1834a63f7c1	2931	#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /!< bit 18 /
Sergunb	0:f1834a63f7c1	2932	#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /!< bit 19 /
Sergunb	0:f1834a63f7c1	2933	#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /!< bit 20 /
Sergunb	0:f1834a63f7c1	2934	#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /!< bit 21 /
Sergunb	0:f1834a63f7c1	2935	#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /!< bit 22 /
Sergunb	0:f1834a63f7c1	2936	#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /!< bit 23 /
Sergunb	0:f1834a63f7c1	2937	#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /!< bit 24 /
Sergunb	0:f1834a63f7c1	2938	#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /!< bit 25 /
Sergunb	0:f1834a63f7c1	2939	#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /!< bit 26 /
Sergunb	0:f1834a63f7c1	2940	#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /!< bit 27 /
Sergunb	0:f1834a63f7c1	2941	#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /!< bit 28 /
Sergunb	0:f1834a63f7c1	2942	#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /!< bit 29 /
Sergunb	0:f1834a63f7c1	2943	#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /!< bit 30 /
Sergunb	0:f1834a63f7c1	2944	#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /!< bit 31 /
Sergunb	0:f1834a63f7c1	2945
Sergunb	0:f1834a63f7c1	2946	/**************** Bit definition for NVIC_ICER register *****************/
Sergunb	0:f1834a63f7c1	2947	#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-enable bits /
Sergunb	0:f1834a63f7c1	2948	#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /!< bit 0 /
Sergunb	0:f1834a63f7c1	2949	#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /!< bit 1 /
Sergunb	0:f1834a63f7c1	2950	#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /!< bit 2 /
Sergunb	0:f1834a63f7c1	2951	#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /!< bit 3 /
Sergunb	0:f1834a63f7c1	2952	#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /!< bit 4 /
Sergunb	0:f1834a63f7c1	2953	#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /!< bit 5 /
Sergunb	0:f1834a63f7c1	2954	#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /!< bit 6 /
Sergunb	0:f1834a63f7c1	2955	#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /!< bit 7 /
Sergunb	0:f1834a63f7c1	2956	#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /!< bit 8 /
Sergunb	0:f1834a63f7c1	2957	#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /!< bit 9 /
Sergunb	0:f1834a63f7c1	2958	#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /!< bit 10 /
Sergunb	0:f1834a63f7c1	2959	#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /!< bit 11 /
Sergunb	0:f1834a63f7c1	2960	#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /!< bit 12 /
Sergunb	0:f1834a63f7c1	2961	#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /!< bit 13 /
Sergunb	0:f1834a63f7c1	2962	#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /!< bit 14 /
Sergunb	0:f1834a63f7c1	2963	#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /!< bit 15 /
Sergunb	0:f1834a63f7c1	2964	#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /!< bit 16 /
Sergunb	0:f1834a63f7c1	2965	#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /!< bit 17 /
Sergunb	0:f1834a63f7c1	2966	#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /!< bit 18 /
Sergunb	0:f1834a63f7c1	2967	#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /!< bit 19 /
Sergunb	0:f1834a63f7c1	2968	#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /!< bit 20 /
Sergunb	0:f1834a63f7c1	2969	#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /!< bit 21 /
Sergunb	0:f1834a63f7c1	2970	#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /!< bit 22 /
Sergunb	0:f1834a63f7c1	2971	#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /!< bit 23 /
Sergunb	0:f1834a63f7c1	2972	#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /!< bit 24 /
Sergunb	0:f1834a63f7c1	2973	#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /!< bit 25 /
Sergunb	0:f1834a63f7c1	2974	#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /!< bit 26 /
Sergunb	0:f1834a63f7c1	2975	#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /!< bit 27 /
Sergunb	0:f1834a63f7c1	2976	#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /!< bit 28 /
Sergunb	0:f1834a63f7c1	2977	#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /!< bit 29 /
Sergunb	0:f1834a63f7c1	2978	#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /!< bit 30 /
Sergunb	0:f1834a63f7c1	2979	#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /!< bit 31 /
Sergunb	0:f1834a63f7c1	2980
Sergunb	0:f1834a63f7c1	2981	/**************** Bit definition for NVIC_ISPR register *****************/
Sergunb	0:f1834a63f7c1	2982	#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt set-pending bits /
Sergunb	0:f1834a63f7c1	2983	#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
Sergunb	0:f1834a63f7c1	2984	#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
Sergunb	0:f1834a63f7c1	2985	#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
Sergunb	0:f1834a63f7c1	2986	#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
Sergunb	0:f1834a63f7c1	2987	#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
Sergunb	0:f1834a63f7c1	2988	#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
Sergunb	0:f1834a63f7c1	2989	#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
Sergunb	0:f1834a63f7c1	2990	#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
Sergunb	0:f1834a63f7c1	2991	#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
Sergunb	0:f1834a63f7c1	2992	#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
Sergunb	0:f1834a63f7c1	2993	#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
Sergunb	0:f1834a63f7c1	2994	#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
Sergunb	0:f1834a63f7c1	2995	#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
Sergunb	0:f1834a63f7c1	2996	#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
Sergunb	0:f1834a63f7c1	2997	#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
Sergunb	0:f1834a63f7c1	2998	#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
Sergunb	0:f1834a63f7c1	2999	#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
Sergunb	0:f1834a63f7c1	3000	#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
Sergunb	0:f1834a63f7c1	3001	#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
Sergunb	0:f1834a63f7c1	3002	#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
Sergunb	0:f1834a63f7c1	3003	#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
Sergunb	0:f1834a63f7c1	3004	#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
Sergunb	0:f1834a63f7c1	3005	#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
Sergunb	0:f1834a63f7c1	3006	#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
Sergunb	0:f1834a63f7c1	3007	#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
Sergunb	0:f1834a63f7c1	3008	#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
Sergunb	0:f1834a63f7c1	3009	#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
Sergunb	0:f1834a63f7c1	3010	#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
Sergunb	0:f1834a63f7c1	3011	#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
Sergunb	0:f1834a63f7c1	3012	#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
Sergunb	0:f1834a63f7c1	3013	#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
Sergunb	0:f1834a63f7c1	3014	#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
Sergunb	0:f1834a63f7c1	3015
Sergunb	0:f1834a63f7c1	3016	/**************** Bit definition for NVIC_ICPR register *****************/
Sergunb	0:f1834a63f7c1	3017	#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /!< Interrupt clear-pending bits /
Sergunb	0:f1834a63f7c1	3018	#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /!< bit 0 /
Sergunb	0:f1834a63f7c1	3019	#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /!< bit 1 /
Sergunb	0:f1834a63f7c1	3020	#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /!< bit 2 /
Sergunb	0:f1834a63f7c1	3021	#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /!< bit 3 /
Sergunb	0:f1834a63f7c1	3022	#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /!< bit 4 /
Sergunb	0:f1834a63f7c1	3023	#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /!< bit 5 /
Sergunb	0:f1834a63f7c1	3024	#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /!< bit 6 /
Sergunb	0:f1834a63f7c1	3025	#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /!< bit 7 /
Sergunb	0:f1834a63f7c1	3026	#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /!< bit 8 /
Sergunb	0:f1834a63f7c1	3027	#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /!< bit 9 /
Sergunb	0:f1834a63f7c1	3028	#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /!< bit 10 /
Sergunb	0:f1834a63f7c1	3029	#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /!< bit 11 /
Sergunb	0:f1834a63f7c1	3030	#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /!< bit 12 /
Sergunb	0:f1834a63f7c1	3031	#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /!< bit 13 /
Sergunb	0:f1834a63f7c1	3032	#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /!< bit 14 /
Sergunb	0:f1834a63f7c1	3033	#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /!< bit 15 /
Sergunb	0:f1834a63f7c1	3034	#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /!< bit 16 /
Sergunb	0:f1834a63f7c1	3035	#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /!< bit 17 /
Sergunb	0:f1834a63f7c1	3036	#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /!< bit 18 /
Sergunb	0:f1834a63f7c1	3037	#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /!< bit 19 /
Sergunb	0:f1834a63f7c1	3038	#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /!< bit 20 /
Sergunb	0:f1834a63f7c1	3039	#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /!< bit 21 /
Sergunb	0:f1834a63f7c1	3040	#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /!< bit 22 /
Sergunb	0:f1834a63f7c1	3041	#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /!< bit 23 /
Sergunb	0:f1834a63f7c1	3042	#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /!< bit 24 /
Sergunb	0:f1834a63f7c1	3043	#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /!< bit 25 /
Sergunb	0:f1834a63f7c1	3044	#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /!< bit 26 /
Sergunb	0:f1834a63f7c1	3045	#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /!< bit 27 /
Sergunb	0:f1834a63f7c1	3046	#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /!< bit 28 /
Sergunb	0:f1834a63f7c1	3047	#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /!< bit 29 /
Sergunb	0:f1834a63f7c1	3048	#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /!< bit 30 /
Sergunb	0:f1834a63f7c1	3049	#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /!< bit 31 /
Sergunb	0:f1834a63f7c1	3050
Sergunb	0:f1834a63f7c1	3051	/**************** Bit definition for NVIC_IABR register *****************/
Sergunb	0:f1834a63f7c1	3052	#define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /!< Interrupt active flags /
Sergunb	0:f1834a63f7c1	3053	#define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /!< bit 0 /
Sergunb	0:f1834a63f7c1	3054	#define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /!< bit 1 /
Sergunb	0:f1834a63f7c1	3055	#define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /!< bit 2 /
Sergunb	0:f1834a63f7c1	3056	#define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /!< bit 3 /
Sergunb	0:f1834a63f7c1	3057	#define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /!< bit 4 /
Sergunb	0:f1834a63f7c1	3058	#define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /!< bit 5 /
Sergunb	0:f1834a63f7c1	3059	#define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /!< bit 6 /
Sergunb	0:f1834a63f7c1	3060	#define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /!< bit 7 /
Sergunb	0:f1834a63f7c1	3061	#define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /!< bit 8 /
Sergunb	0:f1834a63f7c1	3062	#define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /!< bit 9 /
Sergunb	0:f1834a63f7c1	3063	#define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /!< bit 10 /
Sergunb	0:f1834a63f7c1	3064	#define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /!< bit 11 /
Sergunb	0:f1834a63f7c1	3065	#define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /!< bit 12 /
Sergunb	0:f1834a63f7c1	3066	#define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /!< bit 13 /
Sergunb	0:f1834a63f7c1	3067	#define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /!< bit 14 /
Sergunb	0:f1834a63f7c1	3068	#define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /!< bit 15 /
Sergunb	0:f1834a63f7c1	3069	#define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /!< bit 16 /
Sergunb	0:f1834a63f7c1	3070	#define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /!< bit 17 /
Sergunb	0:f1834a63f7c1	3071	#define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /!< bit 18 /
Sergunb	0:f1834a63f7c1	3072	#define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /!< bit 19 /
Sergunb	0:f1834a63f7c1	3073	#define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /!< bit 20 /
Sergunb	0:f1834a63f7c1	3074	#define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /!< bit 21 /
Sergunb	0:f1834a63f7c1	3075	#define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /!< bit 22 /
Sergunb	0:f1834a63f7c1	3076	#define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /!< bit 23 /
Sergunb	0:f1834a63f7c1	3077	#define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /!< bit 24 /
Sergunb	0:f1834a63f7c1	3078	#define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /!< bit 25 /
Sergunb	0:f1834a63f7c1	3079	#define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /!< bit 26 /
Sergunb	0:f1834a63f7c1	3080	#define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /!< bit 27 /
Sergunb	0:f1834a63f7c1	3081	#define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /!< bit 28 /
Sergunb	0:f1834a63f7c1	3082	#define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /!< bit 29 /
Sergunb	0:f1834a63f7c1	3083	#define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /!< bit 30 /
Sergunb	0:f1834a63f7c1	3084	#define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /!< bit 31 /
Sergunb	0:f1834a63f7c1	3085
Sergunb	0:f1834a63f7c1	3086	/**************** Bit definition for NVIC_PRI0 register *****************/
Sergunb	0:f1834a63f7c1	3087	#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /!< Priority of interrupt 0 /
Sergunb	0:f1834a63f7c1	3088	#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /!< Priority of interrupt 1 /
Sergunb	0:f1834a63f7c1	3089	#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /!< Priority of interrupt 2 /
Sergunb	0:f1834a63f7c1	3090	#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /!< Priority of interrupt 3 /
Sergunb	0:f1834a63f7c1	3091
Sergunb	0:f1834a63f7c1	3092	/**************** Bit definition for NVIC_PRI1 register *****************/
Sergunb	0:f1834a63f7c1	3093	#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /!< Priority of interrupt 4 /
Sergunb	0:f1834a63f7c1	3094	#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /!< Priority of interrupt 5 /
Sergunb	0:f1834a63f7c1	3095	#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /!< Priority of interrupt 6 /
Sergunb	0:f1834a63f7c1	3096	#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /!< Priority of interrupt 7 /
Sergunb	0:f1834a63f7c1	3097
Sergunb	0:f1834a63f7c1	3098	/**************** Bit definition for NVIC_PRI2 register *****************/
Sergunb	0:f1834a63f7c1	3099	#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /!< Priority of interrupt 8 /
Sergunb	0:f1834a63f7c1	3100	#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /!< Priority of interrupt 9 /
Sergunb	0:f1834a63f7c1	3101	#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /!< Priority of interrupt 10 /
Sergunb	0:f1834a63f7c1	3102	#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /!< Priority of interrupt 11 /
Sergunb	0:f1834a63f7c1	3103
Sergunb	0:f1834a63f7c1	3104	/**************** Bit definition for NVIC_PRI3 register *****************/
Sergunb	0:f1834a63f7c1	3105	#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /!< Priority of interrupt 12 /
Sergunb	0:f1834a63f7c1	3106	#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /!< Priority of interrupt 13 /
Sergunb	0:f1834a63f7c1	3107	#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /!< Priority of interrupt 14 /
Sergunb	0:f1834a63f7c1	3108	#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /!< Priority of interrupt 15 /
Sergunb	0:f1834a63f7c1	3109
Sergunb	0:f1834a63f7c1	3110	/**************** Bit definition for NVIC_PRI4 register *****************/
Sergunb	0:f1834a63f7c1	3111	#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /!< Priority of interrupt 16 /
Sergunb	0:f1834a63f7c1	3112	#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /!< Priority of interrupt 17 /
Sergunb	0:f1834a63f7c1	3113	#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /!< Priority of interrupt 18 /
Sergunb	0:f1834a63f7c1	3114	#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /!< Priority of interrupt 19 /
Sergunb	0:f1834a63f7c1	3115
Sergunb	0:f1834a63f7c1	3116	/**************** Bit definition for NVIC_PRI5 register *****************/
Sergunb	0:f1834a63f7c1	3117	#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /!< Priority of interrupt 20 /
Sergunb	0:f1834a63f7c1	3118	#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /!< Priority of interrupt 21 /
Sergunb	0:f1834a63f7c1	3119	#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /!< Priority of interrupt 22 /
Sergunb	0:f1834a63f7c1	3120	#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /!< Priority of interrupt 23 /
Sergunb	0:f1834a63f7c1	3121
Sergunb	0:f1834a63f7c1	3122	/**************** Bit definition for NVIC_PRI6 register *****************/
Sergunb	0:f1834a63f7c1	3123	#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /!< Priority of interrupt 24 /
Sergunb	0:f1834a63f7c1	3124	#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /!< Priority of interrupt 25 /
Sergunb	0:f1834a63f7c1	3125	#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /!< Priority of interrupt 26 /
Sergunb	0:f1834a63f7c1	3126	#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /!< Priority of interrupt 27 /
Sergunb	0:f1834a63f7c1	3127
Sergunb	0:f1834a63f7c1	3128	/**************** Bit definition for NVIC_PRI7 register *****************/
Sergunb	0:f1834a63f7c1	3129	#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /!< Priority of interrupt 28 /
Sergunb	0:f1834a63f7c1	3130	#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /!< Priority of interrupt 29 /
Sergunb	0:f1834a63f7c1	3131	#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /!< Priority of interrupt 30 /
Sergunb	0:f1834a63f7c1	3132	#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /!< Priority of interrupt 31 /
Sergunb	0:f1834a63f7c1	3133
Sergunb	0:f1834a63f7c1	3134	/**************** Bit definition for SCB_CPUID register *****************/
Sergunb	0:f1834a63f7c1	3135	#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /!< Implementation defined revision number /
Sergunb	0:f1834a63f7c1	3136	#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /!< Number of processor within family /
Sergunb	0:f1834a63f7c1	3137	#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /!< Reads as 0x0F /
Sergunb	0:f1834a63f7c1	3138	#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /!< Implementation defined variant number /
Sergunb	0:f1834a63f7c1	3139	#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /!< Implementer code. ARM is 0x41 /
Sergunb	0:f1834a63f7c1	3140
Sergunb	0:f1834a63f7c1	3141	/***************** Bit definition for SCB_ICSR register *****************/
Sergunb	0:f1834a63f7c1	3142	#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /!< Active ISR number field /
Sergunb	0:f1834a63f7c1	3143	#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /!< All active exceptions minus the IPSR_current_exception yields the empty set /
Sergunb	0:f1834a63f7c1	3144	#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /!< Pending ISR number field /
Sergunb	0:f1834a63f7c1	3145	#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /!< Interrupt pending flag /
Sergunb	0:f1834a63f7c1	3146	#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /!< It indicates that a pending interrupt becomes active in the next running cycle /
Sergunb	0:f1834a63f7c1	3147	#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /!< Clear pending SysTick bit /
Sergunb	0:f1834a63f7c1	3148	#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /!< Set pending SysTick bit /
Sergunb	0:f1834a63f7c1	3149	#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /!< Clear pending pendSV bit /
Sergunb	0:f1834a63f7c1	3150	#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /!< Set pending pendSV bit /
Sergunb	0:f1834a63f7c1	3151	#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /!< Set pending NMI bit /
Sergunb	0:f1834a63f7c1	3152
Sergunb	0:f1834a63f7c1	3153	/***************** Bit definition for SCB_VTOR register *****************/
Sergunb	0:f1834a63f7c1	3154	#define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /!< Vector table base offset field /
Sergunb	0:f1834a63f7c1	3155	#define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /!< Table base in code(0) or RAM(1) /
Sergunb	0:f1834a63f7c1	3156
Sergunb	0:f1834a63f7c1	3157	/!<************** Bit definition for SCB_AIRCR register *****************/
Sergunb	0:f1834a63f7c1	3158	#define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /!< System Reset bit /
Sergunb	0:f1834a63f7c1	3159	#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /!< Clear active vector bit /
Sergunb	0:f1834a63f7c1	3160	#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /!< Requests chip control logic to generate a reset /
Sergunb	0:f1834a63f7c1	3161
Sergunb	0:f1834a63f7c1	3162	#define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /!< PRIGROUP[2:0] bits (Priority group) /
Sergunb	0:f1834a63f7c1	3163	#define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3164	#define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3165	#define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3166
Sergunb	0:f1834a63f7c1	3167	/* prority group configuration */
Sergunb	0:f1834a63f7c1	3168	#define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) /
Sergunb	0:f1834a63f7c1	3169	#define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) /
Sergunb	0:f1834a63f7c1	3170	#define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) /
Sergunb	0:f1834a63f7c1	3171	#define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) /
Sergunb	0:f1834a63f7c1	3172	#define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) /
Sergunb	0:f1834a63f7c1	3173	#define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) /
Sergunb	0:f1834a63f7c1	3174	#define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) /
Sergunb	0:f1834a63f7c1	3175	#define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) /
Sergunb	0:f1834a63f7c1	3176
Sergunb	0:f1834a63f7c1	3177	#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /!< Data endianness bit /
Sergunb	0:f1834a63f7c1	3178	#define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) /
Sergunb	0:f1834a63f7c1	3179
Sergunb	0:f1834a63f7c1	3180	/***************** Bit definition for SCB_SCR register ******************/
Sergunb	0:f1834a63f7c1	3181	#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /!< Sleep on exit bit /
Sergunb	0:f1834a63f7c1	3182	#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /!< Sleep deep bit /
Sergunb	0:f1834a63f7c1	3183	#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /!< Wake up from WFE /
Sergunb	0:f1834a63f7c1	3184
Sergunb	0:f1834a63f7c1	3185	/****************** Bit definition for SCB_CCR register *****************/
Sergunb	0:f1834a63f7c1	3186	#define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /!< Thread mode can be entered from any level in Handler mode by controlled return value /
Sergunb	0:f1834a63f7c1	3187	#define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception /
Sergunb	0:f1834a63f7c1	3188	#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /!< Trap for unaligned access /
Sergunb	0:f1834a63f7c1	3189	#define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /!< Trap on Divide by 0 /
Sergunb	0:f1834a63f7c1	3190	#define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /!< Handlers running at priority -1 and -2 /
Sergunb	0:f1834a63f7c1	3191	#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned /
Sergunb	0:f1834a63f7c1	3192
Sergunb	0:f1834a63f7c1	3193	/***************** Bit definition for SCB_SHPR register ******************/
Sergunb	0:f1834a63f7c1	3194	#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor /
Sergunb	0:f1834a63f7c1	3195	#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved /
Sergunb	0:f1834a63f7c1	3196	#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV /
Sergunb	0:f1834a63f7c1	3197	#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick /
Sergunb	0:f1834a63f7c1	3198
Sergunb	0:f1834a63f7c1	3199	/**************** Bit definition for SCB_SHCSR register *****************/
Sergunb	0:f1834a63f7c1	3200	#define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /!< MemManage is active /
Sergunb	0:f1834a63f7c1	3201	#define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /!< BusFault is active /
Sergunb	0:f1834a63f7c1	3202	#define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /!< UsageFault is active /
Sergunb	0:f1834a63f7c1	3203	#define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /!< SVCall is active /
Sergunb	0:f1834a63f7c1	3204	#define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /!< Monitor is active /
Sergunb	0:f1834a63f7c1	3205	#define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /!< PendSV is active /
Sergunb	0:f1834a63f7c1	3206	#define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /!< SysTick is active /
Sergunb	0:f1834a63f7c1	3207	#define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /!< Usage Fault is pended /
Sergunb	0:f1834a63f7c1	3208	#define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /!< MemManage is pended /
Sergunb	0:f1834a63f7c1	3209	#define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /!< Bus Fault is pended /
Sergunb	0:f1834a63f7c1	3210	#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /!< SVCall is pended /
Sergunb	0:f1834a63f7c1	3211	#define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /!< MemManage enable /
Sergunb	0:f1834a63f7c1	3212	#define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /!< Bus Fault enable /
Sergunb	0:f1834a63f7c1	3213	#define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /!< UsageFault enable /
Sergunb	0:f1834a63f7c1	3214
Sergunb	0:f1834a63f7c1	3215	/***************** Bit definition for SCB_CFSR register *****************/
Sergunb	0:f1834a63f7c1	3216	/!< MFSR /
Sergunb	0:f1834a63f7c1	3217	#define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /!< Instruction access violation /
Sergunb	0:f1834a63f7c1	3218	#define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /!< Data access violation /
Sergunb	0:f1834a63f7c1	3219	#define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /!< Unstacking error /
Sergunb	0:f1834a63f7c1	3220	#define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /!< Stacking error /
Sergunb	0:f1834a63f7c1	3221	#define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /!< Memory Manage Address Register address valid flag /
Sergunb	0:f1834a63f7c1	3222	/!< BFSR /
Sergunb	0:f1834a63f7c1	3223	#define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /!< Instruction bus error flag /
Sergunb	0:f1834a63f7c1	3224	#define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /!< Precise data bus error /
Sergunb	0:f1834a63f7c1	3225	#define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /!< Imprecise data bus error /
Sergunb	0:f1834a63f7c1	3226	#define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /!< Unstacking error /
Sergunb	0:f1834a63f7c1	3227	#define SCB_CFSR_STKERR ((uint32_t)0x00001000) /!< Stacking error /
Sergunb	0:f1834a63f7c1	3228	#define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /!< Bus Fault Address Register address valid flag /
Sergunb	0:f1834a63f7c1	3229	/!< UFSR /
Sergunb	0:f1834a63f7c1	3230	#define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /!< The processor attempt to execute an undefined instruction /
Sergunb	0:f1834a63f7c1	3231	#define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /!< Invalid combination of EPSR and instruction /
Sergunb	0:f1834a63f7c1	3232	#define SCB_CFSR_INVPC ((uint32_t)0x00040000) /!< Attempt to load EXC_RETURN into pc illegally /
Sergunb	0:f1834a63f7c1	3233	#define SCB_CFSR_NOCP ((uint32_t)0x00080000) /!< Attempt to use a coprocessor instruction /
Sergunb	0:f1834a63f7c1	3234	#define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /!< Fault occurs when there is an attempt to make an unaligned memory access /
Sergunb	0:f1834a63f7c1	3235	#define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 /
Sergunb	0:f1834a63f7c1	3236
Sergunb	0:f1834a63f7c1	3237	/***************** Bit definition for SCB_HFSR register *****************/
Sergunb	0:f1834a63f7c1	3238	#define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /!< Fault occurs because of vector table read on exception processing /
Sergunb	0:f1834a63f7c1	3239	#define SCB_HFSR_FORCED ((uint32_t)0x40000000) /!< Hard Fault activated when a configurable Fault was received and cannot activate /
Sergunb	0:f1834a63f7c1	3240	#define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /!< Fault related to debug /
Sergunb	0:f1834a63f7c1	3241
Sergunb	0:f1834a63f7c1	3242	/***************** Bit definition for SCB_DFSR register *****************/
Sergunb	0:f1834a63f7c1	3243	#define SCB_DFSR_HALTED ((uint8_t)0x01) /!< Halt request flag /
Sergunb	0:f1834a63f7c1	3244	#define SCB_DFSR_BKPT ((uint8_t)0x02) /!< BKPT flag /
Sergunb	0:f1834a63f7c1	3245	#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /!< Data Watchpoint and Trace (DWT) flag /
Sergunb	0:f1834a63f7c1	3246	#define SCB_DFSR_VCATCH ((uint8_t)0x08) /!< Vector catch flag /
Sergunb	0:f1834a63f7c1	3247	#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /!< External debug request flag /
Sergunb	0:f1834a63f7c1	3248
Sergunb	0:f1834a63f7c1	3249	/***************** Bit definition for SCB_MMFAR register ****************/
Sergunb	0:f1834a63f7c1	3250	#define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Mem Manage fault address field /
Sergunb	0:f1834a63f7c1	3251
Sergunb	0:f1834a63f7c1	3252	/***************** Bit definition for SCB_BFAR register *****************/
Sergunb	0:f1834a63f7c1	3253	#define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /!< Bus fault address field /
Sergunb	0:f1834a63f7c1	3254
Sergunb	0:f1834a63f7c1	3255	/***************** Bit definition for SCB_afsr register *****************/
Sergunb	0:f1834a63f7c1	3256	#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /!< Implementation defined /
Sergunb	0:f1834a63f7c1	3257
Sergunb	0:f1834a63f7c1	3258	/******************************************************************************/
Sergunb	0:f1834a63f7c1	3259	/* */
Sergunb	0:f1834a63f7c1	3260	/* External Interrupt/Event Controller */
Sergunb	0:f1834a63f7c1	3261	/* */
Sergunb	0:f1834a63f7c1	3262	/******************************************************************************/
Sergunb	0:f1834a63f7c1	3263
Sergunb	0:f1834a63f7c1	3264	/***************** Bit definition for EXTI_IMR register *****************/
Sergunb	0:f1834a63f7c1	3265	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
Sergunb	0:f1834a63f7c1	3266	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
Sergunb	0:f1834a63f7c1	3267	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
Sergunb	0:f1834a63f7c1	3268	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
Sergunb	0:f1834a63f7c1	3269	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
Sergunb	0:f1834a63f7c1	3270	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
Sergunb	0:f1834a63f7c1	3271	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
Sergunb	0:f1834a63f7c1	3272	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
Sergunb	0:f1834a63f7c1	3273	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
Sergunb	0:f1834a63f7c1	3274	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
Sergunb	0:f1834a63f7c1	3275	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
Sergunb	0:f1834a63f7c1	3276	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
Sergunb	0:f1834a63f7c1	3277	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
Sergunb	0:f1834a63f7c1	3278	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
Sergunb	0:f1834a63f7c1	3279	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
Sergunb	0:f1834a63f7c1	3280	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
Sergunb	0:f1834a63f7c1	3281	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
Sergunb	0:f1834a63f7c1	3282	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
Sergunb	0:f1834a63f7c1	3283	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
Sergunb	0:f1834a63f7c1	3284	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
Sergunb	0:f1834a63f7c1	3285
Sergunb	0:f1834a63f7c1	3286	/***************** Bit definition for EXTI_EMR register *****************/
Sergunb	0:f1834a63f7c1	3287	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
Sergunb	0:f1834a63f7c1	3288	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
Sergunb	0:f1834a63f7c1	3289	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
Sergunb	0:f1834a63f7c1	3290	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
Sergunb	0:f1834a63f7c1	3291	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
Sergunb	0:f1834a63f7c1	3292	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
Sergunb	0:f1834a63f7c1	3293	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
Sergunb	0:f1834a63f7c1	3294	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
Sergunb	0:f1834a63f7c1	3295	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
Sergunb	0:f1834a63f7c1	3296	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
Sergunb	0:f1834a63f7c1	3297	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
Sergunb	0:f1834a63f7c1	3298	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
Sergunb	0:f1834a63f7c1	3299	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
Sergunb	0:f1834a63f7c1	3300	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
Sergunb	0:f1834a63f7c1	3301	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
Sergunb	0:f1834a63f7c1	3302	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
Sergunb	0:f1834a63f7c1	3303	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
Sergunb	0:f1834a63f7c1	3304	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
Sergunb	0:f1834a63f7c1	3305	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
Sergunb	0:f1834a63f7c1	3306	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
Sergunb	0:f1834a63f7c1	3307
Sergunb	0:f1834a63f7c1	3308	/**************** Bit definition for EXTI_RTSR register *****************/
Sergunb	0:f1834a63f7c1	3309	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
Sergunb	0:f1834a63f7c1	3310	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
Sergunb	0:f1834a63f7c1	3311	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
Sergunb	0:f1834a63f7c1	3312	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
Sergunb	0:f1834a63f7c1	3313	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
Sergunb	0:f1834a63f7c1	3314	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
Sergunb	0:f1834a63f7c1	3315	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
Sergunb	0:f1834a63f7c1	3316	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
Sergunb	0:f1834a63f7c1	3317	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
Sergunb	0:f1834a63f7c1	3318	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
Sergunb	0:f1834a63f7c1	3319	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
Sergunb	0:f1834a63f7c1	3320	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
Sergunb	0:f1834a63f7c1	3321	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
Sergunb	0:f1834a63f7c1	3322	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
Sergunb	0:f1834a63f7c1	3323	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
Sergunb	0:f1834a63f7c1	3324	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
Sergunb	0:f1834a63f7c1	3325	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
Sergunb	0:f1834a63f7c1	3326	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
Sergunb	0:f1834a63f7c1	3327	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
Sergunb	0:f1834a63f7c1	3328	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
Sergunb	0:f1834a63f7c1	3329
Sergunb	0:f1834a63f7c1	3330	/**************** Bit definition for EXTI_FTSR register *****************/
Sergunb	0:f1834a63f7c1	3331	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
Sergunb	0:f1834a63f7c1	3332	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
Sergunb	0:f1834a63f7c1	3333	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
Sergunb	0:f1834a63f7c1	3334	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
Sergunb	0:f1834a63f7c1	3335	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
Sergunb	0:f1834a63f7c1	3336	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
Sergunb	0:f1834a63f7c1	3337	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
Sergunb	0:f1834a63f7c1	3338	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
Sergunb	0:f1834a63f7c1	3339	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
Sergunb	0:f1834a63f7c1	3340	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
Sergunb	0:f1834a63f7c1	3341	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
Sergunb	0:f1834a63f7c1	3342	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
Sergunb	0:f1834a63f7c1	3343	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
Sergunb	0:f1834a63f7c1	3344	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
Sergunb	0:f1834a63f7c1	3345	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
Sergunb	0:f1834a63f7c1	3346	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
Sergunb	0:f1834a63f7c1	3347	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
Sergunb	0:f1834a63f7c1	3348	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
Sergunb	0:f1834a63f7c1	3349	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
Sergunb	0:f1834a63f7c1	3350	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
Sergunb	0:f1834a63f7c1	3351
Sergunb	0:f1834a63f7c1	3352	/**************** Bit definition for EXTI_SWIER register ****************/
Sergunb	0:f1834a63f7c1	3353	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
Sergunb	0:f1834a63f7c1	3354	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
Sergunb	0:f1834a63f7c1	3355	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
Sergunb	0:f1834a63f7c1	3356	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
Sergunb	0:f1834a63f7c1	3357	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
Sergunb	0:f1834a63f7c1	3358	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
Sergunb	0:f1834a63f7c1	3359	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
Sergunb	0:f1834a63f7c1	3360	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
Sergunb	0:f1834a63f7c1	3361	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
Sergunb	0:f1834a63f7c1	3362	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
Sergunb	0:f1834a63f7c1	3363	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
Sergunb	0:f1834a63f7c1	3364	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
Sergunb	0:f1834a63f7c1	3365	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
Sergunb	0:f1834a63f7c1	3366	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
Sergunb	0:f1834a63f7c1	3367	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
Sergunb	0:f1834a63f7c1	3368	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
Sergunb	0:f1834a63f7c1	3369	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
Sergunb	0:f1834a63f7c1	3370	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
Sergunb	0:f1834a63f7c1	3371	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
Sergunb	0:f1834a63f7c1	3372	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
Sergunb	0:f1834a63f7c1	3373
Sergunb	0:f1834a63f7c1	3374	/***************** Bit definition for EXTI_PR register ******************/
Sergunb	0:f1834a63f7c1	3375	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
Sergunb	0:f1834a63f7c1	3376	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
Sergunb	0:f1834a63f7c1	3377	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
Sergunb	0:f1834a63f7c1	3378	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
Sergunb	0:f1834a63f7c1	3379	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
Sergunb	0:f1834a63f7c1	3380	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
Sergunb	0:f1834a63f7c1	3381	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
Sergunb	0:f1834a63f7c1	3382	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
Sergunb	0:f1834a63f7c1	3383	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
Sergunb	0:f1834a63f7c1	3384	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
Sergunb	0:f1834a63f7c1	3385	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
Sergunb	0:f1834a63f7c1	3386	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
Sergunb	0:f1834a63f7c1	3387	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
Sergunb	0:f1834a63f7c1	3388	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
Sergunb	0:f1834a63f7c1	3389	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
Sergunb	0:f1834a63f7c1	3390	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
Sergunb	0:f1834a63f7c1	3391	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
Sergunb	0:f1834a63f7c1	3392	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
Sergunb	0:f1834a63f7c1	3393	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
Sergunb	0:f1834a63f7c1	3394	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
Sergunb	0:f1834a63f7c1	3395
Sergunb	0:f1834a63f7c1	3396	/******************************************************************************/
Sergunb	0:f1834a63f7c1	3397	/* */
Sergunb	0:f1834a63f7c1	3398	/* DMA Controller */
Sergunb	0:f1834a63f7c1	3399	/* */
Sergunb	0:f1834a63f7c1	3400	/******************************************************************************/
Sergunb	0:f1834a63f7c1	3401
Sergunb	0:f1834a63f7c1	3402	/***************** Bit definition for DMA_ISR register ******************/
Sergunb	0:f1834a63f7c1	3403	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
Sergunb	0:f1834a63f7c1	3404	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
Sergunb	0:f1834a63f7c1	3405	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
Sergunb	0:f1834a63f7c1	3406	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
Sergunb	0:f1834a63f7c1	3407	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
Sergunb	0:f1834a63f7c1	3408	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
Sergunb	0:f1834a63f7c1	3409	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
Sergunb	0:f1834a63f7c1	3410	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
Sergunb	0:f1834a63f7c1	3411	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
Sergunb	0:f1834a63f7c1	3412	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
Sergunb	0:f1834a63f7c1	3413	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
Sergunb	0:f1834a63f7c1	3414	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
Sergunb	0:f1834a63f7c1	3415	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
Sergunb	0:f1834a63f7c1	3416	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
Sergunb	0:f1834a63f7c1	3417	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
Sergunb	0:f1834a63f7c1	3418	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
Sergunb	0:f1834a63f7c1	3419	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
Sergunb	0:f1834a63f7c1	3420	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
Sergunb	0:f1834a63f7c1	3421	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
Sergunb	0:f1834a63f7c1	3422	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
Sergunb	0:f1834a63f7c1	3423	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
Sergunb	0:f1834a63f7c1	3424	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
Sergunb	0:f1834a63f7c1	3425	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
Sergunb	0:f1834a63f7c1	3426	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
Sergunb	0:f1834a63f7c1	3427	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
Sergunb	0:f1834a63f7c1	3428	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
Sergunb	0:f1834a63f7c1	3429	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
Sergunb	0:f1834a63f7c1	3430	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
Sergunb	0:f1834a63f7c1	3431
Sergunb	0:f1834a63f7c1	3432	/***************** Bit definition for DMA_IFCR register *****************/
Sergunb	0:f1834a63f7c1	3433	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
Sergunb	0:f1834a63f7c1	3434	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
Sergunb	0:f1834a63f7c1	3435	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
Sergunb	0:f1834a63f7c1	3436	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
Sergunb	0:f1834a63f7c1	3437	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
Sergunb	0:f1834a63f7c1	3438	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
Sergunb	0:f1834a63f7c1	3439	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
Sergunb	0:f1834a63f7c1	3440	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
Sergunb	0:f1834a63f7c1	3441	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
Sergunb	0:f1834a63f7c1	3442	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
Sergunb	0:f1834a63f7c1	3443	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
Sergunb	0:f1834a63f7c1	3444	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
Sergunb	0:f1834a63f7c1	3445	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
Sergunb	0:f1834a63f7c1	3446	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
Sergunb	0:f1834a63f7c1	3447	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
Sergunb	0:f1834a63f7c1	3448	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
Sergunb	0:f1834a63f7c1	3449	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
Sergunb	0:f1834a63f7c1	3450	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
Sergunb	0:f1834a63f7c1	3451	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
Sergunb	0:f1834a63f7c1	3452	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
Sergunb	0:f1834a63f7c1	3453	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
Sergunb	0:f1834a63f7c1	3454	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
Sergunb	0:f1834a63f7c1	3455	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
Sergunb	0:f1834a63f7c1	3456	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
Sergunb	0:f1834a63f7c1	3457	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
Sergunb	0:f1834a63f7c1	3458	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
Sergunb	0:f1834a63f7c1	3459	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
Sergunb	0:f1834a63f7c1	3460	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
Sergunb	0:f1834a63f7c1	3461
Sergunb	0:f1834a63f7c1	3462	/***************** Bit definition for DMA_CCR1 register *****************/
Sergunb	0:f1834a63f7c1	3463	#define DMA_CCR1_EN ((uint16_t)0x0001) /!< Channel enable/
Sergunb	0:f1834a63f7c1	3464	#define DMA_CCR1_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
Sergunb	0:f1834a63f7c1	3465	#define DMA_CCR1_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
Sergunb	0:f1834a63f7c1	3466	#define DMA_CCR1_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
Sergunb	0:f1834a63f7c1	3467	#define DMA_CCR1_DIR ((uint16_t)0x0010) /!< Data transfer direction /
Sergunb	0:f1834a63f7c1	3468	#define DMA_CCR1_CIRC ((uint16_t)0x0020) /!< Circular mode /
Sergunb	0:f1834a63f7c1	3469	#define DMA_CCR1_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
Sergunb	0:f1834a63f7c1	3470	#define DMA_CCR1_MINC ((uint16_t)0x0080) /!< Memory increment mode /
Sergunb	0:f1834a63f7c1	3471
Sergunb	0:f1834a63f7c1	3472	#define DMA_CCR1_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
Sergunb	0:f1834a63f7c1	3473	#define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3474	#define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3475
Sergunb	0:f1834a63f7c1	3476	#define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
Sergunb	0:f1834a63f7c1	3477	#define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3478	#define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3479
Sergunb	0:f1834a63f7c1	3480	#define DMA_CCR1_PL ((uint16_t)0x3000) /!< PL[1:0] bits(Channel Priority level) /
Sergunb	0:f1834a63f7c1	3481	#define DMA_CCR1_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3482	#define DMA_CCR1_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3483
Sergunb	0:f1834a63f7c1	3484	#define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
Sergunb	0:f1834a63f7c1	3485
Sergunb	0:f1834a63f7c1	3486	/***************** Bit definition for DMA_CCR2 register *****************/
Sergunb	0:f1834a63f7c1	3487	#define DMA_CCR2_EN ((uint16_t)0x0001) /!< Channel enable /
Sergunb	0:f1834a63f7c1	3488	#define DMA_CCR2_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
Sergunb	0:f1834a63f7c1	3489	#define DMA_CCR2_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
Sergunb	0:f1834a63f7c1	3490	#define DMA_CCR2_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
Sergunb	0:f1834a63f7c1	3491	#define DMA_CCR2_DIR ((uint16_t)0x0010) /!< Data transfer direction /
Sergunb	0:f1834a63f7c1	3492	#define DMA_CCR2_CIRC ((uint16_t)0x0020) /!< Circular mode /
Sergunb	0:f1834a63f7c1	3493	#define DMA_CCR2_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
Sergunb	0:f1834a63f7c1	3494	#define DMA_CCR2_MINC ((uint16_t)0x0080) /!< Memory increment mode /
Sergunb	0:f1834a63f7c1	3495
Sergunb	0:f1834a63f7c1	3496	#define DMA_CCR2_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
Sergunb	0:f1834a63f7c1	3497	#define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3498	#define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3499
Sergunb	0:f1834a63f7c1	3500	#define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
Sergunb	0:f1834a63f7c1	3501	#define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3502	#define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3503
Sergunb	0:f1834a63f7c1	3504	#define DMA_CCR2_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
Sergunb	0:f1834a63f7c1	3505	#define DMA_CCR2_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3506	#define DMA_CCR2_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3507
Sergunb	0:f1834a63f7c1	3508	#define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
Sergunb	0:f1834a63f7c1	3509
Sergunb	0:f1834a63f7c1	3510	/***************** Bit definition for DMA_CCR3 register *****************/
Sergunb	0:f1834a63f7c1	3511	#define DMA_CCR3_EN ((uint16_t)0x0001) /!< Channel enable /
Sergunb	0:f1834a63f7c1	3512	#define DMA_CCR3_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
Sergunb	0:f1834a63f7c1	3513	#define DMA_CCR3_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
Sergunb	0:f1834a63f7c1	3514	#define DMA_CCR3_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
Sergunb	0:f1834a63f7c1	3515	#define DMA_CCR3_DIR ((uint16_t)0x0010) /!< Data transfer direction /
Sergunb	0:f1834a63f7c1	3516	#define DMA_CCR3_CIRC ((uint16_t)0x0020) /!< Circular mode /
Sergunb	0:f1834a63f7c1	3517	#define DMA_CCR3_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
Sergunb	0:f1834a63f7c1	3518	#define DMA_CCR3_MINC ((uint16_t)0x0080) /!< Memory increment mode /
Sergunb	0:f1834a63f7c1	3519
Sergunb	0:f1834a63f7c1	3520	#define DMA_CCR3_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
Sergunb	0:f1834a63f7c1	3521	#define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3522	#define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3523
Sergunb	0:f1834a63f7c1	3524	#define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
Sergunb	0:f1834a63f7c1	3525	#define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3526	#define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3527
Sergunb	0:f1834a63f7c1	3528	#define DMA_CCR3_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
Sergunb	0:f1834a63f7c1	3529	#define DMA_CCR3_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3530	#define DMA_CCR3_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3531
Sergunb	0:f1834a63f7c1	3532	#define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
Sergunb	0:f1834a63f7c1	3533
Sergunb	0:f1834a63f7c1	3534	/!<*************** Bit definition for DMA_CCR4 register *****************/
Sergunb	0:f1834a63f7c1	3535	#define DMA_CCR4_EN ((uint16_t)0x0001) /!< Channel enable /
Sergunb	0:f1834a63f7c1	3536	#define DMA_CCR4_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
Sergunb	0:f1834a63f7c1	3537	#define DMA_CCR4_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
Sergunb	0:f1834a63f7c1	3538	#define DMA_CCR4_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
Sergunb	0:f1834a63f7c1	3539	#define DMA_CCR4_DIR ((uint16_t)0x0010) /!< Data transfer direction /
Sergunb	0:f1834a63f7c1	3540	#define DMA_CCR4_CIRC ((uint16_t)0x0020) /!< Circular mode /
Sergunb	0:f1834a63f7c1	3541	#define DMA_CCR4_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
Sergunb	0:f1834a63f7c1	3542	#define DMA_CCR4_MINC ((uint16_t)0x0080) /!< Memory increment mode /
Sergunb	0:f1834a63f7c1	3543
Sergunb	0:f1834a63f7c1	3544	#define DMA_CCR4_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
Sergunb	0:f1834a63f7c1	3545	#define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3546	#define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3547
Sergunb	0:f1834a63f7c1	3548	#define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
Sergunb	0:f1834a63f7c1	3549	#define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3550	#define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3551
Sergunb	0:f1834a63f7c1	3552	#define DMA_CCR4_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
Sergunb	0:f1834a63f7c1	3553	#define DMA_CCR4_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3554	#define DMA_CCR4_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3555
Sergunb	0:f1834a63f7c1	3556	#define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
Sergunb	0:f1834a63f7c1	3557
Sergunb	0:f1834a63f7c1	3558	/**************** Bit definition for DMA_CCR5 register *****************/
Sergunb	0:f1834a63f7c1	3559	#define DMA_CCR5_EN ((uint16_t)0x0001) /!< Channel enable /
Sergunb	0:f1834a63f7c1	3560	#define DMA_CCR5_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
Sergunb	0:f1834a63f7c1	3561	#define DMA_CCR5_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
Sergunb	0:f1834a63f7c1	3562	#define DMA_CCR5_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
Sergunb	0:f1834a63f7c1	3563	#define DMA_CCR5_DIR ((uint16_t)0x0010) /!< Data transfer direction /
Sergunb	0:f1834a63f7c1	3564	#define DMA_CCR5_CIRC ((uint16_t)0x0020) /!< Circular mode /
Sergunb	0:f1834a63f7c1	3565	#define DMA_CCR5_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
Sergunb	0:f1834a63f7c1	3566	#define DMA_CCR5_MINC ((uint16_t)0x0080) /!< Memory increment mode /
Sergunb	0:f1834a63f7c1	3567
Sergunb	0:f1834a63f7c1	3568	#define DMA_CCR5_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
Sergunb	0:f1834a63f7c1	3569	#define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3570	#define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3571
Sergunb	0:f1834a63f7c1	3572	#define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
Sergunb	0:f1834a63f7c1	3573	#define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3574	#define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3575
Sergunb	0:f1834a63f7c1	3576	#define DMA_CCR5_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
Sergunb	0:f1834a63f7c1	3577	#define DMA_CCR5_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3578	#define DMA_CCR5_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3579
Sergunb	0:f1834a63f7c1	3580	#define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode enable /
Sergunb	0:f1834a63f7c1	3581
Sergunb	0:f1834a63f7c1	3582	/***************** Bit definition for DMA_CCR6 register *****************/
Sergunb	0:f1834a63f7c1	3583	#define DMA_CCR6_EN ((uint16_t)0x0001) /!< Channel enable /
Sergunb	0:f1834a63f7c1	3584	#define DMA_CCR6_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
Sergunb	0:f1834a63f7c1	3585	#define DMA_CCR6_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
Sergunb	0:f1834a63f7c1	3586	#define DMA_CCR6_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
Sergunb	0:f1834a63f7c1	3587	#define DMA_CCR6_DIR ((uint16_t)0x0010) /!< Data transfer direction /
Sergunb	0:f1834a63f7c1	3588	#define DMA_CCR6_CIRC ((uint16_t)0x0020) /!< Circular mode /
Sergunb	0:f1834a63f7c1	3589	#define DMA_CCR6_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
Sergunb	0:f1834a63f7c1	3590	#define DMA_CCR6_MINC ((uint16_t)0x0080) /!< Memory increment mode /
Sergunb	0:f1834a63f7c1	3591
Sergunb	0:f1834a63f7c1	3592	#define DMA_CCR6_PSIZE ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
Sergunb	0:f1834a63f7c1	3593	#define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3594	#define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3595
Sergunb	0:f1834a63f7c1	3596	#define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
Sergunb	0:f1834a63f7c1	3597	#define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3598	#define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3599
Sergunb	0:f1834a63f7c1	3600	#define DMA_CCR6_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
Sergunb	0:f1834a63f7c1	3601	#define DMA_CCR6_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3602	#define DMA_CCR6_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3603
Sergunb	0:f1834a63f7c1	3604	#define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode /
Sergunb	0:f1834a63f7c1	3605
Sergunb	0:f1834a63f7c1	3606	/***************** Bit definition for DMA_CCR7 register *****************/
Sergunb	0:f1834a63f7c1	3607	#define DMA_CCR7_EN ((uint16_t)0x0001) /!< Channel enable /
Sergunb	0:f1834a63f7c1	3608	#define DMA_CCR7_TCIE ((uint16_t)0x0002) /!< Transfer complete interrupt enable /
Sergunb	0:f1834a63f7c1	3609	#define DMA_CCR7_HTIE ((uint16_t)0x0004) /!< Half Transfer interrupt enable /
Sergunb	0:f1834a63f7c1	3610	#define DMA_CCR7_TEIE ((uint16_t)0x0008) /!< Transfer error interrupt enable /
Sergunb	0:f1834a63f7c1	3611	#define DMA_CCR7_DIR ((uint16_t)0x0010) /!< Data transfer direction /
Sergunb	0:f1834a63f7c1	3612	#define DMA_CCR7_CIRC ((uint16_t)0x0020) /!< Circular mode /
Sergunb	0:f1834a63f7c1	3613	#define DMA_CCR7_PINC ((uint16_t)0x0040) /!< Peripheral increment mode /
Sergunb	0:f1834a63f7c1	3614	#define DMA_CCR7_MINC ((uint16_t)0x0080) /!< Memory increment mode /
Sergunb	0:f1834a63f7c1	3615
Sergunb	0:f1834a63f7c1	3616	#define DMA_CCR7_PSIZE , ((uint16_t)0x0300) /!< PSIZE[1:0] bits (Peripheral size) /
Sergunb	0:f1834a63f7c1	3617	#define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3618	#define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3619
Sergunb	0:f1834a63f7c1	3620	#define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /!< MSIZE[1:0] bits (Memory size) /
Sergunb	0:f1834a63f7c1	3621	#define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3622	#define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3623
Sergunb	0:f1834a63f7c1	3624	#define DMA_CCR7_PL ((uint16_t)0x3000) /!< PL[1:0] bits (Channel Priority level) /
Sergunb	0:f1834a63f7c1	3625	#define DMA_CCR7_PL_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3626	#define DMA_CCR7_PL_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3627
Sergunb	0:f1834a63f7c1	3628	#define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /!< Memory to memory mode enable /
Sergunb	0:f1834a63f7c1	3629
Sergunb	0:f1834a63f7c1	3630	/**************** Bit definition for DMA_CNDTR1 register ****************/
Sergunb	0:f1834a63f7c1	3631	#define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
Sergunb	0:f1834a63f7c1	3632
Sergunb	0:f1834a63f7c1	3633	/**************** Bit definition for DMA_CNDTR2 register ****************/
Sergunb	0:f1834a63f7c1	3634	#define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
Sergunb	0:f1834a63f7c1	3635
Sergunb	0:f1834a63f7c1	3636	/**************** Bit definition for DMA_CNDTR3 register ****************/
Sergunb	0:f1834a63f7c1	3637	#define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
Sergunb	0:f1834a63f7c1	3638
Sergunb	0:f1834a63f7c1	3639	/**************** Bit definition for DMA_CNDTR4 register ****************/
Sergunb	0:f1834a63f7c1	3640	#define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
Sergunb	0:f1834a63f7c1	3641
Sergunb	0:f1834a63f7c1	3642	/**************** Bit definition for DMA_CNDTR5 register ****************/
Sergunb	0:f1834a63f7c1	3643	#define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
Sergunb	0:f1834a63f7c1	3644
Sergunb	0:f1834a63f7c1	3645	/**************** Bit definition for DMA_CNDTR6 register ****************/
Sergunb	0:f1834a63f7c1	3646	#define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
Sergunb	0:f1834a63f7c1	3647
Sergunb	0:f1834a63f7c1	3648	/**************** Bit definition for DMA_CNDTR7 register ****************/
Sergunb	0:f1834a63f7c1	3649	#define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /!< Number of data to Transfer /
Sergunb	0:f1834a63f7c1	3650
Sergunb	0:f1834a63f7c1	3651	/**************** Bit definition for DMA_CPAR1 register *****************/
Sergunb	0:f1834a63f7c1	3652	#define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Sergunb	0:f1834a63f7c1	3653
Sergunb	0:f1834a63f7c1	3654	/**************** Bit definition for DMA_CPAR2 register *****************/
Sergunb	0:f1834a63f7c1	3655	#define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Sergunb	0:f1834a63f7c1	3656
Sergunb	0:f1834a63f7c1	3657	/**************** Bit definition for DMA_CPAR3 register *****************/
Sergunb	0:f1834a63f7c1	3658	#define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Sergunb	0:f1834a63f7c1	3659
Sergunb	0:f1834a63f7c1	3660
Sergunb	0:f1834a63f7c1	3661	/**************** Bit definition for DMA_CPAR4 register *****************/
Sergunb	0:f1834a63f7c1	3662	#define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Sergunb	0:f1834a63f7c1	3663
Sergunb	0:f1834a63f7c1	3664	/**************** Bit definition for DMA_CPAR5 register *****************/
Sergunb	0:f1834a63f7c1	3665	#define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Sergunb	0:f1834a63f7c1	3666
Sergunb	0:f1834a63f7c1	3667	/**************** Bit definition for DMA_CPAR6 register *****************/
Sergunb	0:f1834a63f7c1	3668	#define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Sergunb	0:f1834a63f7c1	3669
Sergunb	0:f1834a63f7c1	3670
Sergunb	0:f1834a63f7c1	3671	/**************** Bit definition for DMA_CPAR7 register *****************/
Sergunb	0:f1834a63f7c1	3672	#define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
Sergunb	0:f1834a63f7c1	3673
Sergunb	0:f1834a63f7c1	3674	/**************** Bit definition for DMA_CMAR1 register *****************/
Sergunb	0:f1834a63f7c1	3675	#define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Sergunb	0:f1834a63f7c1	3676
Sergunb	0:f1834a63f7c1	3677	/**************** Bit definition for DMA_CMAR2 register *****************/
Sergunb	0:f1834a63f7c1	3678	#define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Sergunb	0:f1834a63f7c1	3679
Sergunb	0:f1834a63f7c1	3680	/**************** Bit definition for DMA_CMAR3 register *****************/
Sergunb	0:f1834a63f7c1	3681	#define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Sergunb	0:f1834a63f7c1	3682
Sergunb	0:f1834a63f7c1	3683
Sergunb	0:f1834a63f7c1	3684	/**************** Bit definition for DMA_CMAR4 register *****************/
Sergunb	0:f1834a63f7c1	3685	#define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Sergunb	0:f1834a63f7c1	3686
Sergunb	0:f1834a63f7c1	3687	/**************** Bit definition for DMA_CMAR5 register *****************/
Sergunb	0:f1834a63f7c1	3688	#define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Sergunb	0:f1834a63f7c1	3689
Sergunb	0:f1834a63f7c1	3690	/**************** Bit definition for DMA_CMAR6 register *****************/
Sergunb	0:f1834a63f7c1	3691	#define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Sergunb	0:f1834a63f7c1	3692
Sergunb	0:f1834a63f7c1	3693	/**************** Bit definition for DMA_CMAR7 register *****************/
Sergunb	0:f1834a63f7c1	3694	#define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
Sergunb	0:f1834a63f7c1	3695
Sergunb	0:f1834a63f7c1	3696	/******************************************************************************/
Sergunb	0:f1834a63f7c1	3697	/* */
Sergunb	0:f1834a63f7c1	3698	/* Analog to Digital Converter */
Sergunb	0:f1834a63f7c1	3699	/* */
Sergunb	0:f1834a63f7c1	3700	/******************************************************************************/
Sergunb	0:f1834a63f7c1	3701
Sergunb	0:f1834a63f7c1	3702	/****************** Bit definition for ADC_SR register ******************/
Sergunb	0:f1834a63f7c1	3703	#define ADC_SR_AWD ((uint8_t)0x01) /!< Analog watchdog flag /
Sergunb	0:f1834a63f7c1	3704	#define ADC_SR_EOC ((uint8_t)0x02) /!< End of conversion /
Sergunb	0:f1834a63f7c1	3705	#define ADC_SR_JEOC ((uint8_t)0x04) /!< Injected channel end of conversion /
Sergunb	0:f1834a63f7c1	3706	#define ADC_SR_JSTRT ((uint8_t)0x08) /!< Injected channel Start flag /
Sergunb	0:f1834a63f7c1	3707	#define ADC_SR_STRT ((uint8_t)0x10) /!< Regular channel Start flag /
Sergunb	0:f1834a63f7c1	3708
Sergunb	0:f1834a63f7c1	3709	/***************** Bit definition for ADC_CR1 register ******************/
Sergunb	0:f1834a63f7c1	3710	#define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
Sergunb	0:f1834a63f7c1	3711	#define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3712	#define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3713	#define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3714	#define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3715	#define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3716
Sergunb	0:f1834a63f7c1	3717	#define ADC_CR1_EOCIE ((uint32_t)0x00000020) /!< Interrupt enable for EOC /
Sergunb	0:f1834a63f7c1	3718	#define ADC_CR1_AWDIE ((uint32_t)0x00000040) /!< Analog Watchdog interrupt enable /
Sergunb	0:f1834a63f7c1	3719	#define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /!< Interrupt enable for injected channels /
Sergunb	0:f1834a63f7c1	3720	#define ADC_CR1_SCAN ((uint32_t)0x00000100) /!< Scan mode /
Sergunb	0:f1834a63f7c1	3721	#define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /!< Enable the watchdog on a single channel in scan mode /
Sergunb	0:f1834a63f7c1	3722	#define ADC_CR1_JAUTO ((uint32_t)0x00000400) /!< Automatic injected group conversion /
Sergunb	0:f1834a63f7c1	3723	#define ADC_CR1_DISCEN ((uint32_t)0x00000800) /!< Discontinuous mode on regular channels /
Sergunb	0:f1834a63f7c1	3724	#define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /!< Discontinuous mode on injected channels /
Sergunb	0:f1834a63f7c1	3725
Sergunb	0:f1834a63f7c1	3726	#define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /!< DISCNUM[2:0] bits (Discontinuous mode channel count) /
Sergunb	0:f1834a63f7c1	3727	#define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3728	#define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3729	#define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3730
Sergunb	0:f1834a63f7c1	3731	#define ADC_CR1_DUALMOD ((uint32_t)0x000F0000) /!< DUALMOD[3:0] bits (Dual mode selection) /
Sergunb	0:f1834a63f7c1	3732	#define ADC_CR1_DUALMOD_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3733	#define ADC_CR1_DUALMOD_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3734	#define ADC_CR1_DUALMOD_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3735	#define ADC_CR1_DUALMOD_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3736
Sergunb	0:f1834a63f7c1	3737	#define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /!< Analog watchdog enable on injected channels /
Sergunb	0:f1834a63f7c1	3738	#define ADC_CR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
Sergunb	0:f1834a63f7c1	3739
Sergunb	0:f1834a63f7c1	3740
Sergunb	0:f1834a63f7c1	3741	/***************** Bit definition for ADC_CR2 register ******************/
Sergunb	0:f1834a63f7c1	3742	#define ADC_CR2_ADON ((uint32_t)0x00000001) /!< A/D Converter ON / OFF /
Sergunb	0:f1834a63f7c1	3743	#define ADC_CR2_CONT ((uint32_t)0x00000002) /!< Continuous Conversion /
Sergunb	0:f1834a63f7c1	3744	#define ADC_CR2_CAL ((uint32_t)0x00000004) /!< A/D Calibration /
Sergunb	0:f1834a63f7c1	3745	#define ADC_CR2_RSTCAL ((uint32_t)0x00000008) /!< Reset Calibration /
Sergunb	0:f1834a63f7c1	3746	#define ADC_CR2_DMA ((uint32_t)0x00000100) /!< Direct Memory access mode /
Sergunb	0:f1834a63f7c1	3747	#define ADC_CR2_ALIGN ((uint32_t)0x00000800) /!< Data Alignment /
Sergunb	0:f1834a63f7c1	3748
Sergunb	0:f1834a63f7c1	3749	#define ADC_CR2_JEXTSEL ((uint32_t)0x00007000) /!< JEXTSEL[2:0] bits (External event select for injected group) /
Sergunb	0:f1834a63f7c1	3750	#define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3751	#define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3752	#define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00004000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3753
Sergunb	0:f1834a63f7c1	3754	#define ADC_CR2_JEXTTRIG ((uint32_t)0x00008000) /!< External Trigger Conversion mode for injected channels /
Sergunb	0:f1834a63f7c1	3755
Sergunb	0:f1834a63f7c1	3756	#define ADC_CR2_EXTSEL ((uint32_t)0x000E0000) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
Sergunb	0:f1834a63f7c1	3757	#define ADC_CR2_EXTSEL_0 ((uint32_t)0x00020000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3758	#define ADC_CR2_EXTSEL_1 ((uint32_t)0x00040000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3759	#define ADC_CR2_EXTSEL_2 ((uint32_t)0x00080000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3760
Sergunb	0:f1834a63f7c1	3761	#define ADC_CR2_EXTTRIG ((uint32_t)0x00100000) /!< External Trigger Conversion mode for regular channels /
Sergunb	0:f1834a63f7c1	3762	#define ADC_CR2_JSWSTART ((uint32_t)0x00200000) /!< Start Conversion of injected channels /
Sergunb	0:f1834a63f7c1	3763	#define ADC_CR2_SWSTART ((uint32_t)0x00400000) /!< Start Conversion of regular channels /
Sergunb	0:f1834a63f7c1	3764	#define ADC_CR2_TSVREFE ((uint32_t)0x00800000) /!< Temperature Sensor and VREFINT Enable /
Sergunb	0:f1834a63f7c1	3765
Sergunb	0:f1834a63f7c1	3766	/**************** Bit definition for ADC_SMPR1 register *****************/
Sergunb	0:f1834a63f7c1	3767	#define ADC_SMPR1_SMP10 ((uint32_t)0x00000007) /!< SMP10[2:0] bits (Channel 10 Sample time selection) /
Sergunb	0:f1834a63f7c1	3768	#define ADC_SMPR1_SMP10_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3769	#define ADC_SMPR1_SMP10_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3770	#define ADC_SMPR1_SMP10_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3771
Sergunb	0:f1834a63f7c1	3772	#define ADC_SMPR1_SMP11 ((uint32_t)0x00000038) /!< SMP11[2:0] bits (Channel 11 Sample time selection) /
Sergunb	0:f1834a63f7c1	3773	#define ADC_SMPR1_SMP11_0 ((uint32_t)0x00000008) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3774	#define ADC_SMPR1_SMP11_1 ((uint32_t)0x00000010) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3775	#define ADC_SMPR1_SMP11_2 ((uint32_t)0x00000020) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3776
Sergunb	0:f1834a63f7c1	3777	#define ADC_SMPR1_SMP12 ((uint32_t)0x000001C0) /!< SMP12[2:0] bits (Channel 12 Sample time selection) /
Sergunb	0:f1834a63f7c1	3778	#define ADC_SMPR1_SMP12_0 ((uint32_t)0x00000040) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3779	#define ADC_SMPR1_SMP12_1 ((uint32_t)0x00000080) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3780	#define ADC_SMPR1_SMP12_2 ((uint32_t)0x00000100) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3781
Sergunb	0:f1834a63f7c1	3782	#define ADC_SMPR1_SMP13 ((uint32_t)0x00000E00) /!< SMP13[2:0] bits (Channel 13 Sample time selection) /
Sergunb	0:f1834a63f7c1	3783	#define ADC_SMPR1_SMP13_0 ((uint32_t)0x00000200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3784	#define ADC_SMPR1_SMP13_1 ((uint32_t)0x00000400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3785	#define ADC_SMPR1_SMP13_2 ((uint32_t)0x00000800) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3786
Sergunb	0:f1834a63f7c1	3787	#define ADC_SMPR1_SMP14 ((uint32_t)0x00007000) /!< SMP14[2:0] bits (Channel 14 Sample time selection) /
Sergunb	0:f1834a63f7c1	3788	#define ADC_SMPR1_SMP14_0 ((uint32_t)0x00001000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3789	#define ADC_SMPR1_SMP14_1 ((uint32_t)0x00002000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3790	#define ADC_SMPR1_SMP14_2 ((uint32_t)0x00004000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3791
Sergunb	0:f1834a63f7c1	3792	#define ADC_SMPR1_SMP15 ((uint32_t)0x00038000) /!< SMP15[2:0] bits (Channel 15 Sample time selection) /
Sergunb	0:f1834a63f7c1	3793	#define ADC_SMPR1_SMP15_0 ((uint32_t)0x00008000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3794	#define ADC_SMPR1_SMP15_1 ((uint32_t)0x00010000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3795	#define ADC_SMPR1_SMP15_2 ((uint32_t)0x00020000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3796
Sergunb	0:f1834a63f7c1	3797	#define ADC_SMPR1_SMP16 ((uint32_t)0x001C0000) /!< SMP16[2:0] bits (Channel 16 Sample time selection) /
Sergunb	0:f1834a63f7c1	3798	#define ADC_SMPR1_SMP16_0 ((uint32_t)0x00040000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3799	#define ADC_SMPR1_SMP16_1 ((uint32_t)0x00080000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3800	#define ADC_SMPR1_SMP16_2 ((uint32_t)0x00100000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3801
Sergunb	0:f1834a63f7c1	3802	#define ADC_SMPR1_SMP17 ((uint32_t)0x00E00000) /!< SMP17[2:0] bits (Channel 17 Sample time selection) /
Sergunb	0:f1834a63f7c1	3803	#define ADC_SMPR1_SMP17_0 ((uint32_t)0x00200000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3804	#define ADC_SMPR1_SMP17_1 ((uint32_t)0x00400000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3805	#define ADC_SMPR1_SMP17_2 ((uint32_t)0x00800000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3806
Sergunb	0:f1834a63f7c1	3807	/**************** Bit definition for ADC_SMPR2 register *****************/
Sergunb	0:f1834a63f7c1	3808	#define ADC_SMPR2_SMP0 ((uint32_t)0x00000007) /!< SMP0[2:0] bits (Channel 0 Sample time selection) /
Sergunb	0:f1834a63f7c1	3809	#define ADC_SMPR2_SMP0_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3810	#define ADC_SMPR2_SMP0_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3811	#define ADC_SMPR2_SMP0_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3812
Sergunb	0:f1834a63f7c1	3813	#define ADC_SMPR2_SMP1 ((uint32_t)0x00000038) /!< SMP1[2:0] bits (Channel 1 Sample time selection) /
Sergunb	0:f1834a63f7c1	3814	#define ADC_SMPR2_SMP1_0 ((uint32_t)0x00000008) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3815	#define ADC_SMPR2_SMP1_1 ((uint32_t)0x00000010) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3816	#define ADC_SMPR2_SMP1_2 ((uint32_t)0x00000020) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3817
Sergunb	0:f1834a63f7c1	3818	#define ADC_SMPR2_SMP2 ((uint32_t)0x000001C0) /!< SMP2[2:0] bits (Channel 2 Sample time selection) /
Sergunb	0:f1834a63f7c1	3819	#define ADC_SMPR2_SMP2_0 ((uint32_t)0x00000040) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3820	#define ADC_SMPR2_SMP2_1 ((uint32_t)0x00000080) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3821	#define ADC_SMPR2_SMP2_2 ((uint32_t)0x00000100) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3822
Sergunb	0:f1834a63f7c1	3823	#define ADC_SMPR2_SMP3 ((uint32_t)0x00000E00) /!< SMP3[2:0] bits (Channel 3 Sample time selection) /
Sergunb	0:f1834a63f7c1	3824	#define ADC_SMPR2_SMP3_0 ((uint32_t)0x00000200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3825	#define ADC_SMPR2_SMP3_1 ((uint32_t)0x00000400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3826	#define ADC_SMPR2_SMP3_2 ((uint32_t)0x00000800) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3827
Sergunb	0:f1834a63f7c1	3828	#define ADC_SMPR2_SMP4 ((uint32_t)0x00007000) /!< SMP4[2:0] bits (Channel 4 Sample time selection) /
Sergunb	0:f1834a63f7c1	3829	#define ADC_SMPR2_SMP4_0 ((uint32_t)0x00001000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3830	#define ADC_SMPR2_SMP4_1 ((uint32_t)0x00002000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3831	#define ADC_SMPR2_SMP4_2 ((uint32_t)0x00004000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3832
Sergunb	0:f1834a63f7c1	3833	#define ADC_SMPR2_SMP5 ((uint32_t)0x00038000) /!< SMP5[2:0] bits (Channel 5 Sample time selection) /
Sergunb	0:f1834a63f7c1	3834	#define ADC_SMPR2_SMP5_0 ((uint32_t)0x00008000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3835	#define ADC_SMPR2_SMP5_1 ((uint32_t)0x00010000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3836	#define ADC_SMPR2_SMP5_2 ((uint32_t)0x00020000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3837
Sergunb	0:f1834a63f7c1	3838	#define ADC_SMPR2_SMP6 ((uint32_t)0x001C0000) /!< SMP6[2:0] bits (Channel 6 Sample time selection) /
Sergunb	0:f1834a63f7c1	3839	#define ADC_SMPR2_SMP6_0 ((uint32_t)0x00040000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3840	#define ADC_SMPR2_SMP6_1 ((uint32_t)0x00080000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3841	#define ADC_SMPR2_SMP6_2 ((uint32_t)0x00100000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3842
Sergunb	0:f1834a63f7c1	3843	#define ADC_SMPR2_SMP7 ((uint32_t)0x00E00000) /!< SMP7[2:0] bits (Channel 7 Sample time selection) /
Sergunb	0:f1834a63f7c1	3844	#define ADC_SMPR2_SMP7_0 ((uint32_t)0x00200000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3845	#define ADC_SMPR2_SMP7_1 ((uint32_t)0x00400000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3846	#define ADC_SMPR2_SMP7_2 ((uint32_t)0x00800000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3847
Sergunb	0:f1834a63f7c1	3848	#define ADC_SMPR2_SMP8 ((uint32_t)0x07000000) /!< SMP8[2:0] bits (Channel 8 Sample time selection) /
Sergunb	0:f1834a63f7c1	3849	#define ADC_SMPR2_SMP8_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3850	#define ADC_SMPR2_SMP8_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3851	#define ADC_SMPR2_SMP8_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3852
Sergunb	0:f1834a63f7c1	3853	#define ADC_SMPR2_SMP9 ((uint32_t)0x38000000) /!< SMP9[2:0] bits (Channel 9 Sample time selection) /
Sergunb	0:f1834a63f7c1	3854	#define ADC_SMPR2_SMP9_0 ((uint32_t)0x08000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3855	#define ADC_SMPR2_SMP9_1 ((uint32_t)0x10000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3856	#define ADC_SMPR2_SMP9_2 ((uint32_t)0x20000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3857
Sergunb	0:f1834a63f7c1	3858	/**************** Bit definition for ADC_JOFR1 register *****************/
Sergunb	0:f1834a63f7c1	3859	#define ADC_JOFR1_JOFFSET1 ((uint16_t)0x0FFF) /!< Data offset for injected channel 1 /
Sergunb	0:f1834a63f7c1	3860
Sergunb	0:f1834a63f7c1	3861	/**************** Bit definition for ADC_JOFR2 register *****************/
Sergunb	0:f1834a63f7c1	3862	#define ADC_JOFR2_JOFFSET2 ((uint16_t)0x0FFF) /!< Data offset for injected channel 2 /
Sergunb	0:f1834a63f7c1	3863
Sergunb	0:f1834a63f7c1	3864	/**************** Bit definition for ADC_JOFR3 register *****************/
Sergunb	0:f1834a63f7c1	3865	#define ADC_JOFR3_JOFFSET3 ((uint16_t)0x0FFF) /!< Data offset for injected channel 3 /
Sergunb	0:f1834a63f7c1	3866
Sergunb	0:f1834a63f7c1	3867	/**************** Bit definition for ADC_JOFR4 register *****************/
Sergunb	0:f1834a63f7c1	3868	#define ADC_JOFR4_JOFFSET4 ((uint16_t)0x0FFF) /!< Data offset for injected channel 4 /
Sergunb	0:f1834a63f7c1	3869
Sergunb	0:f1834a63f7c1	3870	/***************** Bit definition for ADC_HTR register ******************/
Sergunb	0:f1834a63f7c1	3871	#define ADC_HTR_HT ((uint16_t)0x0FFF) /!< Analog watchdog high threshold /
Sergunb	0:f1834a63f7c1	3872
Sergunb	0:f1834a63f7c1	3873	/***************** Bit definition for ADC_LTR register ******************/
Sergunb	0:f1834a63f7c1	3874	#define ADC_LTR_LT ((uint16_t)0x0FFF) /!< Analog watchdog low threshold /
Sergunb	0:f1834a63f7c1	3875
Sergunb	0:f1834a63f7c1	3876	/***************** Bit definition for ADC_SQR1 register *****************/
Sergunb	0:f1834a63f7c1	3877	#define ADC_SQR1_SQ13 ((uint32_t)0x0000001F) /!< SQ13[4:0] bits (13th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3878	#define ADC_SQR1_SQ13_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3879	#define ADC_SQR1_SQ13_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3880	#define ADC_SQR1_SQ13_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3881	#define ADC_SQR1_SQ13_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3882	#define ADC_SQR1_SQ13_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3883
Sergunb	0:f1834a63f7c1	3884	#define ADC_SQR1_SQ14 ((uint32_t)0x000003E0) /!< SQ14[4:0] bits (14th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3885	#define ADC_SQR1_SQ14_0 ((uint32_t)0x00000020) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3886	#define ADC_SQR1_SQ14_1 ((uint32_t)0x00000040) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3887	#define ADC_SQR1_SQ14_2 ((uint32_t)0x00000080) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3888	#define ADC_SQR1_SQ14_3 ((uint32_t)0x00000100) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3889	#define ADC_SQR1_SQ14_4 ((uint32_t)0x00000200) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3890
Sergunb	0:f1834a63f7c1	3891	#define ADC_SQR1_SQ15 ((uint32_t)0x00007C00) /!< SQ15[4:0] bits (15th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3892	#define ADC_SQR1_SQ15_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3893	#define ADC_SQR1_SQ15_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3894	#define ADC_SQR1_SQ15_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3895	#define ADC_SQR1_SQ15_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3896	#define ADC_SQR1_SQ15_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3897
Sergunb	0:f1834a63f7c1	3898	#define ADC_SQR1_SQ16 ((uint32_t)0x000F8000) /!< SQ16[4:0] bits (16th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3899	#define ADC_SQR1_SQ16_0 ((uint32_t)0x00008000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3900	#define ADC_SQR1_SQ16_1 ((uint32_t)0x00010000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3901	#define ADC_SQR1_SQ16_2 ((uint32_t)0x00020000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3902	#define ADC_SQR1_SQ16_3 ((uint32_t)0x00040000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3903	#define ADC_SQR1_SQ16_4 ((uint32_t)0x00080000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3904
Sergunb	0:f1834a63f7c1	3905	#define ADC_SQR1_L ((uint32_t)0x00F00000) /!< L[3:0] bits (Regular channel sequence length) /
Sergunb	0:f1834a63f7c1	3906	#define ADC_SQR1_L_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3907	#define ADC_SQR1_L_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3908	#define ADC_SQR1_L_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3909	#define ADC_SQR1_L_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3910
Sergunb	0:f1834a63f7c1	3911	/***************** Bit definition for ADC_SQR2 register *****************/
Sergunb	0:f1834a63f7c1	3912	#define ADC_SQR2_SQ7 ((uint32_t)0x0000001F) /!< SQ7[4:0] bits (7th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3913	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3914	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3915	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3916	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3917	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3918
Sergunb	0:f1834a63f7c1	3919	#define ADC_SQR2_SQ8 ((uint32_t)0x000003E0) /!< SQ8[4:0] bits (8th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3920	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00000020) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3921	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00000040) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3922	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00000080) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3923	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00000100) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3924	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00000200) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3925
Sergunb	0:f1834a63f7c1	3926	#define ADC_SQR2_SQ9 ((uint32_t)0x00007C00) /!< SQ9[4:0] bits (9th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3927	#define ADC_SQR2_SQ9_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3928	#define ADC_SQR2_SQ9_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3929	#define ADC_SQR2_SQ9_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3930	#define ADC_SQR2_SQ9_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3931	#define ADC_SQR2_SQ9_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3932
Sergunb	0:f1834a63f7c1	3933	#define ADC_SQR2_SQ10 ((uint32_t)0x000F8000) /!< SQ10[4:0] bits (10th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3934	#define ADC_SQR2_SQ10_0 ((uint32_t)0x00008000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3935	#define ADC_SQR2_SQ10_1 ((uint32_t)0x00010000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3936	#define ADC_SQR2_SQ10_2 ((uint32_t)0x00020000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3937	#define ADC_SQR2_SQ10_3 ((uint32_t)0x00040000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3938	#define ADC_SQR2_SQ10_4 ((uint32_t)0x00080000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3939
Sergunb	0:f1834a63f7c1	3940	#define ADC_SQR2_SQ11 ((uint32_t)0x01F00000) /!< SQ11[4:0] bits (11th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3941	#define ADC_SQR2_SQ11_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3942	#define ADC_SQR2_SQ11_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3943	#define ADC_SQR2_SQ11_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3944	#define ADC_SQR2_SQ11_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3945	#define ADC_SQR2_SQ11_4 ((uint32_t)0x01000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3946
Sergunb	0:f1834a63f7c1	3947	#define ADC_SQR2_SQ12 ((uint32_t)0x3E000000) /!< SQ12[4:0] bits (12th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3948	#define ADC_SQR2_SQ12_0 ((uint32_t)0x02000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3949	#define ADC_SQR2_SQ12_1 ((uint32_t)0x04000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3950	#define ADC_SQR2_SQ12_2 ((uint32_t)0x08000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3951	#define ADC_SQR2_SQ12_3 ((uint32_t)0x10000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3952	#define ADC_SQR2_SQ12_4 ((uint32_t)0x20000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3953
Sergunb	0:f1834a63f7c1	3954	/***************** Bit definition for ADC_SQR3 register *****************/
Sergunb	0:f1834a63f7c1	3955	#define ADC_SQR3_SQ1 ((uint32_t)0x0000001F) /!< SQ1[4:0] bits (1st conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3956	#define ADC_SQR3_SQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3957	#define ADC_SQR3_SQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3958	#define ADC_SQR3_SQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3959	#define ADC_SQR3_SQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3960	#define ADC_SQR3_SQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3961
Sergunb	0:f1834a63f7c1	3962	#define ADC_SQR3_SQ2 ((uint32_t)0x000003E0) /!< SQ2[4:0] bits (2nd conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3963	#define ADC_SQR3_SQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3964	#define ADC_SQR3_SQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3965	#define ADC_SQR3_SQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3966	#define ADC_SQR3_SQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3967	#define ADC_SQR3_SQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3968
Sergunb	0:f1834a63f7c1	3969	#define ADC_SQR3_SQ3 ((uint32_t)0x00007C00) /!< SQ3[4:0] bits (3rd conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3970	#define ADC_SQR3_SQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3971	#define ADC_SQR3_SQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3972	#define ADC_SQR3_SQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3973	#define ADC_SQR3_SQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3974	#define ADC_SQR3_SQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3975
Sergunb	0:f1834a63f7c1	3976	#define ADC_SQR3_SQ4 ((uint32_t)0x000F8000) /!< SQ4[4:0] bits (4th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3977	#define ADC_SQR3_SQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3978	#define ADC_SQR3_SQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3979	#define ADC_SQR3_SQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3980	#define ADC_SQR3_SQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3981	#define ADC_SQR3_SQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3982
Sergunb	0:f1834a63f7c1	3983	#define ADC_SQR3_SQ5 ((uint32_t)0x01F00000) /!< SQ5[4:0] bits (5th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3984	#define ADC_SQR3_SQ5_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3985	#define ADC_SQR3_SQ5_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3986	#define ADC_SQR3_SQ5_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3987	#define ADC_SQR3_SQ5_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3988	#define ADC_SQR3_SQ5_4 ((uint32_t)0x01000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3989
Sergunb	0:f1834a63f7c1	3990	#define ADC_SQR3_SQ6 ((uint32_t)0x3E000000) /!< SQ6[4:0] bits (6th conversion in regular sequence) /
Sergunb	0:f1834a63f7c1	3991	#define ADC_SQR3_SQ6_0 ((uint32_t)0x02000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	3992	#define ADC_SQR3_SQ6_1 ((uint32_t)0x04000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	3993	#define ADC_SQR3_SQ6_2 ((uint32_t)0x08000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	3994	#define ADC_SQR3_SQ6_3 ((uint32_t)0x10000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	3995	#define ADC_SQR3_SQ6_4 ((uint32_t)0x20000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	3996
Sergunb	0:f1834a63f7c1	3997	/***************** Bit definition for ADC_JSQR register *****************/
Sergunb	0:f1834a63f7c1	3998	#define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /!< JSQ1[4:0] bits (1st conversion in injected sequence) /
Sergunb	0:f1834a63f7c1	3999	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4000	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4001	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4002	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4003	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	4004
Sergunb	0:f1834a63f7c1	4005	#define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /!< JSQ2[4:0] bits (2nd conversion in injected sequence) /
Sergunb	0:f1834a63f7c1	4006	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4007	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4008	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4009	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4010	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	4011
Sergunb	0:f1834a63f7c1	4012	#define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /!< JSQ3[4:0] bits (3rd conversion in injected sequence) /
Sergunb	0:f1834a63f7c1	4013	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4014	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4015	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4016	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4017	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	4018
Sergunb	0:f1834a63f7c1	4019	#define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /!< JSQ4[4:0] bits (4th conversion in injected sequence) /
Sergunb	0:f1834a63f7c1	4020	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4021	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4022	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4023	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4024	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	4025
Sergunb	0:f1834a63f7c1	4026	#define ADC_JSQR_JL ((uint32_t)0x00300000) /!< JL[1:0] bits (Injected Sequence length) /
Sergunb	0:f1834a63f7c1	4027	#define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4028	#define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4029
Sergunb	0:f1834a63f7c1	4030	/***************** Bit definition for ADC_JDR1 register *****************/
Sergunb	0:f1834a63f7c1	4031	#define ADC_JDR1_JDATA ((uint16_t)0xFFFF) /!< Injected data /
Sergunb	0:f1834a63f7c1	4032
Sergunb	0:f1834a63f7c1	4033	/***************** Bit definition for ADC_JDR2 register *****************/
Sergunb	0:f1834a63f7c1	4034	#define ADC_JDR2_JDATA ((uint16_t)0xFFFF) /!< Injected data /
Sergunb	0:f1834a63f7c1	4035
Sergunb	0:f1834a63f7c1	4036	/***************** Bit definition for ADC_JDR3 register *****************/
Sergunb	0:f1834a63f7c1	4037	#define ADC_JDR3_JDATA ((uint16_t)0xFFFF) /!< Injected data /
Sergunb	0:f1834a63f7c1	4038
Sergunb	0:f1834a63f7c1	4039	/***************** Bit definition for ADC_JDR4 register *****************/
Sergunb	0:f1834a63f7c1	4040	#define ADC_JDR4_JDATA ((uint16_t)0xFFFF) /!< Injected data /
Sergunb	0:f1834a63f7c1	4041
Sergunb	0:f1834a63f7c1	4042	/****************** Bit definition for ADC_DR register ******************/
Sergunb	0:f1834a63f7c1	4043	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
Sergunb	0:f1834a63f7c1	4044	#define ADC_DR_ADC2DATA ((uint32_t)0xFFFF0000) /!< ADC2 data /
Sergunb	0:f1834a63f7c1	4045
Sergunb	0:f1834a63f7c1	4046	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4047	/* */
Sergunb	0:f1834a63f7c1	4048	/* Digital to Analog Converter */
Sergunb	0:f1834a63f7c1	4049	/* */
Sergunb	0:f1834a63f7c1	4050	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4051
Sergunb	0:f1834a63f7c1	4052	/****************** Bit definition for DAC_CR register ******************/
Sergunb	0:f1834a63f7c1	4053	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
Sergunb	0:f1834a63f7c1	4054	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
Sergunb	0:f1834a63f7c1	4055	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
Sergunb	0:f1834a63f7c1	4056
Sergunb	0:f1834a63f7c1	4057	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
Sergunb	0:f1834a63f7c1	4058	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4059	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4060	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4061
Sergunb	0:f1834a63f7c1	4062	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
Sergunb	0:f1834a63f7c1	4063	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4064	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4065
Sergunb	0:f1834a63f7c1	4066	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
Sergunb	0:f1834a63f7c1	4067	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4068	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4069	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4070	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4071
Sergunb	0:f1834a63f7c1	4072	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
Sergunb	0:f1834a63f7c1	4073	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
Sergunb	0:f1834a63f7c1	4074	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
Sergunb	0:f1834a63f7c1	4075	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
Sergunb	0:f1834a63f7c1	4076
Sergunb	0:f1834a63f7c1	4077	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
Sergunb	0:f1834a63f7c1	4078	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4079	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4080	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4081
Sergunb	0:f1834a63f7c1	4082	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
Sergunb	0:f1834a63f7c1	4083	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4084	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4085
Sergunb	0:f1834a63f7c1	4086	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
Sergunb	0:f1834a63f7c1	4087	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4088	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4089	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4090	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4091
Sergunb	0:f1834a63f7c1	4092	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
Sergunb	0:f1834a63f7c1	4093
Sergunb	0:f1834a63f7c1	4094	/*************** Bit definition for DAC_SWTRIGR register ****************/
Sergunb	0:f1834a63f7c1	4095	#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /!< DAC channel1 software trigger /
Sergunb	0:f1834a63f7c1	4096	#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /!< DAC channel2 software trigger /
Sergunb	0:f1834a63f7c1	4097
Sergunb	0:f1834a63f7c1	4098	/*************** Bit definition for DAC_DHR12R1 register ****************/
Sergunb	0:f1834a63f7c1	4099	#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /!< DAC channel1 12-bit Right aligned data /
Sergunb	0:f1834a63f7c1	4100
Sergunb	0:f1834a63f7c1	4101	/*************** Bit definition for DAC_DHR12L1 register ****************/
Sergunb	0:f1834a63f7c1	4102	#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /!< DAC channel1 12-bit Left aligned data /
Sergunb	0:f1834a63f7c1	4103
Sergunb	0:f1834a63f7c1	4104	/**************** Bit definition for DAC_DHR8R1 register ****************/
Sergunb	0:f1834a63f7c1	4105	#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /!< DAC channel1 8-bit Right aligned data /
Sergunb	0:f1834a63f7c1	4106
Sergunb	0:f1834a63f7c1	4107	/*************** Bit definition for DAC_DHR12R2 register ****************/
Sergunb	0:f1834a63f7c1	4108	#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /!< DAC channel2 12-bit Right aligned data /
Sergunb	0:f1834a63f7c1	4109
Sergunb	0:f1834a63f7c1	4110	/*************** Bit definition for DAC_DHR12L2 register ****************/
Sergunb	0:f1834a63f7c1	4111	#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /!< DAC channel2 12-bit Left aligned data /
Sergunb	0:f1834a63f7c1	4112
Sergunb	0:f1834a63f7c1	4113	/**************** Bit definition for DAC_DHR8R2 register ****************/
Sergunb	0:f1834a63f7c1	4114	#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /!< DAC channel2 8-bit Right aligned data /
Sergunb	0:f1834a63f7c1	4115
Sergunb	0:f1834a63f7c1	4116	/*************** Bit definition for DAC_DHR12RD register ****************/
Sergunb	0:f1834a63f7c1	4117	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
Sergunb	0:f1834a63f7c1	4118	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!< DAC channel2 12-bit Right aligned data /
Sergunb	0:f1834a63f7c1	4119
Sergunb	0:f1834a63f7c1	4120	/*************** Bit definition for DAC_DHR12LD register ****************/
Sergunb	0:f1834a63f7c1	4121	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
Sergunb	0:f1834a63f7c1	4122	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!< DAC channel2 12-bit Left aligned data /
Sergunb	0:f1834a63f7c1	4123
Sergunb	0:f1834a63f7c1	4124	/**************** Bit definition for DAC_DHR8RD register ****************/
Sergunb	0:f1834a63f7c1	4125	#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /!< DAC channel1 8-bit Right aligned data /
Sergunb	0:f1834a63f7c1	4126	#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /!< DAC channel2 8-bit Right aligned data /
Sergunb	0:f1834a63f7c1	4127
Sergunb	0:f1834a63f7c1	4128	/***************** Bit definition for DAC_DOR1 register *****************/
Sergunb	0:f1834a63f7c1	4129	#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /!< DAC channel1 data output /
Sergunb	0:f1834a63f7c1	4130
Sergunb	0:f1834a63f7c1	4131	/***************** Bit definition for DAC_DOR2 register *****************/
Sergunb	0:f1834a63f7c1	4132	#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /!< DAC channel2 data output /
Sergunb	0:f1834a63f7c1	4133
Sergunb	0:f1834a63f7c1	4134	/****************** Bit definition for DAC_SR register ******************/
Sergunb	0:f1834a63f7c1	4135	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun flag /
Sergunb	0:f1834a63f7c1	4136	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun flag /
Sergunb	0:f1834a63f7c1	4137
Sergunb	0:f1834a63f7c1	4138	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4139	/* */
Sergunb	0:f1834a63f7c1	4140	/* CEC */
Sergunb	0:f1834a63f7c1	4141	/* */
Sergunb	0:f1834a63f7c1	4142	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4143	/****************** Bit definition for CEC_CFGR register ****************/
Sergunb	0:f1834a63f7c1	4144	#define CEC_CFGR_PE ((uint16_t)0x0001) /!< Peripheral Enable /
Sergunb	0:f1834a63f7c1	4145	#define CEC_CFGR_IE ((uint16_t)0x0002) /!< Interrupt Enable /
Sergunb	0:f1834a63f7c1	4146	#define CEC_CFGR_BTEM ((uint16_t)0x0004) /!< Bit Timing Error Mode /
Sergunb	0:f1834a63f7c1	4147	#define CEC_CFGR_BPEM ((uint16_t)0x0008) /!< Bit Period Error Mode /
Sergunb	0:f1834a63f7c1	4148
Sergunb	0:f1834a63f7c1	4149	/****************** Bit definition for CEC_OAR register ****************/
Sergunb	0:f1834a63f7c1	4150	#define CEC_OAR_OA ((uint16_t)0x000F) /!< OA[3:0]: Own Address /
Sergunb	0:f1834a63f7c1	4151	#define CEC_OAR_OA_0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4152	#define CEC_OAR_OA_1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4153	#define CEC_OAR_OA_2 ((uint16_t)0x0004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4154	#define CEC_OAR_OA_3 ((uint16_t)0x0008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4155
Sergunb	0:f1834a63f7c1	4156	/****************** Bit definition for CEC_PRES register ****************/
Sergunb	0:f1834a63f7c1	4157	#define CEC_PRES_PRES ((uint16_t)0x3FFF) /!< Prescaler Counter Value /
Sergunb	0:f1834a63f7c1	4158
Sergunb	0:f1834a63f7c1	4159	/****************** Bit definition for CEC_ESR register ****************/
Sergunb	0:f1834a63f7c1	4160	#define CEC_ESR_BTE ((uint16_t)0x0001) /!< Bit Timing Error /
Sergunb	0:f1834a63f7c1	4161	#define CEC_ESR_BPE ((uint16_t)0x0002) /!< Bit Period Error /
Sergunb	0:f1834a63f7c1	4162	#define CEC_ESR_RBTFE ((uint16_t)0x0004) /!< Rx Block Transfer Finished Error /
Sergunb	0:f1834a63f7c1	4163	#define CEC_ESR_SBE ((uint16_t)0x0008) /!< Start Bit Error /
Sergunb	0:f1834a63f7c1	4164	#define CEC_ESR_ACKE ((uint16_t)0x0010) /!< Block Acknowledge Error /
Sergunb	0:f1834a63f7c1	4165	#define CEC_ESR_LINE ((uint16_t)0x0020) /!< Line Error /
Sergunb	0:f1834a63f7c1	4166	#define CEC_ESR_TBTFE ((uint16_t)0x0040) /!< Tx Block Transfer Finished Error /
Sergunb	0:f1834a63f7c1	4167
Sergunb	0:f1834a63f7c1	4168	/****************** Bit definition for CEC_CSR register ****************/
Sergunb	0:f1834a63f7c1	4169	#define CEC_CSR_TSOM ((uint16_t)0x0001) /!< Tx Start Of Message /
Sergunb	0:f1834a63f7c1	4170	#define CEC_CSR_TEOM ((uint16_t)0x0002) /!< Tx End Of Message /
Sergunb	0:f1834a63f7c1	4171	#define CEC_CSR_TERR ((uint16_t)0x0004) /!< Tx Error /
Sergunb	0:f1834a63f7c1	4172	#define CEC_CSR_TBTRF ((uint16_t)0x0008) /!< Tx Byte Transfer Request or Block Transfer Finished /
Sergunb	0:f1834a63f7c1	4173	#define CEC_CSR_RSOM ((uint16_t)0x0010) /!< Rx Start Of Message /
Sergunb	0:f1834a63f7c1	4174	#define CEC_CSR_REOM ((uint16_t)0x0020) /!< Rx End Of Message /
Sergunb	0:f1834a63f7c1	4175	#define CEC_CSR_RERR ((uint16_t)0x0040) /!< Rx Error /
Sergunb	0:f1834a63f7c1	4176	#define CEC_CSR_RBTF ((uint16_t)0x0080) /!< Rx Block Transfer Finished /
Sergunb	0:f1834a63f7c1	4177
Sergunb	0:f1834a63f7c1	4178	/****************** Bit definition for CEC_TXD register ****************/
Sergunb	0:f1834a63f7c1	4179	#define CEC_TXD_TXD ((uint16_t)0x00FF) /!< Tx Data register /
Sergunb	0:f1834a63f7c1	4180
Sergunb	0:f1834a63f7c1	4181	/****************** Bit definition for CEC_RXD register ****************/
Sergunb	0:f1834a63f7c1	4182	#define CEC_RXD_RXD ((uint16_t)0x00FF) /!< Rx Data register /
Sergunb	0:f1834a63f7c1	4183
Sergunb	0:f1834a63f7c1	4184	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4185	/* */
Sergunb	0:f1834a63f7c1	4186	/* TIM */
Sergunb	0:f1834a63f7c1	4187	/* */
Sergunb	0:f1834a63f7c1	4188	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4189
Sergunb	0:f1834a63f7c1	4190	/***************** Bit definition for TIM_CR1 register ******************/
Sergunb	0:f1834a63f7c1	4191	#define TIM_CR1_CEN ((uint16_t)0x0001) /!< Counter enable /
Sergunb	0:f1834a63f7c1	4192	#define TIM_CR1_UDIS ((uint16_t)0x0002) /!< Update disable /
Sergunb	0:f1834a63f7c1	4193	#define TIM_CR1_URS ((uint16_t)0x0004) /!< Update request source /
Sergunb	0:f1834a63f7c1	4194	#define TIM_CR1_OPM ((uint16_t)0x0008) /!< One pulse mode /
Sergunb	0:f1834a63f7c1	4195	#define TIM_CR1_DIR ((uint16_t)0x0010) /!< Direction /
Sergunb	0:f1834a63f7c1	4196
Sergunb	0:f1834a63f7c1	4197	#define TIM_CR1_CMS ((uint16_t)0x0060) /!< CMS[1:0] bits (Center-aligned mode selection) /
Sergunb	0:f1834a63f7c1	4198	#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4199	#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4200
Sergunb	0:f1834a63f7c1	4201	#define TIM_CR1_ARPE ((uint16_t)0x0080) /!< Auto-reload preload enable /
Sergunb	0:f1834a63f7c1	4202
Sergunb	0:f1834a63f7c1	4203	#define TIM_CR1_CKD ((uint16_t)0x0300) /!< CKD[1:0] bits (clock division) /
Sergunb	0:f1834a63f7c1	4204	#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4205	#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4206
Sergunb	0:f1834a63f7c1	4207	/***************** Bit definition for TIM_CR2 register ******************/
Sergunb	0:f1834a63f7c1	4208	#define TIM_CR2_CCPC ((uint16_t)0x0001) /!< Capture/Compare Preloaded Control /
Sergunb	0:f1834a63f7c1	4209	#define TIM_CR2_CCUS ((uint16_t)0x0004) /!< Capture/Compare Control Update Selection /
Sergunb	0:f1834a63f7c1	4210	#define TIM_CR2_CCDS ((uint16_t)0x0008) /!< Capture/Compare DMA Selection /
Sergunb	0:f1834a63f7c1	4211
Sergunb	0:f1834a63f7c1	4212	#define TIM_CR2_MMS ((uint16_t)0x0070) /!< MMS[2:0] bits (Master Mode Selection) /
Sergunb	0:f1834a63f7c1	4213	#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4214	#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4215	#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4216
Sergunb	0:f1834a63f7c1	4217	#define TIM_CR2_TI1S ((uint16_t)0x0080) /!< TI1 Selection /
Sergunb	0:f1834a63f7c1	4218	#define TIM_CR2_OIS1 ((uint16_t)0x0100) /!< Output Idle state 1 (OC1 output) /
Sergunb	0:f1834a63f7c1	4219	#define TIM_CR2_OIS1N ((uint16_t)0x0200) /!< Output Idle state 1 (OC1N output) /
Sergunb	0:f1834a63f7c1	4220	#define TIM_CR2_OIS2 ((uint16_t)0x0400) /!< Output Idle state 2 (OC2 output) /
Sergunb	0:f1834a63f7c1	4221	#define TIM_CR2_OIS2N ((uint16_t)0x0800) /!< Output Idle state 2 (OC2N output) /
Sergunb	0:f1834a63f7c1	4222	#define TIM_CR2_OIS3 ((uint16_t)0x1000) /!< Output Idle state 3 (OC3 output) /
Sergunb	0:f1834a63f7c1	4223	#define TIM_CR2_OIS3N ((uint16_t)0x2000) /!< Output Idle state 3 (OC3N output) /
Sergunb	0:f1834a63f7c1	4224	#define TIM_CR2_OIS4 ((uint16_t)0x4000) /!< Output Idle state 4 (OC4 output) /
Sergunb	0:f1834a63f7c1	4225
Sergunb	0:f1834a63f7c1	4226	/***************** Bit definition for TIM_SMCR register *****************/
Sergunb	0:f1834a63f7c1	4227	#define TIM_SMCR_SMS ((uint16_t)0x0007) /!< SMS[2:0] bits (Slave mode selection) /
Sergunb	0:f1834a63f7c1	4228	#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4229	#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4230	#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4231
Sergunb	0:f1834a63f7c1	4232	#define TIM_SMCR_TS ((uint16_t)0x0070) /!< TS[2:0] bits (Trigger selection) /
Sergunb	0:f1834a63f7c1	4233	#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4234	#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4235	#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4236
Sergunb	0:f1834a63f7c1	4237	#define TIM_SMCR_MSM ((uint16_t)0x0080) /!< Master/slave mode /
Sergunb	0:f1834a63f7c1	4238
Sergunb	0:f1834a63f7c1	4239	#define TIM_SMCR_ETF ((uint16_t)0x0F00) /!< ETF[3:0] bits (External trigger filter) /
Sergunb	0:f1834a63f7c1	4240	#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4241	#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4242	#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4243	#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4244
Sergunb	0:f1834a63f7c1	4245	#define TIM_SMCR_ETPS ((uint16_t)0x3000) /!< ETPS[1:0] bits (External trigger prescaler) /
Sergunb	0:f1834a63f7c1	4246	#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4247	#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4248
Sergunb	0:f1834a63f7c1	4249	#define TIM_SMCR_ECE ((uint16_t)0x4000) /!< External clock enable /
Sergunb	0:f1834a63f7c1	4250	#define TIM_SMCR_ETP ((uint16_t)0x8000) /!< External trigger polarity /
Sergunb	0:f1834a63f7c1	4251
Sergunb	0:f1834a63f7c1	4252	/***************** Bit definition for TIM_DIER register *****************/
Sergunb	0:f1834a63f7c1	4253	#define TIM_DIER_UIE ((uint16_t)0x0001) /!< Update interrupt enable /
Sergunb	0:f1834a63f7c1	4254	#define TIM_DIER_CC1IE ((uint16_t)0x0002) /!< Capture/Compare 1 interrupt enable /
Sergunb	0:f1834a63f7c1	4255	#define TIM_DIER_CC2IE ((uint16_t)0x0004) /!< Capture/Compare 2 interrupt enable /
Sergunb	0:f1834a63f7c1	4256	#define TIM_DIER_CC3IE ((uint16_t)0x0008) /!< Capture/Compare 3 interrupt enable /
Sergunb	0:f1834a63f7c1	4257	#define TIM_DIER_CC4IE ((uint16_t)0x0010) /!< Capture/Compare 4 interrupt enable /
Sergunb	0:f1834a63f7c1	4258	#define TIM_DIER_COMIE ((uint16_t)0x0020) /!< COM interrupt enable /
Sergunb	0:f1834a63f7c1	4259	#define TIM_DIER_TIE ((uint16_t)0x0040) /!< Trigger interrupt enable /
Sergunb	0:f1834a63f7c1	4260	#define TIM_DIER_BIE ((uint16_t)0x0080) /!< Break interrupt enable /
Sergunb	0:f1834a63f7c1	4261	#define TIM_DIER_UDE ((uint16_t)0x0100) /!< Update DMA request enable /
Sergunb	0:f1834a63f7c1	4262	#define TIM_DIER_CC1DE ((uint16_t)0x0200) /!< Capture/Compare 1 DMA request enable /
Sergunb	0:f1834a63f7c1	4263	#define TIM_DIER_CC2DE ((uint16_t)0x0400) /!< Capture/Compare 2 DMA request enable /
Sergunb	0:f1834a63f7c1	4264	#define TIM_DIER_CC3DE ((uint16_t)0x0800) /!< Capture/Compare 3 DMA request enable /
Sergunb	0:f1834a63f7c1	4265	#define TIM_DIER_CC4DE ((uint16_t)0x1000) /!< Capture/Compare 4 DMA request enable /
Sergunb	0:f1834a63f7c1	4266	#define TIM_DIER_COMDE ((uint16_t)0x2000) /!< COM DMA request enable /
Sergunb	0:f1834a63f7c1	4267	#define TIM_DIER_TDE ((uint16_t)0x4000) /!< Trigger DMA request enable /
Sergunb	0:f1834a63f7c1	4268
Sergunb	0:f1834a63f7c1	4269	/****************** Bit definition for TIM_SR register ******************/
Sergunb	0:f1834a63f7c1	4270	#define TIM_SR_UIF ((uint16_t)0x0001) /!< Update interrupt Flag /
Sergunb	0:f1834a63f7c1	4271	#define TIM_SR_CC1IF ((uint16_t)0x0002) /!< Capture/Compare 1 interrupt Flag /
Sergunb	0:f1834a63f7c1	4272	#define TIM_SR_CC2IF ((uint16_t)0x0004) /!< Capture/Compare 2 interrupt Flag /
Sergunb	0:f1834a63f7c1	4273	#define TIM_SR_CC3IF ((uint16_t)0x0008) /!< Capture/Compare 3 interrupt Flag /
Sergunb	0:f1834a63f7c1	4274	#define TIM_SR_CC4IF ((uint16_t)0x0010) /!< Capture/Compare 4 interrupt Flag /
Sergunb	0:f1834a63f7c1	4275	#define TIM_SR_COMIF ((uint16_t)0x0020) /!< COM interrupt Flag /
Sergunb	0:f1834a63f7c1	4276	#define TIM_SR_TIF ((uint16_t)0x0040) /!< Trigger interrupt Flag /
Sergunb	0:f1834a63f7c1	4277	#define TIM_SR_BIF ((uint16_t)0x0080) /!< Break interrupt Flag /
Sergunb	0:f1834a63f7c1	4278	#define TIM_SR_CC1OF ((uint16_t)0x0200) /!< Capture/Compare 1 Overcapture Flag /
Sergunb	0:f1834a63f7c1	4279	#define TIM_SR_CC2OF ((uint16_t)0x0400) /!< Capture/Compare 2 Overcapture Flag /
Sergunb	0:f1834a63f7c1	4280	#define TIM_SR_CC3OF ((uint16_t)0x0800) /!< Capture/Compare 3 Overcapture Flag /
Sergunb	0:f1834a63f7c1	4281	#define TIM_SR_CC4OF ((uint16_t)0x1000) /!< Capture/Compare 4 Overcapture Flag /
Sergunb	0:f1834a63f7c1	4282
Sergunb	0:f1834a63f7c1	4283	/***************** Bit definition for TIM_EGR register ******************/
Sergunb	0:f1834a63f7c1	4284	#define TIM_EGR_UG ((uint8_t)0x01) /!< Update Generation /
Sergunb	0:f1834a63f7c1	4285	#define TIM_EGR_CC1G ((uint8_t)0x02) /!< Capture/Compare 1 Generation /
Sergunb	0:f1834a63f7c1	4286	#define TIM_EGR_CC2G ((uint8_t)0x04) /!< Capture/Compare 2 Generation /
Sergunb	0:f1834a63f7c1	4287	#define TIM_EGR_CC3G ((uint8_t)0x08) /!< Capture/Compare 3 Generation /
Sergunb	0:f1834a63f7c1	4288	#define TIM_EGR_CC4G ((uint8_t)0x10) /!< Capture/Compare 4 Generation /
Sergunb	0:f1834a63f7c1	4289	#define TIM_EGR_COMG ((uint8_t)0x20) /!< Capture/Compare Control Update Generation /
Sergunb	0:f1834a63f7c1	4290	#define TIM_EGR_TG ((uint8_t)0x40) /!< Trigger Generation /
Sergunb	0:f1834a63f7c1	4291	#define TIM_EGR_BG ((uint8_t)0x80) /!< Break Generation /
Sergunb	0:f1834a63f7c1	4292
Sergunb	0:f1834a63f7c1	4293	/**************** Bit definition for TIM_CCMR1 register *****************/
Sergunb	0:f1834a63f7c1	4294	#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /!< CC1S[1:0] bits (Capture/Compare 1 Selection) /
Sergunb	0:f1834a63f7c1	4295	#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4296	#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4297
Sergunb	0:f1834a63f7c1	4298	#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /!< Output Compare 1 Fast enable /
Sergunb	0:f1834a63f7c1	4299	#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /!< Output Compare 1 Preload enable /
Sergunb	0:f1834a63f7c1	4300
Sergunb	0:f1834a63f7c1	4301	#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /!< OC1M[2:0] bits (Output Compare 1 Mode) /
Sergunb	0:f1834a63f7c1	4302	#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4303	#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4304	#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4305
Sergunb	0:f1834a63f7c1	4306	#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /!< Output Compare 1Clear Enable /
Sergunb	0:f1834a63f7c1	4307
Sergunb	0:f1834a63f7c1	4308	#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /!< CC2S[1:0] bits (Capture/Compare 2 Selection) /
Sergunb	0:f1834a63f7c1	4309	#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4310	#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4311
Sergunb	0:f1834a63f7c1	4312	#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /!< Output Compare 2 Fast enable /
Sergunb	0:f1834a63f7c1	4313	#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /!< Output Compare 2 Preload enable /
Sergunb	0:f1834a63f7c1	4314
Sergunb	0:f1834a63f7c1	4315	#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /!< OC2M[2:0] bits (Output Compare 2 Mode) /
Sergunb	0:f1834a63f7c1	4316	#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4317	#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4318	#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4319
Sergunb	0:f1834a63f7c1	4320	#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /!< Output Compare 2 Clear Enable /
Sergunb	0:f1834a63f7c1	4321
Sergunb	0:f1834a63f7c1	4322	/----------------------------------------------------------------------------/
Sergunb	0:f1834a63f7c1	4323
Sergunb	0:f1834a63f7c1	4324	#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /!< IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
Sergunb	0:f1834a63f7c1	4325	#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4326	#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4327
Sergunb	0:f1834a63f7c1	4328	#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /!< IC1F[3:0] bits (Input Capture 1 Filter) /
Sergunb	0:f1834a63f7c1	4329	#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4330	#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4331	#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4332	#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4333
Sergunb	0:f1834a63f7c1	4334	#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /!< IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
Sergunb	0:f1834a63f7c1	4335	#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4336	#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4337
Sergunb	0:f1834a63f7c1	4338	#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /!< IC2F[3:0] bits (Input Capture 2 Filter) /
Sergunb	0:f1834a63f7c1	4339	#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4340	#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4341	#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4342	#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4343
Sergunb	0:f1834a63f7c1	4344	/**************** Bit definition for TIM_CCMR2 register *****************/
Sergunb	0:f1834a63f7c1	4345	#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /!< CC3S[1:0] bits (Capture/Compare 3 Selection) /
Sergunb	0:f1834a63f7c1	4346	#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4347	#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4348
Sergunb	0:f1834a63f7c1	4349	#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /!< Output Compare 3 Fast enable /
Sergunb	0:f1834a63f7c1	4350	#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /!< Output Compare 3 Preload enable /
Sergunb	0:f1834a63f7c1	4351
Sergunb	0:f1834a63f7c1	4352	#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /!< OC3M[2:0] bits (Output Compare 3 Mode) /
Sergunb	0:f1834a63f7c1	4353	#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4354	#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4355	#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4356
Sergunb	0:f1834a63f7c1	4357	#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /!< Output Compare 3 Clear Enable /
Sergunb	0:f1834a63f7c1	4358
Sergunb	0:f1834a63f7c1	4359	#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /!< CC4S[1:0] bits (Capture/Compare 4 Selection) /
Sergunb	0:f1834a63f7c1	4360	#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4361	#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4362
Sergunb	0:f1834a63f7c1	4363	#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /!< Output Compare 4 Fast enable /
Sergunb	0:f1834a63f7c1	4364	#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /!< Output Compare 4 Preload enable /
Sergunb	0:f1834a63f7c1	4365
Sergunb	0:f1834a63f7c1	4366	#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /!< OC4M[2:0] bits (Output Compare 4 Mode) /
Sergunb	0:f1834a63f7c1	4367	#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4368	#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4369	#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4370
Sergunb	0:f1834a63f7c1	4371	#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /!< Output Compare 4 Clear Enable /
Sergunb	0:f1834a63f7c1	4372
Sergunb	0:f1834a63f7c1	4373	/----------------------------------------------------------------------------/
Sergunb	0:f1834a63f7c1	4374
Sergunb	0:f1834a63f7c1	4375	#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /!< IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
Sergunb	0:f1834a63f7c1	4376	#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4377	#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4378
Sergunb	0:f1834a63f7c1	4379	#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /!< IC3F[3:0] bits (Input Capture 3 Filter) /
Sergunb	0:f1834a63f7c1	4380	#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4381	#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4382	#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4383	#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4384
Sergunb	0:f1834a63f7c1	4385	#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /!< IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
Sergunb	0:f1834a63f7c1	4386	#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4387	#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4388
Sergunb	0:f1834a63f7c1	4389	#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /!< IC4F[3:0] bits (Input Capture 4 Filter) /
Sergunb	0:f1834a63f7c1	4390	#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4391	#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4392	#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4393	#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4394
Sergunb	0:f1834a63f7c1	4395	/***************** Bit definition for TIM_CCER register *****************/
Sergunb	0:f1834a63f7c1	4396	#define TIM_CCER_CC1E ((uint16_t)0x0001) /!< Capture/Compare 1 output enable /
Sergunb	0:f1834a63f7c1	4397	#define TIM_CCER_CC1P ((uint16_t)0x0002) /!< Capture/Compare 1 output Polarity /
Sergunb	0:f1834a63f7c1	4398	#define TIM_CCER_CC1NE ((uint16_t)0x0004) /!< Capture/Compare 1 Complementary output enable /
Sergunb	0:f1834a63f7c1	4399	#define TIM_CCER_CC1NP ((uint16_t)0x0008) /!< Capture/Compare 1 Complementary output Polarity /
Sergunb	0:f1834a63f7c1	4400	#define TIM_CCER_CC2E ((uint16_t)0x0010) /!< Capture/Compare 2 output enable /
Sergunb	0:f1834a63f7c1	4401	#define TIM_CCER_CC2P ((uint16_t)0x0020) /!< Capture/Compare 2 output Polarity /
Sergunb	0:f1834a63f7c1	4402	#define TIM_CCER_CC2NE ((uint16_t)0x0040) /!< Capture/Compare 2 Complementary output enable /
Sergunb	0:f1834a63f7c1	4403	#define TIM_CCER_CC2NP ((uint16_t)0x0080) /!< Capture/Compare 2 Complementary output Polarity /
Sergunb	0:f1834a63f7c1	4404	#define TIM_CCER_CC3E ((uint16_t)0x0100) /!< Capture/Compare 3 output enable /
Sergunb	0:f1834a63f7c1	4405	#define TIM_CCER_CC3P ((uint16_t)0x0200) /!< Capture/Compare 3 output Polarity /
Sergunb	0:f1834a63f7c1	4406	#define TIM_CCER_CC3NE ((uint16_t)0x0400) /!< Capture/Compare 3 Complementary output enable /
Sergunb	0:f1834a63f7c1	4407	#define TIM_CCER_CC3NP ((uint16_t)0x0800) /!< Capture/Compare 3 Complementary output Polarity /
Sergunb	0:f1834a63f7c1	4408	#define TIM_CCER_CC4E ((uint16_t)0x1000) /!< Capture/Compare 4 output enable /
Sergunb	0:f1834a63f7c1	4409	#define TIM_CCER_CC4P ((uint16_t)0x2000) /!< Capture/Compare 4 output Polarity /
Sergunb	0:f1834a63f7c1	4410	#define TIM_CCER_CC4NP ((uint16_t)0x8000) /!< Capture/Compare 4 Complementary output Polarity /
Sergunb	0:f1834a63f7c1	4411
Sergunb	0:f1834a63f7c1	4412	/***************** Bit definition for TIM_CNT register ******************/
Sergunb	0:f1834a63f7c1	4413	#define TIM_CNT_CNT ((uint16_t)0xFFFF) /!< Counter Value /
Sergunb	0:f1834a63f7c1	4414
Sergunb	0:f1834a63f7c1	4415	/***************** Bit definition for TIM_PSC register ******************/
Sergunb	0:f1834a63f7c1	4416	#define TIM_PSC_PSC ((uint16_t)0xFFFF) /!< Prescaler Value /
Sergunb	0:f1834a63f7c1	4417
Sergunb	0:f1834a63f7c1	4418	/***************** Bit definition for TIM_ARR register ******************/
Sergunb	0:f1834a63f7c1	4419	#define TIM_ARR_ARR ((uint16_t)0xFFFF) /!< actual auto-reload Value /
Sergunb	0:f1834a63f7c1	4420
Sergunb	0:f1834a63f7c1	4421	/***************** Bit definition for TIM_RCR register ******************/
Sergunb	0:f1834a63f7c1	4422	#define TIM_RCR_REP ((uint8_t)0xFF) /!< Repetition Counter Value /
Sergunb	0:f1834a63f7c1	4423
Sergunb	0:f1834a63f7c1	4424	/***************** Bit definition for TIM_CCR1 register *****************/
Sergunb	0:f1834a63f7c1	4425	#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /!< Capture/Compare 1 Value /
Sergunb	0:f1834a63f7c1	4426
Sergunb	0:f1834a63f7c1	4427	/***************** Bit definition for TIM_CCR2 register *****************/
Sergunb	0:f1834a63f7c1	4428	#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /!< Capture/Compare 2 Value /
Sergunb	0:f1834a63f7c1	4429
Sergunb	0:f1834a63f7c1	4430	/***************** Bit definition for TIM_CCR3 register *****************/
Sergunb	0:f1834a63f7c1	4431	#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /!< Capture/Compare 3 Value /
Sergunb	0:f1834a63f7c1	4432
Sergunb	0:f1834a63f7c1	4433	/***************** Bit definition for TIM_CCR4 register *****************/
Sergunb	0:f1834a63f7c1	4434	#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /!< Capture/Compare 4 Value /
Sergunb	0:f1834a63f7c1	4435
Sergunb	0:f1834a63f7c1	4436	/***************** Bit definition for TIM_BDTR register *****************/
Sergunb	0:f1834a63f7c1	4437	#define TIM_BDTR_DTG ((uint16_t)0x00FF) /!< DTG[0:7] bits (Dead-Time Generator set-up) /
Sergunb	0:f1834a63f7c1	4438	#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4439	#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4440	#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4441	#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4442	#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	4443	#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	4444	#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	4445	#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	4446
Sergunb	0:f1834a63f7c1	4447	#define TIM_BDTR_LOCK ((uint16_t)0x0300) /!< LOCK[1:0] bits (Lock Configuration) /
Sergunb	0:f1834a63f7c1	4448	#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4449	#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4450
Sergunb	0:f1834a63f7c1	4451	#define TIM_BDTR_OSSI ((uint16_t)0x0400) /!< Off-State Selection for Idle mode /
Sergunb	0:f1834a63f7c1	4452	#define TIM_BDTR_OSSR ((uint16_t)0x0800) /!< Off-State Selection for Run mode /
Sergunb	0:f1834a63f7c1	4453	#define TIM_BDTR_BKE ((uint16_t)0x1000) /!< Break enable /
Sergunb	0:f1834a63f7c1	4454	#define TIM_BDTR_BKP ((uint16_t)0x2000) /!< Break Polarity /
Sergunb	0:f1834a63f7c1	4455	#define TIM_BDTR_AOE ((uint16_t)0x4000) /!< Automatic Output enable /
Sergunb	0:f1834a63f7c1	4456	#define TIM_BDTR_MOE ((uint16_t)0x8000) /!< Main Output enable /
Sergunb	0:f1834a63f7c1	4457
Sergunb	0:f1834a63f7c1	4458	/***************** Bit definition for TIM_DCR register ******************/
Sergunb	0:f1834a63f7c1	4459	#define TIM_DCR_DBA ((uint16_t)0x001F) /!< DBA[4:0] bits (DMA Base Address) /
Sergunb	0:f1834a63f7c1	4460	#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4461	#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4462	#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4463	#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4464	#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	4465
Sergunb	0:f1834a63f7c1	4466	#define TIM_DCR_DBL ((uint16_t)0x1F00) /!< DBL[4:0] bits (DMA Burst Length) /
Sergunb	0:f1834a63f7c1	4467	#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4468	#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4469	#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4470	#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4471	#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	4472
Sergunb	0:f1834a63f7c1	4473	/***************** Bit definition for TIM_DMAR register *****************/
Sergunb	0:f1834a63f7c1	4474	#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /!< DMA register for burst accesses /
Sergunb	0:f1834a63f7c1	4475
Sergunb	0:f1834a63f7c1	4476	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4477	/* */
Sergunb	0:f1834a63f7c1	4478	/* Real-Time Clock */
Sergunb	0:f1834a63f7c1	4479	/* */
Sergunb	0:f1834a63f7c1	4480	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4481
Sergunb	0:f1834a63f7c1	4482	/***************** Bit definition for RTC_CRH register ******************/
Sergunb	0:f1834a63f7c1	4483	#define RTC_CRH_SECIE ((uint8_t)0x01) /!< Second Interrupt Enable /
Sergunb	0:f1834a63f7c1	4484	#define RTC_CRH_ALRIE ((uint8_t)0x02) /!< Alarm Interrupt Enable /
Sergunb	0:f1834a63f7c1	4485	#define RTC_CRH_OWIE ((uint8_t)0x04) /!< OverfloW Interrupt Enable /
Sergunb	0:f1834a63f7c1	4486
Sergunb	0:f1834a63f7c1	4487	/***************** Bit definition for RTC_CRL register ******************/
Sergunb	0:f1834a63f7c1	4488	#define RTC_CRL_SECF ((uint8_t)0x01) /!< Second Flag /
Sergunb	0:f1834a63f7c1	4489	#define RTC_CRL_ALRF ((uint8_t)0x02) /!< Alarm Flag /
Sergunb	0:f1834a63f7c1	4490	#define RTC_CRL_OWF ((uint8_t)0x04) /!< OverfloW Flag /
Sergunb	0:f1834a63f7c1	4491	#define RTC_CRL_RSF ((uint8_t)0x08) /!< Registers Synchronized Flag /
Sergunb	0:f1834a63f7c1	4492	#define RTC_CRL_CNF ((uint8_t)0x10) /!< Configuration Flag /
Sergunb	0:f1834a63f7c1	4493	#define RTC_CRL_RTOFF ((uint8_t)0x20) /!< RTC operation OFF /
Sergunb	0:f1834a63f7c1	4494
Sergunb	0:f1834a63f7c1	4495	/***************** Bit definition for RTC_PRLH register *****************/
Sergunb	0:f1834a63f7c1	4496	#define RTC_PRLH_PRL ((uint16_t)0x000F) /!< RTC Prescaler Reload Value High /
Sergunb	0:f1834a63f7c1	4497
Sergunb	0:f1834a63f7c1	4498	/***************** Bit definition for RTC_PRLL register *****************/
Sergunb	0:f1834a63f7c1	4499	#define RTC_PRLL_PRL ((uint16_t)0xFFFF) /!< RTC Prescaler Reload Value Low /
Sergunb	0:f1834a63f7c1	4500
Sergunb	0:f1834a63f7c1	4501	/***************** Bit definition for RTC_DIVH register *****************/
Sergunb	0:f1834a63f7c1	4502	#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /!< RTC Clock Divider High /
Sergunb	0:f1834a63f7c1	4503
Sergunb	0:f1834a63f7c1	4504	/***************** Bit definition for RTC_DIVL register *****************/
Sergunb	0:f1834a63f7c1	4505	#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /!< RTC Clock Divider Low /
Sergunb	0:f1834a63f7c1	4506
Sergunb	0:f1834a63f7c1	4507	/***************** Bit definition for RTC_CNTH register *****************/
Sergunb	0:f1834a63f7c1	4508	#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /!< RTC Counter High /
Sergunb	0:f1834a63f7c1	4509
Sergunb	0:f1834a63f7c1	4510	/***************** Bit definition for RTC_CNTL register *****************/
Sergunb	0:f1834a63f7c1	4511	#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /!< RTC Counter Low /
Sergunb	0:f1834a63f7c1	4512
Sergunb	0:f1834a63f7c1	4513	/***************** Bit definition for RTC_ALRH register *****************/
Sergunb	0:f1834a63f7c1	4514	#define RTC_ALRH_RTC_ALR ((uint16_t)0xFFFF) /!< RTC Alarm High /
Sergunb	0:f1834a63f7c1	4515
Sergunb	0:f1834a63f7c1	4516	/***************** Bit definition for RTC_ALRL register *****************/
Sergunb	0:f1834a63f7c1	4517	#define RTC_ALRL_RTC_ALR ((uint16_t)0xFFFF) /!< RTC Alarm Low /
Sergunb	0:f1834a63f7c1	4518
Sergunb	0:f1834a63f7c1	4519	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4520	/* */
Sergunb	0:f1834a63f7c1	4521	/* Independent WATCHDOG */
Sergunb	0:f1834a63f7c1	4522	/* */
Sergunb	0:f1834a63f7c1	4523	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4524
Sergunb	0:f1834a63f7c1	4525	/***************** Bit definition for IWDG_KR register ******************/
Sergunb	0:f1834a63f7c1	4526	#define IWDG_KR_KEY ((uint16_t)0xFFFF) /!< Key value (write only, read 0000h) /
Sergunb	0:f1834a63f7c1	4527
Sergunb	0:f1834a63f7c1	4528	/***************** Bit definition for IWDG_PR register ******************/
Sergunb	0:f1834a63f7c1	4529	#define IWDG_PR_PR ((uint8_t)0x07) /!< PR[2:0] (Prescaler divider) /
Sergunb	0:f1834a63f7c1	4530	#define IWDG_PR_PR_0 ((uint8_t)0x01) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4531	#define IWDG_PR_PR_1 ((uint8_t)0x02) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4532	#define IWDG_PR_PR_2 ((uint8_t)0x04) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4533
Sergunb	0:f1834a63f7c1	4534	/***************** Bit definition for IWDG_RLR register *****************/
Sergunb	0:f1834a63f7c1	4535	#define IWDG_RLR_RL ((uint16_t)0x0FFF) /!< Watchdog counter reload value /
Sergunb	0:f1834a63f7c1	4536
Sergunb	0:f1834a63f7c1	4537	/***************** Bit definition for IWDG_SR register ******************/
Sergunb	0:f1834a63f7c1	4538	#define IWDG_SR_PVU ((uint8_t)0x01) /!< Watchdog prescaler value update /
Sergunb	0:f1834a63f7c1	4539	#define IWDG_SR_RVU ((uint8_t)0x02) /!< Watchdog counter reload value update /
Sergunb	0:f1834a63f7c1	4540
Sergunb	0:f1834a63f7c1	4541	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4542	/* */
Sergunb	0:f1834a63f7c1	4543	/* Window WATCHDOG */
Sergunb	0:f1834a63f7c1	4544	/* */
Sergunb	0:f1834a63f7c1	4545	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4546
Sergunb	0:f1834a63f7c1	4547	/***************** Bit definition for WWDG_CR register ******************/
Sergunb	0:f1834a63f7c1	4548	#define WWDG_CR_T ((uint8_t)0x7F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
Sergunb	0:f1834a63f7c1	4549	#define WWDG_CR_T0 ((uint8_t)0x01) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4550	#define WWDG_CR_T1 ((uint8_t)0x02) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4551	#define WWDG_CR_T2 ((uint8_t)0x04) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4552	#define WWDG_CR_T3 ((uint8_t)0x08) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4553	#define WWDG_CR_T4 ((uint8_t)0x10) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	4554	#define WWDG_CR_T5 ((uint8_t)0x20) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	4555	#define WWDG_CR_T6 ((uint8_t)0x40) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	4556
Sergunb	0:f1834a63f7c1	4557	#define WWDG_CR_WDGA ((uint8_t)0x80) /!< Activation bit /
Sergunb	0:f1834a63f7c1	4558
Sergunb	0:f1834a63f7c1	4559	/***************** Bit definition for WWDG_CFR register *****************/
Sergunb	0:f1834a63f7c1	4560	#define WWDG_CFR_W ((uint16_t)0x007F) /!< W[6:0] bits (7-bit window value) /
Sergunb	0:f1834a63f7c1	4561	#define WWDG_CFR_W0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4562	#define WWDG_CFR_W1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4563	#define WWDG_CFR_W2 ((uint16_t)0x0004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4564	#define WWDG_CFR_W3 ((uint16_t)0x0008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4565	#define WWDG_CFR_W4 ((uint16_t)0x0010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	4566	#define WWDG_CFR_W5 ((uint16_t)0x0020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	4567	#define WWDG_CFR_W6 ((uint16_t)0x0040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	4568
Sergunb	0:f1834a63f7c1	4569	#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /!< WDGTB[1:0] bits (Timer Base) /
Sergunb	0:f1834a63f7c1	4570	#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4571	#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4572
Sergunb	0:f1834a63f7c1	4573	#define WWDG_CFR_EWI ((uint16_t)0x0200) /!< Early Wakeup Interrupt /
Sergunb	0:f1834a63f7c1	4574
Sergunb	0:f1834a63f7c1	4575	/***************** Bit definition for WWDG_SR register ******************/
Sergunb	0:f1834a63f7c1	4576	#define WWDG_SR_EWIF ((uint8_t)0x01) /!< Early Wakeup Interrupt Flag /
Sergunb	0:f1834a63f7c1	4577
Sergunb	0:f1834a63f7c1	4578	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4579	/* */
Sergunb	0:f1834a63f7c1	4580	/* Flexible Static Memory Controller */
Sergunb	0:f1834a63f7c1	4581	/* */
Sergunb	0:f1834a63f7c1	4582	/******************************************************************************/
Sergunb	0:f1834a63f7c1	4583
Sergunb	0:f1834a63f7c1	4584	/**************** Bit definition for FSMC_BCR1 register *****************/
Sergunb	0:f1834a63f7c1	4585	#define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
Sergunb	0:f1834a63f7c1	4586	#define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
Sergunb	0:f1834a63f7c1	4587
Sergunb	0:f1834a63f7c1	4588	#define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
Sergunb	0:f1834a63f7c1	4589	#define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4590	#define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4591
Sergunb	0:f1834a63f7c1	4592	#define FSMC_BCR1_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
Sergunb	0:f1834a63f7c1	4593	#define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4594	#define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4595
Sergunb	0:f1834a63f7c1	4596	#define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
Sergunb	0:f1834a63f7c1	4597	#define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
Sergunb	0:f1834a63f7c1	4598	#define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit /
Sergunb	0:f1834a63f7c1	4599	#define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
Sergunb	0:f1834a63f7c1	4600	#define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
Sergunb	0:f1834a63f7c1	4601	#define FSMC_BCR1_WREN ((uint32_t)0x00001000) /!< Write enable bit /
Sergunb	0:f1834a63f7c1	4602	#define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
Sergunb	0:f1834a63f7c1	4603	#define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
Sergunb	0:f1834a63f7c1	4604	#define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
Sergunb	0:f1834a63f7c1	4605	#define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
Sergunb	0:f1834a63f7c1	4606
Sergunb	0:f1834a63f7c1	4607	/**************** Bit definition for FSMC_BCR2 register *****************/
Sergunb	0:f1834a63f7c1	4608	#define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
Sergunb	0:f1834a63f7c1	4609	#define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
Sergunb	0:f1834a63f7c1	4610
Sergunb	0:f1834a63f7c1	4611	#define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
Sergunb	0:f1834a63f7c1	4612	#define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4613	#define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4614
Sergunb	0:f1834a63f7c1	4615	#define FSMC_BCR2_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
Sergunb	0:f1834a63f7c1	4616	#define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4617	#define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4618
Sergunb	0:f1834a63f7c1	4619	#define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
Sergunb	0:f1834a63f7c1	4620	#define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
Sergunb	0:f1834a63f7c1	4621	#define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit /
Sergunb	0:f1834a63f7c1	4622	#define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
Sergunb	0:f1834a63f7c1	4623	#define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
Sergunb	0:f1834a63f7c1	4624	#define FSMC_BCR2_WREN ((uint32_t)0x00001000) /!< Write enable bit /
Sergunb	0:f1834a63f7c1	4625	#define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
Sergunb	0:f1834a63f7c1	4626	#define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
Sergunb	0:f1834a63f7c1	4627	#define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
Sergunb	0:f1834a63f7c1	4628	#define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
Sergunb	0:f1834a63f7c1	4629
Sergunb	0:f1834a63f7c1	4630	/**************** Bit definition for FSMC_BCR3 register *****************/
Sergunb	0:f1834a63f7c1	4631	#define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
Sergunb	0:f1834a63f7c1	4632	#define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
Sergunb	0:f1834a63f7c1	4633
Sergunb	0:f1834a63f7c1	4634	#define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
Sergunb	0:f1834a63f7c1	4635	#define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4636	#define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4637
Sergunb	0:f1834a63f7c1	4638	#define FSMC_BCR3_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
Sergunb	0:f1834a63f7c1	4639	#define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4640	#define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4641
Sergunb	0:f1834a63f7c1	4642	#define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
Sergunb	0:f1834a63f7c1	4643	#define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
Sergunb	0:f1834a63f7c1	4644	#define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit. /
Sergunb	0:f1834a63f7c1	4645	#define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
Sergunb	0:f1834a63f7c1	4646	#define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
Sergunb	0:f1834a63f7c1	4647	#define FSMC_BCR3_WREN ((uint32_t)0x00001000) /!< Write enable bit /
Sergunb	0:f1834a63f7c1	4648	#define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
Sergunb	0:f1834a63f7c1	4649	#define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
Sergunb	0:f1834a63f7c1	4650	#define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
Sergunb	0:f1834a63f7c1	4651	#define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
Sergunb	0:f1834a63f7c1	4652
Sergunb	0:f1834a63f7c1	4653	/**************** Bit definition for FSMC_BCR4 register *****************/
Sergunb	0:f1834a63f7c1	4654	#define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /!< Memory bank enable bit /
Sergunb	0:f1834a63f7c1	4655	#define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /!< Address/data multiplexing enable bit /
Sergunb	0:f1834a63f7c1	4656
Sergunb	0:f1834a63f7c1	4657	#define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /!< MTYP[1:0] bits (Memory type) /
Sergunb	0:f1834a63f7c1	4658	#define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4659	#define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4660
Sergunb	0:f1834a63f7c1	4661	#define FSMC_BCR4_MWID ((uint32_t)0x00000030) /!< MWID[1:0] bits (Memory data bus width) /
Sergunb	0:f1834a63f7c1	4662	#define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4663	#define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4664
Sergunb	0:f1834a63f7c1	4665	#define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /!< Flash access enable /
Sergunb	0:f1834a63f7c1	4666	#define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /!< Burst enable bit /
Sergunb	0:f1834a63f7c1	4667	#define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /!< Wait signal polarity bit /
Sergunb	0:f1834a63f7c1	4668	#define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /!< Wrapped burst mode support /
Sergunb	0:f1834a63f7c1	4669	#define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /!< Wait timing configuration /
Sergunb	0:f1834a63f7c1	4670	#define FSMC_BCR4_WREN ((uint32_t)0x00001000) /!< Write enable bit /
Sergunb	0:f1834a63f7c1	4671	#define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /!< Wait enable bit /
Sergunb	0:f1834a63f7c1	4672	#define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /!< Extended mode enable /
Sergunb	0:f1834a63f7c1	4673	#define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /!< Asynchronous wait /
Sergunb	0:f1834a63f7c1	4674	#define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /!< Write burst enable /
Sergunb	0:f1834a63f7c1	4675
Sergunb	0:f1834a63f7c1	4676	/**************** Bit definition for FSMC_BTR1 register ****************/
Sergunb	0:f1834a63f7c1	4677	#define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
Sergunb	0:f1834a63f7c1	4678	#define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4679	#define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4680	#define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4681	#define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4682
Sergunb	0:f1834a63f7c1	4683	#define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
Sergunb	0:f1834a63f7c1	4684	#define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4685	#define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4686	#define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4687	#define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4688
Sergunb	0:f1834a63f7c1	4689	#define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
Sergunb	0:f1834a63f7c1	4690	#define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4691	#define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4692	#define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4693	#define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4694
Sergunb	0:f1834a63f7c1	4695	#define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
Sergunb	0:f1834a63f7c1	4696	#define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4697	#define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4698	#define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4699	#define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4700
Sergunb	0:f1834a63f7c1	4701	#define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
Sergunb	0:f1834a63f7c1	4702	#define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4703	#define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4704	#define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4705	#define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4706
Sergunb	0:f1834a63f7c1	4707	#define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
Sergunb	0:f1834a63f7c1	4708	#define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4709	#define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4710	#define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4711	#define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4712
Sergunb	0:f1834a63f7c1	4713	#define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
Sergunb	0:f1834a63f7c1	4714	#define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4715	#define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4716
Sergunb	0:f1834a63f7c1	4717	/**************** Bit definition for FSMC_BTR2 register *****************/
Sergunb	0:f1834a63f7c1	4718	#define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
Sergunb	0:f1834a63f7c1	4719	#define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4720	#define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4721	#define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4722	#define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4723
Sergunb	0:f1834a63f7c1	4724	#define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
Sergunb	0:f1834a63f7c1	4725	#define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4726	#define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4727	#define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4728	#define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4729
Sergunb	0:f1834a63f7c1	4730	#define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
Sergunb	0:f1834a63f7c1	4731	#define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4732	#define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4733	#define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4734	#define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4735
Sergunb	0:f1834a63f7c1	4736	#define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
Sergunb	0:f1834a63f7c1	4737	#define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4738	#define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4739	#define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4740	#define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4741
Sergunb	0:f1834a63f7c1	4742	#define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
Sergunb	0:f1834a63f7c1	4743	#define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4744	#define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4745	#define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4746	#define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4747
Sergunb	0:f1834a63f7c1	4748	#define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
Sergunb	0:f1834a63f7c1	4749	#define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4750	#define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4751	#define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4752	#define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4753
Sergunb	0:f1834a63f7c1	4754	#define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
Sergunb	0:f1834a63f7c1	4755	#define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4756	#define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4757
Sergunb	0:f1834a63f7c1	4758	/***************** Bit definition for FSMC_BTR3 register *****************/
Sergunb	0:f1834a63f7c1	4759	#define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
Sergunb	0:f1834a63f7c1	4760	#define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4761	#define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4762	#define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4763	#define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4764
Sergunb	0:f1834a63f7c1	4765	#define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
Sergunb	0:f1834a63f7c1	4766	#define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4767	#define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4768	#define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4769	#define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4770
Sergunb	0:f1834a63f7c1	4771	#define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
Sergunb	0:f1834a63f7c1	4772	#define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4773	#define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4774	#define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4775	#define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4776
Sergunb	0:f1834a63f7c1	4777	#define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
Sergunb	0:f1834a63f7c1	4778	#define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4779	#define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4780	#define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4781	#define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4782
Sergunb	0:f1834a63f7c1	4783	#define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
Sergunb	0:f1834a63f7c1	4784	#define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4785	#define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4786	#define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4787	#define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4788
Sergunb	0:f1834a63f7c1	4789	#define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
Sergunb	0:f1834a63f7c1	4790	#define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4791	#define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4792	#define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4793	#define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4794
Sergunb	0:f1834a63f7c1	4795	#define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
Sergunb	0:f1834a63f7c1	4796	#define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4797	#define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4798
Sergunb	0:f1834a63f7c1	4799	/**************** Bit definition for FSMC_BTR4 register *****************/
Sergunb	0:f1834a63f7c1	4800	#define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
Sergunb	0:f1834a63f7c1	4801	#define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4802	#define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4803	#define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4804	#define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4805
Sergunb	0:f1834a63f7c1	4806	#define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
Sergunb	0:f1834a63f7c1	4807	#define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4808	#define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4809	#define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4810	#define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4811
Sergunb	0:f1834a63f7c1	4812	#define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
Sergunb	0:f1834a63f7c1	4813	#define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4814	#define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4815	#define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4816	#define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4817
Sergunb	0:f1834a63f7c1	4818	#define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /!< BUSTURN[3:0] bits (Bus turnaround phase duration) /
Sergunb	0:f1834a63f7c1	4819	#define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4820	#define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4821	#define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4822	#define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4823
Sergunb	0:f1834a63f7c1	4824	#define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
Sergunb	0:f1834a63f7c1	4825	#define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4826	#define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4827	#define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4828	#define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4829
Sergunb	0:f1834a63f7c1	4830	#define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
Sergunb	0:f1834a63f7c1	4831	#define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4832	#define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4833	#define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4834	#define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4835
Sergunb	0:f1834a63f7c1	4836	#define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
Sergunb	0:f1834a63f7c1	4837	#define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4838	#define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4839
Sergunb	0:f1834a63f7c1	4840	/**************** Bit definition for FSMC_BWTR1 register ****************/
Sergunb	0:f1834a63f7c1	4841	#define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
Sergunb	0:f1834a63f7c1	4842	#define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4843	#define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4844	#define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4845	#define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4846
Sergunb	0:f1834a63f7c1	4847	#define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
Sergunb	0:f1834a63f7c1	4848	#define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4849	#define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4850	#define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4851	#define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4852
Sergunb	0:f1834a63f7c1	4853	#define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
Sergunb	0:f1834a63f7c1	4854	#define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4855	#define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4856	#define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4857	#define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4858
Sergunb	0:f1834a63f7c1	4859	#define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
Sergunb	0:f1834a63f7c1	4860	#define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4861	#define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4862	#define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4863	#define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4864
Sergunb	0:f1834a63f7c1	4865	#define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
Sergunb	0:f1834a63f7c1	4866	#define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4867	#define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4868	#define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4869	#define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4870
Sergunb	0:f1834a63f7c1	4871	#define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
Sergunb	0:f1834a63f7c1	4872	#define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4873	#define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4874
Sergunb	0:f1834a63f7c1	4875	/**************** Bit definition for FSMC_BWTR2 register ****************/
Sergunb	0:f1834a63f7c1	4876	#define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
Sergunb	0:f1834a63f7c1	4877	#define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4878	#define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4879	#define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4880	#define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4881
Sergunb	0:f1834a63f7c1	4882	#define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
Sergunb	0:f1834a63f7c1	4883	#define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4884	#define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4885	#define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4886	#define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4887
Sergunb	0:f1834a63f7c1	4888	#define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
Sergunb	0:f1834a63f7c1	4889	#define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4890	#define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4891	#define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4892	#define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4893
Sergunb	0:f1834a63f7c1	4894	#define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
Sergunb	0:f1834a63f7c1	4895	#define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4896	#define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1/
Sergunb	0:f1834a63f7c1	4897	#define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4898	#define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4899
Sergunb	0:f1834a63f7c1	4900	#define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
Sergunb	0:f1834a63f7c1	4901	#define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4902	#define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4903	#define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4904	#define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4905
Sergunb	0:f1834a63f7c1	4906	#define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
Sergunb	0:f1834a63f7c1	4907	#define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4908	#define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4909
Sergunb	0:f1834a63f7c1	4910	/**************** Bit definition for FSMC_BWTR3 register ****************/
Sergunb	0:f1834a63f7c1	4911	#define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
Sergunb	0:f1834a63f7c1	4912	#define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4913	#define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4914	#define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4915	#define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4916
Sergunb	0:f1834a63f7c1	4917	#define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
Sergunb	0:f1834a63f7c1	4918	#define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4919	#define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4920	#define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4921	#define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4922
Sergunb	0:f1834a63f7c1	4923	#define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
Sergunb	0:f1834a63f7c1	4924	#define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4925	#define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4926	#define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4927	#define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4928
Sergunb	0:f1834a63f7c1	4929	#define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
Sergunb	0:f1834a63f7c1	4930	#define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4931	#define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4932	#define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4933	#define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4934
Sergunb	0:f1834a63f7c1	4935	#define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
Sergunb	0:f1834a63f7c1	4936	#define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4937	#define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4938	#define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4939	#define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4940
Sergunb	0:f1834a63f7c1	4941	#define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
Sergunb	0:f1834a63f7c1	4942	#define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4943	#define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4944
Sergunb	0:f1834a63f7c1	4945	/**************** Bit definition for FSMC_BWTR4 register ****************/
Sergunb	0:f1834a63f7c1	4946	#define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /!< ADDSET[3:0] bits (Address setup phase duration) /
Sergunb	0:f1834a63f7c1	4947	#define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4948	#define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4949	#define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4950	#define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4951
Sergunb	0:f1834a63f7c1	4952	#define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /!< ADDHLD[3:0] bits (Address-hold phase duration) /
Sergunb	0:f1834a63f7c1	4953	#define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4954	#define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4955	#define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4956	#define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4957
Sergunb	0:f1834a63f7c1	4958	#define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /!< DATAST [3:0] bits (Data-phase duration) /
Sergunb	0:f1834a63f7c1	4959	#define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4960	#define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4961	#define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4962	#define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4963
Sergunb	0:f1834a63f7c1	4964	#define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /!< CLKDIV[3:0] bits (Clock divide ratio) /
Sergunb	0:f1834a63f7c1	4965	#define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4966	#define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4967	#define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4968	#define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4969
Sergunb	0:f1834a63f7c1	4970	#define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /!< DATLA[3:0] bits (Data latency) /
Sergunb	0:f1834a63f7c1	4971	#define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4972	#define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4973	#define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4974	#define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4975
Sergunb	0:f1834a63f7c1	4976	#define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /!< ACCMOD[1:0] bits (Access mode) /
Sergunb	0:f1834a63f7c1	4977	#define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4978	#define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4979
Sergunb	0:f1834a63f7c1	4980	/**************** Bit definition for FSMC_PCR2 register *****************/
Sergunb	0:f1834a63f7c1	4981	#define FSMC_PCR2_PWAITEN ((uint32_t)0x00000002) /!< Wait feature enable bit /
Sergunb	0:f1834a63f7c1	4982	#define FSMC_PCR2_PBKEN ((uint32_t)0x00000004) /!< PC Card/NAND Flash memory bank enable bit /
Sergunb	0:f1834a63f7c1	4983	#define FSMC_PCR2_PTYP ((uint32_t)0x00000008) /!< Memory type /
Sergunb	0:f1834a63f7c1	4984
Sergunb	0:f1834a63f7c1	4985	#define FSMC_PCR2_PWID ((uint32_t)0x00000030) /!< PWID[1:0] bits (NAND Flash databus width) /
Sergunb	0:f1834a63f7c1	4986	#define FSMC_PCR2_PWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4987	#define FSMC_PCR2_PWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4988
Sergunb	0:f1834a63f7c1	4989	#define FSMC_PCR2_ECCEN ((uint32_t)0x00000040) /!< ECC computation logic enable bit /
Sergunb	0:f1834a63f7c1	4990
Sergunb	0:f1834a63f7c1	4991	#define FSMC_PCR2_TCLR ((uint32_t)0x00001E00) /!< TCLR[3:0] bits (CLE to RE delay) /
Sergunb	0:f1834a63f7c1	4992	#define FSMC_PCR2_TCLR_0 ((uint32_t)0x00000200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4993	#define FSMC_PCR2_TCLR_1 ((uint32_t)0x00000400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	4994	#define FSMC_PCR2_TCLR_2 ((uint32_t)0x00000800) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	4995	#define FSMC_PCR2_TCLR_3 ((uint32_t)0x00001000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	4996
Sergunb	0:f1834a63f7c1	4997	#define FSMC_PCR2_TAR ((uint32_t)0x0001E000) /!< TAR[3:0] bits (ALE to RE delay) /
Sergunb	0:f1834a63f7c1	4998	#define FSMC_PCR2_TAR_0 ((uint32_t)0x00002000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	4999	#define FSMC_PCR2_TAR_1 ((uint32_t)0x00004000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5000	#define FSMC_PCR2_TAR_2 ((uint32_t)0x00008000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5001	#define FSMC_PCR2_TAR_3 ((uint32_t)0x00010000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5002
Sergunb	0:f1834a63f7c1	5003	#define FSMC_PCR2_ECCPS ((uint32_t)0x000E0000) /!< ECCPS[1:0] bits (ECC page size) /
Sergunb	0:f1834a63f7c1	5004	#define FSMC_PCR2_ECCPS_0 ((uint32_t)0x00020000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5005	#define FSMC_PCR2_ECCPS_1 ((uint32_t)0x00040000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5006	#define FSMC_PCR2_ECCPS_2 ((uint32_t)0x00080000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5007
Sergunb	0:f1834a63f7c1	5008	/**************** Bit definition for FSMC_PCR3 register *****************/
Sergunb	0:f1834a63f7c1	5009	#define FSMC_PCR3_PWAITEN ((uint32_t)0x00000002) /!< Wait feature enable bit /
Sergunb	0:f1834a63f7c1	5010	#define FSMC_PCR3_PBKEN ((uint32_t)0x00000004) /!< PC Card/NAND Flash memory bank enable bit /
Sergunb	0:f1834a63f7c1	5011	#define FSMC_PCR3_PTYP ((uint32_t)0x00000008) /!< Memory type /
Sergunb	0:f1834a63f7c1	5012
Sergunb	0:f1834a63f7c1	5013	#define FSMC_PCR3_PWID ((uint32_t)0x00000030) /!< PWID[1:0] bits (NAND Flash databus width) /
Sergunb	0:f1834a63f7c1	5014	#define FSMC_PCR3_PWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5015	#define FSMC_PCR3_PWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5016
Sergunb	0:f1834a63f7c1	5017	#define FSMC_PCR3_ECCEN ((uint32_t)0x00000040) /!< ECC computation logic enable bit /
Sergunb	0:f1834a63f7c1	5018
Sergunb	0:f1834a63f7c1	5019	#define FSMC_PCR3_TCLR ((uint32_t)0x00001E00) /!< TCLR[3:0] bits (CLE to RE delay) /
Sergunb	0:f1834a63f7c1	5020	#define FSMC_PCR3_TCLR_0 ((uint32_t)0x00000200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5021	#define FSMC_PCR3_TCLR_1 ((uint32_t)0x00000400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5022	#define FSMC_PCR3_TCLR_2 ((uint32_t)0x00000800) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5023	#define FSMC_PCR3_TCLR_3 ((uint32_t)0x00001000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5024
Sergunb	0:f1834a63f7c1	5025	#define FSMC_PCR3_TAR ((uint32_t)0x0001E000) /!< TAR[3:0] bits (ALE to RE delay) /
Sergunb	0:f1834a63f7c1	5026	#define FSMC_PCR3_TAR_0 ((uint32_t)0x00002000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5027	#define FSMC_PCR3_TAR_1 ((uint32_t)0x00004000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5028	#define FSMC_PCR3_TAR_2 ((uint32_t)0x00008000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5029	#define FSMC_PCR3_TAR_3 ((uint32_t)0x00010000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5030
Sergunb	0:f1834a63f7c1	5031	#define FSMC_PCR3_ECCPS ((uint32_t)0x000E0000) /!< ECCPS[2:0] bits (ECC page size) /
Sergunb	0:f1834a63f7c1	5032	#define FSMC_PCR3_ECCPS_0 ((uint32_t)0x00020000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5033	#define FSMC_PCR3_ECCPS_1 ((uint32_t)0x00040000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5034	#define FSMC_PCR3_ECCPS_2 ((uint32_t)0x00080000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5035
Sergunb	0:f1834a63f7c1	5036	/**************** Bit definition for FSMC_PCR4 register *****************/
Sergunb	0:f1834a63f7c1	5037	#define FSMC_PCR4_PWAITEN ((uint32_t)0x00000002) /!< Wait feature enable bit /
Sergunb	0:f1834a63f7c1	5038	#define FSMC_PCR4_PBKEN ((uint32_t)0x00000004) /!< PC Card/NAND Flash memory bank enable bit /
Sergunb	0:f1834a63f7c1	5039	#define FSMC_PCR4_PTYP ((uint32_t)0x00000008) /!< Memory type /
Sergunb	0:f1834a63f7c1	5040
Sergunb	0:f1834a63f7c1	5041	#define FSMC_PCR4_PWID ((uint32_t)0x00000030) /!< PWID[1:0] bits (NAND Flash databus width) /
Sergunb	0:f1834a63f7c1	5042	#define FSMC_PCR4_PWID_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5043	#define FSMC_PCR4_PWID_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5044
Sergunb	0:f1834a63f7c1	5045	#define FSMC_PCR4_ECCEN ((uint32_t)0x00000040) /!< ECC computation logic enable bit /
Sergunb	0:f1834a63f7c1	5046
Sergunb	0:f1834a63f7c1	5047	#define FSMC_PCR4_TCLR ((uint32_t)0x00001E00) /!< TCLR[3:0] bits (CLE to RE delay) /
Sergunb	0:f1834a63f7c1	5048	#define FSMC_PCR4_TCLR_0 ((uint32_t)0x00000200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5049	#define FSMC_PCR4_TCLR_1 ((uint32_t)0x00000400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5050	#define FSMC_PCR4_TCLR_2 ((uint32_t)0x00000800) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5051	#define FSMC_PCR4_TCLR_3 ((uint32_t)0x00001000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5052
Sergunb	0:f1834a63f7c1	5053	#define FSMC_PCR4_TAR ((uint32_t)0x0001E000) /!< TAR[3:0] bits (ALE to RE delay) /
Sergunb	0:f1834a63f7c1	5054	#define FSMC_PCR4_TAR_0 ((uint32_t)0x00002000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5055	#define FSMC_PCR4_TAR_1 ((uint32_t)0x00004000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5056	#define FSMC_PCR4_TAR_2 ((uint32_t)0x00008000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5057	#define FSMC_PCR4_TAR_3 ((uint32_t)0x00010000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5058
Sergunb	0:f1834a63f7c1	5059	#define FSMC_PCR4_ECCPS ((uint32_t)0x000E0000) /!< ECCPS[2:0] bits (ECC page size) /
Sergunb	0:f1834a63f7c1	5060	#define FSMC_PCR4_ECCPS_0 ((uint32_t)0x00020000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5061	#define FSMC_PCR4_ECCPS_1 ((uint32_t)0x00040000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5062	#define FSMC_PCR4_ECCPS_2 ((uint32_t)0x00080000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5063
Sergunb	0:f1834a63f7c1	5064	/***************** Bit definition for FSMC_SR2 register *****************/
Sergunb	0:f1834a63f7c1	5065	#define FSMC_SR2_IRS ((uint8_t)0x01) /!< Interrupt Rising Edge status /
Sergunb	0:f1834a63f7c1	5066	#define FSMC_SR2_ILS ((uint8_t)0x02) /!< Interrupt Level status /
Sergunb	0:f1834a63f7c1	5067	#define FSMC_SR2_IFS ((uint8_t)0x04) /!< Interrupt Falling Edge status /
Sergunb	0:f1834a63f7c1	5068	#define FSMC_SR2_IREN ((uint8_t)0x08) /!< Interrupt Rising Edge detection Enable bit /
Sergunb	0:f1834a63f7c1	5069	#define FSMC_SR2_ILEN ((uint8_t)0x10) /!< Interrupt Level detection Enable bit /
Sergunb	0:f1834a63f7c1	5070	#define FSMC_SR2_IFEN ((uint8_t)0x20) /!< Interrupt Falling Edge detection Enable bit /
Sergunb	0:f1834a63f7c1	5071	#define FSMC_SR2_FEMPT ((uint8_t)0x40) /!< FIFO empty /
Sergunb	0:f1834a63f7c1	5072
Sergunb	0:f1834a63f7c1	5073	/***************** Bit definition for FSMC_SR3 register *****************/
Sergunb	0:f1834a63f7c1	5074	#define FSMC_SR3_IRS ((uint8_t)0x01) /!< Interrupt Rising Edge status /
Sergunb	0:f1834a63f7c1	5075	#define FSMC_SR3_ILS ((uint8_t)0x02) /!< Interrupt Level status /
Sergunb	0:f1834a63f7c1	5076	#define FSMC_SR3_IFS ((uint8_t)0x04) /!< Interrupt Falling Edge status /
Sergunb	0:f1834a63f7c1	5077	#define FSMC_SR3_IREN ((uint8_t)0x08) /!< Interrupt Rising Edge detection Enable bit /
Sergunb	0:f1834a63f7c1	5078	#define FSMC_SR3_ILEN ((uint8_t)0x10) /!< Interrupt Level detection Enable bit /
Sergunb	0:f1834a63f7c1	5079	#define FSMC_SR3_IFEN ((uint8_t)0x20) /!< Interrupt Falling Edge detection Enable bit /
Sergunb	0:f1834a63f7c1	5080	#define FSMC_SR3_FEMPT ((uint8_t)0x40) /!< FIFO empty /
Sergunb	0:f1834a63f7c1	5081
Sergunb	0:f1834a63f7c1	5082	/***************** Bit definition for FSMC_SR4 register *****************/
Sergunb	0:f1834a63f7c1	5083	#define FSMC_SR4_IRS ((uint8_t)0x01) /!< Interrupt Rising Edge status /
Sergunb	0:f1834a63f7c1	5084	#define FSMC_SR4_ILS ((uint8_t)0x02) /!< Interrupt Level status /
Sergunb	0:f1834a63f7c1	5085	#define FSMC_SR4_IFS ((uint8_t)0x04) /!< Interrupt Falling Edge status /
Sergunb	0:f1834a63f7c1	5086	#define FSMC_SR4_IREN ((uint8_t)0x08) /!< Interrupt Rising Edge detection Enable bit /
Sergunb	0:f1834a63f7c1	5087	#define FSMC_SR4_ILEN ((uint8_t)0x10) /!< Interrupt Level detection Enable bit /
Sergunb	0:f1834a63f7c1	5088	#define FSMC_SR4_IFEN ((uint8_t)0x20) /!< Interrupt Falling Edge detection Enable bit /
Sergunb	0:f1834a63f7c1	5089	#define FSMC_SR4_FEMPT ((uint8_t)0x40) /!< FIFO empty /
Sergunb	0:f1834a63f7c1	5090
Sergunb	0:f1834a63f7c1	5091	/**************** Bit definition for FSMC_PMEM2 register ****************/
Sergunb	0:f1834a63f7c1	5092	#define FSMC_PMEM2_MEMSET2 ((uint32_t)0x000000FF) /!< MEMSET2[7:0] bits (Common memory 2 setup time) /
Sergunb	0:f1834a63f7c1	5093	#define FSMC_PMEM2_MEMSET2_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5094	#define FSMC_PMEM2_MEMSET2_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5095	#define FSMC_PMEM2_MEMSET2_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5096	#define FSMC_PMEM2_MEMSET2_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5097	#define FSMC_PMEM2_MEMSET2_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5098	#define FSMC_PMEM2_MEMSET2_5 ((uint32_t)0x00000020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5099	#define FSMC_PMEM2_MEMSET2_6 ((uint32_t)0x00000040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5100	#define FSMC_PMEM2_MEMSET2_7 ((uint32_t)0x00000080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5101
Sergunb	0:f1834a63f7c1	5102	#define FSMC_PMEM2_MEMWAIT2 ((uint32_t)0x0000FF00) /!< MEMWAIT2[7:0] bits (Common memory 2 wait time) /
Sergunb	0:f1834a63f7c1	5103	#define FSMC_PMEM2_MEMWAIT2_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5104	#define FSMC_PMEM2_MEMWAIT2_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5105	#define FSMC_PMEM2_MEMWAIT2_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5106	#define FSMC_PMEM2_MEMWAIT2_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5107	#define FSMC_PMEM2_MEMWAIT2_4 ((uint32_t)0x00001000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5108	#define FSMC_PMEM2_MEMWAIT2_5 ((uint32_t)0x00002000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5109	#define FSMC_PMEM2_MEMWAIT2_6 ((uint32_t)0x00004000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5110	#define FSMC_PMEM2_MEMWAIT2_7 ((uint32_t)0x00008000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5111
Sergunb	0:f1834a63f7c1	5112	#define FSMC_PMEM2_MEMHOLD2 ((uint32_t)0x00FF0000) /!< MEMHOLD2[7:0] bits (Common memory 2 hold time) /
Sergunb	0:f1834a63f7c1	5113	#define FSMC_PMEM2_MEMHOLD2_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5114	#define FSMC_PMEM2_MEMHOLD2_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5115	#define FSMC_PMEM2_MEMHOLD2_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5116	#define FSMC_PMEM2_MEMHOLD2_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5117	#define FSMC_PMEM2_MEMHOLD2_4 ((uint32_t)0x00100000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5118	#define FSMC_PMEM2_MEMHOLD2_5 ((uint32_t)0x00200000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5119	#define FSMC_PMEM2_MEMHOLD2_6 ((uint32_t)0x00400000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5120	#define FSMC_PMEM2_MEMHOLD2_7 ((uint32_t)0x00800000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5121
Sergunb	0:f1834a63f7c1	5122	#define FSMC_PMEM2_MEMHIZ2 ((uint32_t)0xFF000000) /!< MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) /
Sergunb	0:f1834a63f7c1	5123	#define FSMC_PMEM2_MEMHIZ2_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5124	#define FSMC_PMEM2_MEMHIZ2_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5125	#define FSMC_PMEM2_MEMHIZ2_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5126	#define FSMC_PMEM2_MEMHIZ2_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5127	#define FSMC_PMEM2_MEMHIZ2_4 ((uint32_t)0x10000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5128	#define FSMC_PMEM2_MEMHIZ2_5 ((uint32_t)0x20000000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5129	#define FSMC_PMEM2_MEMHIZ2_6 ((uint32_t)0x40000000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5130	#define FSMC_PMEM2_MEMHIZ2_7 ((uint32_t)0x80000000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5131
Sergunb	0:f1834a63f7c1	5132	/**************** Bit definition for FSMC_PMEM3 register ****************/
Sergunb	0:f1834a63f7c1	5133	#define FSMC_PMEM3_MEMSET3 ((uint32_t)0x000000FF) /!< MEMSET3[7:0] bits (Common memory 3 setup time) /
Sergunb	0:f1834a63f7c1	5134	#define FSMC_PMEM3_MEMSET3_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5135	#define FSMC_PMEM3_MEMSET3_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5136	#define FSMC_PMEM3_MEMSET3_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5137	#define FSMC_PMEM3_MEMSET3_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5138	#define FSMC_PMEM3_MEMSET3_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5139	#define FSMC_PMEM3_MEMSET3_5 ((uint32_t)0x00000020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5140	#define FSMC_PMEM3_MEMSET3_6 ((uint32_t)0x00000040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5141	#define FSMC_PMEM3_MEMSET3_7 ((uint32_t)0x00000080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5142
Sergunb	0:f1834a63f7c1	5143	#define FSMC_PMEM3_MEMWAIT3 ((uint32_t)0x0000FF00) /!< MEMWAIT3[7:0] bits (Common memory 3 wait time) /
Sergunb	0:f1834a63f7c1	5144	#define FSMC_PMEM3_MEMWAIT3_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5145	#define FSMC_PMEM3_MEMWAIT3_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5146	#define FSMC_PMEM3_MEMWAIT3_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5147	#define FSMC_PMEM3_MEMWAIT3_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5148	#define FSMC_PMEM3_MEMWAIT3_4 ((uint32_t)0x00001000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5149	#define FSMC_PMEM3_MEMWAIT3_5 ((uint32_t)0x00002000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5150	#define FSMC_PMEM3_MEMWAIT3_6 ((uint32_t)0x00004000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5151	#define FSMC_PMEM3_MEMWAIT3_7 ((uint32_t)0x00008000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5152
Sergunb	0:f1834a63f7c1	5153	#define FSMC_PMEM3_MEMHOLD3 ((uint32_t)0x00FF0000) /!< MEMHOLD3[7:0] bits (Common memory 3 hold time) /
Sergunb	0:f1834a63f7c1	5154	#define FSMC_PMEM3_MEMHOLD3_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5155	#define FSMC_PMEM3_MEMHOLD3_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5156	#define FSMC_PMEM3_MEMHOLD3_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5157	#define FSMC_PMEM3_MEMHOLD3_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5158	#define FSMC_PMEM3_MEMHOLD3_4 ((uint32_t)0x00100000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5159	#define FSMC_PMEM3_MEMHOLD3_5 ((uint32_t)0x00200000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5160	#define FSMC_PMEM3_MEMHOLD3_6 ((uint32_t)0x00400000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5161	#define FSMC_PMEM3_MEMHOLD3_7 ((uint32_t)0x00800000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5162
Sergunb	0:f1834a63f7c1	5163	#define FSMC_PMEM3_MEMHIZ3 ((uint32_t)0xFF000000) /!< MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) /
Sergunb	0:f1834a63f7c1	5164	#define FSMC_PMEM3_MEMHIZ3_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5165	#define FSMC_PMEM3_MEMHIZ3_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5166	#define FSMC_PMEM3_MEMHIZ3_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5167	#define FSMC_PMEM3_MEMHIZ3_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5168	#define FSMC_PMEM3_MEMHIZ3_4 ((uint32_t)0x10000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5169	#define FSMC_PMEM3_MEMHIZ3_5 ((uint32_t)0x20000000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5170	#define FSMC_PMEM3_MEMHIZ3_6 ((uint32_t)0x40000000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5171	#define FSMC_PMEM3_MEMHIZ3_7 ((uint32_t)0x80000000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5172
Sergunb	0:f1834a63f7c1	5173	/**************** Bit definition for FSMC_PMEM4 register ****************/
Sergunb	0:f1834a63f7c1	5174	#define FSMC_PMEM4_MEMSET4 ((uint32_t)0x000000FF) /!< MEMSET4[7:0] bits (Common memory 4 setup time) /
Sergunb	0:f1834a63f7c1	5175	#define FSMC_PMEM4_MEMSET4_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5176	#define FSMC_PMEM4_MEMSET4_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5177	#define FSMC_PMEM4_MEMSET4_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5178	#define FSMC_PMEM4_MEMSET4_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5179	#define FSMC_PMEM4_MEMSET4_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5180	#define FSMC_PMEM4_MEMSET4_5 ((uint32_t)0x00000020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5181	#define FSMC_PMEM4_MEMSET4_6 ((uint32_t)0x00000040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5182	#define FSMC_PMEM4_MEMSET4_7 ((uint32_t)0x00000080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5183
Sergunb	0:f1834a63f7c1	5184	#define FSMC_PMEM4_MEMWAIT4 ((uint32_t)0x0000FF00) /!< MEMWAIT4[7:0] bits (Common memory 4 wait time) /
Sergunb	0:f1834a63f7c1	5185	#define FSMC_PMEM4_MEMWAIT4_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5186	#define FSMC_PMEM4_MEMWAIT4_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5187	#define FSMC_PMEM4_MEMWAIT4_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5188	#define FSMC_PMEM4_MEMWAIT4_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5189	#define FSMC_PMEM4_MEMWAIT4_4 ((uint32_t)0x00001000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5190	#define FSMC_PMEM4_MEMWAIT4_5 ((uint32_t)0x00002000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5191	#define FSMC_PMEM4_MEMWAIT4_6 ((uint32_t)0x00004000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5192	#define FSMC_PMEM4_MEMWAIT4_7 ((uint32_t)0x00008000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5193
Sergunb	0:f1834a63f7c1	5194	#define FSMC_PMEM4_MEMHOLD4 ((uint32_t)0x00FF0000) /!< MEMHOLD4[7:0] bits (Common memory 4 hold time) /
Sergunb	0:f1834a63f7c1	5195	#define FSMC_PMEM4_MEMHOLD4_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5196	#define FSMC_PMEM4_MEMHOLD4_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5197	#define FSMC_PMEM4_MEMHOLD4_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5198	#define FSMC_PMEM4_MEMHOLD4_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5199	#define FSMC_PMEM4_MEMHOLD4_4 ((uint32_t)0x00100000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5200	#define FSMC_PMEM4_MEMHOLD4_5 ((uint32_t)0x00200000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5201	#define FSMC_PMEM4_MEMHOLD4_6 ((uint32_t)0x00400000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5202	#define FSMC_PMEM4_MEMHOLD4_7 ((uint32_t)0x00800000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5203
Sergunb	0:f1834a63f7c1	5204	#define FSMC_PMEM4_MEMHIZ4 ((uint32_t)0xFF000000) /!< MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) /
Sergunb	0:f1834a63f7c1	5205	#define FSMC_PMEM4_MEMHIZ4_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5206	#define FSMC_PMEM4_MEMHIZ4_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5207	#define FSMC_PMEM4_MEMHIZ4_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5208	#define FSMC_PMEM4_MEMHIZ4_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5209	#define FSMC_PMEM4_MEMHIZ4_4 ((uint32_t)0x10000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5210	#define FSMC_PMEM4_MEMHIZ4_5 ((uint32_t)0x20000000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5211	#define FSMC_PMEM4_MEMHIZ4_6 ((uint32_t)0x40000000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5212	#define FSMC_PMEM4_MEMHIZ4_7 ((uint32_t)0x80000000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5213
Sergunb	0:f1834a63f7c1	5214	/**************** Bit definition for FSMC_PATT2 register ****************/
Sergunb	0:f1834a63f7c1	5215	#define FSMC_PATT2_ATTSET2 ((uint32_t)0x000000FF) /!< ATTSET2[7:0] bits (Attribute memory 2 setup time) /
Sergunb	0:f1834a63f7c1	5216	#define FSMC_PATT2_ATTSET2_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5217	#define FSMC_PATT2_ATTSET2_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5218	#define FSMC_PATT2_ATTSET2_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5219	#define FSMC_PATT2_ATTSET2_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5220	#define FSMC_PATT2_ATTSET2_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5221	#define FSMC_PATT2_ATTSET2_5 ((uint32_t)0x00000020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5222	#define FSMC_PATT2_ATTSET2_6 ((uint32_t)0x00000040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5223	#define FSMC_PATT2_ATTSET2_7 ((uint32_t)0x00000080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5224
Sergunb	0:f1834a63f7c1	5225	#define FSMC_PATT2_ATTWAIT2 ((uint32_t)0x0000FF00) /!< ATTWAIT2[7:0] bits (Attribute memory 2 wait time) /
Sergunb	0:f1834a63f7c1	5226	#define FSMC_PATT2_ATTWAIT2_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5227	#define FSMC_PATT2_ATTWAIT2_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5228	#define FSMC_PATT2_ATTWAIT2_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5229	#define FSMC_PATT2_ATTWAIT2_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5230	#define FSMC_PATT2_ATTWAIT2_4 ((uint32_t)0x00001000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5231	#define FSMC_PATT2_ATTWAIT2_5 ((uint32_t)0x00002000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5232	#define FSMC_PATT2_ATTWAIT2_6 ((uint32_t)0x00004000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5233	#define FSMC_PATT2_ATTWAIT2_7 ((uint32_t)0x00008000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5234
Sergunb	0:f1834a63f7c1	5235	#define FSMC_PATT2_ATTHOLD2 ((uint32_t)0x00FF0000) /!< ATTHOLD2[7:0] bits (Attribute memory 2 hold time) /
Sergunb	0:f1834a63f7c1	5236	#define FSMC_PATT2_ATTHOLD2_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5237	#define FSMC_PATT2_ATTHOLD2_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5238	#define FSMC_PATT2_ATTHOLD2_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5239	#define FSMC_PATT2_ATTHOLD2_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5240	#define FSMC_PATT2_ATTHOLD2_4 ((uint32_t)0x00100000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5241	#define FSMC_PATT2_ATTHOLD2_5 ((uint32_t)0x00200000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5242	#define FSMC_PATT2_ATTHOLD2_6 ((uint32_t)0x00400000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5243	#define FSMC_PATT2_ATTHOLD2_7 ((uint32_t)0x00800000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5244
Sergunb	0:f1834a63f7c1	5245	#define FSMC_PATT2_ATTHIZ2 ((uint32_t)0xFF000000) /!< ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) /
Sergunb	0:f1834a63f7c1	5246	#define FSMC_PATT2_ATTHIZ2_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5247	#define FSMC_PATT2_ATTHIZ2_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5248	#define FSMC_PATT2_ATTHIZ2_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5249	#define FSMC_PATT2_ATTHIZ2_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5250	#define FSMC_PATT2_ATTHIZ2_4 ((uint32_t)0x10000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5251	#define FSMC_PATT2_ATTHIZ2_5 ((uint32_t)0x20000000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5252	#define FSMC_PATT2_ATTHIZ2_6 ((uint32_t)0x40000000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5253	#define FSMC_PATT2_ATTHIZ2_7 ((uint32_t)0x80000000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5254
Sergunb	0:f1834a63f7c1	5255	/**************** Bit definition for FSMC_PATT3 register ****************/
Sergunb	0:f1834a63f7c1	5256	#define FSMC_PATT3_ATTSET3 ((uint32_t)0x000000FF) /!< ATTSET3[7:0] bits (Attribute memory 3 setup time) /
Sergunb	0:f1834a63f7c1	5257	#define FSMC_PATT3_ATTSET3_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5258	#define FSMC_PATT3_ATTSET3_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5259	#define FSMC_PATT3_ATTSET3_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5260	#define FSMC_PATT3_ATTSET3_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5261	#define FSMC_PATT3_ATTSET3_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5262	#define FSMC_PATT3_ATTSET3_5 ((uint32_t)0x00000020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5263	#define FSMC_PATT3_ATTSET3_6 ((uint32_t)0x00000040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5264	#define FSMC_PATT3_ATTSET3_7 ((uint32_t)0x00000080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5265
Sergunb	0:f1834a63f7c1	5266	#define FSMC_PATT3_ATTWAIT3 ((uint32_t)0x0000FF00) /!< ATTWAIT3[7:0] bits (Attribute memory 3 wait time) /
Sergunb	0:f1834a63f7c1	5267	#define FSMC_PATT3_ATTWAIT3_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5268	#define FSMC_PATT3_ATTWAIT3_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5269	#define FSMC_PATT3_ATTWAIT3_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5270	#define FSMC_PATT3_ATTWAIT3_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5271	#define FSMC_PATT3_ATTWAIT3_4 ((uint32_t)0x00001000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5272	#define FSMC_PATT3_ATTWAIT3_5 ((uint32_t)0x00002000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5273	#define FSMC_PATT3_ATTWAIT3_6 ((uint32_t)0x00004000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5274	#define FSMC_PATT3_ATTWAIT3_7 ((uint32_t)0x00008000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5275
Sergunb	0:f1834a63f7c1	5276	#define FSMC_PATT3_ATTHOLD3 ((uint32_t)0x00FF0000) /!< ATTHOLD3[7:0] bits (Attribute memory 3 hold time) /
Sergunb	0:f1834a63f7c1	5277	#define FSMC_PATT3_ATTHOLD3_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5278	#define FSMC_PATT3_ATTHOLD3_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5279	#define FSMC_PATT3_ATTHOLD3_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5280	#define FSMC_PATT3_ATTHOLD3_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5281	#define FSMC_PATT3_ATTHOLD3_4 ((uint32_t)0x00100000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5282	#define FSMC_PATT3_ATTHOLD3_5 ((uint32_t)0x00200000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5283	#define FSMC_PATT3_ATTHOLD3_6 ((uint32_t)0x00400000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5284	#define FSMC_PATT3_ATTHOLD3_7 ((uint32_t)0x00800000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5285
Sergunb	0:f1834a63f7c1	5286	#define FSMC_PATT3_ATTHIZ3 ((uint32_t)0xFF000000) /!< ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) /
Sergunb	0:f1834a63f7c1	5287	#define FSMC_PATT3_ATTHIZ3_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5288	#define FSMC_PATT3_ATTHIZ3_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5289	#define FSMC_PATT3_ATTHIZ3_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5290	#define FSMC_PATT3_ATTHIZ3_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5291	#define FSMC_PATT3_ATTHIZ3_4 ((uint32_t)0x10000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5292	#define FSMC_PATT3_ATTHIZ3_5 ((uint32_t)0x20000000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5293	#define FSMC_PATT3_ATTHIZ3_6 ((uint32_t)0x40000000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5294	#define FSMC_PATT3_ATTHIZ3_7 ((uint32_t)0x80000000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5295
Sergunb	0:f1834a63f7c1	5296	/**************** Bit definition for FSMC_PATT4 register ****************/
Sergunb	0:f1834a63f7c1	5297	#define FSMC_PATT4_ATTSET4 ((uint32_t)0x000000FF) /!< ATTSET4[7:0] bits (Attribute memory 4 setup time) /
Sergunb	0:f1834a63f7c1	5298	#define FSMC_PATT4_ATTSET4_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5299	#define FSMC_PATT4_ATTSET4_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5300	#define FSMC_PATT4_ATTSET4_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5301	#define FSMC_PATT4_ATTSET4_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5302	#define FSMC_PATT4_ATTSET4_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5303	#define FSMC_PATT4_ATTSET4_5 ((uint32_t)0x00000020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5304	#define FSMC_PATT4_ATTSET4_6 ((uint32_t)0x00000040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5305	#define FSMC_PATT4_ATTSET4_7 ((uint32_t)0x00000080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5306
Sergunb	0:f1834a63f7c1	5307	#define FSMC_PATT4_ATTWAIT4 ((uint32_t)0x0000FF00) /!< ATTWAIT4[7:0] bits (Attribute memory 4 wait time) /
Sergunb	0:f1834a63f7c1	5308	#define FSMC_PATT4_ATTWAIT4_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5309	#define FSMC_PATT4_ATTWAIT4_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5310	#define FSMC_PATT4_ATTWAIT4_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5311	#define FSMC_PATT4_ATTWAIT4_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5312	#define FSMC_PATT4_ATTWAIT4_4 ((uint32_t)0x00001000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5313	#define FSMC_PATT4_ATTWAIT4_5 ((uint32_t)0x00002000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5314	#define FSMC_PATT4_ATTWAIT4_6 ((uint32_t)0x00004000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5315	#define FSMC_PATT4_ATTWAIT4_7 ((uint32_t)0x00008000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5316
Sergunb	0:f1834a63f7c1	5317	#define FSMC_PATT4_ATTHOLD4 ((uint32_t)0x00FF0000) /!< ATTHOLD4[7:0] bits (Attribute memory 4 hold time) /
Sergunb	0:f1834a63f7c1	5318	#define FSMC_PATT4_ATTHOLD4_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5319	#define FSMC_PATT4_ATTHOLD4_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5320	#define FSMC_PATT4_ATTHOLD4_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5321	#define FSMC_PATT4_ATTHOLD4_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5322	#define FSMC_PATT4_ATTHOLD4_4 ((uint32_t)0x00100000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5323	#define FSMC_PATT4_ATTHOLD4_5 ((uint32_t)0x00200000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5324	#define FSMC_PATT4_ATTHOLD4_6 ((uint32_t)0x00400000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5325	#define FSMC_PATT4_ATTHOLD4_7 ((uint32_t)0x00800000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5326
Sergunb	0:f1834a63f7c1	5327	#define FSMC_PATT4_ATTHIZ4 ((uint32_t)0xFF000000) /!< ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) /
Sergunb	0:f1834a63f7c1	5328	#define FSMC_PATT4_ATTHIZ4_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5329	#define FSMC_PATT4_ATTHIZ4_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5330	#define FSMC_PATT4_ATTHIZ4_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5331	#define FSMC_PATT4_ATTHIZ4_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5332	#define FSMC_PATT4_ATTHIZ4_4 ((uint32_t)0x10000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5333	#define FSMC_PATT4_ATTHIZ4_5 ((uint32_t)0x20000000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5334	#define FSMC_PATT4_ATTHIZ4_6 ((uint32_t)0x40000000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5335	#define FSMC_PATT4_ATTHIZ4_7 ((uint32_t)0x80000000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5336
Sergunb	0:f1834a63f7c1	5337	/**************** Bit definition for FSMC_PIO4 register *****************/
Sergunb	0:f1834a63f7c1	5338	#define FSMC_PIO4_IOSET4 ((uint32_t)0x000000FF) /!< IOSET4[7:0] bits (I/O 4 setup time) /
Sergunb	0:f1834a63f7c1	5339	#define FSMC_PIO4_IOSET4_0 ((uint32_t)0x00000001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5340	#define FSMC_PIO4_IOSET4_1 ((uint32_t)0x00000002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5341	#define FSMC_PIO4_IOSET4_2 ((uint32_t)0x00000004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5342	#define FSMC_PIO4_IOSET4_3 ((uint32_t)0x00000008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5343	#define FSMC_PIO4_IOSET4_4 ((uint32_t)0x00000010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5344	#define FSMC_PIO4_IOSET4_5 ((uint32_t)0x00000020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5345	#define FSMC_PIO4_IOSET4_6 ((uint32_t)0x00000040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5346	#define FSMC_PIO4_IOSET4_7 ((uint32_t)0x00000080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5347
Sergunb	0:f1834a63f7c1	5348	#define FSMC_PIO4_IOWAIT4 ((uint32_t)0x0000FF00) /!< IOWAIT4[7:0] bits (I/O 4 wait time) /
Sergunb	0:f1834a63f7c1	5349	#define FSMC_PIO4_IOWAIT4_0 ((uint32_t)0x00000100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5350	#define FSMC_PIO4_IOWAIT4_1 ((uint32_t)0x00000200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5351	#define FSMC_PIO4_IOWAIT4_2 ((uint32_t)0x00000400) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5352	#define FSMC_PIO4_IOWAIT4_3 ((uint32_t)0x00000800) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5353	#define FSMC_PIO4_IOWAIT4_4 ((uint32_t)0x00001000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5354	#define FSMC_PIO4_IOWAIT4_5 ((uint32_t)0x00002000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5355	#define FSMC_PIO4_IOWAIT4_6 ((uint32_t)0x00004000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5356	#define FSMC_PIO4_IOWAIT4_7 ((uint32_t)0x00008000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5357
Sergunb	0:f1834a63f7c1	5358	#define FSMC_PIO4_IOHOLD4 ((uint32_t)0x00FF0000) /!< IOHOLD4[7:0] bits (I/O 4 hold time) /
Sergunb	0:f1834a63f7c1	5359	#define FSMC_PIO4_IOHOLD4_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5360	#define FSMC_PIO4_IOHOLD4_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5361	#define FSMC_PIO4_IOHOLD4_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5362	#define FSMC_PIO4_IOHOLD4_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5363	#define FSMC_PIO4_IOHOLD4_4 ((uint32_t)0x00100000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5364	#define FSMC_PIO4_IOHOLD4_5 ((uint32_t)0x00200000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5365	#define FSMC_PIO4_IOHOLD4_6 ((uint32_t)0x00400000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5366	#define FSMC_PIO4_IOHOLD4_7 ((uint32_t)0x00800000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5367
Sergunb	0:f1834a63f7c1	5368	#define FSMC_PIO4_IOHIZ4 ((uint32_t)0xFF000000) /!< IOHIZ4[7:0] bits (I/O 4 databus HiZ time) /
Sergunb	0:f1834a63f7c1	5369	#define FSMC_PIO4_IOHIZ4_0 ((uint32_t)0x01000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5370	#define FSMC_PIO4_IOHIZ4_1 ((uint32_t)0x02000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5371	#define FSMC_PIO4_IOHIZ4_2 ((uint32_t)0x04000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5372	#define FSMC_PIO4_IOHIZ4_3 ((uint32_t)0x08000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5373	#define FSMC_PIO4_IOHIZ4_4 ((uint32_t)0x10000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5374	#define FSMC_PIO4_IOHIZ4_5 ((uint32_t)0x20000000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5375	#define FSMC_PIO4_IOHIZ4_6 ((uint32_t)0x40000000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5376	#define FSMC_PIO4_IOHIZ4_7 ((uint32_t)0x80000000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	5377
Sergunb	0:f1834a63f7c1	5378	/**************** Bit definition for FSMC_ECCR2 register ****************/
Sergunb	0:f1834a63f7c1	5379	#define FSMC_ECCR2_ECC2 ((uint32_t)0xFFFFFFFF) /!< ECC result /
Sergunb	0:f1834a63f7c1	5380
Sergunb	0:f1834a63f7c1	5381	/**************** Bit definition for FSMC_ECCR3 register ****************/
Sergunb	0:f1834a63f7c1	5382	#define FSMC_ECCR3_ECC3 ((uint32_t)0xFFFFFFFF) /!< ECC result /
Sergunb	0:f1834a63f7c1	5383
Sergunb	0:f1834a63f7c1	5384	/******************************************************************************/
Sergunb	0:f1834a63f7c1	5385	/* */
Sergunb	0:f1834a63f7c1	5386	/* SD host Interface */
Sergunb	0:f1834a63f7c1	5387	/* */
Sergunb	0:f1834a63f7c1	5388	/******************************************************************************/
Sergunb	0:f1834a63f7c1	5389
Sergunb	0:f1834a63f7c1	5390	/**************** Bit definition for SDIO_POWER register ****************/
Sergunb	0:f1834a63f7c1	5391	#define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /!< PWRCTRL[1:0] bits (Power supply control bits) /
Sergunb	0:f1834a63f7c1	5392	#define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5393	#define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5394
Sergunb	0:f1834a63f7c1	5395	/**************** Bit definition for SDIO_CLKCR register ****************/
Sergunb	0:f1834a63f7c1	5396	#define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /!< Clock divide factor /
Sergunb	0:f1834a63f7c1	5397	#define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /!< Clock enable bit /
Sergunb	0:f1834a63f7c1	5398	#define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /!< Power saving configuration bit /
Sergunb	0:f1834a63f7c1	5399	#define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /!< Clock divider bypass enable bit /
Sergunb	0:f1834a63f7c1	5400
Sergunb	0:f1834a63f7c1	5401	#define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /!< WIDBUS[1:0] bits (Wide bus mode enable bit) /
Sergunb	0:f1834a63f7c1	5402	#define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5403	#define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5404
Sergunb	0:f1834a63f7c1	5405	#define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /!< SDIO_CK dephasing selection bit /
Sergunb	0:f1834a63f7c1	5406	#define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /!< HW Flow Control enable /
Sergunb	0:f1834a63f7c1	5407
Sergunb	0:f1834a63f7c1	5408	/***************** Bit definition for SDIO_ARG register *****************/
Sergunb	0:f1834a63f7c1	5409	#define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /!< Command argument /
Sergunb	0:f1834a63f7c1	5410
Sergunb	0:f1834a63f7c1	5411	/***************** Bit definition for SDIO_CMD register *****************/
Sergunb	0:f1834a63f7c1	5412	#define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /!< Command Index /
Sergunb	0:f1834a63f7c1	5413
Sergunb	0:f1834a63f7c1	5414	#define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /!< WAITRESP[1:0] bits (Wait for response bits) /
Sergunb	0:f1834a63f7c1	5415	#define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5416	#define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5417
Sergunb	0:f1834a63f7c1	5418	#define SDIO_CMD_WAITINT ((uint16_t)0x0100) /!< CPSM Waits for Interrupt Request /
Sergunb	0:f1834a63f7c1	5419	#define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /!< CPSM Waits for ends of data transfer (CmdPend internal signal) /
Sergunb	0:f1834a63f7c1	5420	#define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /!< Command path state machine (CPSM) Enable bit /
Sergunb	0:f1834a63f7c1	5421	#define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /!< SD I/O suspend command /
Sergunb	0:f1834a63f7c1	5422	#define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /!< Enable CMD completion /
Sergunb	0:f1834a63f7c1	5423	#define SDIO_CMD_NIEN ((uint16_t)0x2000) /!< Not Interrupt Enable /
Sergunb	0:f1834a63f7c1	5424	#define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /!< CE-ATA command /
Sergunb	0:f1834a63f7c1	5425
Sergunb	0:f1834a63f7c1	5426	/*************** Bit definition for SDIO_RESPCMD register ***************/
Sergunb	0:f1834a63f7c1	5427	#define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /!< Response command index /
Sergunb	0:f1834a63f7c1	5428
Sergunb	0:f1834a63f7c1	5429	/**************** Bit definition for SDIO_RESP0 register ****************/
Sergunb	0:f1834a63f7c1	5430	#define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /!< Card Status /
Sergunb	0:f1834a63f7c1	5431
Sergunb	0:f1834a63f7c1	5432	/**************** Bit definition for SDIO_RESP1 register ****************/
Sergunb	0:f1834a63f7c1	5433	#define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /!< Card Status /
Sergunb	0:f1834a63f7c1	5434
Sergunb	0:f1834a63f7c1	5435	/**************** Bit definition for SDIO_RESP2 register ****************/
Sergunb	0:f1834a63f7c1	5436	#define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /!< Card Status /
Sergunb	0:f1834a63f7c1	5437
Sergunb	0:f1834a63f7c1	5438	/**************** Bit definition for SDIO_RESP3 register ****************/
Sergunb	0:f1834a63f7c1	5439	#define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /!< Card Status /
Sergunb	0:f1834a63f7c1	5440
Sergunb	0:f1834a63f7c1	5441	/**************** Bit definition for SDIO_RESP4 register ****************/
Sergunb	0:f1834a63f7c1	5442	#define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /!< Card Status /
Sergunb	0:f1834a63f7c1	5443
Sergunb	0:f1834a63f7c1	5444	/**************** Bit definition for SDIO_DTIMER register ***************/
Sergunb	0:f1834a63f7c1	5445	#define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /!< Data timeout period. /
Sergunb	0:f1834a63f7c1	5446
Sergunb	0:f1834a63f7c1	5447	/**************** Bit definition for SDIO_DLEN register *****************/
Sergunb	0:f1834a63f7c1	5448	#define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /!< Data length value /
Sergunb	0:f1834a63f7c1	5449
Sergunb	0:f1834a63f7c1	5450	/**************** Bit definition for SDIO_DCTRL register ****************/
Sergunb	0:f1834a63f7c1	5451	#define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /!< Data transfer enabled bit /
Sergunb	0:f1834a63f7c1	5452	#define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /!< Data transfer direction selection /
Sergunb	0:f1834a63f7c1	5453	#define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /!< Data transfer mode selection /
Sergunb	0:f1834a63f7c1	5454	#define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /!< DMA enabled bit /
Sergunb	0:f1834a63f7c1	5455
Sergunb	0:f1834a63f7c1	5456	#define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /!< DBLOCKSIZE[3:0] bits (Data block size) /
Sergunb	0:f1834a63f7c1	5457	#define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5458	#define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5459	#define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5460	#define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5461
Sergunb	0:f1834a63f7c1	5462	#define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /!< Read wait start /
Sergunb	0:f1834a63f7c1	5463	#define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /!< Read wait stop /
Sergunb	0:f1834a63f7c1	5464	#define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /!< Read wait mode /
Sergunb	0:f1834a63f7c1	5465	#define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /!< SD I/O enable functions /
Sergunb	0:f1834a63f7c1	5466
Sergunb	0:f1834a63f7c1	5467	/**************** Bit definition for SDIO_DCOUNT register ***************/
Sergunb	0:f1834a63f7c1	5468	#define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /!< Data count value /
Sergunb	0:f1834a63f7c1	5469
Sergunb	0:f1834a63f7c1	5470	/**************** Bit definition for SDIO_STA register ******************/
Sergunb	0:f1834a63f7c1	5471	#define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /!< Command response received (CRC check failed) /
Sergunb	0:f1834a63f7c1	5472	#define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /!< Data block sent/received (CRC check failed) /
Sergunb	0:f1834a63f7c1	5473	#define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /!< Command response timeout /
Sergunb	0:f1834a63f7c1	5474	#define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /!< Data timeout /
Sergunb	0:f1834a63f7c1	5475	#define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /!< Transmit FIFO underrun error /
Sergunb	0:f1834a63f7c1	5476	#define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /!< Received FIFO overrun error /
Sergunb	0:f1834a63f7c1	5477	#define SDIO_STA_CMDREND ((uint32_t)0x00000040) /!< Command response received (CRC check passed) /
Sergunb	0:f1834a63f7c1	5478	#define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /!< Command sent (no response required) /
Sergunb	0:f1834a63f7c1	5479	#define SDIO_STA_DATAEND ((uint32_t)0x00000100) /!< Data end (data counter, SDIDCOUNT, is zero) /
Sergunb	0:f1834a63f7c1	5480	#define SDIO_STA_STBITERR ((uint32_t)0x00000200) /!< Start bit not detected on all data signals in wide bus mode /
Sergunb	0:f1834a63f7c1	5481	#define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /!< Data block sent/received (CRC check passed) /
Sergunb	0:f1834a63f7c1	5482	#define SDIO_STA_CMDACT ((uint32_t)0x00000800) /!< Command transfer in progress /
Sergunb	0:f1834a63f7c1	5483	#define SDIO_STA_TXACT ((uint32_t)0x00001000) /!< Data transmit in progress /
Sergunb	0:f1834a63f7c1	5484	#define SDIO_STA_RXACT ((uint32_t)0x00002000) /!< Data receive in progress /
Sergunb	0:f1834a63f7c1	5485	#define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
Sergunb	0:f1834a63f7c1	5486	#define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /!< Receive FIFO Half Full: there are at least 8 words in the FIFO /
Sergunb	0:f1834a63f7c1	5487	#define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /!< Transmit FIFO full /
Sergunb	0:f1834a63f7c1	5488	#define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /!< Receive FIFO full /
Sergunb	0:f1834a63f7c1	5489	#define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /!< Transmit FIFO empty /
Sergunb	0:f1834a63f7c1	5490	#define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /!< Receive FIFO empty /
Sergunb	0:f1834a63f7c1	5491	#define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /!< Data available in transmit FIFO /
Sergunb	0:f1834a63f7c1	5492	#define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /!< Data available in receive FIFO /
Sergunb	0:f1834a63f7c1	5493	#define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /!< SDIO interrupt received /
Sergunb	0:f1834a63f7c1	5494	#define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /!< CE-ATA command completion signal received for CMD61 /
Sergunb	0:f1834a63f7c1	5495
Sergunb	0:f1834a63f7c1	5496	/***************** Bit definition for SDIO_ICR register *****************/
Sergunb	0:f1834a63f7c1	5497	#define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /!< CCRCFAIL flag clear bit /
Sergunb	0:f1834a63f7c1	5498	#define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /!< DCRCFAIL flag clear bit /
Sergunb	0:f1834a63f7c1	5499	#define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /!< CTIMEOUT flag clear bit /
Sergunb	0:f1834a63f7c1	5500	#define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /!< DTIMEOUT flag clear bit /
Sergunb	0:f1834a63f7c1	5501	#define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /!< TXUNDERR flag clear bit /
Sergunb	0:f1834a63f7c1	5502	#define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /!< RXOVERR flag clear bit /
Sergunb	0:f1834a63f7c1	5503	#define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /!< CMDREND flag clear bit /
Sergunb	0:f1834a63f7c1	5504	#define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /!< CMDSENT flag clear bit /
Sergunb	0:f1834a63f7c1	5505	#define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /!< DATAEND flag clear bit /
Sergunb	0:f1834a63f7c1	5506	#define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /!< STBITERR flag clear bit /
Sergunb	0:f1834a63f7c1	5507	#define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /!< DBCKEND flag clear bit /
Sergunb	0:f1834a63f7c1	5508	#define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /!< SDIOIT flag clear bit /
Sergunb	0:f1834a63f7c1	5509	#define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /!< CEATAEND flag clear bit /
Sergunb	0:f1834a63f7c1	5510
Sergunb	0:f1834a63f7c1	5511	/**************** Bit definition for SDIO_MASK register *****************/
Sergunb	0:f1834a63f7c1	5512	#define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /!< Command CRC Fail Interrupt Enable /
Sergunb	0:f1834a63f7c1	5513	#define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /!< Data CRC Fail Interrupt Enable /
Sergunb	0:f1834a63f7c1	5514	#define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /!< Command TimeOut Interrupt Enable /
Sergunb	0:f1834a63f7c1	5515	#define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /!< Data TimeOut Interrupt Enable /
Sergunb	0:f1834a63f7c1	5516	#define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /!< Tx FIFO UnderRun Error Interrupt Enable /
Sergunb	0:f1834a63f7c1	5517	#define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /!< Rx FIFO OverRun Error Interrupt Enable /
Sergunb	0:f1834a63f7c1	5518	#define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /!< Command Response Received Interrupt Enable /
Sergunb	0:f1834a63f7c1	5519	#define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /!< Command Sent Interrupt Enable /
Sergunb	0:f1834a63f7c1	5520	#define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /!< Data End Interrupt Enable /
Sergunb	0:f1834a63f7c1	5521	#define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /!< Start Bit Error Interrupt Enable /
Sergunb	0:f1834a63f7c1	5522	#define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /!< Data Block End Interrupt Enable /
Sergunb	0:f1834a63f7c1	5523	#define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /!< Command Acting Interrupt Enable /
Sergunb	0:f1834a63f7c1	5524	#define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /!< Data Transmit Acting Interrupt Enable /
Sergunb	0:f1834a63f7c1	5525	#define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /!< Data receive acting interrupt enabled /
Sergunb	0:f1834a63f7c1	5526	#define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /!< Tx FIFO Half Empty interrupt Enable /
Sergunb	0:f1834a63f7c1	5527	#define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /!< Rx FIFO Half Full interrupt Enable /
Sergunb	0:f1834a63f7c1	5528	#define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /!< Tx FIFO Full interrupt Enable /
Sergunb	0:f1834a63f7c1	5529	#define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /!< Rx FIFO Full interrupt Enable /
Sergunb	0:f1834a63f7c1	5530	#define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /!< Tx FIFO Empty interrupt Enable /
Sergunb	0:f1834a63f7c1	5531	#define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /!< Rx FIFO Empty interrupt Enable /
Sergunb	0:f1834a63f7c1	5532	#define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /!< Data available in Tx FIFO interrupt Enable /
Sergunb	0:f1834a63f7c1	5533	#define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /!< Data available in Rx FIFO interrupt Enable /
Sergunb	0:f1834a63f7c1	5534	#define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /!< SDIO Mode Interrupt Received interrupt Enable /
Sergunb	0:f1834a63f7c1	5535	#define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /!< CE-ATA command completion signal received Interrupt Enable /
Sergunb	0:f1834a63f7c1	5536
Sergunb	0:f1834a63f7c1	5537	/*************** Bit definition for SDIO_FIFOCNT register ***************/
Sergunb	0:f1834a63f7c1	5538	#define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /!< Remaining number of words to be written to or read from the FIFO /
Sergunb	0:f1834a63f7c1	5539
Sergunb	0:f1834a63f7c1	5540	/**************** Bit definition for SDIO_FIFO register *****************/
Sergunb	0:f1834a63f7c1	5541	#define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /!< Receive and transmit FIFO data /
Sergunb	0:f1834a63f7c1	5542
Sergunb	0:f1834a63f7c1	5543	/******************************************************************************/
Sergunb	0:f1834a63f7c1	5544	/* */
Sergunb	0:f1834a63f7c1	5545	/* USB Device FS */
Sergunb	0:f1834a63f7c1	5546	/* */
Sergunb	0:f1834a63f7c1	5547	/******************************************************************************/
Sergunb	0:f1834a63f7c1	5548
Sergunb	0:f1834a63f7c1	5549	/!< Endpoint-specific registers /
Sergunb	0:f1834a63f7c1	5550	/***************** Bit definition for USB_EP0R register *****************/
Sergunb	0:f1834a63f7c1	5551	#define USB_EP0R_EA ((uint16_t)0x000F) /!< Endpoint Address /
Sergunb	0:f1834a63f7c1	5552
Sergunb	0:f1834a63f7c1	5553	#define USB_EP0R_STAT_TX ((uint16_t)0x0030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Sergunb	0:f1834a63f7c1	5554	#define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5555	#define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5556
Sergunb	0:f1834a63f7c1	5557	#define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /!< Data Toggle, for transmission transfers /
Sergunb	0:f1834a63f7c1	5558	#define USB_EP0R_CTR_TX ((uint16_t)0x0080) /!< Correct Transfer for transmission /
Sergunb	0:f1834a63f7c1	5559	#define USB_EP0R_EP_KIND ((uint16_t)0x0100) /!< Endpoint Kind /
Sergunb	0:f1834a63f7c1	5560
Sergunb	0:f1834a63f7c1	5561	#define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /!< EP_TYPE[1:0] bits (Endpoint type) /
Sergunb	0:f1834a63f7c1	5562	#define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5563	#define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5564
Sergunb	0:f1834a63f7c1	5565	#define USB_EP0R_SETUP ((uint16_t)0x0800) /!< Setup transaction completed /
Sergunb	0:f1834a63f7c1	5566
Sergunb	0:f1834a63f7c1	5567	#define USB_EP0R_STAT_RX ((uint16_t)0x3000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
Sergunb	0:f1834a63f7c1	5568	#define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5569	#define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5570
Sergunb	0:f1834a63f7c1	5571	#define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /!< Data Toggle, for reception transfers /
Sergunb	0:f1834a63f7c1	5572	#define USB_EP0R_CTR_RX ((uint16_t)0x8000) /!< Correct Transfer for reception /
Sergunb	0:f1834a63f7c1	5573
Sergunb	0:f1834a63f7c1	5574	/***************** Bit definition for USB_EP1R register *****************/
Sergunb	0:f1834a63f7c1	5575	#define USB_EP1R_EA ((uint16_t)0x000F) /!< Endpoint Address /
Sergunb	0:f1834a63f7c1	5576
Sergunb	0:f1834a63f7c1	5577	#define USB_EP1R_STAT_TX ((uint16_t)0x0030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Sergunb	0:f1834a63f7c1	5578	#define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5579	#define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5580
Sergunb	0:f1834a63f7c1	5581	#define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /!< Data Toggle, for transmission transfers /
Sergunb	0:f1834a63f7c1	5582	#define USB_EP1R_CTR_TX ((uint16_t)0x0080) /!< Correct Transfer for transmission /
Sergunb	0:f1834a63f7c1	5583	#define USB_EP1R_EP_KIND ((uint16_t)0x0100) /!< Endpoint Kind /
Sergunb	0:f1834a63f7c1	5584
Sergunb	0:f1834a63f7c1	5585	#define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /!< EP_TYPE[1:0] bits (Endpoint type) /
Sergunb	0:f1834a63f7c1	5586	#define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5587	#define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5588
Sergunb	0:f1834a63f7c1	5589	#define USB_EP1R_SETUP ((uint16_t)0x0800) /!< Setup transaction completed /
Sergunb	0:f1834a63f7c1	5590
Sergunb	0:f1834a63f7c1	5591	#define USB_EP1R_STAT_RX ((uint16_t)0x3000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
Sergunb	0:f1834a63f7c1	5592	#define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5593	#define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5594
Sergunb	0:f1834a63f7c1	5595	#define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /!< Data Toggle, for reception transfers /
Sergunb	0:f1834a63f7c1	5596	#define USB_EP1R_CTR_RX ((uint16_t)0x8000) /!< Correct Transfer for reception /
Sergunb	0:f1834a63f7c1	5597
Sergunb	0:f1834a63f7c1	5598	/***************** Bit definition for USB_EP2R register *****************/
Sergunb	0:f1834a63f7c1	5599	#define USB_EP2R_EA ((uint16_t)0x000F) /!< Endpoint Address /
Sergunb	0:f1834a63f7c1	5600
Sergunb	0:f1834a63f7c1	5601	#define USB_EP2R_STAT_TX ((uint16_t)0x0030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Sergunb	0:f1834a63f7c1	5602	#define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5603	#define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5604
Sergunb	0:f1834a63f7c1	5605	#define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /!< Data Toggle, for transmission transfers /
Sergunb	0:f1834a63f7c1	5606	#define USB_EP2R_CTR_TX ((uint16_t)0x0080) /!< Correct Transfer for transmission /
Sergunb	0:f1834a63f7c1	5607	#define USB_EP2R_EP_KIND ((uint16_t)0x0100) /!< Endpoint Kind /
Sergunb	0:f1834a63f7c1	5608
Sergunb	0:f1834a63f7c1	5609	#define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /!< EP_TYPE[1:0] bits (Endpoint type) /
Sergunb	0:f1834a63f7c1	5610	#define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5611	#define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5612
Sergunb	0:f1834a63f7c1	5613	#define USB_EP2R_SETUP ((uint16_t)0x0800) /!< Setup transaction completed /
Sergunb	0:f1834a63f7c1	5614
Sergunb	0:f1834a63f7c1	5615	#define USB_EP2R_STAT_RX ((uint16_t)0x3000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
Sergunb	0:f1834a63f7c1	5616	#define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5617	#define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5618
Sergunb	0:f1834a63f7c1	5619	#define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /!< Data Toggle, for reception transfers /
Sergunb	0:f1834a63f7c1	5620	#define USB_EP2R_CTR_RX ((uint16_t)0x8000) /!< Correct Transfer for reception /
Sergunb	0:f1834a63f7c1	5621
Sergunb	0:f1834a63f7c1	5622	/***************** Bit definition for USB_EP3R register *****************/
Sergunb	0:f1834a63f7c1	5623	#define USB_EP3R_EA ((uint16_t)0x000F) /!< Endpoint Address /
Sergunb	0:f1834a63f7c1	5624
Sergunb	0:f1834a63f7c1	5625	#define USB_EP3R_STAT_TX ((uint16_t)0x0030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Sergunb	0:f1834a63f7c1	5626	#define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5627	#define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5628
Sergunb	0:f1834a63f7c1	5629	#define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /!< Data Toggle, for transmission transfers /
Sergunb	0:f1834a63f7c1	5630	#define USB_EP3R_CTR_TX ((uint16_t)0x0080) /!< Correct Transfer for transmission /
Sergunb	0:f1834a63f7c1	5631	#define USB_EP3R_EP_KIND ((uint16_t)0x0100) /!< Endpoint Kind /
Sergunb	0:f1834a63f7c1	5632
Sergunb	0:f1834a63f7c1	5633	#define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /!< EP_TYPE[1:0] bits (Endpoint type) /
Sergunb	0:f1834a63f7c1	5634	#define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5635	#define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5636
Sergunb	0:f1834a63f7c1	5637	#define USB_EP3R_SETUP ((uint16_t)0x0800) /!< Setup transaction completed /
Sergunb	0:f1834a63f7c1	5638
Sergunb	0:f1834a63f7c1	5639	#define USB_EP3R_STAT_RX ((uint16_t)0x3000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
Sergunb	0:f1834a63f7c1	5640	#define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5641	#define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5642
Sergunb	0:f1834a63f7c1	5643	#define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /!< Data Toggle, for reception transfers /
Sergunb	0:f1834a63f7c1	5644	#define USB_EP3R_CTR_RX ((uint16_t)0x8000) /!< Correct Transfer for reception /
Sergunb	0:f1834a63f7c1	5645
Sergunb	0:f1834a63f7c1	5646	/***************** Bit definition for USB_EP4R register *****************/
Sergunb	0:f1834a63f7c1	5647	#define USB_EP4R_EA ((uint16_t)0x000F) /!< Endpoint Address /
Sergunb	0:f1834a63f7c1	5648
Sergunb	0:f1834a63f7c1	5649	#define USB_EP4R_STAT_TX ((uint16_t)0x0030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Sergunb	0:f1834a63f7c1	5650	#define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5651	#define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5652
Sergunb	0:f1834a63f7c1	5653	#define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /!< Data Toggle, for transmission transfers /
Sergunb	0:f1834a63f7c1	5654	#define USB_EP4R_CTR_TX ((uint16_t)0x0080) /!< Correct Transfer for transmission /
Sergunb	0:f1834a63f7c1	5655	#define USB_EP4R_EP_KIND ((uint16_t)0x0100) /!< Endpoint Kind /
Sergunb	0:f1834a63f7c1	5656
Sergunb	0:f1834a63f7c1	5657	#define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /!< EP_TYPE[1:0] bits (Endpoint type) /
Sergunb	0:f1834a63f7c1	5658	#define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5659	#define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5660
Sergunb	0:f1834a63f7c1	5661	#define USB_EP4R_SETUP ((uint16_t)0x0800) /!< Setup transaction completed /
Sergunb	0:f1834a63f7c1	5662
Sergunb	0:f1834a63f7c1	5663	#define USB_EP4R_STAT_RX ((uint16_t)0x3000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
Sergunb	0:f1834a63f7c1	5664	#define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5665	#define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5666
Sergunb	0:f1834a63f7c1	5667	#define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /!< Data Toggle, for reception transfers /
Sergunb	0:f1834a63f7c1	5668	#define USB_EP4R_CTR_RX ((uint16_t)0x8000) /!< Correct Transfer for reception /
Sergunb	0:f1834a63f7c1	5669
Sergunb	0:f1834a63f7c1	5670	/***************** Bit definition for USB_EP5R register *****************/
Sergunb	0:f1834a63f7c1	5671	#define USB_EP5R_EA ((uint16_t)0x000F) /!< Endpoint Address /
Sergunb	0:f1834a63f7c1	5672
Sergunb	0:f1834a63f7c1	5673	#define USB_EP5R_STAT_TX ((uint16_t)0x0030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Sergunb	0:f1834a63f7c1	5674	#define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5675	#define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5676
Sergunb	0:f1834a63f7c1	5677	#define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /!< Data Toggle, for transmission transfers /
Sergunb	0:f1834a63f7c1	5678	#define USB_EP5R_CTR_TX ((uint16_t)0x0080) /!< Correct Transfer for transmission /
Sergunb	0:f1834a63f7c1	5679	#define USB_EP5R_EP_KIND ((uint16_t)0x0100) /!< Endpoint Kind /
Sergunb	0:f1834a63f7c1	5680
Sergunb	0:f1834a63f7c1	5681	#define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /!< EP_TYPE[1:0] bits (Endpoint type) /
Sergunb	0:f1834a63f7c1	5682	#define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5683	#define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5684
Sergunb	0:f1834a63f7c1	5685	#define USB_EP5R_SETUP ((uint16_t)0x0800) /!< Setup transaction completed /
Sergunb	0:f1834a63f7c1	5686
Sergunb	0:f1834a63f7c1	5687	#define USB_EP5R_STAT_RX ((uint16_t)0x3000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
Sergunb	0:f1834a63f7c1	5688	#define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5689	#define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5690
Sergunb	0:f1834a63f7c1	5691	#define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /!< Data Toggle, for reception transfers /
Sergunb	0:f1834a63f7c1	5692	#define USB_EP5R_CTR_RX ((uint16_t)0x8000) /!< Correct Transfer for reception /
Sergunb	0:f1834a63f7c1	5693
Sergunb	0:f1834a63f7c1	5694	/***************** Bit definition for USB_EP6R register *****************/
Sergunb	0:f1834a63f7c1	5695	#define USB_EP6R_EA ((uint16_t)0x000F) /!< Endpoint Address /
Sergunb	0:f1834a63f7c1	5696
Sergunb	0:f1834a63f7c1	5697	#define USB_EP6R_STAT_TX ((uint16_t)0x0030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Sergunb	0:f1834a63f7c1	5698	#define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5699	#define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5700
Sergunb	0:f1834a63f7c1	5701	#define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /!< Data Toggle, for transmission transfers /
Sergunb	0:f1834a63f7c1	5702	#define USB_EP6R_CTR_TX ((uint16_t)0x0080) /!< Correct Transfer for transmission /
Sergunb	0:f1834a63f7c1	5703	#define USB_EP6R_EP_KIND ((uint16_t)0x0100) /!< Endpoint Kind /
Sergunb	0:f1834a63f7c1	5704
Sergunb	0:f1834a63f7c1	5705	#define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /!< EP_TYPE[1:0] bits (Endpoint type) /
Sergunb	0:f1834a63f7c1	5706	#define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5707	#define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5708
Sergunb	0:f1834a63f7c1	5709	#define USB_EP6R_SETUP ((uint16_t)0x0800) /!< Setup transaction completed /
Sergunb	0:f1834a63f7c1	5710
Sergunb	0:f1834a63f7c1	5711	#define USB_EP6R_STAT_RX ((uint16_t)0x3000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
Sergunb	0:f1834a63f7c1	5712	#define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5713	#define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5714
Sergunb	0:f1834a63f7c1	5715	#define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /!< Data Toggle, for reception transfers /
Sergunb	0:f1834a63f7c1	5716	#define USB_EP6R_CTR_RX ((uint16_t)0x8000) /!< Correct Transfer for reception /
Sergunb	0:f1834a63f7c1	5717
Sergunb	0:f1834a63f7c1	5718	/***************** Bit definition for USB_EP7R register *****************/
Sergunb	0:f1834a63f7c1	5719	#define USB_EP7R_EA ((uint16_t)0x000F) /!< Endpoint Address /
Sergunb	0:f1834a63f7c1	5720
Sergunb	0:f1834a63f7c1	5721	#define USB_EP7R_STAT_TX ((uint16_t)0x0030) /!< STAT_TX[1:0] bits (Status bits, for transmission transfers) /
Sergunb	0:f1834a63f7c1	5722	#define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5723	#define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5724
Sergunb	0:f1834a63f7c1	5725	#define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /!< Data Toggle, for transmission transfers /
Sergunb	0:f1834a63f7c1	5726	#define USB_EP7R_CTR_TX ((uint16_t)0x0080) /!< Correct Transfer for transmission /
Sergunb	0:f1834a63f7c1	5727	#define USB_EP7R_EP_KIND ((uint16_t)0x0100) /!< Endpoint Kind /
Sergunb	0:f1834a63f7c1	5728
Sergunb	0:f1834a63f7c1	5729	#define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /!< EP_TYPE[1:0] bits (Endpoint type) /
Sergunb	0:f1834a63f7c1	5730	#define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5731	#define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5732
Sergunb	0:f1834a63f7c1	5733	#define USB_EP7R_SETUP ((uint16_t)0x0800) /!< Setup transaction completed /
Sergunb	0:f1834a63f7c1	5734
Sergunb	0:f1834a63f7c1	5735	#define USB_EP7R_STAT_RX ((uint16_t)0x3000) /!< STAT_RX[1:0] bits (Status bits, for reception transfers) /
Sergunb	0:f1834a63f7c1	5736	#define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5737	#define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5738
Sergunb	0:f1834a63f7c1	5739	#define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /!< Data Toggle, for reception transfers /
Sergunb	0:f1834a63f7c1	5740	#define USB_EP7R_CTR_RX ((uint16_t)0x8000) /!< Correct Transfer for reception /
Sergunb	0:f1834a63f7c1	5741
Sergunb	0:f1834a63f7c1	5742	/!< Common registers /
Sergunb	0:f1834a63f7c1	5743	/***************** Bit definition for USB_CNTR register *****************/
Sergunb	0:f1834a63f7c1	5744	#define USB_CNTR_FRES ((uint16_t)0x0001) /!< Force USB Reset /
Sergunb	0:f1834a63f7c1	5745	#define USB_CNTR_PDWN ((uint16_t)0x0002) /!< Power down /
Sergunb	0:f1834a63f7c1	5746	#define USB_CNTR_LP_MODE ((uint16_t)0x0004) /!< Low-power mode /
Sergunb	0:f1834a63f7c1	5747	#define USB_CNTR_FSUSP ((uint16_t)0x0008) /!< Force suspend /
Sergunb	0:f1834a63f7c1	5748	#define USB_CNTR_RESUME ((uint16_t)0x0010) /!< Resume request /
Sergunb	0:f1834a63f7c1	5749	#define USB_CNTR_ESOFM ((uint16_t)0x0100) /!< Expected Start Of Frame Interrupt Mask /
Sergunb	0:f1834a63f7c1	5750	#define USB_CNTR_SOFM ((uint16_t)0x0200) /!< Start Of Frame Interrupt Mask /
Sergunb	0:f1834a63f7c1	5751	#define USB_CNTR_RESETM ((uint16_t)0x0400) /!< RESET Interrupt Mask /
Sergunb	0:f1834a63f7c1	5752	#define USB_CNTR_SUSPM ((uint16_t)0x0800) /!< Suspend mode Interrupt Mask /
Sergunb	0:f1834a63f7c1	5753	#define USB_CNTR_WKUPM ((uint16_t)0x1000) /!< Wakeup Interrupt Mask /
Sergunb	0:f1834a63f7c1	5754	#define USB_CNTR_ERRM ((uint16_t)0x2000) /!< Error Interrupt Mask /
Sergunb	0:f1834a63f7c1	5755	#define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /!< Packet Memory Area Over / Underrun Interrupt Mask /
Sergunb	0:f1834a63f7c1	5756	#define USB_CNTR_CTRM ((uint16_t)0x8000) /!< Correct Transfer Interrupt Mask /
Sergunb	0:f1834a63f7c1	5757
Sergunb	0:f1834a63f7c1	5758	/***************** Bit definition for USB_ISTR register *****************/
Sergunb	0:f1834a63f7c1	5759	#define USB_ISTR_EP_ID ((uint16_t)0x000F) /!< Endpoint Identifier /
Sergunb	0:f1834a63f7c1	5760	#define USB_ISTR_DIR ((uint16_t)0x0010) /!< Direction of transaction /
Sergunb	0:f1834a63f7c1	5761	#define USB_ISTR_ESOF ((uint16_t)0x0100) /!< Expected Start Of Frame /
Sergunb	0:f1834a63f7c1	5762	#define USB_ISTR_SOF ((uint16_t)0x0200) /!< Start Of Frame /
Sergunb	0:f1834a63f7c1	5763	#define USB_ISTR_RESET ((uint16_t)0x0400) /!< USB RESET request /
Sergunb	0:f1834a63f7c1	5764	#define USB_ISTR_SUSP ((uint16_t)0x0800) /!< Suspend mode request /
Sergunb	0:f1834a63f7c1	5765	#define USB_ISTR_WKUP ((uint16_t)0x1000) /!< Wake up /
Sergunb	0:f1834a63f7c1	5766	#define USB_ISTR_ERR ((uint16_t)0x2000) /!< Error /
Sergunb	0:f1834a63f7c1	5767	#define USB_ISTR_PMAOVR ((uint16_t)0x4000) /!< Packet Memory Area Over / Underrun /
Sergunb	0:f1834a63f7c1	5768	#define USB_ISTR_CTR ((uint16_t)0x8000) /!< Correct Transfer /
Sergunb	0:f1834a63f7c1	5769
Sergunb	0:f1834a63f7c1	5770	/***************** Bit definition for USB_FNR register ******************/
Sergunb	0:f1834a63f7c1	5771	#define USB_FNR_FN ((uint16_t)0x07FF) /!< Frame Number /
Sergunb	0:f1834a63f7c1	5772	#define USB_FNR_LSOF ((uint16_t)0x1800) /!< Lost SOF /
Sergunb	0:f1834a63f7c1	5773	#define USB_FNR_LCK ((uint16_t)0x2000) /!< Locked /
Sergunb	0:f1834a63f7c1	5774	#define USB_FNR_RXDM ((uint16_t)0x4000) /!< Receive Data - Line Status /
Sergunb	0:f1834a63f7c1	5775	#define USB_FNR_RXDP ((uint16_t)0x8000) /!< Receive Data + Line Status /
Sergunb	0:f1834a63f7c1	5776
Sergunb	0:f1834a63f7c1	5777	/**************** Bit definition for USB_DADDR register *****************/
Sergunb	0:f1834a63f7c1	5778	#define USB_DADDR_ADD ((uint8_t)0x7F) /!< ADD[6:0] bits (Device Address) /
Sergunb	0:f1834a63f7c1	5779	#define USB_DADDR_ADD0 ((uint8_t)0x01) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5780	#define USB_DADDR_ADD1 ((uint8_t)0x02) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5781	#define USB_DADDR_ADD2 ((uint8_t)0x04) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5782	#define USB_DADDR_ADD3 ((uint8_t)0x08) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5783	#define USB_DADDR_ADD4 ((uint8_t)0x10) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5784	#define USB_DADDR_ADD5 ((uint8_t)0x20) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	5785	#define USB_DADDR_ADD6 ((uint8_t)0x40) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	5786
Sergunb	0:f1834a63f7c1	5787	#define USB_DADDR_EF ((uint8_t)0x80) /!< Enable Function /
Sergunb	0:f1834a63f7c1	5788
Sergunb	0:f1834a63f7c1	5789	/**************** Bit definition for USB_BTABLE register ****************/
Sergunb	0:f1834a63f7c1	5790	#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /!< Buffer Table /
Sergunb	0:f1834a63f7c1	5791
Sergunb	0:f1834a63f7c1	5792	/!< Buffer descriptor table /
Sergunb	0:f1834a63f7c1	5793	/*************** Bit definition for USB_ADDR0_TX register ***************/
Sergunb	0:f1834a63f7c1	5794	#define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 0 /
Sergunb	0:f1834a63f7c1	5795
Sergunb	0:f1834a63f7c1	5796	/*************** Bit definition for USB_ADDR1_TX register ***************/
Sergunb	0:f1834a63f7c1	5797	#define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 1 /
Sergunb	0:f1834a63f7c1	5798
Sergunb	0:f1834a63f7c1	5799	/*************** Bit definition for USB_ADDR2_TX register ***************/
Sergunb	0:f1834a63f7c1	5800	#define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 2 /
Sergunb	0:f1834a63f7c1	5801
Sergunb	0:f1834a63f7c1	5802	/*************** Bit definition for USB_ADDR3_TX register ***************/
Sergunb	0:f1834a63f7c1	5803	#define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 3 /
Sergunb	0:f1834a63f7c1	5804
Sergunb	0:f1834a63f7c1	5805	/*************** Bit definition for USB_ADDR4_TX register ***************/
Sergunb	0:f1834a63f7c1	5806	#define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 4 /
Sergunb	0:f1834a63f7c1	5807
Sergunb	0:f1834a63f7c1	5808	/*************** Bit definition for USB_ADDR5_TX register ***************/
Sergunb	0:f1834a63f7c1	5809	#define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 5 /
Sergunb	0:f1834a63f7c1	5810
Sergunb	0:f1834a63f7c1	5811	/*************** Bit definition for USB_ADDR6_TX register ***************/
Sergunb	0:f1834a63f7c1	5812	#define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 6 /
Sergunb	0:f1834a63f7c1	5813
Sergunb	0:f1834a63f7c1	5814	/*************** Bit definition for USB_ADDR7_TX register ***************/
Sergunb	0:f1834a63f7c1	5815	#define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /!< Transmission Buffer Address 7 /
Sergunb	0:f1834a63f7c1	5816
Sergunb	0:f1834a63f7c1	5817	/----------------------------------------------------------------------------/
Sergunb	0:f1834a63f7c1	5818
Sergunb	0:f1834a63f7c1	5819	/*************** Bit definition for USB_COUNT0_TX register **************/
Sergunb	0:f1834a63f7c1	5820	#define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 0 /
Sergunb	0:f1834a63f7c1	5821
Sergunb	0:f1834a63f7c1	5822	/*************** Bit definition for USB_COUNT1_TX register **************/
Sergunb	0:f1834a63f7c1	5823	#define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 1 /
Sergunb	0:f1834a63f7c1	5824
Sergunb	0:f1834a63f7c1	5825	/*************** Bit definition for USB_COUNT2_TX register **************/
Sergunb	0:f1834a63f7c1	5826	#define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 2 /
Sergunb	0:f1834a63f7c1	5827
Sergunb	0:f1834a63f7c1	5828	/*************** Bit definition for USB_COUNT3_TX register **************/
Sergunb	0:f1834a63f7c1	5829	#define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 3 /
Sergunb	0:f1834a63f7c1	5830
Sergunb	0:f1834a63f7c1	5831	/*************** Bit definition for USB_COUNT4_TX register **************/
Sergunb	0:f1834a63f7c1	5832	#define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 4 /
Sergunb	0:f1834a63f7c1	5833
Sergunb	0:f1834a63f7c1	5834	/*************** Bit definition for USB_COUNT5_TX register **************/
Sergunb	0:f1834a63f7c1	5835	#define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 5 /
Sergunb	0:f1834a63f7c1	5836
Sergunb	0:f1834a63f7c1	5837	/*************** Bit definition for USB_COUNT6_TX register **************/
Sergunb	0:f1834a63f7c1	5838	#define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 6 /
Sergunb	0:f1834a63f7c1	5839
Sergunb	0:f1834a63f7c1	5840	/*************** Bit definition for USB_COUNT7_TX register **************/
Sergunb	0:f1834a63f7c1	5841	#define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /!< Transmission Byte Count 7 /
Sergunb	0:f1834a63f7c1	5842
Sergunb	0:f1834a63f7c1	5843	/----------------------------------------------------------------------------/
Sergunb	0:f1834a63f7c1	5844
Sergunb	0:f1834a63f7c1	5845	/************** Bit definition for USB_COUNT0_TX_0 register *************/
Sergunb	0:f1834a63f7c1	5846	#define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 0 (low) /
Sergunb	0:f1834a63f7c1	5847
Sergunb	0:f1834a63f7c1	5848	/************** Bit definition for USB_COUNT0_TX_1 register *************/
Sergunb	0:f1834a63f7c1	5849	#define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 0 (high) /
Sergunb	0:f1834a63f7c1	5850
Sergunb	0:f1834a63f7c1	5851	/************** Bit definition for USB_COUNT1_TX_0 register *************/
Sergunb	0:f1834a63f7c1	5852	#define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 1 (low) /
Sergunb	0:f1834a63f7c1	5853
Sergunb	0:f1834a63f7c1	5854	/************** Bit definition for USB_COUNT1_TX_1 register *************/
Sergunb	0:f1834a63f7c1	5855	#define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 1 (high) /
Sergunb	0:f1834a63f7c1	5856
Sergunb	0:f1834a63f7c1	5857	/************** Bit definition for USB_COUNT2_TX_0 register *************/
Sergunb	0:f1834a63f7c1	5858	#define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 2 (low) /
Sergunb	0:f1834a63f7c1	5859
Sergunb	0:f1834a63f7c1	5860	/************** Bit definition for USB_COUNT2_TX_1 register *************/
Sergunb	0:f1834a63f7c1	5861	#define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 2 (high) /
Sergunb	0:f1834a63f7c1	5862
Sergunb	0:f1834a63f7c1	5863	/************** Bit definition for USB_COUNT3_TX_0 register *************/
Sergunb	0:f1834a63f7c1	5864	#define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /!< Transmission Byte Count 3 (low) /
Sergunb	0:f1834a63f7c1	5865
Sergunb	0:f1834a63f7c1	5866	/************** Bit definition for USB_COUNT3_TX_1 register *************/
Sergunb	0:f1834a63f7c1	5867	#define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /!< Transmission Byte Count 3 (high) /
Sergunb	0:f1834a63f7c1	5868
Sergunb	0:f1834a63f7c1	5869	/************** Bit definition for USB_COUNT4_TX_0 register *************/
Sergunb	0:f1834a63f7c1	5870	#define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 4 (low) /
Sergunb	0:f1834a63f7c1	5871
Sergunb	0:f1834a63f7c1	5872	/************** Bit definition for USB_COUNT4_TX_1 register *************/
Sergunb	0:f1834a63f7c1	5873	#define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 4 (high) /
Sergunb	0:f1834a63f7c1	5874
Sergunb	0:f1834a63f7c1	5875	/************** Bit definition for USB_COUNT5_TX_0 register *************/
Sergunb	0:f1834a63f7c1	5876	#define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 5 (low) /
Sergunb	0:f1834a63f7c1	5877
Sergunb	0:f1834a63f7c1	5878	/************** Bit definition for USB_COUNT5_TX_1 register *************/
Sergunb	0:f1834a63f7c1	5879	#define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 5 (high) /
Sergunb	0:f1834a63f7c1	5880
Sergunb	0:f1834a63f7c1	5881	/************** Bit definition for USB_COUNT6_TX_0 register *************/
Sergunb	0:f1834a63f7c1	5882	#define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 6 (low) /
Sergunb	0:f1834a63f7c1	5883
Sergunb	0:f1834a63f7c1	5884	/************** Bit definition for USB_COUNT6_TX_1 register *************/
Sergunb	0:f1834a63f7c1	5885	#define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 6 (high) /
Sergunb	0:f1834a63f7c1	5886
Sergunb	0:f1834a63f7c1	5887	/************** Bit definition for USB_COUNT7_TX_0 register *************/
Sergunb	0:f1834a63f7c1	5888	#define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /!< Transmission Byte Count 7 (low) /
Sergunb	0:f1834a63f7c1	5889
Sergunb	0:f1834a63f7c1	5890	/************** Bit definition for USB_COUNT7_TX_1 register *************/
Sergunb	0:f1834a63f7c1	5891	#define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /!< Transmission Byte Count 7 (high) /
Sergunb	0:f1834a63f7c1	5892
Sergunb	0:f1834a63f7c1	5893	/----------------------------------------------------------------------------/
Sergunb	0:f1834a63f7c1	5894
Sergunb	0:f1834a63f7c1	5895	/*************** Bit definition for USB_ADDR0_RX register ***************/
Sergunb	0:f1834a63f7c1	5896	#define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 0 /
Sergunb	0:f1834a63f7c1	5897
Sergunb	0:f1834a63f7c1	5898	/*************** Bit definition for USB_ADDR1_RX register ***************/
Sergunb	0:f1834a63f7c1	5899	#define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 1 /
Sergunb	0:f1834a63f7c1	5900
Sergunb	0:f1834a63f7c1	5901	/*************** Bit definition for USB_ADDR2_RX register ***************/
Sergunb	0:f1834a63f7c1	5902	#define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 2 /
Sergunb	0:f1834a63f7c1	5903
Sergunb	0:f1834a63f7c1	5904	/*************** Bit definition for USB_ADDR3_RX register ***************/
Sergunb	0:f1834a63f7c1	5905	#define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 3 /
Sergunb	0:f1834a63f7c1	5906
Sergunb	0:f1834a63f7c1	5907	/*************** Bit definition for USB_ADDR4_RX register ***************/
Sergunb	0:f1834a63f7c1	5908	#define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 4 /
Sergunb	0:f1834a63f7c1	5909
Sergunb	0:f1834a63f7c1	5910	/*************** Bit definition for USB_ADDR5_RX register ***************/
Sergunb	0:f1834a63f7c1	5911	#define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 5 /
Sergunb	0:f1834a63f7c1	5912
Sergunb	0:f1834a63f7c1	5913	/*************** Bit definition for USB_ADDR6_RX register ***************/
Sergunb	0:f1834a63f7c1	5914	#define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 6 /
Sergunb	0:f1834a63f7c1	5915
Sergunb	0:f1834a63f7c1	5916	/*************** Bit definition for USB_ADDR7_RX register ***************/
Sergunb	0:f1834a63f7c1	5917	#define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /!< Reception Buffer Address 7 /
Sergunb	0:f1834a63f7c1	5918
Sergunb	0:f1834a63f7c1	5919	/----------------------------------------------------------------------------/
Sergunb	0:f1834a63f7c1	5920
Sergunb	0:f1834a63f7c1	5921	/*************** Bit definition for USB_COUNT0_RX register **************/
Sergunb	0:f1834a63f7c1	5922	#define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
Sergunb	0:f1834a63f7c1	5923
Sergunb	0:f1834a63f7c1	5924	#define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Sergunb	0:f1834a63f7c1	5925	#define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5926	#define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5927	#define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5928	#define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5929	#define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5930
Sergunb	0:f1834a63f7c1	5931	#define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
Sergunb	0:f1834a63f7c1	5932
Sergunb	0:f1834a63f7c1	5933	/*************** Bit definition for USB_COUNT1_RX register **************/
Sergunb	0:f1834a63f7c1	5934	#define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
Sergunb	0:f1834a63f7c1	5935
Sergunb	0:f1834a63f7c1	5936	#define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Sergunb	0:f1834a63f7c1	5937	#define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5938	#define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5939	#define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5940	#define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5941	#define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5942
Sergunb	0:f1834a63f7c1	5943	#define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
Sergunb	0:f1834a63f7c1	5944
Sergunb	0:f1834a63f7c1	5945	/*************** Bit definition for USB_COUNT2_RX register **************/
Sergunb	0:f1834a63f7c1	5946	#define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
Sergunb	0:f1834a63f7c1	5947
Sergunb	0:f1834a63f7c1	5948	#define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Sergunb	0:f1834a63f7c1	5949	#define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5950	#define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5951	#define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5952	#define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5953	#define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5954
Sergunb	0:f1834a63f7c1	5955	#define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
Sergunb	0:f1834a63f7c1	5956
Sergunb	0:f1834a63f7c1	5957	/*************** Bit definition for USB_COUNT3_RX register **************/
Sergunb	0:f1834a63f7c1	5958	#define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
Sergunb	0:f1834a63f7c1	5959
Sergunb	0:f1834a63f7c1	5960	#define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Sergunb	0:f1834a63f7c1	5961	#define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5962	#define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5963	#define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5964	#define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5965	#define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5966
Sergunb	0:f1834a63f7c1	5967	#define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
Sergunb	0:f1834a63f7c1	5968
Sergunb	0:f1834a63f7c1	5969	/*************** Bit definition for USB_COUNT4_RX register **************/
Sergunb	0:f1834a63f7c1	5970	#define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
Sergunb	0:f1834a63f7c1	5971
Sergunb	0:f1834a63f7c1	5972	#define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Sergunb	0:f1834a63f7c1	5973	#define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5974	#define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5975	#define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5976	#define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5977	#define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5978
Sergunb	0:f1834a63f7c1	5979	#define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
Sergunb	0:f1834a63f7c1	5980
Sergunb	0:f1834a63f7c1	5981	/*************** Bit definition for USB_COUNT5_RX register **************/
Sergunb	0:f1834a63f7c1	5982	#define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
Sergunb	0:f1834a63f7c1	5983
Sergunb	0:f1834a63f7c1	5984	#define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Sergunb	0:f1834a63f7c1	5985	#define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5986	#define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5987	#define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	5988	#define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	5989	#define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	5990
Sergunb	0:f1834a63f7c1	5991	#define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
Sergunb	0:f1834a63f7c1	5992
Sergunb	0:f1834a63f7c1	5993	/*************** Bit definition for USB_COUNT6_RX register **************/
Sergunb	0:f1834a63f7c1	5994	#define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
Sergunb	0:f1834a63f7c1	5995
Sergunb	0:f1834a63f7c1	5996	#define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Sergunb	0:f1834a63f7c1	5997	#define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	5998	#define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	5999	#define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6000	#define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6001	#define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6002
Sergunb	0:f1834a63f7c1	6003	#define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
Sergunb	0:f1834a63f7c1	6004
Sergunb	0:f1834a63f7c1	6005	/*************** Bit definition for USB_COUNT7_RX register **************/
Sergunb	0:f1834a63f7c1	6006	#define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /!< Reception Byte Count /
Sergunb	0:f1834a63f7c1	6007
Sergunb	0:f1834a63f7c1	6008	#define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /!< NUM_BLOCK[4:0] bits (Number of blocks) /
Sergunb	0:f1834a63f7c1	6009	#define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6010	#define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6011	#define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6012	#define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6013	#define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6014
Sergunb	0:f1834a63f7c1	6015	#define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /!< BLock SIZE /
Sergunb	0:f1834a63f7c1	6016
Sergunb	0:f1834a63f7c1	6017	/----------------------------------------------------------------------------/
Sergunb	0:f1834a63f7c1	6018
Sergunb	0:f1834a63f7c1	6019	/************** Bit definition for USB_COUNT0_RX_0 register *************/
Sergunb	0:f1834a63f7c1	6020	#define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Sergunb	0:f1834a63f7c1	6021
Sergunb	0:f1834a63f7c1	6022	#define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Sergunb	0:f1834a63f7c1	6023	#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6024	#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6025	#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6026	#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6027	#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6028
Sergunb	0:f1834a63f7c1	6029	#define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Sergunb	0:f1834a63f7c1	6030
Sergunb	0:f1834a63f7c1	6031	/************** Bit definition for USB_COUNT0_RX_1 register *************/
Sergunb	0:f1834a63f7c1	6032	#define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Sergunb	0:f1834a63f7c1	6033
Sergunb	0:f1834a63f7c1	6034	#define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Sergunb	0:f1834a63f7c1	6035	#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6036	#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6037	#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6038	#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6039	#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6040
Sergunb	0:f1834a63f7c1	6041	#define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Sergunb	0:f1834a63f7c1	6042
Sergunb	0:f1834a63f7c1	6043	/************** Bit definition for USB_COUNT1_RX_0 register *************/
Sergunb	0:f1834a63f7c1	6044	#define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Sergunb	0:f1834a63f7c1	6045
Sergunb	0:f1834a63f7c1	6046	#define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Sergunb	0:f1834a63f7c1	6047	#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6048	#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6049	#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6050	#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6051	#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6052
Sergunb	0:f1834a63f7c1	6053	#define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Sergunb	0:f1834a63f7c1	6054
Sergunb	0:f1834a63f7c1	6055	/************** Bit definition for USB_COUNT1_RX_1 register *************/
Sergunb	0:f1834a63f7c1	6056	#define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Sergunb	0:f1834a63f7c1	6057
Sergunb	0:f1834a63f7c1	6058	#define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Sergunb	0:f1834a63f7c1	6059	#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6060	#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6061	#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6062	#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6063	#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6064
Sergunb	0:f1834a63f7c1	6065	#define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Sergunb	0:f1834a63f7c1	6066
Sergunb	0:f1834a63f7c1	6067	/************** Bit definition for USB_COUNT2_RX_0 register *************/
Sergunb	0:f1834a63f7c1	6068	#define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Sergunb	0:f1834a63f7c1	6069
Sergunb	0:f1834a63f7c1	6070	#define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Sergunb	0:f1834a63f7c1	6071	#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6072	#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6073	#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6074	#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6075	#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6076
Sergunb	0:f1834a63f7c1	6077	#define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Sergunb	0:f1834a63f7c1	6078
Sergunb	0:f1834a63f7c1	6079	/************** Bit definition for USB_COUNT2_RX_1 register *************/
Sergunb	0:f1834a63f7c1	6080	#define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Sergunb	0:f1834a63f7c1	6081
Sergunb	0:f1834a63f7c1	6082	#define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Sergunb	0:f1834a63f7c1	6083	#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6084	#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6085	#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6086	#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6087	#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6088
Sergunb	0:f1834a63f7c1	6089	#define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Sergunb	0:f1834a63f7c1	6090
Sergunb	0:f1834a63f7c1	6091	/************** Bit definition for USB_COUNT3_RX_0 register *************/
Sergunb	0:f1834a63f7c1	6092	#define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Sergunb	0:f1834a63f7c1	6093
Sergunb	0:f1834a63f7c1	6094	#define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Sergunb	0:f1834a63f7c1	6095	#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6096	#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6097	#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6098	#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6099	#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6100
Sergunb	0:f1834a63f7c1	6101	#define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Sergunb	0:f1834a63f7c1	6102
Sergunb	0:f1834a63f7c1	6103	/************** Bit definition for USB_COUNT3_RX_1 register *************/
Sergunb	0:f1834a63f7c1	6104	#define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Sergunb	0:f1834a63f7c1	6105
Sergunb	0:f1834a63f7c1	6106	#define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Sergunb	0:f1834a63f7c1	6107	#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6108	#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6109	#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6110	#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6111	#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6112
Sergunb	0:f1834a63f7c1	6113	#define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Sergunb	0:f1834a63f7c1	6114
Sergunb	0:f1834a63f7c1	6115	/************** Bit definition for USB_COUNT4_RX_0 register *************/
Sergunb	0:f1834a63f7c1	6116	#define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Sergunb	0:f1834a63f7c1	6117
Sergunb	0:f1834a63f7c1	6118	#define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Sergunb	0:f1834a63f7c1	6119	#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6120	#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6121	#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6122	#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6123	#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6124
Sergunb	0:f1834a63f7c1	6125	#define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Sergunb	0:f1834a63f7c1	6126
Sergunb	0:f1834a63f7c1	6127	/************** Bit definition for USB_COUNT4_RX_1 register *************/
Sergunb	0:f1834a63f7c1	6128	#define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Sergunb	0:f1834a63f7c1	6129
Sergunb	0:f1834a63f7c1	6130	#define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Sergunb	0:f1834a63f7c1	6131	#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6132	#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6133	#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6134	#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6135	#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6136
Sergunb	0:f1834a63f7c1	6137	#define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Sergunb	0:f1834a63f7c1	6138
Sergunb	0:f1834a63f7c1	6139	/************** Bit definition for USB_COUNT5_RX_0 register *************/
Sergunb	0:f1834a63f7c1	6140	#define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Sergunb	0:f1834a63f7c1	6141
Sergunb	0:f1834a63f7c1	6142	#define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Sergunb	0:f1834a63f7c1	6143	#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6144	#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6145	#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6146	#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6147	#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6148
Sergunb	0:f1834a63f7c1	6149	#define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Sergunb	0:f1834a63f7c1	6150
Sergunb	0:f1834a63f7c1	6151	/************** Bit definition for USB_COUNT5_RX_1 register *************/
Sergunb	0:f1834a63f7c1	6152	#define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Sergunb	0:f1834a63f7c1	6153
Sergunb	0:f1834a63f7c1	6154	#define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Sergunb	0:f1834a63f7c1	6155	#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6156	#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6157	#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6158	#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6159	#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6160
Sergunb	0:f1834a63f7c1	6161	#define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Sergunb	0:f1834a63f7c1	6162
Sergunb	0:f1834a63f7c1	6163	/************* Bit definition for USB_COUNT6_RX_0 register *************/
Sergunb	0:f1834a63f7c1	6164	#define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Sergunb	0:f1834a63f7c1	6165
Sergunb	0:f1834a63f7c1	6166	#define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Sergunb	0:f1834a63f7c1	6167	#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6168	#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6169	#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6170	#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6171	#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6172
Sergunb	0:f1834a63f7c1	6173	#define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Sergunb	0:f1834a63f7c1	6174
Sergunb	0:f1834a63f7c1	6175	/************** Bit definition for USB_COUNT6_RX_1 register *************/
Sergunb	0:f1834a63f7c1	6176	#define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Sergunb	0:f1834a63f7c1	6177
Sergunb	0:f1834a63f7c1	6178	#define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Sergunb	0:f1834a63f7c1	6179	#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6180	#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6181	#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6182	#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6183	#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6184
Sergunb	0:f1834a63f7c1	6185	#define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Sergunb	0:f1834a63f7c1	6186
Sergunb	0:f1834a63f7c1	6187	/************* Bit definition for USB_COUNT7_RX_0 register **************/
Sergunb	0:f1834a63f7c1	6188	#define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /!< Reception Byte Count (low) /
Sergunb	0:f1834a63f7c1	6189
Sergunb	0:f1834a63f7c1	6190	#define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) /
Sergunb	0:f1834a63f7c1	6191	#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6192	#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6193	#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6194	#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6195	#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6196
Sergunb	0:f1834a63f7c1	6197	#define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /!< BLock SIZE (low) /
Sergunb	0:f1834a63f7c1	6198
Sergunb	0:f1834a63f7c1	6199	/************* Bit definition for USB_COUNT7_RX_1 register **************/
Sergunb	0:f1834a63f7c1	6200	#define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /!< Reception Byte Count (high) /
Sergunb	0:f1834a63f7c1	6201
Sergunb	0:f1834a63f7c1	6202	#define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) /
Sergunb	0:f1834a63f7c1	6203	#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6204	#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6205	#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6206	#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	6207	#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	6208
Sergunb	0:f1834a63f7c1	6209	#define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /!< BLock SIZE (high) /
Sergunb	0:f1834a63f7c1	6210
Sergunb	0:f1834a63f7c1	6211	/******************************************************************************/
Sergunb	0:f1834a63f7c1	6212	/* */
Sergunb	0:f1834a63f7c1	6213	/* Controller Area Network */
Sergunb	0:f1834a63f7c1	6214	/* */
Sergunb	0:f1834a63f7c1	6215	/******************************************************************************/
Sergunb	0:f1834a63f7c1	6216
Sergunb	0:f1834a63f7c1	6217	/!< CAN control and status registers /
Sergunb	0:f1834a63f7c1	6218	/***************** Bit definition for CAN_MCR register ******************/
Sergunb	0:f1834a63f7c1	6219	#define CAN_MCR_INRQ ((uint16_t)0x0001) /!< Initialization Request /
Sergunb	0:f1834a63f7c1	6220	#define CAN_MCR_SLEEP ((uint16_t)0x0002) /!< Sleep Mode Request /
Sergunb	0:f1834a63f7c1	6221	#define CAN_MCR_TXFP ((uint16_t)0x0004) /!< Transmit FIFO Priority /
Sergunb	0:f1834a63f7c1	6222	#define CAN_MCR_RFLM ((uint16_t)0x0008) /!< Receive FIFO Locked Mode /
Sergunb	0:f1834a63f7c1	6223	#define CAN_MCR_NART ((uint16_t)0x0010) /!< No Automatic Retransmission /
Sergunb	0:f1834a63f7c1	6224	#define CAN_MCR_AWUM ((uint16_t)0x0020) /!< Automatic Wakeup Mode /
Sergunb	0:f1834a63f7c1	6225	#define CAN_MCR_ABOM ((uint16_t)0x0040) /!< Automatic Bus-Off Management /
Sergunb	0:f1834a63f7c1	6226	#define CAN_MCR_TTCM ((uint16_t)0x0080) /!< Time Triggered Communication Mode /
Sergunb	0:f1834a63f7c1	6227	#define CAN_MCR_RESET ((uint16_t)0x8000) /!< CAN software master reset /
Sergunb	0:f1834a63f7c1	6228
Sergunb	0:f1834a63f7c1	6229	/***************** Bit definition for CAN_MSR register ******************/
Sergunb	0:f1834a63f7c1	6230	#define CAN_MSR_INAK ((uint16_t)0x0001) /!< Initialization Acknowledge /
Sergunb	0:f1834a63f7c1	6231	#define CAN_MSR_SLAK ((uint16_t)0x0002) /!< Sleep Acknowledge /
Sergunb	0:f1834a63f7c1	6232	#define CAN_MSR_ERRI ((uint16_t)0x0004) /!< Error Interrupt /
Sergunb	0:f1834a63f7c1	6233	#define CAN_MSR_WKUI ((uint16_t)0x0008) /!< Wakeup Interrupt /
Sergunb	0:f1834a63f7c1	6234	#define CAN_MSR_SLAKI ((uint16_t)0x0010) /!< Sleep Acknowledge Interrupt /
Sergunb	0:f1834a63f7c1	6235	#define CAN_MSR_TXM ((uint16_t)0x0100) /!< Transmit Mode /
Sergunb	0:f1834a63f7c1	6236	#define CAN_MSR_RXM ((uint16_t)0x0200) /!< Receive Mode /
Sergunb	0:f1834a63f7c1	6237	#define CAN_MSR_SAMP ((uint16_t)0x0400) /!< Last Sample Point /
Sergunb	0:f1834a63f7c1	6238	#define CAN_MSR_RX ((uint16_t)0x0800) /!< CAN Rx Signal /
Sergunb	0:f1834a63f7c1	6239
Sergunb	0:f1834a63f7c1	6240	/***************** Bit definition for CAN_TSR register ******************/
Sergunb	0:f1834a63f7c1	6241	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!< Request Completed Mailbox0 /
Sergunb	0:f1834a63f7c1	6242	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!< Transmission OK of Mailbox0 /
Sergunb	0:f1834a63f7c1	6243	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!< Arbitration Lost for Mailbox0 /
Sergunb	0:f1834a63f7c1	6244	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!< Transmission Error of Mailbox0 /
Sergunb	0:f1834a63f7c1	6245	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!< Abort Request for Mailbox0 /
Sergunb	0:f1834a63f7c1	6246	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!< Request Completed Mailbox1 /
Sergunb	0:f1834a63f7c1	6247	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!< Transmission OK of Mailbox1 /
Sergunb	0:f1834a63f7c1	6248	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!< Arbitration Lost for Mailbox1 /
Sergunb	0:f1834a63f7c1	6249	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!< Transmission Error of Mailbox1 /
Sergunb	0:f1834a63f7c1	6250	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!< Abort Request for Mailbox 1 /
Sergunb	0:f1834a63f7c1	6251	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!< Request Completed Mailbox2 /
Sergunb	0:f1834a63f7c1	6252	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!< Transmission OK of Mailbox 2 /
Sergunb	0:f1834a63f7c1	6253	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!< Arbitration Lost for mailbox 2 /
Sergunb	0:f1834a63f7c1	6254	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!< Transmission Error of Mailbox 2 /
Sergunb	0:f1834a63f7c1	6255	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!< Abort Request for Mailbox 2 /
Sergunb	0:f1834a63f7c1	6256	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!< Mailbox Code /
Sergunb	0:f1834a63f7c1	6257
Sergunb	0:f1834a63f7c1	6258	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!< TME[2:0] bits /
Sergunb	0:f1834a63f7c1	6259	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!< Transmit Mailbox 0 Empty /
Sergunb	0:f1834a63f7c1	6260	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!< Transmit Mailbox 1 Empty /
Sergunb	0:f1834a63f7c1	6261	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!< Transmit Mailbox 2 Empty /
Sergunb	0:f1834a63f7c1	6262
Sergunb	0:f1834a63f7c1	6263	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!< LOW[2:0] bits /
Sergunb	0:f1834a63f7c1	6264	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!< Lowest Priority Flag for Mailbox 0 /
Sergunb	0:f1834a63f7c1	6265	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!< Lowest Priority Flag for Mailbox 1 /
Sergunb	0:f1834a63f7c1	6266	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!< Lowest Priority Flag for Mailbox 2 /
Sergunb	0:f1834a63f7c1	6267
Sergunb	0:f1834a63f7c1	6268	/***************** Bit definition for CAN_RF0R register *****************/
Sergunb	0:f1834a63f7c1	6269	#define CAN_RF0R_FMP0 ((uint8_t)0x03) /!< FIFO 0 Message Pending /
Sergunb	0:f1834a63f7c1	6270	#define CAN_RF0R_FULL0 ((uint8_t)0x08) /!< FIFO 0 Full /
Sergunb	0:f1834a63f7c1	6271	#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /!< FIFO 0 Overrun /
Sergunb	0:f1834a63f7c1	6272	#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /!< Release FIFO 0 Output Mailbox /
Sergunb	0:f1834a63f7c1	6273
Sergunb	0:f1834a63f7c1	6274	/***************** Bit definition for CAN_RF1R register *****************/
Sergunb	0:f1834a63f7c1	6275	#define CAN_RF1R_FMP1 ((uint8_t)0x03) /!< FIFO 1 Message Pending /
Sergunb	0:f1834a63f7c1	6276	#define CAN_RF1R_FULL1 ((uint8_t)0x08) /!< FIFO 1 Full /
Sergunb	0:f1834a63f7c1	6277	#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /!< FIFO 1 Overrun /
Sergunb	0:f1834a63f7c1	6278	#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /!< Release FIFO 1 Output Mailbox /
Sergunb	0:f1834a63f7c1	6279
Sergunb	0:f1834a63f7c1	6280	/****************** Bit definition for CAN_IER register *****************/
Sergunb	0:f1834a63f7c1	6281	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!< Transmit Mailbox Empty Interrupt Enable /
Sergunb	0:f1834a63f7c1	6282	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!< FIFO Message Pending Interrupt Enable /
Sergunb	0:f1834a63f7c1	6283	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!< FIFO Full Interrupt Enable /
Sergunb	0:f1834a63f7c1	6284	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!< FIFO Overrun Interrupt Enable /
Sergunb	0:f1834a63f7c1	6285	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!< FIFO Message Pending Interrupt Enable /
Sergunb	0:f1834a63f7c1	6286	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!< FIFO Full Interrupt Enable /
Sergunb	0:f1834a63f7c1	6287	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!< FIFO Overrun Interrupt Enable /
Sergunb	0:f1834a63f7c1	6288	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!< Error Warning Interrupt Enable /
Sergunb	0:f1834a63f7c1	6289	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!< Error Passive Interrupt Enable /
Sergunb	0:f1834a63f7c1	6290	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!< Bus-Off Interrupt Enable /
Sergunb	0:f1834a63f7c1	6291	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!< Last Error Code Interrupt Enable /
Sergunb	0:f1834a63f7c1	6292	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!< Error Interrupt Enable /
Sergunb	0:f1834a63f7c1	6293	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!< Wakeup Interrupt Enable /
Sergunb	0:f1834a63f7c1	6294	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!< Sleep Interrupt Enable /
Sergunb	0:f1834a63f7c1	6295
Sergunb	0:f1834a63f7c1	6296	/****************** Bit definition for CAN_ESR register *****************/
Sergunb	0:f1834a63f7c1	6297	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!< Error Warning Flag /
Sergunb	0:f1834a63f7c1	6298	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!< Error Passive Flag /
Sergunb	0:f1834a63f7c1	6299	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!< Bus-Off Flag /
Sergunb	0:f1834a63f7c1	6300
Sergunb	0:f1834a63f7c1	6301	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!< LEC[2:0] bits (Last Error Code) /
Sergunb	0:f1834a63f7c1	6302	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	6303	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	6304	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	6305
Sergunb	0:f1834a63f7c1	6306	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!< Least significant byte of the 9-bit Transmit Error Counter /
Sergunb	0:f1834a63f7c1	6307	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!< Receive Error Counter /
Sergunb	0:f1834a63f7c1	6308
Sergunb	0:f1834a63f7c1	6309	/***************** Bit definition for CAN_BTR register ******************/
Sergunb	0:f1834a63f7c1	6310	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!< Baud Rate Prescaler /
Sergunb	0:f1834a63f7c1	6311	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!< Time Segment 1 /
Sergunb	0:f1834a63f7c1	6312	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!< Time Segment 2 /
Sergunb	0:f1834a63f7c1	6313	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!< Resynchronization Jump Width /
Sergunb	0:f1834a63f7c1	6314	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!< Loop Back Mode (Debug) /
Sergunb	0:f1834a63f7c1	6315	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!< Silent Mode /
Sergunb	0:f1834a63f7c1	6316
Sergunb	0:f1834a63f7c1	6317	/!< Mailbox registers /
Sergunb	0:f1834a63f7c1	6318	/**************** Bit definition for CAN_TI0R register ******************/
Sergunb	0:f1834a63f7c1	6319	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
Sergunb	0:f1834a63f7c1	6320	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
Sergunb	0:f1834a63f7c1	6321	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
Sergunb	0:f1834a63f7c1	6322	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
Sergunb	0:f1834a63f7c1	6323	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
Sergunb	0:f1834a63f7c1	6324
Sergunb	0:f1834a63f7c1	6325	/**************** Bit definition for CAN_TDT0R register *****************/
Sergunb	0:f1834a63f7c1	6326	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
Sergunb	0:f1834a63f7c1	6327	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
Sergunb	0:f1834a63f7c1	6328	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
Sergunb	0:f1834a63f7c1	6329
Sergunb	0:f1834a63f7c1	6330	/**************** Bit definition for CAN_TDL0R register *****************/
Sergunb	0:f1834a63f7c1	6331	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
Sergunb	0:f1834a63f7c1	6332	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
Sergunb	0:f1834a63f7c1	6333	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
Sergunb	0:f1834a63f7c1	6334	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
Sergunb	0:f1834a63f7c1	6335
Sergunb	0:f1834a63f7c1	6336	/**************** Bit definition for CAN_TDH0R register *****************/
Sergunb	0:f1834a63f7c1	6337	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
Sergunb	0:f1834a63f7c1	6338	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
Sergunb	0:f1834a63f7c1	6339	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
Sergunb	0:f1834a63f7c1	6340	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
Sergunb	0:f1834a63f7c1	6341
Sergunb	0:f1834a63f7c1	6342	/***************** Bit definition for CAN_TI1R register *****************/
Sergunb	0:f1834a63f7c1	6343	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
Sergunb	0:f1834a63f7c1	6344	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
Sergunb	0:f1834a63f7c1	6345	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
Sergunb	0:f1834a63f7c1	6346	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
Sergunb	0:f1834a63f7c1	6347	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
Sergunb	0:f1834a63f7c1	6348
Sergunb	0:f1834a63f7c1	6349	/***************** Bit definition for CAN_TDT1R register ****************/
Sergunb	0:f1834a63f7c1	6350	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
Sergunb	0:f1834a63f7c1	6351	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
Sergunb	0:f1834a63f7c1	6352	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
Sergunb	0:f1834a63f7c1	6353
Sergunb	0:f1834a63f7c1	6354	/***************** Bit definition for CAN_TDL1R register ****************/
Sergunb	0:f1834a63f7c1	6355	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
Sergunb	0:f1834a63f7c1	6356	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
Sergunb	0:f1834a63f7c1	6357	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
Sergunb	0:f1834a63f7c1	6358	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
Sergunb	0:f1834a63f7c1	6359
Sergunb	0:f1834a63f7c1	6360	/***************** Bit definition for CAN_TDH1R register ****************/
Sergunb	0:f1834a63f7c1	6361	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
Sergunb	0:f1834a63f7c1	6362	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
Sergunb	0:f1834a63f7c1	6363	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
Sergunb	0:f1834a63f7c1	6364	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
Sergunb	0:f1834a63f7c1	6365
Sergunb	0:f1834a63f7c1	6366	/***************** Bit definition for CAN_TI2R register *****************/
Sergunb	0:f1834a63f7c1	6367	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!< Transmit Mailbox Request /
Sergunb	0:f1834a63f7c1	6368	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
Sergunb	0:f1834a63f7c1	6369	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
Sergunb	0:f1834a63f7c1	6370	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
Sergunb	0:f1834a63f7c1	6371	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
Sergunb	0:f1834a63f7c1	6372
Sergunb	0:f1834a63f7c1	6373	/***************** Bit definition for CAN_TDT2R register ****************/
Sergunb	0:f1834a63f7c1	6374	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
Sergunb	0:f1834a63f7c1	6375	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!< Transmit Global Time /
Sergunb	0:f1834a63f7c1	6376	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
Sergunb	0:f1834a63f7c1	6377
Sergunb	0:f1834a63f7c1	6378	/***************** Bit definition for CAN_TDL2R register ****************/
Sergunb	0:f1834a63f7c1	6379	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
Sergunb	0:f1834a63f7c1	6380	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
Sergunb	0:f1834a63f7c1	6381	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
Sergunb	0:f1834a63f7c1	6382	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
Sergunb	0:f1834a63f7c1	6383
Sergunb	0:f1834a63f7c1	6384	/***************** Bit definition for CAN_TDH2R register ****************/
Sergunb	0:f1834a63f7c1	6385	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
Sergunb	0:f1834a63f7c1	6386	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
Sergunb	0:f1834a63f7c1	6387	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
Sergunb	0:f1834a63f7c1	6388	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
Sergunb	0:f1834a63f7c1	6389
Sergunb	0:f1834a63f7c1	6390	/***************** Bit definition for CAN_RI0R register *****************/
Sergunb	0:f1834a63f7c1	6391	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
Sergunb	0:f1834a63f7c1	6392	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
Sergunb	0:f1834a63f7c1	6393	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!< Extended Identifier /
Sergunb	0:f1834a63f7c1	6394	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
Sergunb	0:f1834a63f7c1	6395
Sergunb	0:f1834a63f7c1	6396	/***************** Bit definition for CAN_RDT0R register ****************/
Sergunb	0:f1834a63f7c1	6397	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
Sergunb	0:f1834a63f7c1	6398	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
Sergunb	0:f1834a63f7c1	6399	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
Sergunb	0:f1834a63f7c1	6400
Sergunb	0:f1834a63f7c1	6401	/***************** Bit definition for CAN_RDL0R register ****************/
Sergunb	0:f1834a63f7c1	6402	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
Sergunb	0:f1834a63f7c1	6403	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
Sergunb	0:f1834a63f7c1	6404	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
Sergunb	0:f1834a63f7c1	6405	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
Sergunb	0:f1834a63f7c1	6406
Sergunb	0:f1834a63f7c1	6407	/***************** Bit definition for CAN_RDH0R register ****************/
Sergunb	0:f1834a63f7c1	6408	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
Sergunb	0:f1834a63f7c1	6409	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
Sergunb	0:f1834a63f7c1	6410	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
Sergunb	0:f1834a63f7c1	6411	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
Sergunb	0:f1834a63f7c1	6412
Sergunb	0:f1834a63f7c1	6413	/***************** Bit definition for CAN_RI1R register *****************/
Sergunb	0:f1834a63f7c1	6414	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!< Remote Transmission Request /
Sergunb	0:f1834a63f7c1	6415	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!< Identifier Extension /
Sergunb	0:f1834a63f7c1	6416	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!< Extended identifier /
Sergunb	0:f1834a63f7c1	6417	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!< Standard Identifier or Extended Identifier /
Sergunb	0:f1834a63f7c1	6418
Sergunb	0:f1834a63f7c1	6419	/***************** Bit definition for CAN_RDT1R register ****************/
Sergunb	0:f1834a63f7c1	6420	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!< Data Length Code /
Sergunb	0:f1834a63f7c1	6421	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!< Filter Match Index /
Sergunb	0:f1834a63f7c1	6422	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!< Message Time Stamp /
Sergunb	0:f1834a63f7c1	6423
Sergunb	0:f1834a63f7c1	6424	/***************** Bit definition for CAN_RDL1R register ****************/
Sergunb	0:f1834a63f7c1	6425	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!< Data byte 0 /
Sergunb	0:f1834a63f7c1	6426	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!< Data byte 1 /
Sergunb	0:f1834a63f7c1	6427	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!< Data byte 2 /
Sergunb	0:f1834a63f7c1	6428	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!< Data byte 3 /
Sergunb	0:f1834a63f7c1	6429
Sergunb	0:f1834a63f7c1	6430	/***************** Bit definition for CAN_RDH1R register ****************/
Sergunb	0:f1834a63f7c1	6431	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!< Data byte 4 /
Sergunb	0:f1834a63f7c1	6432	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!< Data byte 5 /
Sergunb	0:f1834a63f7c1	6433	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!< Data byte 6 /
Sergunb	0:f1834a63f7c1	6434	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!< Data byte 7 /
Sergunb	0:f1834a63f7c1	6435
Sergunb	0:f1834a63f7c1	6436	/!< CAN filter registers /
Sergunb	0:f1834a63f7c1	6437	/***************** Bit definition for CAN_FMR register ******************/
Sergunb	0:f1834a63f7c1	6438	#define CAN_FMR_FINIT ((uint8_t)0x01) /!< Filter Init Mode /
Sergunb	0:f1834a63f7c1	6439
Sergunb	0:f1834a63f7c1	6440	/***************** Bit definition for CAN_FM1R register *****************/
Sergunb	0:f1834a63f7c1	6441	#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /!< Filter Mode /
Sergunb	0:f1834a63f7c1	6442	#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /!< Filter Init Mode bit 0 /
Sergunb	0:f1834a63f7c1	6443	#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /!< Filter Init Mode bit 1 /
Sergunb	0:f1834a63f7c1	6444	#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /!< Filter Init Mode bit 2 /
Sergunb	0:f1834a63f7c1	6445	#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /!< Filter Init Mode bit 3 /
Sergunb	0:f1834a63f7c1	6446	#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /!< Filter Init Mode bit 4 /
Sergunb	0:f1834a63f7c1	6447	#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /!< Filter Init Mode bit 5 /
Sergunb	0:f1834a63f7c1	6448	#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /!< Filter Init Mode bit 6 /
Sergunb	0:f1834a63f7c1	6449	#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /!< Filter Init Mode bit 7 /
Sergunb	0:f1834a63f7c1	6450	#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /!< Filter Init Mode bit 8 /
Sergunb	0:f1834a63f7c1	6451	#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /!< Filter Init Mode bit 9 /
Sergunb	0:f1834a63f7c1	6452	#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /!< Filter Init Mode bit 10 /
Sergunb	0:f1834a63f7c1	6453	#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /!< Filter Init Mode bit 11 /
Sergunb	0:f1834a63f7c1	6454	#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /!< Filter Init Mode bit 12 /
Sergunb	0:f1834a63f7c1	6455	#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /!< Filter Init Mode bit 13 /
Sergunb	0:f1834a63f7c1	6456
Sergunb	0:f1834a63f7c1	6457	/***************** Bit definition for CAN_FS1R register *****************/
Sergunb	0:f1834a63f7c1	6458	#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /!< Filter Scale Configuration /
Sergunb	0:f1834a63f7c1	6459	#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /!< Filter Scale Configuration bit 0 /
Sergunb	0:f1834a63f7c1	6460	#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /!< Filter Scale Configuration bit 1 /
Sergunb	0:f1834a63f7c1	6461	#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /!< Filter Scale Configuration bit 2 /
Sergunb	0:f1834a63f7c1	6462	#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /!< Filter Scale Configuration bit 3 /
Sergunb	0:f1834a63f7c1	6463	#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /!< Filter Scale Configuration bit 4 /
Sergunb	0:f1834a63f7c1	6464	#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /!< Filter Scale Configuration bit 5 /
Sergunb	0:f1834a63f7c1	6465	#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /!< Filter Scale Configuration bit 6 /
Sergunb	0:f1834a63f7c1	6466	#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /!< Filter Scale Configuration bit 7 /
Sergunb	0:f1834a63f7c1	6467	#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /!< Filter Scale Configuration bit 8 /
Sergunb	0:f1834a63f7c1	6468	#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /!< Filter Scale Configuration bit 9 /
Sergunb	0:f1834a63f7c1	6469	#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /!< Filter Scale Configuration bit 10 /
Sergunb	0:f1834a63f7c1	6470	#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /!< Filter Scale Configuration bit 11 /
Sergunb	0:f1834a63f7c1	6471	#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /!< Filter Scale Configuration bit 12 /
Sergunb	0:f1834a63f7c1	6472	#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /!< Filter Scale Configuration bit 13 /
Sergunb	0:f1834a63f7c1	6473
Sergunb	0:f1834a63f7c1	6474	/**************** Bit definition for CAN_FFA1R register *****************/
Sergunb	0:f1834a63f7c1	6475	#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /!< Filter FIFO Assignment /
Sergunb	0:f1834a63f7c1	6476	#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /!< Filter FIFO Assignment for Filter 0 /
Sergunb	0:f1834a63f7c1	6477	#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /!< Filter FIFO Assignment for Filter 1 /
Sergunb	0:f1834a63f7c1	6478	#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /!< Filter FIFO Assignment for Filter 2 /
Sergunb	0:f1834a63f7c1	6479	#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /!< Filter FIFO Assignment for Filter 3 /
Sergunb	0:f1834a63f7c1	6480	#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /!< Filter FIFO Assignment for Filter 4 /
Sergunb	0:f1834a63f7c1	6481	#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /!< Filter FIFO Assignment for Filter 5 /
Sergunb	0:f1834a63f7c1	6482	#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /!< Filter FIFO Assignment for Filter 6 /
Sergunb	0:f1834a63f7c1	6483	#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /!< Filter FIFO Assignment for Filter 7 /
Sergunb	0:f1834a63f7c1	6484	#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /!< Filter FIFO Assignment for Filter 8 /
Sergunb	0:f1834a63f7c1	6485	#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /!< Filter FIFO Assignment for Filter 9 /
Sergunb	0:f1834a63f7c1	6486	#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /!< Filter FIFO Assignment for Filter 10 /
Sergunb	0:f1834a63f7c1	6487	#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /!< Filter FIFO Assignment for Filter 11 /
Sergunb	0:f1834a63f7c1	6488	#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /!< Filter FIFO Assignment for Filter 12 /
Sergunb	0:f1834a63f7c1	6489	#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /!< Filter FIFO Assignment for Filter 13 /
Sergunb	0:f1834a63f7c1	6490
Sergunb	0:f1834a63f7c1	6491	/***************** Bit definition for CAN_FA1R register *****************/
Sergunb	0:f1834a63f7c1	6492	#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /!< Filter Active /
Sergunb	0:f1834a63f7c1	6493	#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /!< Filter 0 Active /
Sergunb	0:f1834a63f7c1	6494	#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /!< Filter 1 Active /
Sergunb	0:f1834a63f7c1	6495	#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /!< Filter 2 Active /
Sergunb	0:f1834a63f7c1	6496	#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /!< Filter 3 Active /
Sergunb	0:f1834a63f7c1	6497	#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /!< Filter 4 Active /
Sergunb	0:f1834a63f7c1	6498	#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /!< Filter 5 Active /
Sergunb	0:f1834a63f7c1	6499	#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /!< Filter 6 Active /
Sergunb	0:f1834a63f7c1	6500	#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /!< Filter 7 Active /
Sergunb	0:f1834a63f7c1	6501	#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /!< Filter 8 Active /
Sergunb	0:f1834a63f7c1	6502	#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /!< Filter 9 Active /
Sergunb	0:f1834a63f7c1	6503	#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /!< Filter 10 Active /
Sergunb	0:f1834a63f7c1	6504	#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /!< Filter 11 Active /
Sergunb	0:f1834a63f7c1	6505	#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /!< Filter 12 Active /
Sergunb	0:f1834a63f7c1	6506	#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /!< Filter 13 Active /
Sergunb	0:f1834a63f7c1	6507
Sergunb	0:f1834a63f7c1	6508	/***************** Bit definition for CAN_F0R1 register *****************/
Sergunb	0:f1834a63f7c1	6509	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6510	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6511	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6512	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6513	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6514	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6515	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6516	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6517	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6518	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6519	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6520	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6521	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6522	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6523	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6524	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6525	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6526	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6527	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6528	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6529	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6530	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6531	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6532	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6533	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6534	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6535	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6536	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6537	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6538	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6539	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6540	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6541
Sergunb	0:f1834a63f7c1	6542	/***************** Bit definition for CAN_F1R1 register *****************/
Sergunb	0:f1834a63f7c1	6543	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6544	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6545	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6546	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6547	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6548	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6549	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6550	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6551	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6552	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6553	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6554	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6555	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6556	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6557	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6558	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6559	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6560	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6561	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6562	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6563	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6564	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6565	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6566	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6567	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6568	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6569	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6570	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6571	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6572	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6573	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6574	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6575
Sergunb	0:f1834a63f7c1	6576	/***************** Bit definition for CAN_F2R1 register *****************/
Sergunb	0:f1834a63f7c1	6577	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6578	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6579	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6580	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6581	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6582	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6583	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6584	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6585	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6586	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6587	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6588	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6589	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6590	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6591	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6592	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6593	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6594	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6595	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6596	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6597	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6598	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6599	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6600	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6601	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6602	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6603	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6604	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6605	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6606	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6607	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6608	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6609
Sergunb	0:f1834a63f7c1	6610	/***************** Bit definition for CAN_F3R1 register *****************/
Sergunb	0:f1834a63f7c1	6611	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6612	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6613	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6614	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6615	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6616	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6617	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6618	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6619	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6620	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6621	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6622	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6623	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6624	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6625	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6626	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6627	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6628	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6629	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6630	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6631	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6632	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6633	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6634	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6635	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6636	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6637	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6638	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6639	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6640	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6641	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6642	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6643
Sergunb	0:f1834a63f7c1	6644	/***************** Bit definition for CAN_F4R1 register *****************/
Sergunb	0:f1834a63f7c1	6645	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6646	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6647	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6648	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6649	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6650	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6651	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6652	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6653	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6654	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6655	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6656	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6657	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6658	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6659	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6660	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6661	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6662	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6663	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6664	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6665	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6666	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6667	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6668	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6669	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6670	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6671	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6672	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6673	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6674	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6675	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6676	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6677
Sergunb	0:f1834a63f7c1	6678	/***************** Bit definition for CAN_F5R1 register *****************/
Sergunb	0:f1834a63f7c1	6679	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6680	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6681	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6682	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6683	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6684	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6685	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6686	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6687	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6688	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6689	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6690	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6691	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6692	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6693	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6694	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6695	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6696	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6697	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6698	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6699	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6700	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6701	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6702	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6703	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6704	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6705	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6706	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6707	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6708	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6709	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6710	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6711
Sergunb	0:f1834a63f7c1	6712	/***************** Bit definition for CAN_F6R1 register *****************/
Sergunb	0:f1834a63f7c1	6713	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6714	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6715	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6716	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6717	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6718	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6719	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6720	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6721	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6722	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6723	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6724	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6725	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6726	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6727	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6728	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6729	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6730	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6731	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6732	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6733	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6734	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6735	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6736	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6737	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6738	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6739	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6740	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6741	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6742	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6743	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6744	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6745
Sergunb	0:f1834a63f7c1	6746	/***************** Bit definition for CAN_F7R1 register *****************/
Sergunb	0:f1834a63f7c1	6747	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6748	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6749	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6750	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6751	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6752	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6753	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6754	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6755	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6756	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6757	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6758	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6759	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6760	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6761	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6762	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6763	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6764	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6765	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6766	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6767	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6768	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6769	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6770	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6771	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6772	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6773	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6774	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6775	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6776	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6777	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6778	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6779
Sergunb	0:f1834a63f7c1	6780	/***************** Bit definition for CAN_F8R1 register *****************/
Sergunb	0:f1834a63f7c1	6781	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6782	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6783	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6784	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6785	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6786	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6787	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6788	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6789	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6790	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6791	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6792	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6793	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6794	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6795	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6796	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6797	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6798	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6799	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6800	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6801	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6802	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6803	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6804	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6805	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6806	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6807	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6808	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6809	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6810	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6811	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6812	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6813
Sergunb	0:f1834a63f7c1	6814	/***************** Bit definition for CAN_F9R1 register *****************/
Sergunb	0:f1834a63f7c1	6815	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6816	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6817	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6818	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6819	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6820	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6821	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6822	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6823	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6824	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6825	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6826	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6827	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6828	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6829	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6830	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6831	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6832	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6833	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6834	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6835	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6836	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6837	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6838	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6839	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6840	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6841	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6842	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6843	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6844	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6845	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6846	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6847
Sergunb	0:f1834a63f7c1	6848	/***************** Bit definition for CAN_F10R1 register ****************/
Sergunb	0:f1834a63f7c1	6849	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6850	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6851	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6852	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6853	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6854	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6855	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6856	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6857	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6858	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6859	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6860	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6861	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6862	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6863	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6864	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6865	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6866	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6867	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6868	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6869	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6870	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6871	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6872	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6873	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6874	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6875	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6876	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6877	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6878	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6879	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6880	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6881
Sergunb	0:f1834a63f7c1	6882	/***************** Bit definition for CAN_F11R1 register ****************/
Sergunb	0:f1834a63f7c1	6883	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6884	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6885	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6886	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6887	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6888	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6889	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6890	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6891	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6892	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6893	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6894	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6895	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6896	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6897	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6898	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6899	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6900	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6901	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6902	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6903	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6904	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6905	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6906	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6907	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6908	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6909	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6910	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6911	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6912	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6913	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6914	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6915
Sergunb	0:f1834a63f7c1	6916	/***************** Bit definition for CAN_F12R1 register ****************/
Sergunb	0:f1834a63f7c1	6917	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6918	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6919	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6920	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6921	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6922	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6923	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6924	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6925	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6926	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6927	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6928	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6929	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6930	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6931	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6932	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6933	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6934	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6935	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6936	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6937	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6938	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6939	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6940	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6941	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6942	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6943	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6944	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6945	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6946	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6947	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6948	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6949
Sergunb	0:f1834a63f7c1	6950	/***************** Bit definition for CAN_F13R1 register ****************/
Sergunb	0:f1834a63f7c1	6951	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6952	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6953	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6954	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6955	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6956	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6957	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6958	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6959	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6960	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6961	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6962	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6963	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6964	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6965	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	6966	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	6967	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	6968	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	6969	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	6970	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	6971	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	6972	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	6973	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	6974	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	6975	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	6976	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	6977	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	6978	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	6979	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	6980	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	6981	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	6982	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	6983
Sergunb	0:f1834a63f7c1	6984	/***************** Bit definition for CAN_F0R2 register *****************/
Sergunb	0:f1834a63f7c1	6985	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	6986	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	6987	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	6988	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	6989	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	6990	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	6991	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	6992	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	6993	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	6994	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	6995	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	6996	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	6997	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	6998	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	6999	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7000	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7001	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7002	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7003	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7004	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7005	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7006	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7007	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7008	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7009	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7010	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7011	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7012	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7013	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7014	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7015	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7016	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7017
Sergunb	0:f1834a63f7c1	7018	/***************** Bit definition for CAN_F1R2 register *****************/
Sergunb	0:f1834a63f7c1	7019	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7020	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7021	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7022	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7023	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7024	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7025	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7026	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7027	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7028	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7029	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7030	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7031	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7032	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7033	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7034	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7035	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7036	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7037	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7038	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7039	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7040	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7041	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7042	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7043	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7044	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7045	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7046	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7047	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7048	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7049	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7050	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7051
Sergunb	0:f1834a63f7c1	7052	/***************** Bit definition for CAN_F2R2 register *****************/
Sergunb	0:f1834a63f7c1	7053	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7054	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7055	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7056	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7057	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7058	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7059	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7060	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7061	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7062	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7063	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7064	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7065	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7066	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7067	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7068	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7069	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7070	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7071	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7072	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7073	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7074	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7075	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7076	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7077	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7078	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7079	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7080	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7081	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7082	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7083	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7084	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7085
Sergunb	0:f1834a63f7c1	7086	/***************** Bit definition for CAN_F3R2 register *****************/
Sergunb	0:f1834a63f7c1	7087	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7088	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7089	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7090	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7091	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7092	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7093	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7094	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7095	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7096	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7097	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7098	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7099	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7100	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7101	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7102	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7103	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7104	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7105	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7106	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7107	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7108	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7109	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7110	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7111	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7112	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7113	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7114	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7115	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7116	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7117	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7118	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7119
Sergunb	0:f1834a63f7c1	7120	/***************** Bit definition for CAN_F4R2 register *****************/
Sergunb	0:f1834a63f7c1	7121	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7122	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7123	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7124	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7125	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7126	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7127	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7128	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7129	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7130	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7131	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7132	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7133	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7134	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7135	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7136	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7137	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7138	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7139	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7140	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7141	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7142	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7143	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7144	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7145	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7146	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7147	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7148	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7149	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7150	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7151	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7152	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7153
Sergunb	0:f1834a63f7c1	7154	/***************** Bit definition for CAN_F5R2 register *****************/
Sergunb	0:f1834a63f7c1	7155	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7156	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7157	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7158	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7159	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7160	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7161	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7162	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7163	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7164	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7165	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7166	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7167	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7168	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7169	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7170	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7171	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7172	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7173	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7174	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7175	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7176	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7177	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7178	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7179	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7180	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7181	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7182	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7183	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7184	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7185	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7186	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7187
Sergunb	0:f1834a63f7c1	7188	/***************** Bit definition for CAN_F6R2 register *****************/
Sergunb	0:f1834a63f7c1	7189	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7190	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7191	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7192	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7193	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7194	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7195	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7196	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7197	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7198	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7199	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7200	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7201	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7202	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7203	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7204	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7205	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7206	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7207	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7208	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7209	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7210	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7211	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7212	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7213	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7214	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7215	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7216	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7217	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7218	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7219	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7220	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7221
Sergunb	0:f1834a63f7c1	7222	/***************** Bit definition for CAN_F7R2 register *****************/
Sergunb	0:f1834a63f7c1	7223	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7224	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7225	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7226	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7227	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7228	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7229	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7230	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7231	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7232	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7233	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7234	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7235	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7236	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7237	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7238	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7239	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7240	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7241	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7242	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7243	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7244	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7245	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7246	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7247	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7248	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7249	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7250	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7251	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7252	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7253	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7254	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7255
Sergunb	0:f1834a63f7c1	7256	/***************** Bit definition for CAN_F8R2 register *****************/
Sergunb	0:f1834a63f7c1	7257	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7258	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7259	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7260	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7261	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7262	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7263	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7264	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7265	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7266	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7267	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7268	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7269	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7270	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7271	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7272	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7273	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7274	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7275	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7276	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7277	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7278	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7279	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7280	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7281	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7282	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7283	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7284	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7285	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7286	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7287	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7288	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7289
Sergunb	0:f1834a63f7c1	7290	/***************** Bit definition for CAN_F9R2 register *****************/
Sergunb	0:f1834a63f7c1	7291	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7292	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7293	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7294	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7295	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7296	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7297	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7298	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7299	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7300	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7301	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7302	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7303	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7304	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7305	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7306	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7307	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7308	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7309	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7310	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7311	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7312	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7313	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7314	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7315	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7316	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7317	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7318	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7319	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7320	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7321	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7322	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7323
Sergunb	0:f1834a63f7c1	7324	/***************** Bit definition for CAN_F10R2 register ****************/
Sergunb	0:f1834a63f7c1	7325	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7326	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7327	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7328	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7329	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7330	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7331	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7332	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7333	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7334	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7335	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7336	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7337	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7338	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7339	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7340	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7341	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7342	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7343	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7344	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7345	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7346	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7347	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7348	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7349	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7350	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7351	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7352	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7353	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7354	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7355	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7356	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7357
Sergunb	0:f1834a63f7c1	7358	/***************** Bit definition for CAN_F11R2 register ****************/
Sergunb	0:f1834a63f7c1	7359	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7360	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7361	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7362	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7363	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7364	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7365	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7366	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7367	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7368	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7369	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7370	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7371	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7372	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7373	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7374	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7375	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7376	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7377	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7378	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7379	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7380	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7381	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7382	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7383	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7384	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7385	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7386	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7387	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7388	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7389	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7390	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7391
Sergunb	0:f1834a63f7c1	7392	/***************** Bit definition for CAN_F12R2 register ****************/
Sergunb	0:f1834a63f7c1	7393	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7394	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7395	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7396	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7397	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7398	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7399	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7400	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7401	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7402	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7403	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7404	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7405	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7406	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7407	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7408	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7409	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7410	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7411	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7412	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7413	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7414	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7415	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7416	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7417	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7418	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7419	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7420	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7421	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7422	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7423	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7424	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7425
Sergunb	0:f1834a63f7c1	7426	/***************** Bit definition for CAN_F13R2 register ****************/
Sergunb	0:f1834a63f7c1	7427	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!< Filter bit 0 /
Sergunb	0:f1834a63f7c1	7428	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!< Filter bit 1 /
Sergunb	0:f1834a63f7c1	7429	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!< Filter bit 2 /
Sergunb	0:f1834a63f7c1	7430	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!< Filter bit 3 /
Sergunb	0:f1834a63f7c1	7431	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!< Filter bit 4 /
Sergunb	0:f1834a63f7c1	7432	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!< Filter bit 5 /
Sergunb	0:f1834a63f7c1	7433	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!< Filter bit 6 /
Sergunb	0:f1834a63f7c1	7434	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!< Filter bit 7 /
Sergunb	0:f1834a63f7c1	7435	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!< Filter bit 8 /
Sergunb	0:f1834a63f7c1	7436	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!< Filter bit 9 /
Sergunb	0:f1834a63f7c1	7437	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!< Filter bit 10 /
Sergunb	0:f1834a63f7c1	7438	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!< Filter bit 11 /
Sergunb	0:f1834a63f7c1	7439	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!< Filter bit 12 /
Sergunb	0:f1834a63f7c1	7440	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!< Filter bit 13 /
Sergunb	0:f1834a63f7c1	7441	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!< Filter bit 14 /
Sergunb	0:f1834a63f7c1	7442	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!< Filter bit 15 /
Sergunb	0:f1834a63f7c1	7443	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!< Filter bit 16 /
Sergunb	0:f1834a63f7c1	7444	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!< Filter bit 17 /
Sergunb	0:f1834a63f7c1	7445	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!< Filter bit 18 /
Sergunb	0:f1834a63f7c1	7446	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!< Filter bit 19 /
Sergunb	0:f1834a63f7c1	7447	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!< Filter bit 20 /
Sergunb	0:f1834a63f7c1	7448	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!< Filter bit 21 /
Sergunb	0:f1834a63f7c1	7449	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!< Filter bit 22 /
Sergunb	0:f1834a63f7c1	7450	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!< Filter bit 23 /
Sergunb	0:f1834a63f7c1	7451	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!< Filter bit 24 /
Sergunb	0:f1834a63f7c1	7452	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!< Filter bit 25 /
Sergunb	0:f1834a63f7c1	7453	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!< Filter bit 26 /
Sergunb	0:f1834a63f7c1	7454	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!< Filter bit 27 /
Sergunb	0:f1834a63f7c1	7455	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!< Filter bit 28 /
Sergunb	0:f1834a63f7c1	7456	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!< Filter bit 29 /
Sergunb	0:f1834a63f7c1	7457	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!< Filter bit 30 /
Sergunb	0:f1834a63f7c1	7458	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!< Filter bit 31 /
Sergunb	0:f1834a63f7c1	7459
Sergunb	0:f1834a63f7c1	7460	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7461	/* */
Sergunb	0:f1834a63f7c1	7462	/* Serial Peripheral Interface */
Sergunb	0:f1834a63f7c1	7463	/* */
Sergunb	0:f1834a63f7c1	7464	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7465
Sergunb	0:f1834a63f7c1	7466	/***************** Bit definition for SPI_CR1 register ******************/
Sergunb	0:f1834a63f7c1	7467	#define SPI_CR1_CPHA ((uint16_t)0x0001) /!< Clock Phase /
Sergunb	0:f1834a63f7c1	7468	#define SPI_CR1_CPOL ((uint16_t)0x0002) /!< Clock Polarity /
Sergunb	0:f1834a63f7c1	7469	#define SPI_CR1_MSTR ((uint16_t)0x0004) /!< Master Selection /
Sergunb	0:f1834a63f7c1	7470
Sergunb	0:f1834a63f7c1	7471	#define SPI_CR1_BR ((uint16_t)0x0038) /!< BR[2:0] bits (Baud Rate Control) /
Sergunb	0:f1834a63f7c1	7472	#define SPI_CR1_BR_0 ((uint16_t)0x0008) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7473	#define SPI_CR1_BR_1 ((uint16_t)0x0010) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7474	#define SPI_CR1_BR_2 ((uint16_t)0x0020) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	7475
Sergunb	0:f1834a63f7c1	7476	#define SPI_CR1_SPE ((uint16_t)0x0040) /!< SPI Enable /
Sergunb	0:f1834a63f7c1	7477	#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /!< Frame Format /
Sergunb	0:f1834a63f7c1	7478	#define SPI_CR1_SSI ((uint16_t)0x0100) /!< Internal slave select /
Sergunb	0:f1834a63f7c1	7479	#define SPI_CR1_SSM ((uint16_t)0x0200) /!< Software slave management /
Sergunb	0:f1834a63f7c1	7480	#define SPI_CR1_RXONLY ((uint16_t)0x0400) /!< Receive only /
Sergunb	0:f1834a63f7c1	7481	#define SPI_CR1_DFF ((uint16_t)0x0800) /!< Data Frame Format /
Sergunb	0:f1834a63f7c1	7482	#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /!< Transmit CRC next /
Sergunb	0:f1834a63f7c1	7483	#define SPI_CR1_CRCEN ((uint16_t)0x2000) /!< Hardware CRC calculation enable /
Sergunb	0:f1834a63f7c1	7484	#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /!< Output enable in bidirectional mode /
Sergunb	0:f1834a63f7c1	7485	#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /!< Bidirectional data mode enable /
Sergunb	0:f1834a63f7c1	7486
Sergunb	0:f1834a63f7c1	7487	/***************** Bit definition for SPI_CR2 register ******************/
Sergunb	0:f1834a63f7c1	7488	#define SPI_CR2_RXDMAEN ((uint8_t)0x01) /!< Rx Buffer DMA Enable /
Sergunb	0:f1834a63f7c1	7489	#define SPI_CR2_TXDMAEN ((uint8_t)0x02) /!< Tx Buffer DMA Enable /
Sergunb	0:f1834a63f7c1	7490	#define SPI_CR2_SSOE ((uint8_t)0x04) /!< SS Output Enable /
Sergunb	0:f1834a63f7c1	7491	#define SPI_CR2_ERRIE ((uint8_t)0x20) /!< Error Interrupt Enable /
Sergunb	0:f1834a63f7c1	7492	#define SPI_CR2_RXNEIE ((uint8_t)0x40) /!< RX buffer Not Empty Interrupt Enable /
Sergunb	0:f1834a63f7c1	7493	#define SPI_CR2_TXEIE ((uint8_t)0x80) /!< Tx buffer Empty Interrupt Enable /
Sergunb	0:f1834a63f7c1	7494
Sergunb	0:f1834a63f7c1	7495	/****************** Bit definition for SPI_SR register ******************/
Sergunb	0:f1834a63f7c1	7496	#define SPI_SR_RXNE ((uint8_t)0x01) /!< Receive buffer Not Empty /
Sergunb	0:f1834a63f7c1	7497	#define SPI_SR_TXE ((uint8_t)0x02) /!< Transmit buffer Empty /
Sergunb	0:f1834a63f7c1	7498	#define SPI_SR_CHSIDE ((uint8_t)0x04) /!< Channel side /
Sergunb	0:f1834a63f7c1	7499	#define SPI_SR_UDR ((uint8_t)0x08) /!< Underrun flag /
Sergunb	0:f1834a63f7c1	7500	#define SPI_SR_CRCERR ((uint8_t)0x10) /!< CRC Error flag /
Sergunb	0:f1834a63f7c1	7501	#define SPI_SR_MODF ((uint8_t)0x20) /!< Mode fault /
Sergunb	0:f1834a63f7c1	7502	#define SPI_SR_OVR ((uint8_t)0x40) /!< Overrun flag /
Sergunb	0:f1834a63f7c1	7503	#define SPI_SR_BSY ((uint8_t)0x80) /!< Busy flag /
Sergunb	0:f1834a63f7c1	7504
Sergunb	0:f1834a63f7c1	7505	/****************** Bit definition for SPI_DR register ******************/
Sergunb	0:f1834a63f7c1	7506	#define SPI_DR_DR ((uint16_t)0xFFFF) /!< Data Register /
Sergunb	0:f1834a63f7c1	7507
Sergunb	0:f1834a63f7c1	7508	/***************** Bit definition for SPI_CRCPR register ****************/
Sergunb	0:f1834a63f7c1	7509	#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /!< CRC polynomial register /
Sergunb	0:f1834a63f7c1	7510
Sergunb	0:f1834a63f7c1	7511	/**************** Bit definition for SPI_RXCRCR register ****************/
Sergunb	0:f1834a63f7c1	7512	#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /!< Rx CRC Register /
Sergunb	0:f1834a63f7c1	7513
Sergunb	0:f1834a63f7c1	7514	/**************** Bit definition for SPI_TXCRCR register ****************/
Sergunb	0:f1834a63f7c1	7515	#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /!< Tx CRC Register /
Sergunb	0:f1834a63f7c1	7516
Sergunb	0:f1834a63f7c1	7517	/**************** Bit definition for SPI_I2SCFGR register ***************/
Sergunb	0:f1834a63f7c1	7518	#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /!< Channel length (number of bits per audio channel) /
Sergunb	0:f1834a63f7c1	7519
Sergunb	0:f1834a63f7c1	7520	#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /!< DATLEN[1:0] bits (Data length to be transferred) /
Sergunb	0:f1834a63f7c1	7521	#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7522	#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7523
Sergunb	0:f1834a63f7c1	7524	#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /!< steady state clock polarity /
Sergunb	0:f1834a63f7c1	7525
Sergunb	0:f1834a63f7c1	7526	#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /!< I2SSTD[1:0] bits (I2S standard selection) /
Sergunb	0:f1834a63f7c1	7527	#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7528	#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7529
Sergunb	0:f1834a63f7c1	7530	#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /!< PCM frame synchronization /
Sergunb	0:f1834a63f7c1	7531
Sergunb	0:f1834a63f7c1	7532	#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /!< I2SCFG[1:0] bits (I2S configuration mode) /
Sergunb	0:f1834a63f7c1	7533	#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7534	#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7535
Sergunb	0:f1834a63f7c1	7536	#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /!< I2S Enable /
Sergunb	0:f1834a63f7c1	7537	#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /!< I2S mode selection /
Sergunb	0:f1834a63f7c1	7538
Sergunb	0:f1834a63f7c1	7539	/**************** Bit definition for SPI_I2SPR register *****************/
Sergunb	0:f1834a63f7c1	7540	#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /!< I2S Linear prescaler /
Sergunb	0:f1834a63f7c1	7541	#define SPI_I2SPR_ODD ((uint16_t)0x0100) /!< Odd factor for the prescaler /
Sergunb	0:f1834a63f7c1	7542	#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /!< Master Clock Output Enable /
Sergunb	0:f1834a63f7c1	7543
Sergunb	0:f1834a63f7c1	7544	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7545	/* */
Sergunb	0:f1834a63f7c1	7546	/* Inter-integrated Circuit Interface */
Sergunb	0:f1834a63f7c1	7547	/* */
Sergunb	0:f1834a63f7c1	7548	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7549
Sergunb	0:f1834a63f7c1	7550	/***************** Bit definition for I2C_CR1 register ******************/
Sergunb	0:f1834a63f7c1	7551	#define I2C_CR1_PE ((uint16_t)0x0001) /!< Peripheral Enable /
Sergunb	0:f1834a63f7c1	7552	#define I2C_CR1_SMBUS ((uint16_t)0x0002) /!< SMBus Mode /
Sergunb	0:f1834a63f7c1	7553	#define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /!< SMBus Type /
Sergunb	0:f1834a63f7c1	7554	#define I2C_CR1_ENARP ((uint16_t)0x0010) /!< ARP Enable /
Sergunb	0:f1834a63f7c1	7555	#define I2C_CR1_ENPEC ((uint16_t)0x0020) /!< PEC Enable /
Sergunb	0:f1834a63f7c1	7556	#define I2C_CR1_ENGC ((uint16_t)0x0040) /!< General Call Enable /
Sergunb	0:f1834a63f7c1	7557	#define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /!< Clock Stretching Disable (Slave mode) /
Sergunb	0:f1834a63f7c1	7558	#define I2C_CR1_START ((uint16_t)0x0100) /!< Start Generation /
Sergunb	0:f1834a63f7c1	7559	#define I2C_CR1_STOP ((uint16_t)0x0200) /!< Stop Generation /
Sergunb	0:f1834a63f7c1	7560	#define I2C_CR1_ACK ((uint16_t)0x0400) /!< Acknowledge Enable /
Sergunb	0:f1834a63f7c1	7561	#define I2C_CR1_POS ((uint16_t)0x0800) /!< Acknowledge/PEC Position (for data reception) /
Sergunb	0:f1834a63f7c1	7562	#define I2C_CR1_PEC ((uint16_t)0x1000) /!< Packet Error Checking /
Sergunb	0:f1834a63f7c1	7563	#define I2C_CR1_ALERT ((uint16_t)0x2000) /!< SMBus Alert /
Sergunb	0:f1834a63f7c1	7564	#define I2C_CR1_SWRST ((uint16_t)0x8000) /!< Software Reset /
Sergunb	0:f1834a63f7c1	7565
Sergunb	0:f1834a63f7c1	7566	/***************** Bit definition for I2C_CR2 register ******************/
Sergunb	0:f1834a63f7c1	7567	#define I2C_CR2_FREQ ((uint16_t)0x003F) /!< FREQ[5:0] bits (Peripheral Clock Frequency) /
Sergunb	0:f1834a63f7c1	7568	#define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7569	#define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7570	#define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	7571	#define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	7572	#define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	7573	#define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	7574
Sergunb	0:f1834a63f7c1	7575	#define I2C_CR2_ITERREN ((uint16_t)0x0100) /!< Error Interrupt Enable /
Sergunb	0:f1834a63f7c1	7576	#define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /!< Event Interrupt Enable /
Sergunb	0:f1834a63f7c1	7577	#define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /!< Buffer Interrupt Enable /
Sergunb	0:f1834a63f7c1	7578	#define I2C_CR2_DMAEN ((uint16_t)0x0800) /!< DMA Requests Enable /
Sergunb	0:f1834a63f7c1	7579	#define I2C_CR2_LAST ((uint16_t)0x1000) /!< DMA Last Transfer /
Sergunb	0:f1834a63f7c1	7580
Sergunb	0:f1834a63f7c1	7581	/***************** Bit definition for I2C_OAR1 register *****************/
Sergunb	0:f1834a63f7c1	7582	#define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /!< Interface Address /
Sergunb	0:f1834a63f7c1	7583	#define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /!< Interface Address /
Sergunb	0:f1834a63f7c1	7584
Sergunb	0:f1834a63f7c1	7585	#define I2C_OAR1_ADD0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7586	#define I2C_OAR1_ADD1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7587	#define I2C_OAR1_ADD2 ((uint16_t)0x0004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	7588	#define I2C_OAR1_ADD3 ((uint16_t)0x0008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	7589	#define I2C_OAR1_ADD4 ((uint16_t)0x0010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	7590	#define I2C_OAR1_ADD5 ((uint16_t)0x0020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	7591	#define I2C_OAR1_ADD6 ((uint16_t)0x0040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	7592	#define I2C_OAR1_ADD7 ((uint16_t)0x0080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	7593	#define I2C_OAR1_ADD8 ((uint16_t)0x0100) /!< Bit 8 /
Sergunb	0:f1834a63f7c1	7594	#define I2C_OAR1_ADD9 ((uint16_t)0x0200) /!< Bit 9 /
Sergunb	0:f1834a63f7c1	7595
Sergunb	0:f1834a63f7c1	7596	#define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /!< Addressing Mode (Slave mode) /
Sergunb	0:f1834a63f7c1	7597
Sergunb	0:f1834a63f7c1	7598	/***************** Bit definition for I2C_OAR2 register *****************/
Sergunb	0:f1834a63f7c1	7599	#define I2C_OAR2_ENDUAL ((uint8_t)0x01) /!< Dual addressing mode enable /
Sergunb	0:f1834a63f7c1	7600	#define I2C_OAR2_ADD2 ((uint8_t)0xFE) /!< Interface address /
Sergunb	0:f1834a63f7c1	7601
Sergunb	0:f1834a63f7c1	7602	/****************** Bit definition for I2C_DR register ******************/
Sergunb	0:f1834a63f7c1	7603	#define I2C_DR_DR ((uint8_t)0xFF) /!< 8-bit Data Register /
Sergunb	0:f1834a63f7c1	7604
Sergunb	0:f1834a63f7c1	7605	/***************** Bit definition for I2C_SR1 register ******************/
Sergunb	0:f1834a63f7c1	7606	#define I2C_SR1_SB ((uint16_t)0x0001) /!< Start Bit (Master mode) /
Sergunb	0:f1834a63f7c1	7607	#define I2C_SR1_ADDR ((uint16_t)0x0002) /!< Address sent (master mode)/matched (slave mode) /
Sergunb	0:f1834a63f7c1	7608	#define I2C_SR1_BTF ((uint16_t)0x0004) /!< Byte Transfer Finished /
Sergunb	0:f1834a63f7c1	7609	#define I2C_SR1_ADD10 ((uint16_t)0x0008) /!< 10-bit header sent (Master mode) /
Sergunb	0:f1834a63f7c1	7610	#define I2C_SR1_STOPF ((uint16_t)0x0010) /!< Stop detection (Slave mode) /
Sergunb	0:f1834a63f7c1	7611	#define I2C_SR1_RXNE ((uint16_t)0x0040) /!< Data Register not Empty (receivers) /
Sergunb	0:f1834a63f7c1	7612	#define I2C_SR1_TXE ((uint16_t)0x0080) /!< Data Register Empty (transmitters) /
Sergunb	0:f1834a63f7c1	7613	#define I2C_SR1_BERR ((uint16_t)0x0100) /!< Bus Error /
Sergunb	0:f1834a63f7c1	7614	#define I2C_SR1_ARLO ((uint16_t)0x0200) /!< Arbitration Lost (master mode) /
Sergunb	0:f1834a63f7c1	7615	#define I2C_SR1_AF ((uint16_t)0x0400) /!< Acknowledge Failure /
Sergunb	0:f1834a63f7c1	7616	#define I2C_SR1_OVR ((uint16_t)0x0800) /!< Overrun/Underrun /
Sergunb	0:f1834a63f7c1	7617	#define I2C_SR1_PECERR ((uint16_t)0x1000) /!< PEC Error in reception /
Sergunb	0:f1834a63f7c1	7618	#define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /!< Timeout or Tlow Error /
Sergunb	0:f1834a63f7c1	7619	#define I2C_SR1_SMBALERT ((uint16_t)0x8000) /!< SMBus Alert /
Sergunb	0:f1834a63f7c1	7620
Sergunb	0:f1834a63f7c1	7621	/***************** Bit definition for I2C_SR2 register ******************/
Sergunb	0:f1834a63f7c1	7622	#define I2C_SR2_MSL ((uint16_t)0x0001) /!< Master/Slave /
Sergunb	0:f1834a63f7c1	7623	#define I2C_SR2_BUSY ((uint16_t)0x0002) /!< Bus Busy /
Sergunb	0:f1834a63f7c1	7624	#define I2C_SR2_TRA ((uint16_t)0x0004) /!< Transmitter/Receiver /
Sergunb	0:f1834a63f7c1	7625	#define I2C_SR2_GENCALL ((uint16_t)0x0010) /!< General Call Address (Slave mode) /
Sergunb	0:f1834a63f7c1	7626	#define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /!< SMBus Device Default Address (Slave mode) /
Sergunb	0:f1834a63f7c1	7627	#define I2C_SR2_SMBHOST ((uint16_t)0x0040) /!< SMBus Host Header (Slave mode) /
Sergunb	0:f1834a63f7c1	7628	#define I2C_SR2_DUALF ((uint16_t)0x0080) /!< Dual Flag (Slave mode) /
Sergunb	0:f1834a63f7c1	7629	#define I2C_SR2_PEC ((uint16_t)0xFF00) /!< Packet Error Checking Register /
Sergunb	0:f1834a63f7c1	7630
Sergunb	0:f1834a63f7c1	7631	/***************** Bit definition for I2C_CCR register ******************/
Sergunb	0:f1834a63f7c1	7632	#define I2C_CCR_CCR ((uint16_t)0x0FFF) /!< Clock Control Register in Fast/Standard mode (Master mode) /
Sergunb	0:f1834a63f7c1	7633	#define I2C_CCR_DUTY ((uint16_t)0x4000) /!< Fast Mode Duty Cycle /
Sergunb	0:f1834a63f7c1	7634	#define I2C_CCR_FS ((uint16_t)0x8000) /!< I2C Master Mode Selection /
Sergunb	0:f1834a63f7c1	7635
Sergunb	0:f1834a63f7c1	7636	/**************** Bit definition for I2C_TRISE register *****************/
Sergunb	0:f1834a63f7c1	7637	#define I2C_TRISE_TRISE ((uint8_t)0x3F) /!< Maximum Rise Time in Fast/Standard mode (Master mode) /
Sergunb	0:f1834a63f7c1	7638
Sergunb	0:f1834a63f7c1	7639	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7640	/* */
Sergunb	0:f1834a63f7c1	7641	/* Universal Synchronous Asynchronous Receiver Transmitter */
Sergunb	0:f1834a63f7c1	7642	/* */
Sergunb	0:f1834a63f7c1	7643	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7644
Sergunb	0:f1834a63f7c1	7645	/***************** Bit definition for USART_SR register *****************/
Sergunb	0:f1834a63f7c1	7646	#define USART_SR_PE ((uint16_t)0x0001) /!< Parity Error /
Sergunb	0:f1834a63f7c1	7647	#define USART_SR_FE ((uint16_t)0x0002) /!< Framing Error /
Sergunb	0:f1834a63f7c1	7648	#define USART_SR_NE ((uint16_t)0x0004) /!< Noise Error Flag /
Sergunb	0:f1834a63f7c1	7649	#define USART_SR_ORE ((uint16_t)0x0008) /!< OverRun Error /
Sergunb	0:f1834a63f7c1	7650	#define USART_SR_IDLE ((uint16_t)0x0010) /!< IDLE line detected /
Sergunb	0:f1834a63f7c1	7651	#define USART_SR_RXNE ((uint16_t)0x0020) /!< Read Data Register Not Empty /
Sergunb	0:f1834a63f7c1	7652	#define USART_SR_TC ((uint16_t)0x0040) /!< Transmission Complete /
Sergunb	0:f1834a63f7c1	7653	#define USART_SR_TXE ((uint16_t)0x0080) /!< Transmit Data Register Empty /
Sergunb	0:f1834a63f7c1	7654	#define USART_SR_LBD ((uint16_t)0x0100) /!< LIN Break Detection Flag /
Sergunb	0:f1834a63f7c1	7655	#define USART_SR_CTS ((uint16_t)0x0200) /!< CTS Flag /
Sergunb	0:f1834a63f7c1	7656
Sergunb	0:f1834a63f7c1	7657	/***************** Bit definition for USART_DR register *****************/
Sergunb	0:f1834a63f7c1	7658	#define USART_DR_DR ((uint16_t)0x01FF) /!< Data value /
Sergunb	0:f1834a63f7c1	7659
Sergunb	0:f1834a63f7c1	7660	/**************** Bit definition for USART_BRR register *****************/
Sergunb	0:f1834a63f7c1	7661	#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /!< Fraction of USARTDIV /
Sergunb	0:f1834a63f7c1	7662	#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /!< Mantissa of USARTDIV /
Sergunb	0:f1834a63f7c1	7663
Sergunb	0:f1834a63f7c1	7664	/**************** Bit definition for USART_CR1 register *****************/
Sergunb	0:f1834a63f7c1	7665	#define USART_CR1_SBK ((uint16_t)0x0001) /!< Send Break /
Sergunb	0:f1834a63f7c1	7666	#define USART_CR1_RWU ((uint16_t)0x0002) /!< Receiver wakeup /
Sergunb	0:f1834a63f7c1	7667	#define USART_CR1_RE ((uint16_t)0x0004) /!< Receiver Enable /
Sergunb	0:f1834a63f7c1	7668	#define USART_CR1_TE ((uint16_t)0x0008) /!< Transmitter Enable /
Sergunb	0:f1834a63f7c1	7669	#define USART_CR1_IDLEIE ((uint16_t)0x0010) /!< IDLE Interrupt Enable /
Sergunb	0:f1834a63f7c1	7670	#define USART_CR1_RXNEIE ((uint16_t)0x0020) /!< RXNE Interrupt Enable /
Sergunb	0:f1834a63f7c1	7671	#define USART_CR1_TCIE ((uint16_t)0x0040) /!< Transmission Complete Interrupt Enable /
Sergunb	0:f1834a63f7c1	7672	#define USART_CR1_TXEIE ((uint16_t)0x0080) /!< PE Interrupt Enable /
Sergunb	0:f1834a63f7c1	7673	#define USART_CR1_PEIE ((uint16_t)0x0100) /!< PE Interrupt Enable /
Sergunb	0:f1834a63f7c1	7674	#define USART_CR1_PS ((uint16_t)0x0200) /!< Parity Selection /
Sergunb	0:f1834a63f7c1	7675	#define USART_CR1_PCE ((uint16_t)0x0400) /!< Parity Control Enable /
Sergunb	0:f1834a63f7c1	7676	#define USART_CR1_WAKE ((uint16_t)0x0800) /!< Wakeup method /
Sergunb	0:f1834a63f7c1	7677	#define USART_CR1_M ((uint16_t)0x1000) /!< Word length /
Sergunb	0:f1834a63f7c1	7678	#define USART_CR1_UE ((uint16_t)0x2000) /!< USART Enable /
Sergunb	0:f1834a63f7c1	7679	#define USART_CR1_OVER8 ((uint16_t)0x8000) /!< USART Oversmapling 8-bits /
Sergunb	0:f1834a63f7c1	7680
Sergunb	0:f1834a63f7c1	7681	/**************** Bit definition for USART_CR2 register *****************/
Sergunb	0:f1834a63f7c1	7682	#define USART_CR2_ADD ((uint16_t)0x000F) /!< Address of the USART node /
Sergunb	0:f1834a63f7c1	7683	#define USART_CR2_LBDL ((uint16_t)0x0020) /!< LIN Break Detection Length /
Sergunb	0:f1834a63f7c1	7684	#define USART_CR2_LBDIE ((uint16_t)0x0040) /!< LIN Break Detection Interrupt Enable /
Sergunb	0:f1834a63f7c1	7685	#define USART_CR2_LBCL ((uint16_t)0x0100) /!< Last Bit Clock pulse /
Sergunb	0:f1834a63f7c1	7686	#define USART_CR2_CPHA ((uint16_t)0x0200) /!< Clock Phase /
Sergunb	0:f1834a63f7c1	7687	#define USART_CR2_CPOL ((uint16_t)0x0400) /!< Clock Polarity /
Sergunb	0:f1834a63f7c1	7688	#define USART_CR2_CLKEN ((uint16_t)0x0800) /!< Clock Enable /
Sergunb	0:f1834a63f7c1	7689
Sergunb	0:f1834a63f7c1	7690	#define USART_CR2_STOP ((uint16_t)0x3000) /!< STOP[1:0] bits (STOP bits) /
Sergunb	0:f1834a63f7c1	7691	#define USART_CR2_STOP_0 ((uint16_t)0x1000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7692	#define USART_CR2_STOP_1 ((uint16_t)0x2000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7693
Sergunb	0:f1834a63f7c1	7694	#define USART_CR2_LINEN ((uint16_t)0x4000) /!< LIN mode enable /
Sergunb	0:f1834a63f7c1	7695
Sergunb	0:f1834a63f7c1	7696	/**************** Bit definition for USART_CR3 register *****************/
Sergunb	0:f1834a63f7c1	7697	#define USART_CR3_EIE ((uint16_t)0x0001) /!< Error Interrupt Enable /
Sergunb	0:f1834a63f7c1	7698	#define USART_CR3_IREN ((uint16_t)0x0002) /!< IrDA mode Enable /
Sergunb	0:f1834a63f7c1	7699	#define USART_CR3_IRLP ((uint16_t)0x0004) /!< IrDA Low-Power /
Sergunb	0:f1834a63f7c1	7700	#define USART_CR3_HDSEL ((uint16_t)0x0008) /!< Half-Duplex Selection /
Sergunb	0:f1834a63f7c1	7701	#define USART_CR3_NACK ((uint16_t)0x0010) /!< Smartcard NACK enable /
Sergunb	0:f1834a63f7c1	7702	#define USART_CR3_SCEN ((uint16_t)0x0020) /!< Smartcard mode enable /
Sergunb	0:f1834a63f7c1	7703	#define USART_CR3_DMAR ((uint16_t)0x0040) /!< DMA Enable Receiver /
Sergunb	0:f1834a63f7c1	7704	#define USART_CR3_DMAT ((uint16_t)0x0080) /!< DMA Enable Transmitter /
Sergunb	0:f1834a63f7c1	7705	#define USART_CR3_RTSE ((uint16_t)0x0100) /!< RTS Enable /
Sergunb	0:f1834a63f7c1	7706	#define USART_CR3_CTSE ((uint16_t)0x0200) /!< CTS Enable /
Sergunb	0:f1834a63f7c1	7707	#define USART_CR3_CTSIE ((uint16_t)0x0400) /!< CTS Interrupt Enable /
Sergunb	0:f1834a63f7c1	7708	#define USART_CR3_ONEBIT ((uint16_t)0x0800) /!< One Bit method /
Sergunb	0:f1834a63f7c1	7709
Sergunb	0:f1834a63f7c1	7710	/**************** Bit definition for USART_GTPR register ****************/
Sergunb	0:f1834a63f7c1	7711	#define USART_GTPR_PSC ((uint16_t)0x00FF) /!< PSC[7:0] bits (Prescaler value) /
Sergunb	0:f1834a63f7c1	7712	#define USART_GTPR_PSC_0 ((uint16_t)0x0001) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7713	#define USART_GTPR_PSC_1 ((uint16_t)0x0002) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7714	#define USART_GTPR_PSC_2 ((uint16_t)0x0004) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	7715	#define USART_GTPR_PSC_3 ((uint16_t)0x0008) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	7716	#define USART_GTPR_PSC_4 ((uint16_t)0x0010) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	7717	#define USART_GTPR_PSC_5 ((uint16_t)0x0020) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	7718	#define USART_GTPR_PSC_6 ((uint16_t)0x0040) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	7719	#define USART_GTPR_PSC_7 ((uint16_t)0x0080) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	7720
Sergunb	0:f1834a63f7c1	7721	#define USART_GTPR_GT ((uint16_t)0xFF00) /!< Guard time value /
Sergunb	0:f1834a63f7c1	7722
Sergunb	0:f1834a63f7c1	7723	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7724	/* */
Sergunb	0:f1834a63f7c1	7725	/* Debug MCU */
Sergunb	0:f1834a63f7c1	7726	/* */
Sergunb	0:f1834a63f7c1	7727	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7728
Sergunb	0:f1834a63f7c1	7729	/************** Bit definition for DBGMCU_IDCODE register ***************/
Sergunb	0:f1834a63f7c1	7730	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
Sergunb	0:f1834a63f7c1	7731
Sergunb	0:f1834a63f7c1	7732	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
Sergunb	0:f1834a63f7c1	7733	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7734	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7735	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
Sergunb	0:f1834a63f7c1	7736	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
Sergunb	0:f1834a63f7c1	7737	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
Sergunb	0:f1834a63f7c1	7738	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
Sergunb	0:f1834a63f7c1	7739	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
Sergunb	0:f1834a63f7c1	7740	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
Sergunb	0:f1834a63f7c1	7741	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
Sergunb	0:f1834a63f7c1	7742	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
Sergunb	0:f1834a63f7c1	7743	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
Sergunb	0:f1834a63f7c1	7744	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
Sergunb	0:f1834a63f7c1	7745	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
Sergunb	0:f1834a63f7c1	7746	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
Sergunb	0:f1834a63f7c1	7747	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
Sergunb	0:f1834a63f7c1	7748	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
Sergunb	0:f1834a63f7c1	7749
Sergunb	0:f1834a63f7c1	7750	/**************** Bit definition for DBGMCU_CR register *****************/
Sergunb	0:f1834a63f7c1	7751	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /!< Debug Sleep Mode /
Sergunb	0:f1834a63f7c1	7752	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
Sergunb	0:f1834a63f7c1	7753	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
Sergunb	0:f1834a63f7c1	7754	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /!< Trace Pin Assignment Control /
Sergunb	0:f1834a63f7c1	7755
Sergunb	0:f1834a63f7c1	7756	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) /
Sergunb	0:f1834a63f7c1	7757	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7758	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7759
Sergunb	0:f1834a63f7c1	7760	#define DBGMCU_CR_DBG_IWDG_STOP ((uint32_t)0x00000100) /!< Debug Independent Watchdog stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7761	#define DBGMCU_CR_DBG_WWDG_STOP ((uint32_t)0x00000200) /!< Debug Window Watchdog stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7762	#define DBGMCU_CR_DBG_TIM1_STOP ((uint32_t)0x00000400) /!< TIM1 counter stopped when core is halted /
Sergunb	0:f1834a63f7c1	7763	#define DBGMCU_CR_DBG_TIM2_STOP ((uint32_t)0x00000800) /!< TIM2 counter stopped when core is halted /
Sergunb	0:f1834a63f7c1	7764	#define DBGMCU_CR_DBG_TIM3_STOP ((uint32_t)0x00001000) /!< TIM3 counter stopped when core is halted /
Sergunb	0:f1834a63f7c1	7765	#define DBGMCU_CR_DBG_TIM4_STOP ((uint32_t)0x00002000) /!< TIM4 counter stopped when core is halted /
Sergunb	0:f1834a63f7c1	7766	#define DBGMCU_CR_DBG_CAN1_STOP ((uint32_t)0x00004000) /!< Debug CAN1 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7767	#define DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00008000) /!< SMBUS timeout mode stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7768	#define DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00010000) /!< SMBUS timeout mode stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7769	#define DBGMCU_CR_DBG_TIM8_STOP ((uint32_t)0x00020000) /!< TIM8 counter stopped when core is halted /
Sergunb	0:f1834a63f7c1	7770	#define DBGMCU_CR_DBG_TIM5_STOP ((uint32_t)0x00040000) /!< TIM5 counter stopped when core is halted /
Sergunb	0:f1834a63f7c1	7771	#define DBGMCU_CR_DBG_TIM6_STOP ((uint32_t)0x00080000) /!< TIM6 counter stopped when core is halted /
Sergunb	0:f1834a63f7c1	7772	#define DBGMCU_CR_DBG_TIM7_STOP ((uint32_t)0x00100000) /!< TIM7 counter stopped when core is halted /
Sergunb	0:f1834a63f7c1	7773	#define DBGMCU_CR_DBG_CAN2_STOP ((uint32_t)0x00200000) /!< Debug CAN2 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7774	#define DBGMCU_CR_DBG_TIM15_STOP ((uint32_t)0x00400000) /!< Debug TIM15 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7775	#define DBGMCU_CR_DBG_TIM16_STOP ((uint32_t)0x00800000) /!< Debug TIM16 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7776	#define DBGMCU_CR_DBG_TIM17_STOP ((uint32_t)0x01000000) /!< Debug TIM17 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7777	#define DBGMCU_CR_DBG_TIM12_STOP ((uint32_t)0x02000000) /!< Debug TIM12 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7778	#define DBGMCU_CR_DBG_TIM13_STOP ((uint32_t)0x04000000) /!< Debug TIM13 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7779	#define DBGMCU_CR_DBG_TIM14_STOP ((uint32_t)0x08000000) /!< Debug TIM14 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7780	#define DBGMCU_CR_DBG_TIM9_STOP ((uint32_t)0x10000000) /!< Debug TIM9 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7781	#define DBGMCU_CR_DBG_TIM10_STOP ((uint32_t)0x20000000) /!< Debug TIM10 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7782	#define DBGMCU_CR_DBG_TIM11_STOP ((uint32_t)0x40000000) /!< Debug TIM11 stopped when Core is halted /
Sergunb	0:f1834a63f7c1	7783
Sergunb	0:f1834a63f7c1	7784	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7785	/* */
Sergunb	0:f1834a63f7c1	7786	/* FLASH and Option Bytes Registers */
Sergunb	0:f1834a63f7c1	7787	/* */
Sergunb	0:f1834a63f7c1	7788	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7789
Sergunb	0:f1834a63f7c1	7790	/***************** Bit definition for FLASH_ACR register ****************/
Sergunb	0:f1834a63f7c1	7791	#define FLASH_ACR_LATENCY ((uint8_t)0x03) /!< LATENCY[2:0] bits (Latency) /
Sergunb	0:f1834a63f7c1	7792	#define FLASH_ACR_LATENCY_0 ((uint8_t)0x00) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7793	#define FLASH_ACR_LATENCY_1 ((uint8_t)0x01) /!< Bit 0 /
Sergunb	0:f1834a63f7c1	7794	#define FLASH_ACR_LATENCY_2 ((uint8_t)0x02) /!< Bit 1 /
Sergunb	0:f1834a63f7c1	7795
Sergunb	0:f1834a63f7c1	7796	#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /!< Flash Half Cycle Access Enable /
Sergunb	0:f1834a63f7c1	7797	#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /!< Prefetch Buffer Enable /
Sergunb	0:f1834a63f7c1	7798	#define FLASH_ACR_PRFTBS ((uint8_t)0x20) /!< Prefetch Buffer Status /
Sergunb	0:f1834a63f7c1	7799
Sergunb	0:f1834a63f7c1	7800	/**************** Bit definition for FLASH_KEYR register ****************/
Sergunb	0:f1834a63f7c1	7801	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
Sergunb	0:f1834a63f7c1	7802
Sergunb	0:f1834a63f7c1	7803	/*************** Bit definition for FLASH_OPTKEYR register **************/
Sergunb	0:f1834a63f7c1	7804	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
Sergunb	0:f1834a63f7c1	7805
Sergunb	0:f1834a63f7c1	7806	/**************** Bit definition for FLASH_SR register *****************/
Sergunb	0:f1834a63f7c1	7807	#define FLASH_SR_BSY ((uint8_t)0x01) /!< Busy /
Sergunb	0:f1834a63f7c1	7808	#define FLASH_SR_PGERR ((uint8_t)0x04) /!< Programming Error /
Sergunb	0:f1834a63f7c1	7809	#define FLASH_SR_WRPRTERR ((uint8_t)0x10) /!< Write Protection Error /
Sergunb	0:f1834a63f7c1	7810	#define FLASH_SR_EOP ((uint8_t)0x20) /!< End of operation /
Sergunb	0:f1834a63f7c1	7811
Sergunb	0:f1834a63f7c1	7812	/***************** Bit definition for FLASH_CR register *****************/
Sergunb	0:f1834a63f7c1	7813	#define FLASH_CR_PG ((uint16_t)0x0001) /!< Programming /
Sergunb	0:f1834a63f7c1	7814	#define FLASH_CR_PER ((uint16_t)0x0002) /!< Page Erase /
Sergunb	0:f1834a63f7c1	7815	#define FLASH_CR_MER ((uint16_t)0x0004) /!< Mass Erase /
Sergunb	0:f1834a63f7c1	7816	#define FLASH_CR_OPTPG ((uint16_t)0x0010) /!< Option Byte Programming /
Sergunb	0:f1834a63f7c1	7817	#define FLASH_CR_OPTER ((uint16_t)0x0020) /!< Option Byte Erase /
Sergunb	0:f1834a63f7c1	7818	#define FLASH_CR_STRT ((uint16_t)0x0040) /!< Start /
Sergunb	0:f1834a63f7c1	7819	#define FLASH_CR_LOCK ((uint16_t)0x0080) /!< Lock /
Sergunb	0:f1834a63f7c1	7820	#define FLASH_CR_OPTWRE ((uint16_t)0x0200) /!< Option Bytes Write Enable /
Sergunb	0:f1834a63f7c1	7821	#define FLASH_CR_ERRIE ((uint16_t)0x0400) /!< Error Interrupt Enable /
Sergunb	0:f1834a63f7c1	7822	#define FLASH_CR_EOPIE ((uint16_t)0x1000) /!< End of operation interrupt enable /
Sergunb	0:f1834a63f7c1	7823
Sergunb	0:f1834a63f7c1	7824	/***************** Bit definition for FLASH_AR register *****************/
Sergunb	0:f1834a63f7c1	7825	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
Sergunb	0:f1834a63f7c1	7826
Sergunb	0:f1834a63f7c1	7827	/**************** Bit definition for FLASH_OBR register *****************/
Sergunb	0:f1834a63f7c1	7828	#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /!< Option Byte Error /
Sergunb	0:f1834a63f7c1	7829	#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /!< Read protection /
Sergunb	0:f1834a63f7c1	7830
Sergunb	0:f1834a63f7c1	7831	#define FLASH_OBR_USER ((uint16_t)0x03FC) /!< User Option Bytes /
Sergunb	0:f1834a63f7c1	7832	#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /!< WDG_SW /
Sergunb	0:f1834a63f7c1	7833	#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /!< nRST_STOP /
Sergunb	0:f1834a63f7c1	7834	#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /!< nRST_STDBY /
Sergunb	0:f1834a63f7c1	7835	#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /!< BFB2 /
Sergunb	0:f1834a63f7c1	7836
Sergunb	0:f1834a63f7c1	7837	/**************** Bit definition for FLASH_WRPR register ****************/
Sergunb	0:f1834a63f7c1	7838	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
Sergunb	0:f1834a63f7c1	7839
Sergunb	0:f1834a63f7c1	7840	/----------------------------------------------------------------------------/
Sergunb	0:f1834a63f7c1	7841
Sergunb	0:f1834a63f7c1	7842	/**************** Bit definition for FLASH_RDP register *****************/
Sergunb	0:f1834a63f7c1	7843	#define FLASH_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
Sergunb	0:f1834a63f7c1	7844	#define FLASH_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
Sergunb	0:f1834a63f7c1	7845
Sergunb	0:f1834a63f7c1	7846	/**************** Bit definition for FLASH_USER register ****************/
Sergunb	0:f1834a63f7c1	7847	#define FLASH_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
Sergunb	0:f1834a63f7c1	7848	#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
Sergunb	0:f1834a63f7c1	7849
Sergunb	0:f1834a63f7c1	7850	/**************** Bit definition for FLASH_Data0 register ***************/
Sergunb	0:f1834a63f7c1	7851	#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /!< User data storage option byte /
Sergunb	0:f1834a63f7c1	7852	#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /!< User data storage complemented option byte /
Sergunb	0:f1834a63f7c1	7853
Sergunb	0:f1834a63f7c1	7854	/**************** Bit definition for FLASH_Data1 register ***************/
Sergunb	0:f1834a63f7c1	7855	#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /!< User data storage option byte /
Sergunb	0:f1834a63f7c1	7856	#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /!< User data storage complemented option byte /
Sergunb	0:f1834a63f7c1	7857
Sergunb	0:f1834a63f7c1	7858	/**************** Bit definition for FLASH_WRP0 register ****************/
Sergunb	0:f1834a63f7c1	7859	#define FLASH_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
Sergunb	0:f1834a63f7c1	7860	#define FLASH_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
Sergunb	0:f1834a63f7c1	7861
Sergunb	0:f1834a63f7c1	7862	/**************** Bit definition for FLASH_WRP1 register ****************/
Sergunb	0:f1834a63f7c1	7863	#define FLASH_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
Sergunb	0:f1834a63f7c1	7864	#define FLASH_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
Sergunb	0:f1834a63f7c1	7865
Sergunb	0:f1834a63f7c1	7866	/**************** Bit definition for FLASH_WRP2 register ****************/
Sergunb	0:f1834a63f7c1	7867	#define FLASH_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
Sergunb	0:f1834a63f7c1	7868	#define FLASH_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
Sergunb	0:f1834a63f7c1	7869
Sergunb	0:f1834a63f7c1	7870	/**************** Bit definition for FLASH_WRP3 register ****************/
Sergunb	0:f1834a63f7c1	7871	#define FLASH_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
Sergunb	0:f1834a63f7c1	7872	#define FLASH_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
Sergunb	0:f1834a63f7c1	7873
Sergunb	0:f1834a63f7c1	7874	#ifdef STM32F10X_CL
Sergunb	0:f1834a63f7c1	7875	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7876	/* Ethernet MAC Registers bits definitions */
Sergunb	0:f1834a63f7c1	7877	/******************************************************************************/
Sergunb	0:f1834a63f7c1	7878	/* Bit definition for Ethernet MAC Control Register register */
Sergunb	0:f1834a63f7c1	7879	#define ETH_MACCR_WD ((uint32_t)0x00800000) /* Watchdog disable */
Sergunb	0:f1834a63f7c1	7880	#define ETH_MACCR_JD ((uint32_t)0x00400000) /* Jabber disable */
Sergunb	0:f1834a63f7c1	7881	#define ETH_MACCR_IFG ((uint32_t)0x000E0000) /* Inter-frame gap */
Sergunb	0:f1834a63f7c1	7882	#define ETH_MACCR_IFG_96Bit ((uint32_t)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */
Sergunb	0:f1834a63f7c1	7883	#define ETH_MACCR_IFG_88Bit ((uint32_t)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */
Sergunb	0:f1834a63f7c1	7884	#define ETH_MACCR_IFG_80Bit ((uint32_t)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */
Sergunb	0:f1834a63f7c1	7885	#define ETH_MACCR_IFG_72Bit ((uint32_t)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */
Sergunb	0:f1834a63f7c1	7886	#define ETH_MACCR_IFG_64Bit ((uint32_t)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */
Sergunb	0:f1834a63f7c1	7887	#define ETH_MACCR_IFG_56Bit ((uint32_t)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */
Sergunb	0:f1834a63f7c1	7888	#define ETH_MACCR_IFG_48Bit ((uint32_t)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */
Sergunb	0:f1834a63f7c1	7889	#define ETH_MACCR_IFG_40Bit ((uint32_t)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */
Sergunb	0:f1834a63f7c1	7890	#define ETH_MACCR_CSD ((uint32_t)0x00010000) /* Carrier sense disable (during transmission) */
Sergunb	0:f1834a63f7c1	7891	#define ETH_MACCR_FES ((uint32_t)0x00004000) /* Fast ethernet speed */
Sergunb	0:f1834a63f7c1	7892	#define ETH_MACCR_ROD ((uint32_t)0x00002000) /* Receive own disable */
Sergunb	0:f1834a63f7c1	7893	#define ETH_MACCR_LM ((uint32_t)0x00001000) /* loopback mode */
Sergunb	0:f1834a63f7c1	7894	#define ETH_MACCR_DM ((uint32_t)0x00000800) /* Duplex mode */
Sergunb	0:f1834a63f7c1	7895	#define ETH_MACCR_IPCO ((uint32_t)0x00000400) /* IP Checksum offload */
Sergunb	0:f1834a63f7c1	7896	#define ETH_MACCR_RD ((uint32_t)0x00000200) /* Retry disable */
Sergunb	0:f1834a63f7c1	7897	#define ETH_MACCR_APCS ((uint32_t)0x00000080) /* Automatic Pad/CRC stripping */
Sergunb	0:f1834a63f7c1	7898	#define ETH_MACCR_BL ((uint32_t)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before rescheduling
Sergunb	0:f1834a63f7c1	7899	a transmission attempt during retries after a collision: 0 =< r <2^k */
Sergunb	0:f1834a63f7c1	7900	#define ETH_MACCR_BL_10 ((uint32_t)0x00000000) /* k = min (n, 10) */
Sergunb	0:f1834a63f7c1	7901	#define ETH_MACCR_BL_8 ((uint32_t)0x00000020) /* k = min (n, 8) */
Sergunb	0:f1834a63f7c1	7902	#define ETH_MACCR_BL_4 ((uint32_t)0x00000040) /* k = min (n, 4) */
Sergunb	0:f1834a63f7c1	7903	#define ETH_MACCR_BL_1 ((uint32_t)0x00000060) /* k = min (n, 1) */
Sergunb	0:f1834a63f7c1	7904	#define ETH_MACCR_DC ((uint32_t)0x00000010) /* Defferal check */
Sergunb	0:f1834a63f7c1	7905	#define ETH_MACCR_TE ((uint32_t)0x00000008) /* Transmitter enable */
Sergunb	0:f1834a63f7c1	7906	#define ETH_MACCR_RE ((uint32_t)0x00000004) /* Receiver enable */
Sergunb	0:f1834a63f7c1	7907
Sergunb	0:f1834a63f7c1	7908	/* Bit definition for Ethernet MAC Frame Filter Register */
Sergunb	0:f1834a63f7c1	7909	#define ETH_MACFFR_RA ((uint32_t)0x80000000) /* Receive all */
Sergunb	0:f1834a63f7c1	7910	#define ETH_MACFFR_HPF ((uint32_t)0x00000400) /* Hash or perfect filter */
Sergunb	0:f1834a63f7c1	7911	#define ETH_MACFFR_SAF ((uint32_t)0x00000200) /* Source address filter enable */
Sergunb	0:f1834a63f7c1	7912	#define ETH_MACFFR_SAIF ((uint32_t)0x00000100) /* SA inverse filtering */
Sergunb	0:f1834a63f7c1	7913	#define ETH_MACFFR_PCF ((uint32_t)0x000000C0) /* Pass control frames: 3 cases */
Sergunb	0:f1834a63f7c1	7914	#define ETH_MACFFR_PCF_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */
Sergunb	0:f1834a63f7c1	7915	#define ETH_MACFFR_PCF_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */
Sergunb	0:f1834a63f7c1	7916	#define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */
Sergunb	0:f1834a63f7c1	7917	#define ETH_MACFFR_BFD ((uint32_t)0x00000020) /* Broadcast frame disable */
Sergunb	0:f1834a63f7c1	7918	#define ETH_MACFFR_PAM ((uint32_t)0x00000010) /* Pass all mutlicast */
Sergunb	0:f1834a63f7c1	7919	#define ETH_MACFFR_DAIF ((uint32_t)0x00000008) /* DA Inverse filtering */
Sergunb	0:f1834a63f7c1	7920	#define ETH_MACFFR_HM ((uint32_t)0x00000004) /* Hash multicast */
Sergunb	0:f1834a63f7c1	7921	#define ETH_MACFFR_HU ((uint32_t)0x00000002) /* Hash unicast */
Sergunb	0:f1834a63f7c1	7922	#define ETH_MACFFR_PM ((uint32_t)0x00000001) /* Promiscuous mode */
Sergunb	0:f1834a63f7c1	7923
Sergunb	0:f1834a63f7c1	7924	/* Bit definition for Ethernet MAC Hash Table High Register */
Sergunb	0:f1834a63f7c1	7925	#define ETH_MACHTHR_HTH ((uint32_t)0xFFFFFFFF) /* Hash table high */
Sergunb	0:f1834a63f7c1	7926
Sergunb	0:f1834a63f7c1	7927	/* Bit definition for Ethernet MAC Hash Table Low Register */
Sergunb	0:f1834a63f7c1	7928	#define ETH_MACHTLR_HTL ((uint32_t)0xFFFFFFFF) /* Hash table low */
Sergunb	0:f1834a63f7c1	7929
Sergunb	0:f1834a63f7c1	7930	/* Bit definition for Ethernet MAC MII Address Register */
Sergunb	0:f1834a63f7c1	7931	#define ETH_MACMIIAR_PA ((uint32_t)0x0000F800) /* Physical layer address */
Sergunb	0:f1834a63f7c1	7932	#define ETH_MACMIIAR_MR ((uint32_t)0x000007C0) /* MII register in the selected PHY */
Sergunb	0:f1834a63f7c1	7933	#define ETH_MACMIIAR_CR ((uint32_t)0x0000001C) /* CR clock range: 6 cases */
Sergunb	0:f1834a63f7c1	7934	#define ETH_MACMIIAR_CR_Div42 ((uint32_t)0x00000000) /* HCLK:60-72 MHz; MDC clock= HCLK/42 */
Sergunb	0:f1834a63f7c1	7935	#define ETH_MACMIIAR_CR_Div16 ((uint32_t)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
Sergunb	0:f1834a63f7c1	7936	#define ETH_MACMIIAR_CR_Div26 ((uint32_t)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
Sergunb	0:f1834a63f7c1	7937	#define ETH_MACMIIAR_MW ((uint32_t)0x00000002) /* MII write */
Sergunb	0:f1834a63f7c1	7938	#define ETH_MACMIIAR_MB ((uint32_t)0x00000001) /* MII busy */
Sergunb	0:f1834a63f7c1	7939
Sergunb	0:f1834a63f7c1	7940	/* Bit definition for Ethernet MAC MII Data Register */
Sergunb	0:f1834a63f7c1	7941	#define ETH_MACMIIDR_MD ((uint32_t)0x0000FFFF) /* MII data: read/write data from/to PHY */
Sergunb	0:f1834a63f7c1	7942
Sergunb	0:f1834a63f7c1	7943	/* Bit definition for Ethernet MAC Flow Control Register */
Sergunb	0:f1834a63f7c1	7944	#define ETH_MACFCR_PT ((uint32_t)0xFFFF0000) /* Pause time */
Sergunb	0:f1834a63f7c1	7945	#define ETH_MACFCR_ZQPD ((uint32_t)0x00000080) /* Zero-quanta pause disable */
Sergunb	0:f1834a63f7c1	7946	#define ETH_MACFCR_PLT ((uint32_t)0x00000030) /* Pause low threshold: 4 cases */
Sergunb	0:f1834a63f7c1	7947	#define ETH_MACFCR_PLT_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
Sergunb	0:f1834a63f7c1	7948	#define ETH_MACFCR_PLT_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */
Sergunb	0:f1834a63f7c1	7949	#define ETH_MACFCR_PLT_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */
Sergunb	0:f1834a63f7c1	7950	#define ETH_MACFCR_PLT_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */
Sergunb	0:f1834a63f7c1	7951	#define ETH_MACFCR_UPFD ((uint32_t)0x00000008) /* Unicast pause frame detect */
Sergunb	0:f1834a63f7c1	7952	#define ETH_MACFCR_RFCE ((uint32_t)0x00000004) /* Receive flow control enable */
Sergunb	0:f1834a63f7c1	7953	#define ETH_MACFCR_TFCE ((uint32_t)0x00000002) /* Transmit flow control enable */
Sergunb	0:f1834a63f7c1	7954	#define ETH_MACFCR_FCBBPA ((uint32_t)0x00000001) /* Flow control busy/backpressure activate */
Sergunb	0:f1834a63f7c1	7955
Sergunb	0:f1834a63f7c1	7956	/* Bit definition for Ethernet MAC VLAN Tag Register */
Sergunb	0:f1834a63f7c1	7957	#define ETH_MACVLANTR_VLANTC ((uint32_t)0x00010000) /* 12-bit VLAN tag comparison */
Sergunb	0:f1834a63f7c1	7958	#define ETH_MACVLANTR_VLANTI ((uint32_t)0x0000FFFF) /* VLAN tag identifier (for receive frames) */
Sergunb	0:f1834a63f7c1	7959
Sergunb	0:f1834a63f7c1	7960	/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
Sergunb	0:f1834a63f7c1	7961	#define ETH_MACRWUFFR_D ((uint32_t)0xFFFFFFFF) /* Wake-up frame filter register data */
Sergunb	0:f1834a63f7c1	7962	/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Sergunb	0:f1834a63f7c1	7963	Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
Sergunb	0:f1834a63f7c1	7964	/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Sergunb	0:f1834a63f7c1	7965	Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Sergunb	0:f1834a63f7c1	7966	Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Sergunb	0:f1834a63f7c1	7967	Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Sergunb	0:f1834a63f7c1	7968	Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
Sergunb	0:f1834a63f7c1	7969	RSVD - Filter1 Command - RSVD - Filter0 Command
Sergunb	0:f1834a63f7c1	7970	Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Sergunb	0:f1834a63f7c1	7971	Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Sergunb	0:f1834a63f7c1	7972	Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
Sergunb	0:f1834a63f7c1	7973
Sergunb	0:f1834a63f7c1	7974	/* Bit definition for Ethernet MAC PMT Control and Status Register */
Sergunb	0:f1834a63f7c1	7975	#define ETH_MACPMTCSR_WFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */
Sergunb	0:f1834a63f7c1	7976	#define ETH_MACPMTCSR_GU ((uint32_t)0x00000200) /* Global Unicast */
Sergunb	0:f1834a63f7c1	7977	#define ETH_MACPMTCSR_WFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */
Sergunb	0:f1834a63f7c1	7978	#define ETH_MACPMTCSR_MPR ((uint32_t)0x00000020) /* Magic Packet Received */
Sergunb	0:f1834a63f7c1	7979	#define ETH_MACPMTCSR_WFE ((uint32_t)0x00000004) /* Wake-Up Frame Enable */
Sergunb	0:f1834a63f7c1	7980	#define ETH_MACPMTCSR_MPE ((uint32_t)0x00000002) /* Magic Packet Enable */
Sergunb	0:f1834a63f7c1	7981	#define ETH_MACPMTCSR_PD ((uint32_t)0x00000001) /* Power Down */
Sergunb	0:f1834a63f7c1	7982
Sergunb	0:f1834a63f7c1	7983	/* Bit definition for Ethernet MAC Status Register */
Sergunb	0:f1834a63f7c1	7984	#define ETH_MACSR_TSTS ((uint32_t)0x00000200) /* Time stamp trigger status */
Sergunb	0:f1834a63f7c1	7985	#define ETH_MACSR_MMCTS ((uint32_t)0x00000040) /* MMC transmit status */
Sergunb	0:f1834a63f7c1	7986	#define ETH_MACSR_MMMCRS ((uint32_t)0x00000020) /* MMC receive status */
Sergunb	0:f1834a63f7c1	7987	#define ETH_MACSR_MMCS ((uint32_t)0x00000010) /* MMC status */
Sergunb	0:f1834a63f7c1	7988	#define ETH_MACSR_PMTS ((uint32_t)0x00000008) /* PMT status */
Sergunb	0:f1834a63f7c1	7989
Sergunb	0:f1834a63f7c1	7990	/* Bit definition for Ethernet MAC Interrupt Mask Register */
Sergunb	0:f1834a63f7c1	7991	#define ETH_MACIMR_TSTIM ((uint32_t)0x00000200) /* Time stamp trigger interrupt mask */
Sergunb	0:f1834a63f7c1	7992	#define ETH_MACIMR_PMTIM ((uint32_t)0x00000008) /* PMT interrupt mask */
Sergunb	0:f1834a63f7c1	7993
Sergunb	0:f1834a63f7c1	7994	/* Bit definition for Ethernet MAC Address0 High Register */
Sergunb	0:f1834a63f7c1	7995	#define ETH_MACA0HR_MACA0H ((uint32_t)0x0000FFFF) /* MAC address0 high */
Sergunb	0:f1834a63f7c1	7996
Sergunb	0:f1834a63f7c1	7997	/* Bit definition for Ethernet MAC Address0 Low Register */
Sergunb	0:f1834a63f7c1	7998	#define ETH_MACA0LR_MACA0L ((uint32_t)0xFFFFFFFF) /* MAC address0 low */
Sergunb	0:f1834a63f7c1	7999
Sergunb	0:f1834a63f7c1	8000	/* Bit definition for Ethernet MAC Address1 High Register */
Sergunb	0:f1834a63f7c1	8001	#define ETH_MACA1HR_AE ((uint32_t)0x80000000) /* Address enable */
Sergunb	0:f1834a63f7c1	8002	#define ETH_MACA1HR_SA ((uint32_t)0x40000000) /* Source address */
Sergunb	0:f1834a63f7c1	8003	#define ETH_MACA1HR_MBC ((uint32_t)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
Sergunb	0:f1834a63f7c1	8004	#define ETH_MACA1HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Sergunb	0:f1834a63f7c1	8005	#define ETH_MACA1HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Sergunb	0:f1834a63f7c1	8006	#define ETH_MACA1HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Sergunb	0:f1834a63f7c1	8007	#define ETH_MACA1HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Sergunb	0:f1834a63f7c1	8008	#define ETH_MACA1HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Sergunb	0:f1834a63f7c1	8009	#define ETH_MACA1HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
Sergunb	0:f1834a63f7c1	8010	#define ETH_MACA1HR_MACA1H ((uint32_t)0x0000FFFF) /* MAC address1 high */
Sergunb	0:f1834a63f7c1	8011
Sergunb	0:f1834a63f7c1	8012	/* Bit definition for Ethernet MAC Address1 Low Register */
Sergunb	0:f1834a63f7c1	8013	#define ETH_MACA1LR_MACA1L ((uint32_t)0xFFFFFFFF) /* MAC address1 low */
Sergunb	0:f1834a63f7c1	8014
Sergunb	0:f1834a63f7c1	8015	/* Bit definition for Ethernet MAC Address2 High Register */
Sergunb	0:f1834a63f7c1	8016	#define ETH_MACA2HR_AE ((uint32_t)0x80000000) /* Address enable */
Sergunb	0:f1834a63f7c1	8017	#define ETH_MACA2HR_SA ((uint32_t)0x40000000) /* Source address */
Sergunb	0:f1834a63f7c1	8018	#define ETH_MACA2HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
Sergunb	0:f1834a63f7c1	8019	#define ETH_MACA2HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Sergunb	0:f1834a63f7c1	8020	#define ETH_MACA2HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Sergunb	0:f1834a63f7c1	8021	#define ETH_MACA2HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Sergunb	0:f1834a63f7c1	8022	#define ETH_MACA2HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Sergunb	0:f1834a63f7c1	8023	#define ETH_MACA2HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Sergunb	0:f1834a63f7c1	8024	#define ETH_MACA2HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
Sergunb	0:f1834a63f7c1	8025	#define ETH_MACA2HR_MACA2H ((uint32_t)0x0000FFFF) /* MAC address1 high */
Sergunb	0:f1834a63f7c1	8026
Sergunb	0:f1834a63f7c1	8027	/* Bit definition for Ethernet MAC Address2 Low Register */
Sergunb	0:f1834a63f7c1	8028	#define ETH_MACA2LR_MACA2L ((uint32_t)0xFFFFFFFF) /* MAC address2 low */
Sergunb	0:f1834a63f7c1	8029
Sergunb	0:f1834a63f7c1	8030	/* Bit definition for Ethernet MAC Address3 High Register */
Sergunb	0:f1834a63f7c1	8031	#define ETH_MACA3HR_AE ((uint32_t)0x80000000) /* Address enable */
Sergunb	0:f1834a63f7c1	8032	#define ETH_MACA3HR_SA ((uint32_t)0x40000000) /* Source address */
Sergunb	0:f1834a63f7c1	8033	#define ETH_MACA3HR_MBC ((uint32_t)0x3F000000) /* Mask byte control */
Sergunb	0:f1834a63f7c1	8034	#define ETH_MACA3HR_MBC_HBits15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
Sergunb	0:f1834a63f7c1	8035	#define ETH_MACA3HR_MBC_HBits7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
Sergunb	0:f1834a63f7c1	8036	#define ETH_MACA3HR_MBC_LBits31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
Sergunb	0:f1834a63f7c1	8037	#define ETH_MACA3HR_MBC_LBits23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
Sergunb	0:f1834a63f7c1	8038	#define ETH_MACA3HR_MBC_LBits15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
Sergunb	0:f1834a63f7c1	8039	#define ETH_MACA3HR_MBC_LBits7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */
Sergunb	0:f1834a63f7c1	8040	#define ETH_MACA3HR_MACA3H ((uint32_t)0x0000FFFF) /* MAC address3 high */
Sergunb	0:f1834a63f7c1	8041
Sergunb	0:f1834a63f7c1	8042	/* Bit definition for Ethernet MAC Address3 Low Register */
Sergunb	0:f1834a63f7c1	8043	#define ETH_MACA3LR_MACA3L ((uint32_t)0xFFFFFFFF) /* MAC address3 low */
Sergunb	0:f1834a63f7c1	8044
Sergunb	0:f1834a63f7c1	8045	/******************************************************************************/
Sergunb	0:f1834a63f7c1	8046	/* Ethernet MMC Registers bits definition */
Sergunb	0:f1834a63f7c1	8047	/******************************************************************************/
Sergunb	0:f1834a63f7c1	8048
Sergunb	0:f1834a63f7c1	8049	/* Bit definition for Ethernet MMC Contol Register */
Sergunb	0:f1834a63f7c1	8050	#define ETH_MMCCR_MCF ((uint32_t)0x00000008) /* MMC Counter Freeze */
Sergunb	0:f1834a63f7c1	8051	#define ETH_MMCCR_ROR ((uint32_t)0x00000004) /* Reset on Read */
Sergunb	0:f1834a63f7c1	8052	#define ETH_MMCCR_CSR ((uint32_t)0x00000002) /* Counter Stop Rollover */
Sergunb	0:f1834a63f7c1	8053	#define ETH_MMCCR_CR ((uint32_t)0x00000001) /* Counters Reset */
Sergunb	0:f1834a63f7c1	8054
Sergunb	0:f1834a63f7c1	8055	/* Bit definition for Ethernet MMC Receive Interrupt Register */
Sergunb	0:f1834a63f7c1	8056	#define ETH_MMCRIR_RGUFS ((uint32_t)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8057	#define ETH_MMCRIR_RFAES ((uint32_t)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8058	#define ETH_MMCRIR_RFCES ((uint32_t)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8059
Sergunb	0:f1834a63f7c1	8060	/* Bit definition for Ethernet MMC Transmit Interrupt Register */
Sergunb	0:f1834a63f7c1	8061	#define ETH_MMCTIR_TGFS ((uint32_t)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8062	#define ETH_MMCTIR_TGFMSCS ((uint32_t)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8063	#define ETH_MMCTIR_TGFSCS ((uint32_t)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8064
Sergunb	0:f1834a63f7c1	8065	/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
Sergunb	0:f1834a63f7c1	8066	#define ETH_MMCRIMR_RGUFM ((uint32_t)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8067	#define ETH_MMCRIMR_RFAEM ((uint32_t)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8068	#define ETH_MMCRIMR_RFCEM ((uint32_t)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8069
Sergunb	0:f1834a63f7c1	8070	/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
Sergunb	0:f1834a63f7c1	8071	#define ETH_MMCTIMR_TGFM ((uint32_t)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8072	#define ETH_MMCTIMR_TGFMSCM ((uint32_t)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8073	#define ETH_MMCTIMR_TGFSCM ((uint32_t)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
Sergunb	0:f1834a63f7c1	8074
Sergunb	0:f1834a63f7c1	8075	/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
Sergunb	0:f1834a63f7c1	8076	#define ETH_MMCTGFSCCR_TGFSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
Sergunb	0:f1834a63f7c1	8077
Sergunb	0:f1834a63f7c1	8078	/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
Sergunb	0:f1834a63f7c1	8079	#define ETH_MMCTGFMSCCR_TGFMSCC ((uint32_t)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
Sergunb	0:f1834a63f7c1	8080
Sergunb	0:f1834a63f7c1	8081	/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
Sergunb	0:f1834a63f7c1	8082	#define ETH_MMCTGFCR_TGFC ((uint32_t)0xFFFFFFFF) /* Number of good frames transmitted. */
Sergunb	0:f1834a63f7c1	8083
Sergunb	0:f1834a63f7c1	8084	/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
Sergunb	0:f1834a63f7c1	8085	#define ETH_MMCRFCECR_RFCEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with CRC error. */
Sergunb	0:f1834a63f7c1	8086
Sergunb	0:f1834a63f7c1	8087	/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
Sergunb	0:f1834a63f7c1	8088	#define ETH_MMCRFAECR_RFAEC ((uint32_t)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */
Sergunb	0:f1834a63f7c1	8089
Sergunb	0:f1834a63f7c1	8090	/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
Sergunb	0:f1834a63f7c1	8091	#define ETH_MMCRGUFCR_RGUFC ((uint32_t)0xFFFFFFFF) /* Number of good unicast frames received. */
Sergunb	0:f1834a63f7c1	8092
Sergunb	0:f1834a63f7c1	8093	/******************************************************************************/
Sergunb	0:f1834a63f7c1	8094	/* Ethernet PTP Registers bits definition */
Sergunb	0:f1834a63f7c1	8095	/******************************************************************************/
Sergunb	0:f1834a63f7c1	8096
Sergunb	0:f1834a63f7c1	8097	/* Bit definition for Ethernet PTP Time Stamp Contol Register */
Sergunb	0:f1834a63f7c1	8098	#define ETH_PTPTSCR_TSARU ((uint32_t)0x00000020) /* Addend register update */
Sergunb	0:f1834a63f7c1	8099	#define ETH_PTPTSCR_TSITE ((uint32_t)0x00000010) /* Time stamp interrupt trigger enable */
Sergunb	0:f1834a63f7c1	8100	#define ETH_PTPTSCR_TSSTU ((uint32_t)0x00000008) /* Time stamp update */
Sergunb	0:f1834a63f7c1	8101	#define ETH_PTPTSCR_TSSTI ((uint32_t)0x00000004) /* Time stamp initialize */
Sergunb	0:f1834a63f7c1	8102	#define ETH_PTPTSCR_TSFCU ((uint32_t)0x00000002) /* Time stamp fine or coarse update */
Sergunb	0:f1834a63f7c1	8103	#define ETH_PTPTSCR_TSE ((uint32_t)0x00000001) /* Time stamp enable */
Sergunb	0:f1834a63f7c1	8104
Sergunb	0:f1834a63f7c1	8105	/* Bit definition for Ethernet PTP Sub-Second Increment Register */
Sergunb	0:f1834a63f7c1	8106	#define ETH_PTPSSIR_STSSI ((uint32_t)0x000000FF) /* System time Sub-second increment value */
Sergunb	0:f1834a63f7c1	8107
Sergunb	0:f1834a63f7c1	8108	/* Bit definition for Ethernet PTP Time Stamp High Register */
Sergunb	0:f1834a63f7c1	8109	#define ETH_PTPTSHR_STS ((uint32_t)0xFFFFFFFF) /* System Time second */
Sergunb	0:f1834a63f7c1	8110
Sergunb	0:f1834a63f7c1	8111	/* Bit definition for Ethernet PTP Time Stamp Low Register */
Sergunb	0:f1834a63f7c1	8112	#define ETH_PTPTSLR_STPNS ((uint32_t)0x80000000) /* System Time Positive or negative time */
Sergunb	0:f1834a63f7c1	8113	#define ETH_PTPTSLR_STSS ((uint32_t)0x7FFFFFFF) /* System Time sub-seconds */
Sergunb	0:f1834a63f7c1	8114
Sergunb	0:f1834a63f7c1	8115	/* Bit definition for Ethernet PTP Time Stamp High Update Register */
Sergunb	0:f1834a63f7c1	8116	#define ETH_PTPTSHUR_TSUS ((uint32_t)0xFFFFFFFF) /* Time stamp update seconds */
Sergunb	0:f1834a63f7c1	8117
Sergunb	0:f1834a63f7c1	8118	/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
Sergunb	0:f1834a63f7c1	8119	#define ETH_PTPTSLUR_TSUPNS ((uint32_t)0x80000000) /* Time stamp update Positive or negative time */
Sergunb	0:f1834a63f7c1	8120	#define ETH_PTPTSLUR_TSUSS ((uint32_t)0x7FFFFFFF) /* Time stamp update sub-seconds */
Sergunb	0:f1834a63f7c1	8121
Sergunb	0:f1834a63f7c1	8122	/* Bit definition for Ethernet PTP Time Stamp Addend Register */
Sergunb	0:f1834a63f7c1	8123	#define ETH_PTPTSAR_TSA ((uint32_t)0xFFFFFFFF) /* Time stamp addend */
Sergunb	0:f1834a63f7c1	8124
Sergunb	0:f1834a63f7c1	8125	/* Bit definition for Ethernet PTP Target Time High Register */
Sergunb	0:f1834a63f7c1	8126	#define ETH_PTPTTHR_TTSH ((uint32_t)0xFFFFFFFF) /* Target time stamp high */
Sergunb	0:f1834a63f7c1	8127
Sergunb	0:f1834a63f7c1	8128	/* Bit definition for Ethernet PTP Target Time Low Register */
Sergunb	0:f1834a63f7c1	8129	#define ETH_PTPTTLR_TTSL ((uint32_t)0xFFFFFFFF) /* Target time stamp low */
Sergunb	0:f1834a63f7c1	8130
Sergunb	0:f1834a63f7c1	8131	/******************************************************************************/
Sergunb	0:f1834a63f7c1	8132	/* Ethernet DMA Registers bits definition */
Sergunb	0:f1834a63f7c1	8133	/******************************************************************************/
Sergunb	0:f1834a63f7c1	8134
Sergunb	0:f1834a63f7c1	8135	/* Bit definition for Ethernet DMA Bus Mode Register */
Sergunb	0:f1834a63f7c1	8136	#define ETH_DMABMR_AAB ((uint32_t)0x02000000) /* Address-Aligned beats */
Sergunb	0:f1834a63f7c1	8137	#define ETH_DMABMR_FPM ((uint32_t)0x01000000) /* 4xPBL mode */
Sergunb	0:f1834a63f7c1	8138	#define ETH_DMABMR_USP ((uint32_t)0x00800000) /* Use separate PBL */
Sergunb	0:f1834a63f7c1	8139	#define ETH_DMABMR_RDP ((uint32_t)0x007E0000) /* RxDMA PBL */
Sergunb	0:f1834a63f7c1	8140	#define ETH_DMABMR_RDP_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
Sergunb	0:f1834a63f7c1	8141	#define ETH_DMABMR_RDP_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
Sergunb	0:f1834a63f7c1	8142	#define ETH_DMABMR_RDP_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Sergunb	0:f1834a63f7c1	8143	#define ETH_DMABMR_RDP_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Sergunb	0:f1834a63f7c1	8144	#define ETH_DMABMR_RDP_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Sergunb	0:f1834a63f7c1	8145	#define ETH_DMABMR_RDP_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Sergunb	0:f1834a63f7c1	8146	#define ETH_DMABMR_RDP_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Sergunb	0:f1834a63f7c1	8147	#define ETH_DMABMR_RDP_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Sergunb	0:f1834a63f7c1	8148	#define ETH_DMABMR_RDP_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Sergunb	0:f1834a63f7c1	8149	#define ETH_DMABMR_RDP_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Sergunb	0:f1834a63f7c1	8150	#define ETH_DMABMR_RDP_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
Sergunb	0:f1834a63f7c1	8151	#define ETH_DMABMR_RDP_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
Sergunb	0:f1834a63f7c1	8152	#define ETH_DMABMR_FB ((uint32_t)0x00010000) /* Fixed Burst */
Sergunb	0:f1834a63f7c1	8153	#define ETH_DMABMR_RTPR ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
Sergunb	0:f1834a63f7c1	8154	#define ETH_DMABMR_RTPR_1_1 ((uint32_t)0x00000000) /* Rx Tx priority ratio */
Sergunb	0:f1834a63f7c1	8155	#define ETH_DMABMR_RTPR_2_1 ((uint32_t)0x00004000) /* Rx Tx priority ratio */
Sergunb	0:f1834a63f7c1	8156	#define ETH_DMABMR_RTPR_3_1 ((uint32_t)0x00008000) /* Rx Tx priority ratio */
Sergunb	0:f1834a63f7c1	8157	#define ETH_DMABMR_RTPR_4_1 ((uint32_t)0x0000C000) /* Rx Tx priority ratio */
Sergunb	0:f1834a63f7c1	8158	#define ETH_DMABMR_PBL ((uint32_t)0x00003F00) /* Programmable burst length */
Sergunb	0:f1834a63f7c1	8159	#define ETH_DMABMR_PBL_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
Sergunb	0:f1834a63f7c1	8160	#define ETH_DMABMR_PBL_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
Sergunb	0:f1834a63f7c1	8161	#define ETH_DMABMR_PBL_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Sergunb	0:f1834a63f7c1	8162	#define ETH_DMABMR_PBL_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Sergunb	0:f1834a63f7c1	8163	#define ETH_DMABMR_PBL_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Sergunb	0:f1834a63f7c1	8164	#define ETH_DMABMR_PBL_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Sergunb	0:f1834a63f7c1	8165	#define ETH_DMABMR_PBL_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Sergunb	0:f1834a63f7c1	8166	#define ETH_DMABMR_PBL_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Sergunb	0:f1834a63f7c1	8167	#define ETH_DMABMR_PBL_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Sergunb	0:f1834a63f7c1	8168	#define ETH_DMABMR_PBL_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Sergunb	0:f1834a63f7c1	8169	#define ETH_DMABMR_PBL_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
Sergunb	0:f1834a63f7c1	8170	#define ETH_DMABMR_PBL_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Sergunb	0:f1834a63f7c1	8171	#define ETH_DMABMR_DSL ((uint32_t)0x0000007C) /* Descriptor Skip Length */
Sergunb	0:f1834a63f7c1	8172	#define ETH_DMABMR_DA ((uint32_t)0x00000002) /* DMA arbitration scheme */
Sergunb	0:f1834a63f7c1	8173	#define ETH_DMABMR_SR ((uint32_t)0x00000001) /* Software reset */
Sergunb	0:f1834a63f7c1	8174
Sergunb	0:f1834a63f7c1	8175	/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
Sergunb	0:f1834a63f7c1	8176	#define ETH_DMATPDR_TPD ((uint32_t)0xFFFFFFFF) /* Transmit poll demand */
Sergunb	0:f1834a63f7c1	8177
Sergunb	0:f1834a63f7c1	8178	/* Bit definition for Ethernet DMA Receive Poll Demand Register */
Sergunb	0:f1834a63f7c1	8179	#define ETH_DMARPDR_RPD ((uint32_t)0xFFFFFFFF) /* Receive poll demand */
Sergunb	0:f1834a63f7c1	8180
Sergunb	0:f1834a63f7c1	8181	/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
Sergunb	0:f1834a63f7c1	8182	#define ETH_DMARDLAR_SRL ((uint32_t)0xFFFFFFFF) /* Start of receive list */
Sergunb	0:f1834a63f7c1	8183
Sergunb	0:f1834a63f7c1	8184	/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
Sergunb	0:f1834a63f7c1	8185	#define ETH_DMATDLAR_STL ((uint32_t)0xFFFFFFFF) /* Start of transmit list */
Sergunb	0:f1834a63f7c1	8186
Sergunb	0:f1834a63f7c1	8187	/* Bit definition for Ethernet DMA Status Register */
Sergunb	0:f1834a63f7c1	8188	#define ETH_DMASR_TSTS ((uint32_t)0x20000000) /* Time-stamp trigger status */
Sergunb	0:f1834a63f7c1	8189	#define ETH_DMASR_PMTS ((uint32_t)0x10000000) /* PMT status */
Sergunb	0:f1834a63f7c1	8190	#define ETH_DMASR_MMCS ((uint32_t)0x08000000) /* MMC status */
Sergunb	0:f1834a63f7c1	8191	#define ETH_DMASR_EBS ((uint32_t)0x03800000) /* Error bits status */
Sergunb	0:f1834a63f7c1	8192	/* combination with EBS[2:0] for GetFlagStatus function */
Sergunb	0:f1834a63f7c1	8193	#define ETH_DMASR_EBS_DescAccess ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */
Sergunb	0:f1834a63f7c1	8194	#define ETH_DMASR_EBS_ReadTransf ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */
Sergunb	0:f1834a63f7c1	8195	#define ETH_DMASR_EBS_DataTransfTx ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */
Sergunb	0:f1834a63f7c1	8196	#define ETH_DMASR_TPS ((uint32_t)0x00700000) /* Transmit process state */
Sergunb	0:f1834a63f7c1	8197	#define ETH_DMASR_TPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */
Sergunb	0:f1834a63f7c1	8198	#define ETH_DMASR_TPS_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */
Sergunb	0:f1834a63f7c1	8199	#define ETH_DMASR_TPS_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */
Sergunb	0:f1834a63f7c1	8200	#define ETH_DMASR_TPS_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */
Sergunb	0:f1834a63f7c1	8201	#define ETH_DMASR_TPS_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Descriptor unavailabe */
Sergunb	0:f1834a63f7c1	8202	#define ETH_DMASR_TPS_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */
Sergunb	0:f1834a63f7c1	8203	#define ETH_DMASR_RPS ((uint32_t)0x000E0000) /* Receive process state */
Sergunb	0:f1834a63f7c1	8204	#define ETH_DMASR_RPS_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */
Sergunb	0:f1834a63f7c1	8205	#define ETH_DMASR_RPS_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */
Sergunb	0:f1834a63f7c1	8206	#define ETH_DMASR_RPS_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */
Sergunb	0:f1834a63f7c1	8207	#define ETH_DMASR_RPS_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Descriptor unavailable */
Sergunb	0:f1834a63f7c1	8208	#define ETH_DMASR_RPS_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */
Sergunb	0:f1834a63f7c1	8209	#define ETH_DMASR_RPS_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */
Sergunb	0:f1834a63f7c1	8210	#define ETH_DMASR_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */
Sergunb	0:f1834a63f7c1	8211	#define ETH_DMASR_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */
Sergunb	0:f1834a63f7c1	8212	#define ETH_DMASR_ERS ((uint32_t)0x00004000) /* Early receive status */
Sergunb	0:f1834a63f7c1	8213	#define ETH_DMASR_FBES ((uint32_t)0x00002000) /* Fatal bus error status */
Sergunb	0:f1834a63f7c1	8214	#define ETH_DMASR_ETS ((uint32_t)0x00000400) /* Early transmit status */
Sergunb	0:f1834a63f7c1	8215	#define ETH_DMASR_RWTS ((uint32_t)0x00000200) /* Receive watchdog timeout status */
Sergunb	0:f1834a63f7c1	8216	#define ETH_DMASR_RPSS ((uint32_t)0x00000100) /* Receive process stopped status */
Sergunb	0:f1834a63f7c1	8217	#define ETH_DMASR_RBUS ((uint32_t)0x00000080) /* Receive buffer unavailable status */
Sergunb	0:f1834a63f7c1	8218	#define ETH_DMASR_RS ((uint32_t)0x00000040) /* Receive status */
Sergunb	0:f1834a63f7c1	8219	#define ETH_DMASR_TUS ((uint32_t)0x00000020) /* Transmit underflow status */
Sergunb	0:f1834a63f7c1	8220	#define ETH_DMASR_ROS ((uint32_t)0x00000010) /* Receive overflow status */
Sergunb	0:f1834a63f7c1	8221	#define ETH_DMASR_TJTS ((uint32_t)0x00000008) /* Transmit jabber timeout status */
Sergunb	0:f1834a63f7c1	8222	#define ETH_DMASR_TBUS ((uint32_t)0x00000004) /* Transmit buffer unavailable status */
Sergunb	0:f1834a63f7c1	8223	#define ETH_DMASR_TPSS ((uint32_t)0x00000002) /* Transmit process stopped status */
Sergunb	0:f1834a63f7c1	8224	#define ETH_DMASR_TS ((uint32_t)0x00000001) /* Transmit status */
Sergunb	0:f1834a63f7c1	8225
Sergunb	0:f1834a63f7c1	8226	/* Bit definition for Ethernet DMA Operation Mode Register */
Sergunb	0:f1834a63f7c1	8227	#define ETH_DMAOMR_DTCEFD ((uint32_t)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */
Sergunb	0:f1834a63f7c1	8228	#define ETH_DMAOMR_RSF ((uint32_t)0x02000000) /* Receive store and forward */
Sergunb	0:f1834a63f7c1	8229	#define ETH_DMAOMR_DFRF ((uint32_t)0x01000000) /* Disable flushing of received frames */
Sergunb	0:f1834a63f7c1	8230	#define ETH_DMAOMR_TSF ((uint32_t)0x00200000) /* Transmit store and forward */
Sergunb	0:f1834a63f7c1	8231	#define ETH_DMAOMR_FTF ((uint32_t)0x00100000) /* Flush transmit FIFO */
Sergunb	0:f1834a63f7c1	8232	#define ETH_DMAOMR_TTC ((uint32_t)0x0001C000) /* Transmit threshold control */
Sergunb	0:f1834a63f7c1	8233	#define ETH_DMAOMR_TTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */
Sergunb	0:f1834a63f7c1	8234	#define ETH_DMAOMR_TTC_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */
Sergunb	0:f1834a63f7c1	8235	#define ETH_DMAOMR_TTC_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */
Sergunb	0:f1834a63f7c1	8236	#define ETH_DMAOMR_TTC_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */
Sergunb	0:f1834a63f7c1	8237	#define ETH_DMAOMR_TTC_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */
Sergunb	0:f1834a63f7c1	8238	#define ETH_DMAOMR_TTC_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */
Sergunb	0:f1834a63f7c1	8239	#define ETH_DMAOMR_TTC_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */
Sergunb	0:f1834a63f7c1	8240	#define ETH_DMAOMR_TTC_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */
Sergunb	0:f1834a63f7c1	8241	#define ETH_DMAOMR_ST ((uint32_t)0x00002000) /* Start/stop transmission command */
Sergunb	0:f1834a63f7c1	8242	#define ETH_DMAOMR_FEF ((uint32_t)0x00000080) /* Forward error frames */
Sergunb	0:f1834a63f7c1	8243	#define ETH_DMAOMR_FUGF ((uint32_t)0x00000040) /* Forward undersized good frames */
Sergunb	0:f1834a63f7c1	8244	#define ETH_DMAOMR_RTC ((uint32_t)0x00000018) /* receive threshold control */
Sergunb	0:f1834a63f7c1	8245	#define ETH_DMAOMR_RTC_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */
Sergunb	0:f1834a63f7c1	8246	#define ETH_DMAOMR_RTC_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */
Sergunb	0:f1834a63f7c1	8247	#define ETH_DMAOMR_RTC_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */
Sergunb	0:f1834a63f7c1	8248	#define ETH_DMAOMR_RTC_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */
Sergunb	0:f1834a63f7c1	8249	#define ETH_DMAOMR_OSF ((uint32_t)0x00000004) /* operate on second frame */
Sergunb	0:f1834a63f7c1	8250	#define ETH_DMAOMR_SR ((uint32_t)0x00000002) /* Start/stop receive */
Sergunb	0:f1834a63f7c1	8251
Sergunb	0:f1834a63f7c1	8252	/* Bit definition for Ethernet DMA Interrupt Enable Register */
Sergunb	0:f1834a63f7c1	8253	#define ETH_DMAIER_NISE ((uint32_t)0x00010000) /* Normal interrupt summary enable */
Sergunb	0:f1834a63f7c1	8254	#define ETH_DMAIER_AISE ((uint32_t)0x00008000) /* Abnormal interrupt summary enable */
Sergunb	0:f1834a63f7c1	8255	#define ETH_DMAIER_ERIE ((uint32_t)0x00004000) /* Early receive interrupt enable */
Sergunb	0:f1834a63f7c1	8256	#define ETH_DMAIER_FBEIE ((uint32_t)0x00002000) /* Fatal bus error interrupt enable */
Sergunb	0:f1834a63f7c1	8257	#define ETH_DMAIER_ETIE ((uint32_t)0x00000400) /* Early transmit interrupt enable */
Sergunb	0:f1834a63f7c1	8258	#define ETH_DMAIER_RWTIE ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt enable */
Sergunb	0:f1834a63f7c1	8259	#define ETH_DMAIER_RPSIE ((uint32_t)0x00000100) /* Receive process stopped interrupt enable */
Sergunb	0:f1834a63f7c1	8260	#define ETH_DMAIER_RBUIE ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt enable */
Sergunb	0:f1834a63f7c1	8261	#define ETH_DMAIER_RIE ((uint32_t)0x00000040) /* Receive interrupt enable */
Sergunb	0:f1834a63f7c1	8262	#define ETH_DMAIER_TUIE ((uint32_t)0x00000020) /* Transmit Underflow interrupt enable */
Sergunb	0:f1834a63f7c1	8263	#define ETH_DMAIER_ROIE ((uint32_t)0x00000010) /* Receive Overflow interrupt enable */
Sergunb	0:f1834a63f7c1	8264	#define ETH_DMAIER_TJTIE ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt enable */
Sergunb	0:f1834a63f7c1	8265	#define ETH_DMAIER_TBUIE ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt enable */
Sergunb	0:f1834a63f7c1	8266	#define ETH_DMAIER_TPSIE ((uint32_t)0x00000002) /* Transmit process stopped interrupt enable */
Sergunb	0:f1834a63f7c1	8267	#define ETH_DMAIER_TIE ((uint32_t)0x00000001) /* Transmit interrupt enable */
Sergunb	0:f1834a63f7c1	8268
Sergunb	0:f1834a63f7c1	8269	/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
Sergunb	0:f1834a63f7c1	8270	#define ETH_DMAMFBOCR_OFOC ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */
Sergunb	0:f1834a63f7c1	8271	#define ETH_DMAMFBOCR_MFA ((uint32_t)0x0FFE0000) /* Number of frames missed by the application */
Sergunb	0:f1834a63f7c1	8272	#define ETH_DMAMFBOCR_OMFC ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */
Sergunb	0:f1834a63f7c1	8273	#define ETH_DMAMFBOCR_MFC ((uint32_t)0x0000FFFF) /* Number of frames missed by the controller */
Sergunb	0:f1834a63f7c1	8274
Sergunb	0:f1834a63f7c1	8275	/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
Sergunb	0:f1834a63f7c1	8276	#define ETH_DMACHTDR_HTDAP ((uint32_t)0xFFFFFFFF) /* Host transmit descriptor address pointer */
Sergunb	0:f1834a63f7c1	8277
Sergunb	0:f1834a63f7c1	8278	/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
Sergunb	0:f1834a63f7c1	8279	#define ETH_DMACHRDR_HRDAP ((uint32_t)0xFFFFFFFF) /* Host receive descriptor address pointer */
Sergunb	0:f1834a63f7c1	8280
Sergunb	0:f1834a63f7c1	8281	/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
Sergunb	0:f1834a63f7c1	8282	#define ETH_DMACHTBAR_HTBAP ((uint32_t)0xFFFFFFFF) /* Host transmit buffer address pointer */
Sergunb	0:f1834a63f7c1	8283
Sergunb	0:f1834a63f7c1	8284	/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
Sergunb	0:f1834a63f7c1	8285	#define ETH_DMACHRBAR_HRBAP ((uint32_t)0xFFFFFFFF) /* Host receive buffer address pointer */
Sergunb	0:f1834a63f7c1	8286	#endif /* STM32F10X_CL */
Sergunb	0:f1834a63f7c1	8287
Sergunb	0:f1834a63f7c1	8288	/**
Sergunb	0:f1834a63f7c1	8289	* @}
Sergunb	0:f1834a63f7c1	8290	*/
Sergunb	0:f1834a63f7c1	8291
Sergunb	0:f1834a63f7c1	8292	/**
Sergunb	0:f1834a63f7c1	8293	* @}
Sergunb	0:f1834a63f7c1	8294	*/
Sergunb	0:f1834a63f7c1	8295
Sergunb	0:f1834a63f7c1	8296	#ifdef USE_STDPERIPH_DRIVER
Sergunb	0:f1834a63f7c1	8297	#include "stm32f10x_conf.h"
Sergunb	0:f1834a63f7c1	8298	#endif
Sergunb	0:f1834a63f7c1	8299
Sergunb	0:f1834a63f7c1	8300	/** @addtogroup Exported_macro
Sergunb	0:f1834a63f7c1	8301	* @{
Sergunb	0:f1834a63f7c1	8302	*/
Sergunb	0:f1834a63f7c1	8303
Sergunb	0:f1834a63f7c1	8304	#define SET_BIT(REG, BIT) ((REG) \|= (BIT))
Sergunb	0:f1834a63f7c1	8305
Sergunb	0:f1834a63f7c1	8306	#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
Sergunb	0:f1834a63f7c1	8307
Sergunb	0:f1834a63f7c1	8308	#define READ_BIT(REG, BIT) ((REG) & (BIT))
Sergunb	0:f1834a63f7c1	8309
Sergunb	0:f1834a63f7c1	8310	#define CLEAR_REG(REG) ((REG) = (0x0))
Sergunb	0:f1834a63f7c1	8311
Sergunb	0:f1834a63f7c1	8312	#define WRITE_REG(REG, VAL) ((REG) = (VAL))
Sergunb	0:f1834a63f7c1	8313
Sergunb	0:f1834a63f7c1	8314	#define READ_REG(REG) ((REG))
Sergunb	0:f1834a63f7c1	8315
Sergunb	0:f1834a63f7c1	8316	#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) \| (SETMASK)))
Sergunb	0:f1834a63f7c1	8317
Sergunb	0:f1834a63f7c1	8318	/**
Sergunb	0:f1834a63f7c1	8319	* @}
Sergunb	0:f1834a63f7c1	8320	*/
Sergunb	0:f1834a63f7c1	8321
Sergunb	0:f1834a63f7c1	8322	#ifdef __cplusplus
Sergunb	0:f1834a63f7c1	8323	}
Sergunb	0:f1834a63f7c1	8324	#endif
Sergunb	0:f1834a63f7c1	8325
Sergunb	0:f1834a63f7c1	8326	#endif /* __STM32F10x_H */
Sergunb	0:f1834a63f7c1	8327
Sergunb	0:f1834a63f7c1	8328	/**
Sergunb	0:f1834a63f7c1	8329	* @}
Sergunb	0:f1834a63f7c1	8330	*/
Sergunb	0:f1834a63f7c1	8331
Sergunb	0:f1834a63f7c1	8332	/**
Sergunb	0:f1834a63f7c1	8333	* @}
Sergunb	0:f1834a63f7c1	8334	*/
Sergunb	0:f1834a63f7c1	8335
Sergunb	0:f1834a63f7c1	8336	/***************** (C) COPYRIGHT 2011 STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	04 Sep 2017
Imports:	69
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	7

cmsis_boot/stm32f10x.h@0:f1834a63f7c1, 2017-09-04 (annotated)

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