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cyclone_tcp/drivers/sam3x_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file sam3x_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief SAM3X Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include <limits.h>
Sergunb 0:8918a71cdbe9 34 #include "sam3xa.h"
Sergunb 0:8918a71cdbe9 35 #include "core/net.h"
Sergunb 0:8918a71cdbe9 36 #include "drivers/sam3x_eth.h"
Sergunb 0:8918a71cdbe9 37 #include "debug.h"
Sergunb 0:8918a71cdbe9 38
Sergunb 0:8918a71cdbe9 39 //Underlying network interface
Sergunb 0:8918a71cdbe9 40 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 43 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 44
Sergunb 0:8918a71cdbe9 45 //TX buffer
Sergunb 0:8918a71cdbe9 46 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 47 static uint8_t txBuffer[SAM3X_ETH_TX_BUFFER_COUNT][SAM3X_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 48 //RX buffer
Sergunb 0:8918a71cdbe9 49 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 50 static uint8_t rxBuffer[SAM3X_ETH_RX_BUFFER_COUNT][SAM3X_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 51 //TX buffer descriptors
Sergunb 0:8918a71cdbe9 52 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 53 static Sam3xTxBufferDesc txBufferDesc[SAM3X_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 54 //RX buffer descriptors
Sergunb 0:8918a71cdbe9 55 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 56 static Sam3xRxBufferDesc rxBufferDesc[SAM3X_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 57
Sergunb 0:8918a71cdbe9 58 //Keil MDK-ARM or GCC compiler?
Sergunb 0:8918a71cdbe9 59 #else
Sergunb 0:8918a71cdbe9 60
Sergunb 0:8918a71cdbe9 61 //TX buffer
Sergunb 0:8918a71cdbe9 62 static uint8_t txBuffer[SAM3X_ETH_TX_BUFFER_COUNT][SAM3X_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 63 __attribute__((aligned(8)));
Sergunb 0:8918a71cdbe9 64 //RX buffer
Sergunb 0:8918a71cdbe9 65 static uint8_t rxBuffer[SAM3X_ETH_RX_BUFFER_COUNT][SAM3X_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 66 __attribute__((aligned(8)));
Sergunb 0:8918a71cdbe9 67 //TX buffer descriptors
Sergunb 0:8918a71cdbe9 68 static Sam3xTxBufferDesc txBufferDesc[SAM3X_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 69 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 70 //RX buffer descriptors
Sergunb 0:8918a71cdbe9 71 static Sam3xRxBufferDesc rxBufferDesc[SAM3X_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 72 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 73
Sergunb 0:8918a71cdbe9 74 #endif
Sergunb 0:8918a71cdbe9 75
Sergunb 0:8918a71cdbe9 76 //TX buffer index
Sergunb 0:8918a71cdbe9 77 static uint_t txBufferIndex;
Sergunb 0:8918a71cdbe9 78 //RX buffer index
Sergunb 0:8918a71cdbe9 79 static uint_t rxBufferIndex;
Sergunb 0:8918a71cdbe9 80
Sergunb 0:8918a71cdbe9 81
Sergunb 0:8918a71cdbe9 82 /**
Sergunb 0:8918a71cdbe9 83 * @brief SAM3X Ethernet MAC driver
Sergunb 0:8918a71cdbe9 84 **/
Sergunb 0:8918a71cdbe9 85
Sergunb 0:8918a71cdbe9 86 const NicDriver sam3xEthDriver =
Sergunb 0:8918a71cdbe9 87 {
Sergunb 0:8918a71cdbe9 88 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 89 ETH_MTU,
Sergunb 0:8918a71cdbe9 90 sam3xEthInit,
Sergunb 0:8918a71cdbe9 91 sam3xEthTick,
Sergunb 0:8918a71cdbe9 92 sam3xEthEnableIrq,
Sergunb 0:8918a71cdbe9 93 sam3xEthDisableIrq,
Sergunb 0:8918a71cdbe9 94 sam3xEthEventHandler,
Sergunb 0:8918a71cdbe9 95 sam3xEthSendPacket,
Sergunb 0:8918a71cdbe9 96 sam3xEthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 97 sam3xEthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 98 sam3xEthWritePhyReg,
Sergunb 0:8918a71cdbe9 99 sam3xEthReadPhyReg,
Sergunb 0:8918a71cdbe9 100 TRUE,
Sergunb 0:8918a71cdbe9 101 TRUE,
Sergunb 0:8918a71cdbe9 102 TRUE,
Sergunb 0:8918a71cdbe9 103 FALSE
Sergunb 0:8918a71cdbe9 104 };
Sergunb 0:8918a71cdbe9 105
Sergunb 0:8918a71cdbe9 106
Sergunb 0:8918a71cdbe9 107 /**
Sergunb 0:8918a71cdbe9 108 * @brief SAM3X Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 109 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 110 * @return Error code
Sergunb 0:8918a71cdbe9 111 **/
Sergunb 0:8918a71cdbe9 112
Sergunb 0:8918a71cdbe9 113 error_t sam3xEthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 114 {
Sergunb 0:8918a71cdbe9 115 error_t error;
Sergunb 0:8918a71cdbe9 116 volatile uint32_t status;
Sergunb 0:8918a71cdbe9 117
Sergunb 0:8918a71cdbe9 118 //Debug message
Sergunb 0:8918a71cdbe9 119 TRACE_INFO("Initializing SAM3X Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 120
Sergunb 0:8918a71cdbe9 121 //Save underlying network interface
Sergunb 0:8918a71cdbe9 122 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 123
Sergunb 0:8918a71cdbe9 124 //Enable EMAC peripheral clock
Sergunb 0:8918a71cdbe9 125 PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
Sergunb 0:8918a71cdbe9 126
Sergunb 0:8918a71cdbe9 127 //GPIO configuration
Sergunb 0:8918a71cdbe9 128 sam3xEthInitGpio(interface);
Sergunb 0:8918a71cdbe9 129
Sergunb 0:8918a71cdbe9 130 //Configure MDC clock speed
Sergunb 0:8918a71cdbe9 131 EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
Sergunb 0:8918a71cdbe9 132 //Enable management port (MDC and MDIO)
Sergunb 0:8918a71cdbe9 133 EMAC->EMAC_NCR |= EMAC_NCR_MPE;
Sergunb 0:8918a71cdbe9 134
Sergunb 0:8918a71cdbe9 135 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 136 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 137 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 138 if(error)
Sergunb 0:8918a71cdbe9 139 return error;
Sergunb 0:8918a71cdbe9 140
Sergunb 0:8918a71cdbe9 141 //Set the MAC address
Sergunb 0:8918a71cdbe9 142 EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 143 EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 144
Sergunb 0:8918a71cdbe9 145 //Configure the receive filter
Sergunb 0:8918a71cdbe9 146 EMAC->EMAC_NCFGR |= EMAC_NCFGR_UNI | EMAC_NCFGR_MTI;
Sergunb 0:8918a71cdbe9 147
Sergunb 0:8918a71cdbe9 148 //Initialize hash table
Sergunb 0:8918a71cdbe9 149 EMAC->EMAC_HRB = 0;
Sergunb 0:8918a71cdbe9 150 EMAC->EMAC_HRT = 0;
Sergunb 0:8918a71cdbe9 151
Sergunb 0:8918a71cdbe9 152 //Initialize buffer descriptors
Sergunb 0:8918a71cdbe9 153 sam3xEthInitBufferDesc(interface);
Sergunb 0:8918a71cdbe9 154
Sergunb 0:8918a71cdbe9 155 //Clear transmit status register
Sergunb 0:8918a71cdbe9 156 EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
Sergunb 0:8918a71cdbe9 157 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
Sergunb 0:8918a71cdbe9 158 //Clear receive status register
Sergunb 0:8918a71cdbe9 159 EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
Sergunb 0:8918a71cdbe9 160
Sergunb 0:8918a71cdbe9 161 //First disable all EMAC interrupts
Sergunb 0:8918a71cdbe9 162 EMAC->EMAC_IDR = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 163 //Only the desired ones are enabled
Sergunb 0:8918a71cdbe9 164 EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
Sergunb 0:8918a71cdbe9 165 EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
Sergunb 0:8918a71cdbe9 166
Sergunb 0:8918a71cdbe9 167 //Read EMAC ISR register to clear any pending interrupt
Sergunb 0:8918a71cdbe9 168 status = EMAC->EMAC_ISR;
Sergunb 0:8918a71cdbe9 169
Sergunb 0:8918a71cdbe9 170 //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
Sergunb 0:8918a71cdbe9 171 NVIC_SetPriorityGrouping(SAM3X_ETH_IRQ_PRIORITY_GROUPING);
Sergunb 0:8918a71cdbe9 172
Sergunb 0:8918a71cdbe9 173 //Configure EMAC interrupt priority
Sergunb 0:8918a71cdbe9 174 NVIC_SetPriority(EMAC_IRQn, NVIC_EncodePriority(SAM3X_ETH_IRQ_PRIORITY_GROUPING,
Sergunb 0:8918a71cdbe9 175 SAM3X_ETH_IRQ_GROUP_PRIORITY, SAM3X_ETH_IRQ_SUB_PRIORITY));
Sergunb 0:8918a71cdbe9 176
Sergunb 0:8918a71cdbe9 177 //Enable the EMAC to transmit and receive data
Sergunb 0:8918a71cdbe9 178 EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
Sergunb 0:8918a71cdbe9 179
Sergunb 0:8918a71cdbe9 180 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 181 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 182
Sergunb 0:8918a71cdbe9 183 //Successful initialization
Sergunb 0:8918a71cdbe9 184 return NO_ERROR;
Sergunb 0:8918a71cdbe9 185 }
Sergunb 0:8918a71cdbe9 186
Sergunb 0:8918a71cdbe9 187
Sergunb 0:8918a71cdbe9 188 //SAM3X-EK evaluation board?
Sergunb 0:8918a71cdbe9 189 #if defined(USE_SAM3X_EK)
Sergunb 0:8918a71cdbe9 190
Sergunb 0:8918a71cdbe9 191 /**
Sergunb 0:8918a71cdbe9 192 * @brief GPIO configuration
Sergunb 0:8918a71cdbe9 193 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 194 **/
Sergunb 0:8918a71cdbe9 195
Sergunb 0:8918a71cdbe9 196 void sam3xEthInitGpio(NetInterface *interface)
Sergunb 0:8918a71cdbe9 197 {
Sergunb 0:8918a71cdbe9 198 //Enable PIO peripheral clock
Sergunb 0:8918a71cdbe9 199 PMC->PMC_PCER0 = (1 << ID_PIOB);
Sergunb 0:8918a71cdbe9 200
Sergunb 0:8918a71cdbe9 201 //Disable pull-up resistors on RMII pins
Sergunb 0:8918a71cdbe9 202 PIOB->PIO_PUDR = EMAC_RMII_MASK;
Sergunb 0:8918a71cdbe9 203 //Disable interrupts-on-change
Sergunb 0:8918a71cdbe9 204 PIOB->PIO_IDR = EMAC_RMII_MASK;
Sergunb 0:8918a71cdbe9 205 //Assign RMII pins to peripheral A function
Sergunb 0:8918a71cdbe9 206 PIOB->PIO_ABSR &= ~EMAC_RMII_MASK;
Sergunb 0:8918a71cdbe9 207 //Disable the PIO from controlling the corresponding pins
Sergunb 0:8918a71cdbe9 208 PIOB->PIO_PDR = EMAC_RMII_MASK;
Sergunb 0:8918a71cdbe9 209
Sergunb 0:8918a71cdbe9 210 //Select RMII operation mode and enable transceiver clock
Sergunb 0:8918a71cdbe9 211 EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
Sergunb 0:8918a71cdbe9 212 }
Sergunb 0:8918a71cdbe9 213
Sergunb 0:8918a71cdbe9 214 #endif
Sergunb 0:8918a71cdbe9 215
Sergunb 0:8918a71cdbe9 216
Sergunb 0:8918a71cdbe9 217 /**
Sergunb 0:8918a71cdbe9 218 * @brief Initialize buffer descriptors
Sergunb 0:8918a71cdbe9 219 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 220 **/
Sergunb 0:8918a71cdbe9 221
Sergunb 0:8918a71cdbe9 222 void sam3xEthInitBufferDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 223 {
Sergunb 0:8918a71cdbe9 224 uint_t i;
Sergunb 0:8918a71cdbe9 225 uint32_t address;
Sergunb 0:8918a71cdbe9 226
Sergunb 0:8918a71cdbe9 227 //Initialize TX buffer descriptors
Sergunb 0:8918a71cdbe9 228 for(i = 0; i < SAM3X_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 229 {
Sergunb 0:8918a71cdbe9 230 //Calculate the address of the current TX buffer
Sergunb 0:8918a71cdbe9 231 address = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 232 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 233 txBufferDesc[i].address = address;
Sergunb 0:8918a71cdbe9 234 //Initialize status field
Sergunb 0:8918a71cdbe9 235 txBufferDesc[i].status = EMAC_TX_USED;
Sergunb 0:8918a71cdbe9 236 }
Sergunb 0:8918a71cdbe9 237
Sergunb 0:8918a71cdbe9 238 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 239 txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
Sergunb 0:8918a71cdbe9 240 //Initialize TX buffer index
Sergunb 0:8918a71cdbe9 241 txBufferIndex = 0;
Sergunb 0:8918a71cdbe9 242
Sergunb 0:8918a71cdbe9 243 //Initialize RX buffer descriptors
Sergunb 0:8918a71cdbe9 244 for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 245 {
Sergunb 0:8918a71cdbe9 246 //Calculate the address of the current RX buffer
Sergunb 0:8918a71cdbe9 247 address = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 248 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 249 rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
Sergunb 0:8918a71cdbe9 250 //Clear status field
Sergunb 0:8918a71cdbe9 251 rxBufferDesc[i].status = 0;
Sergunb 0:8918a71cdbe9 252 }
Sergunb 0:8918a71cdbe9 253
Sergunb 0:8918a71cdbe9 254 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 255 rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
Sergunb 0:8918a71cdbe9 256 //Initialize RX buffer index
Sergunb 0:8918a71cdbe9 257 rxBufferIndex = 0;
Sergunb 0:8918a71cdbe9 258
Sergunb 0:8918a71cdbe9 259 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 260 EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
Sergunb 0:8918a71cdbe9 261 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 262 EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
Sergunb 0:8918a71cdbe9 263 }
Sergunb 0:8918a71cdbe9 264
Sergunb 0:8918a71cdbe9 265
Sergunb 0:8918a71cdbe9 266 /**
Sergunb 0:8918a71cdbe9 267 * @brief SAM3X Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 268 *
Sergunb 0:8918a71cdbe9 269 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 270 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 271 *
Sergunb 0:8918a71cdbe9 272 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 273 **/
Sergunb 0:8918a71cdbe9 274
Sergunb 0:8918a71cdbe9 275 void sam3xEthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 276 {
Sergunb 0:8918a71cdbe9 277 //Handle periodic operations
Sergunb 0:8918a71cdbe9 278 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 279 }
Sergunb 0:8918a71cdbe9 280
Sergunb 0:8918a71cdbe9 281
Sergunb 0:8918a71cdbe9 282 /**
Sergunb 0:8918a71cdbe9 283 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 284 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 285 **/
Sergunb 0:8918a71cdbe9 286
Sergunb 0:8918a71cdbe9 287 void sam3xEthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 288 {
Sergunb 0:8918a71cdbe9 289 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 290 NVIC_EnableIRQ(EMAC_IRQn);
Sergunb 0:8918a71cdbe9 291 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 292 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 293 }
Sergunb 0:8918a71cdbe9 294
Sergunb 0:8918a71cdbe9 295
Sergunb 0:8918a71cdbe9 296 /**
Sergunb 0:8918a71cdbe9 297 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 298 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 299 **/
Sergunb 0:8918a71cdbe9 300
Sergunb 0:8918a71cdbe9 301 void sam3xEthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 302 {
Sergunb 0:8918a71cdbe9 303 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 304 NVIC_DisableIRQ(EMAC_IRQn);
Sergunb 0:8918a71cdbe9 305 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 306 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 307 }
Sergunb 0:8918a71cdbe9 308
Sergunb 0:8918a71cdbe9 309
Sergunb 0:8918a71cdbe9 310 /**
Sergunb 0:8918a71cdbe9 311 * @brief SAM3X Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 312 **/
Sergunb 0:8918a71cdbe9 313
Sergunb 0:8918a71cdbe9 314 void EMAC_Handler(void)
Sergunb 0:8918a71cdbe9 315 {
Sergunb 0:8918a71cdbe9 316 bool_t flag;
Sergunb 0:8918a71cdbe9 317 volatile uint32_t isr;
Sergunb 0:8918a71cdbe9 318 volatile uint32_t tsr;
Sergunb 0:8918a71cdbe9 319 volatile uint32_t rsr;
Sergunb 0:8918a71cdbe9 320
Sergunb 0:8918a71cdbe9 321 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 322 osEnterIsr();
Sergunb 0:8918a71cdbe9 323
Sergunb 0:8918a71cdbe9 324 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 325 flag = FALSE;
Sergunb 0:8918a71cdbe9 326
Sergunb 0:8918a71cdbe9 327 //Each time the software reads EMAC_ISR, it has to check the
Sergunb 0:8918a71cdbe9 328 //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
Sergunb 0:8918a71cdbe9 329 isr = EMAC->EMAC_ISR;
Sergunb 0:8918a71cdbe9 330 tsr = EMAC->EMAC_TSR;
Sergunb 0:8918a71cdbe9 331 rsr = EMAC->EMAC_RSR;
Sergunb 0:8918a71cdbe9 332
Sergunb 0:8918a71cdbe9 333 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 334 if(tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
Sergunb 0:8918a71cdbe9 335 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR))
Sergunb 0:8918a71cdbe9 336 {
Sergunb 0:8918a71cdbe9 337 //Only clear TSR flags that are currently set
Sergunb 0:8918a71cdbe9 338 EMAC->EMAC_TSR = tsr;
Sergunb 0:8918a71cdbe9 339
Sergunb 0:8918a71cdbe9 340 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 341 if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
Sergunb 0:8918a71cdbe9 342 {
Sergunb 0:8918a71cdbe9 343 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 344 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 345 }
Sergunb 0:8918a71cdbe9 346 }
Sergunb 0:8918a71cdbe9 347
Sergunb 0:8918a71cdbe9 348 //A packet has been received?
Sergunb 0:8918a71cdbe9 349 if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
Sergunb 0:8918a71cdbe9 350 {
Sergunb 0:8918a71cdbe9 351 //Set event flag
Sergunb 0:8918a71cdbe9 352 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 353 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 354 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 355 }
Sergunb 0:8918a71cdbe9 356
Sergunb 0:8918a71cdbe9 357 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 358 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 359 }
Sergunb 0:8918a71cdbe9 360
Sergunb 0:8918a71cdbe9 361
Sergunb 0:8918a71cdbe9 362 /**
Sergunb 0:8918a71cdbe9 363 * @brief SAM3X Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 364 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 365 **/
Sergunb 0:8918a71cdbe9 366
Sergunb 0:8918a71cdbe9 367 void sam3xEthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 368 {
Sergunb 0:8918a71cdbe9 369 error_t error;
Sergunb 0:8918a71cdbe9 370 uint32_t rsr;
Sergunb 0:8918a71cdbe9 371
Sergunb 0:8918a71cdbe9 372 //Read receive status
Sergunb 0:8918a71cdbe9 373 rsr = EMAC->EMAC_RSR;
Sergunb 0:8918a71cdbe9 374
Sergunb 0:8918a71cdbe9 375 //Packet received?
Sergunb 0:8918a71cdbe9 376 if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
Sergunb 0:8918a71cdbe9 377 {
Sergunb 0:8918a71cdbe9 378 //Only clear RSR flags that are currently set
Sergunb 0:8918a71cdbe9 379 EMAC->EMAC_RSR = rsr;
Sergunb 0:8918a71cdbe9 380
Sergunb 0:8918a71cdbe9 381 //Process all pending packets
Sergunb 0:8918a71cdbe9 382 do
Sergunb 0:8918a71cdbe9 383 {
Sergunb 0:8918a71cdbe9 384 //Read incoming packet
Sergunb 0:8918a71cdbe9 385 error = sam3xEthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 386
Sergunb 0:8918a71cdbe9 387 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 388 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 389 }
Sergunb 0:8918a71cdbe9 390 }
Sergunb 0:8918a71cdbe9 391
Sergunb 0:8918a71cdbe9 392
Sergunb 0:8918a71cdbe9 393 /**
Sergunb 0:8918a71cdbe9 394 * @brief Send a packet
Sergunb 0:8918a71cdbe9 395 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 396 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 397 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 398 * @return Error code
Sergunb 0:8918a71cdbe9 399 **/
Sergunb 0:8918a71cdbe9 400
Sergunb 0:8918a71cdbe9 401 error_t sam3xEthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 402 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 403 {
Sergunb 0:8918a71cdbe9 404 size_t length;
Sergunb 0:8918a71cdbe9 405
Sergunb 0:8918a71cdbe9 406 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 407 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 408
Sergunb 0:8918a71cdbe9 409 //Check the frame length
Sergunb 0:8918a71cdbe9 410 if(length > SAM3X_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 411 {
Sergunb 0:8918a71cdbe9 412 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 413 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 414 //Report an error
Sergunb 0:8918a71cdbe9 415 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 416 }
Sergunb 0:8918a71cdbe9 417
Sergunb 0:8918a71cdbe9 418 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 419 if(!(txBufferDesc[txBufferIndex].status & EMAC_TX_USED))
Sergunb 0:8918a71cdbe9 420 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 421
Sergunb 0:8918a71cdbe9 422 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 423 netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
Sergunb 0:8918a71cdbe9 424
Sergunb 0:8918a71cdbe9 425 //Set the necessary flags in the descriptor entry
Sergunb 0:8918a71cdbe9 426 if(txBufferIndex < (SAM3X_ETH_TX_BUFFER_COUNT - 1))
Sergunb 0:8918a71cdbe9 427 {
Sergunb 0:8918a71cdbe9 428 //Write the status word
Sergunb 0:8918a71cdbe9 429 txBufferDesc[txBufferIndex].status =
Sergunb 0:8918a71cdbe9 430 EMAC_TX_LAST | (length & EMAC_TX_LENGTH);
Sergunb 0:8918a71cdbe9 431
Sergunb 0:8918a71cdbe9 432 //Point to the next buffer
Sergunb 0:8918a71cdbe9 433 txBufferIndex++;
Sergunb 0:8918a71cdbe9 434 }
Sergunb 0:8918a71cdbe9 435 else
Sergunb 0:8918a71cdbe9 436 {
Sergunb 0:8918a71cdbe9 437 //Write the status word
Sergunb 0:8918a71cdbe9 438 txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP |
Sergunb 0:8918a71cdbe9 439 EMAC_TX_LAST | (length & EMAC_TX_LENGTH);
Sergunb 0:8918a71cdbe9 440
Sergunb 0:8918a71cdbe9 441 //Wrap around
Sergunb 0:8918a71cdbe9 442 txBufferIndex = 0;
Sergunb 0:8918a71cdbe9 443 }
Sergunb 0:8918a71cdbe9 444
Sergunb 0:8918a71cdbe9 445 //Set the TSTART bit to initiate transmission
Sergunb 0:8918a71cdbe9 446 EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
Sergunb 0:8918a71cdbe9 447
Sergunb 0:8918a71cdbe9 448 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 449 if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
Sergunb 0:8918a71cdbe9 450 {
Sergunb 0:8918a71cdbe9 451 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 452 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 453 }
Sergunb 0:8918a71cdbe9 454
Sergunb 0:8918a71cdbe9 455 //Successful processing
Sergunb 0:8918a71cdbe9 456 return NO_ERROR;
Sergunb 0:8918a71cdbe9 457 }
Sergunb 0:8918a71cdbe9 458
Sergunb 0:8918a71cdbe9 459
Sergunb 0:8918a71cdbe9 460 /**
Sergunb 0:8918a71cdbe9 461 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 462 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 463 * @return Error code
Sergunb 0:8918a71cdbe9 464 **/
Sergunb 0:8918a71cdbe9 465
Sergunb 0:8918a71cdbe9 466 error_t sam3xEthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 467 {
Sergunb 0:8918a71cdbe9 468 static uint8_t temp[ETH_MAX_FRAME_SIZE];
Sergunb 0:8918a71cdbe9 469 error_t error;
Sergunb 0:8918a71cdbe9 470 uint_t i;
Sergunb 0:8918a71cdbe9 471 uint_t j;
Sergunb 0:8918a71cdbe9 472 uint_t sofIndex;
Sergunb 0:8918a71cdbe9 473 uint_t eofIndex;
Sergunb 0:8918a71cdbe9 474 size_t n;
Sergunb 0:8918a71cdbe9 475 size_t size;
Sergunb 0:8918a71cdbe9 476 size_t length;
Sergunb 0:8918a71cdbe9 477
Sergunb 0:8918a71cdbe9 478 //Initialize SOF and EOF indices
Sergunb 0:8918a71cdbe9 479 sofIndex = UINT_MAX;
Sergunb 0:8918a71cdbe9 480 eofIndex = UINT_MAX;
Sergunb 0:8918a71cdbe9 481
Sergunb 0:8918a71cdbe9 482 //Search for SOF and EOF flags
Sergunb 0:8918a71cdbe9 483 for(i = 0; i < SAM3X_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 484 {
Sergunb 0:8918a71cdbe9 485 //Point to the current entry
Sergunb 0:8918a71cdbe9 486 j = rxBufferIndex + i;
Sergunb 0:8918a71cdbe9 487
Sergunb 0:8918a71cdbe9 488 //Wrap around to the beginning of the buffer if necessary
Sergunb 0:8918a71cdbe9 489 if(j >= SAM3X_ETH_RX_BUFFER_COUNT)
Sergunb 0:8918a71cdbe9 490 j -= SAM3X_ETH_RX_BUFFER_COUNT;
Sergunb 0:8918a71cdbe9 491
Sergunb 0:8918a71cdbe9 492 //No more entries to process?
Sergunb 0:8918a71cdbe9 493 if(!(rxBufferDesc[j].address & EMAC_RX_OWNERSHIP))
Sergunb 0:8918a71cdbe9 494 {
Sergunb 0:8918a71cdbe9 495 //Stop processing
Sergunb 0:8918a71cdbe9 496 break;
Sergunb 0:8918a71cdbe9 497 }
Sergunb 0:8918a71cdbe9 498 //A valid SOF has been found?
Sergunb 0:8918a71cdbe9 499 if(rxBufferDesc[j].status & EMAC_RX_SOF)
Sergunb 0:8918a71cdbe9 500 {
Sergunb 0:8918a71cdbe9 501 //Save the position of the SOF
Sergunb 0:8918a71cdbe9 502 sofIndex = i;
Sergunb 0:8918a71cdbe9 503 }
Sergunb 0:8918a71cdbe9 504 //A valid EOF has been found?
Sergunb 0:8918a71cdbe9 505 if((rxBufferDesc[j].status & EMAC_RX_EOF) && sofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 506 {
Sergunb 0:8918a71cdbe9 507 //Save the position of the EOF
Sergunb 0:8918a71cdbe9 508 eofIndex = i;
Sergunb 0:8918a71cdbe9 509 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 510 size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
Sergunb 0:8918a71cdbe9 511 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 512 size = MIN(size, ETH_MAX_FRAME_SIZE);
Sergunb 0:8918a71cdbe9 513 //Stop processing since we have reached the end of the frame
Sergunb 0:8918a71cdbe9 514 break;
Sergunb 0:8918a71cdbe9 515 }
Sergunb 0:8918a71cdbe9 516 }
Sergunb 0:8918a71cdbe9 517
Sergunb 0:8918a71cdbe9 518 //Determine the number of entries to process
Sergunb 0:8918a71cdbe9 519 if(eofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 520 j = eofIndex + 1;
Sergunb 0:8918a71cdbe9 521 else if(sofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 522 j = sofIndex;
Sergunb 0:8918a71cdbe9 523 else
Sergunb 0:8918a71cdbe9 524 j = i;
Sergunb 0:8918a71cdbe9 525
Sergunb 0:8918a71cdbe9 526 //Total number of bytes that have been copied from the receive buffer
Sergunb 0:8918a71cdbe9 527 length = 0;
Sergunb 0:8918a71cdbe9 528
Sergunb 0:8918a71cdbe9 529 //Process incoming frame
Sergunb 0:8918a71cdbe9 530 for(i = 0; i < j; i++)
Sergunb 0:8918a71cdbe9 531 {
Sergunb 0:8918a71cdbe9 532 //Any data to copy from current buffer?
Sergunb 0:8918a71cdbe9 533 if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
Sergunb 0:8918a71cdbe9 534 {
Sergunb 0:8918a71cdbe9 535 //Calculate the number of bytes to read at a time
Sergunb 0:8918a71cdbe9 536 n = MIN(size, SAM3X_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 537 //Copy data from receive buffer
Sergunb 0:8918a71cdbe9 538 memcpy(temp + length, rxBuffer[rxBufferIndex], n);
Sergunb 0:8918a71cdbe9 539 //Update byte counters
Sergunb 0:8918a71cdbe9 540 length += n;
Sergunb 0:8918a71cdbe9 541 size -= n;
Sergunb 0:8918a71cdbe9 542 }
Sergunb 0:8918a71cdbe9 543
Sergunb 0:8918a71cdbe9 544 //Mark the current buffer as free
Sergunb 0:8918a71cdbe9 545 rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
Sergunb 0:8918a71cdbe9 546
Sergunb 0:8918a71cdbe9 547 //Point to the following entry
Sergunb 0:8918a71cdbe9 548 rxBufferIndex++;
Sergunb 0:8918a71cdbe9 549
Sergunb 0:8918a71cdbe9 550 //Wrap around to the beginning of the buffer if necessary
Sergunb 0:8918a71cdbe9 551 if(rxBufferIndex >= SAM3X_ETH_RX_BUFFER_COUNT)
Sergunb 0:8918a71cdbe9 552 rxBufferIndex = 0;
Sergunb 0:8918a71cdbe9 553 }
Sergunb 0:8918a71cdbe9 554
Sergunb 0:8918a71cdbe9 555 //Any packet to process?
Sergunb 0:8918a71cdbe9 556 if(length > 0)
Sergunb 0:8918a71cdbe9 557 {
Sergunb 0:8918a71cdbe9 558 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 559 nicProcessPacket(interface, temp, length);
Sergunb 0:8918a71cdbe9 560 //Valid packet received
Sergunb 0:8918a71cdbe9 561 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 562 }
Sergunb 0:8918a71cdbe9 563 else
Sergunb 0:8918a71cdbe9 564 {
Sergunb 0:8918a71cdbe9 565 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 566 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 567 }
Sergunb 0:8918a71cdbe9 568
Sergunb 0:8918a71cdbe9 569 //Return status code
Sergunb 0:8918a71cdbe9 570 return error;
Sergunb 0:8918a71cdbe9 571 }
Sergunb 0:8918a71cdbe9 572
Sergunb 0:8918a71cdbe9 573
Sergunb 0:8918a71cdbe9 574 /**
Sergunb 0:8918a71cdbe9 575 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 576 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 577 * @return Error code
Sergunb 0:8918a71cdbe9 578 **/
Sergunb 0:8918a71cdbe9 579
Sergunb 0:8918a71cdbe9 580 error_t sam3xEthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 581 {
Sergunb 0:8918a71cdbe9 582 uint_t i;
Sergunb 0:8918a71cdbe9 583 uint_t k;
Sergunb 0:8918a71cdbe9 584 uint8_t *p;
Sergunb 0:8918a71cdbe9 585 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 586 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 587
Sergunb 0:8918a71cdbe9 588 //Debug message
Sergunb 0:8918a71cdbe9 589 TRACE_DEBUG("Updating SAM3X hash table...\r\n");
Sergunb 0:8918a71cdbe9 590
Sergunb 0:8918a71cdbe9 591 //Clear hash table
Sergunb 0:8918a71cdbe9 592 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 593 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 594
Sergunb 0:8918a71cdbe9 595 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 596 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 597 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 598 {
Sergunb 0:8918a71cdbe9 599 //Point to the current entry
Sergunb 0:8918a71cdbe9 600 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 601
Sergunb 0:8918a71cdbe9 602 //Valid entry?
Sergunb 0:8918a71cdbe9 603 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 604 {
Sergunb 0:8918a71cdbe9 605 //Point to the MAC address
Sergunb 0:8918a71cdbe9 606 p = entry->addr.b;
Sergunb 0:8918a71cdbe9 607
Sergunb 0:8918a71cdbe9 608 //Apply the hash function
Sergunb 0:8918a71cdbe9 609 k = (p[0] >> 6) ^ p[0];
Sergunb 0:8918a71cdbe9 610 k ^= (p[1] >> 4) ^ (p[1] << 2);
Sergunb 0:8918a71cdbe9 611 k ^= (p[2] >> 2) ^ (p[2] << 4);
Sergunb 0:8918a71cdbe9 612 k ^= (p[3] >> 6) ^ p[3];
Sergunb 0:8918a71cdbe9 613 k ^= (p[4] >> 4) ^ (p[4] << 2);
Sergunb 0:8918a71cdbe9 614 k ^= (p[5] >> 2) ^ (p[5] << 4);
Sergunb 0:8918a71cdbe9 615
Sergunb 0:8918a71cdbe9 616 //The hash value is reduced to a 6-bit index
Sergunb 0:8918a71cdbe9 617 k &= 0x3F;
Sergunb 0:8918a71cdbe9 618
Sergunb 0:8918a71cdbe9 619 //Update hash table contents
Sergunb 0:8918a71cdbe9 620 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 621 }
Sergunb 0:8918a71cdbe9 622 }
Sergunb 0:8918a71cdbe9 623
Sergunb 0:8918a71cdbe9 624 //Write the hash table
Sergunb 0:8918a71cdbe9 625 EMAC->EMAC_HRB = hashTable[0];
Sergunb 0:8918a71cdbe9 626 EMAC->EMAC_HRT = hashTable[1];
Sergunb 0:8918a71cdbe9 627
Sergunb 0:8918a71cdbe9 628 //Debug message
Sergunb 0:8918a71cdbe9 629 TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
Sergunb 0:8918a71cdbe9 630 TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
Sergunb 0:8918a71cdbe9 631
Sergunb 0:8918a71cdbe9 632 //Successful processing
Sergunb 0:8918a71cdbe9 633 return NO_ERROR;
Sergunb 0:8918a71cdbe9 634 }
Sergunb 0:8918a71cdbe9 635
Sergunb 0:8918a71cdbe9 636
Sergunb 0:8918a71cdbe9 637 /**
Sergunb 0:8918a71cdbe9 638 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 639 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 640 * @return Error code
Sergunb 0:8918a71cdbe9 641 **/
Sergunb 0:8918a71cdbe9 642
Sergunb 0:8918a71cdbe9 643 error_t sam3xEthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 644 {
Sergunb 0:8918a71cdbe9 645 uint32_t config;
Sergunb 0:8918a71cdbe9 646
Sergunb 0:8918a71cdbe9 647 //Read network configuration register
Sergunb 0:8918a71cdbe9 648 config = EMAC->EMAC_NCFGR;
Sergunb 0:8918a71cdbe9 649
Sergunb 0:8918a71cdbe9 650 //10BASE-T or 100BASE-TX operation mode?
Sergunb 0:8918a71cdbe9 651 if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
Sergunb 0:8918a71cdbe9 652 config |= EMAC_NCFGR_SPD;
Sergunb 0:8918a71cdbe9 653 else
Sergunb 0:8918a71cdbe9 654 config &= ~EMAC_NCFGR_SPD;
Sergunb 0:8918a71cdbe9 655
Sergunb 0:8918a71cdbe9 656 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 657 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 658 config |= EMAC_NCFGR_FD;
Sergunb 0:8918a71cdbe9 659 else
Sergunb 0:8918a71cdbe9 660 config &= ~EMAC_NCFGR_FD;
Sergunb 0:8918a71cdbe9 661
Sergunb 0:8918a71cdbe9 662 //Write configuration value back to NCFGR register
Sergunb 0:8918a71cdbe9 663 EMAC->EMAC_NCFGR = config;
Sergunb 0:8918a71cdbe9 664
Sergunb 0:8918a71cdbe9 665 //Successful processing
Sergunb 0:8918a71cdbe9 666 return NO_ERROR;
Sergunb 0:8918a71cdbe9 667 }
Sergunb 0:8918a71cdbe9 668
Sergunb 0:8918a71cdbe9 669
Sergunb 0:8918a71cdbe9 670 /**
Sergunb 0:8918a71cdbe9 671 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 672 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 673 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 674 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 675 **/
Sergunb 0:8918a71cdbe9 676
Sergunb 0:8918a71cdbe9 677 void sam3xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 678 {
Sergunb 0:8918a71cdbe9 679 uint32_t value;
Sergunb 0:8918a71cdbe9 680
Sergunb 0:8918a71cdbe9 681 //Set up a write operation
Sergunb 0:8918a71cdbe9 682 value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
Sergunb 0:8918a71cdbe9 683 //PHY address
Sergunb 0:8918a71cdbe9 684 value |= EMAC_MAN_PHYA(phyAddr);
Sergunb 0:8918a71cdbe9 685 //Register address
Sergunb 0:8918a71cdbe9 686 value |= EMAC_MAN_REGA(regAddr);
Sergunb 0:8918a71cdbe9 687 //Register value
Sergunb 0:8918a71cdbe9 688 value |= EMAC_MAN_DATA(data);
Sergunb 0:8918a71cdbe9 689
Sergunb 0:8918a71cdbe9 690 //Start a write operation
Sergunb 0:8918a71cdbe9 691 EMAC->EMAC_MAN = value;
Sergunb 0:8918a71cdbe9 692 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 693 while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
Sergunb 0:8918a71cdbe9 694 }
Sergunb 0:8918a71cdbe9 695
Sergunb 0:8918a71cdbe9 696
Sergunb 0:8918a71cdbe9 697 /**
Sergunb 0:8918a71cdbe9 698 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 699 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 700 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 701 * @return Register value
Sergunb 0:8918a71cdbe9 702 **/
Sergunb 0:8918a71cdbe9 703
Sergunb 0:8918a71cdbe9 704 uint16_t sam3xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 705 {
Sergunb 0:8918a71cdbe9 706 uint32_t value;
Sergunb 0:8918a71cdbe9 707
Sergunb 0:8918a71cdbe9 708 //Set up a read operation
Sergunb 0:8918a71cdbe9 709 value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
Sergunb 0:8918a71cdbe9 710 //PHY address
Sergunb 0:8918a71cdbe9 711 value |= EMAC_MAN_PHYA(phyAddr);
Sergunb 0:8918a71cdbe9 712 //Register address
Sergunb 0:8918a71cdbe9 713 value |= EMAC_MAN_REGA(regAddr);
Sergunb 0:8918a71cdbe9 714
Sergunb 0:8918a71cdbe9 715 //Start a read operation
Sergunb 0:8918a71cdbe9 716 EMAC->EMAC_MAN = value;
Sergunb 0:8918a71cdbe9 717 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 718 while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
Sergunb 0:8918a71cdbe9 719
Sergunb 0:8918a71cdbe9 720 //Return PHY register contents
Sergunb 0:8918a71cdbe9 721 return EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
Sergunb 0:8918a71cdbe9 722 }
Sergunb 0:8918a71cdbe9 723