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cyclone_tcp/drivers/aps3_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file aps3_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief Cortus APS3 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include <machine/sfradr.h>
Sergunb 0:8918a71cdbe9 34 #include <machine/sfradr_eth.h>
Sergunb 0:8918a71cdbe9 35 #include <machine/ethernet.h>
Sergunb 0:8918a71cdbe9 36 #include <machine/ic.h>
Sergunb 0:8918a71cdbe9 37 #undef _ETHERNET_H
Sergunb 0:8918a71cdbe9 38 #include "core/net.h"
Sergunb 0:8918a71cdbe9 39 #include "drivers/aps3_eth.h"
Sergunb 0:8918a71cdbe9 40 #include "debug.h"
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //Transmit buffer
Sergunb 0:8918a71cdbe9 43 #define txBuffer ((uint8_t *) SFRADR_ETH_TX_MEM_BOTTOM_AD)
Sergunb 0:8918a71cdbe9 44 //Receive buffer
Sergunb 0:8918a71cdbe9 45 #define rxBuffer ((uint8_t *) SFRADR_ETH_RX_MEM_BOTTOM_AD)
Sergunb 0:8918a71cdbe9 46
Sergunb 0:8918a71cdbe9 47 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 48 #define txDmaDesc ((Aps3TxDmaDesc *) (SFRADR_ETH_TX_MEM_BOTTOM_AD + \
Sergunb 0:8918a71cdbe9 49 APS3_ETH_TX_BUFFER_COUNT * APS3_ETH_TX_BUFFER_SIZE))
Sergunb 0:8918a71cdbe9 50
Sergunb 0:8918a71cdbe9 51 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 52 #define rxDmaDesc ((Aps3RxDmaDesc *) (SFRADR_ETH_RX_MEM_BOTTOM_AD + \
Sergunb 0:8918a71cdbe9 53 APS3_ETH_RX_BUFFER_COUNT * APS3_ETH_RX_BUFFER_SIZE))
Sergunb 0:8918a71cdbe9 54
Sergunb 0:8918a71cdbe9 55 //Underlying network interface
Sergunb 0:8918a71cdbe9 56 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 57
Sergunb 0:8918a71cdbe9 58
Sergunb 0:8918a71cdbe9 59 /**
Sergunb 0:8918a71cdbe9 60 * @brief Cortus APS3 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 61 **/
Sergunb 0:8918a71cdbe9 62
Sergunb 0:8918a71cdbe9 63 const NicDriver aps3EthDriver =
Sergunb 0:8918a71cdbe9 64 {
Sergunb 0:8918a71cdbe9 65 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 66 ETH_MTU,
Sergunb 0:8918a71cdbe9 67 aps3EthInit,
Sergunb 0:8918a71cdbe9 68 aps3EthTick,
Sergunb 0:8918a71cdbe9 69 aps3EthEnableIrq,
Sergunb 0:8918a71cdbe9 70 aps3EthDisableIrq,
Sergunb 0:8918a71cdbe9 71 aps3EthEventHandler,
Sergunb 0:8918a71cdbe9 72 aps3EthSendPacket,
Sergunb 0:8918a71cdbe9 73 aps3EthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 74 aps3EthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 75 aps3EthWritePhyReg,
Sergunb 0:8918a71cdbe9 76 aps3EthReadPhyReg,
Sergunb 0:8918a71cdbe9 77 TRUE,
Sergunb 0:8918a71cdbe9 78 TRUE,
Sergunb 0:8918a71cdbe9 79 TRUE,
Sergunb 0:8918a71cdbe9 80 FALSE
Sergunb 0:8918a71cdbe9 81 };
Sergunb 0:8918a71cdbe9 82
Sergunb 0:8918a71cdbe9 83
Sergunb 0:8918a71cdbe9 84 /**
Sergunb 0:8918a71cdbe9 85 * @brief Cortus APS3 Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 86 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 87 * @return Error code
Sergunb 0:8918a71cdbe9 88 **/
Sergunb 0:8918a71cdbe9 89
Sergunb 0:8918a71cdbe9 90 error_t aps3EthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 91 {
Sergunb 0:8918a71cdbe9 92 error_t error;
Sergunb 0:8918a71cdbe9 93
Sergunb 0:8918a71cdbe9 94 //Debug message
Sergunb 0:8918a71cdbe9 95 TRACE_INFO("Initializing Cortus APS3 Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 96
Sergunb 0:8918a71cdbe9 97 //Save underlying network interface
Sergunb 0:8918a71cdbe9 98 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 99
Sergunb 0:8918a71cdbe9 100 //Adjust MDC clock range
Sergunb 0:8918a71cdbe9 101 eth_miim->miim_clock_divider = 32;
Sergunb 0:8918a71cdbe9 102
Sergunb 0:8918a71cdbe9 103 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 104 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 105 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 106 if(error)
Sergunb 0:8918a71cdbe9 107 return error;
Sergunb 0:8918a71cdbe9 108
Sergunb 0:8918a71cdbe9 109 //Reset Ethernet MAC peripheral
Sergunb 0:8918a71cdbe9 110 eth_mac->sw_reset = 1;
Sergunb 0:8918a71cdbe9 111
Sergunb 0:8918a71cdbe9 112 //Set the MAC address
Sergunb 0:8918a71cdbe9 113 eth_mac->addr_low = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 114 eth_mac->addr_high = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 115
Sergunb 0:8918a71cdbe9 116 //Initialize hash table
Sergunb 0:8918a71cdbe9 117 eth_mac->hash_filter_low = 0;
Sergunb 0:8918a71cdbe9 118 eth_mac->hash_filter_high = 0;
Sergunb 0:8918a71cdbe9 119
Sergunb 0:8918a71cdbe9 120 //Configure the receive filter
Sergunb 0:8918a71cdbe9 121 eth_mac->unicast = 1;
Sergunb 0:8918a71cdbe9 122 eth_mac->multicast = 0;
Sergunb 0:8918a71cdbe9 123 eth_mac->broadcast = 1;
Sergunb 0:8918a71cdbe9 124 eth_mac->hash = 1;
Sergunb 0:8918a71cdbe9 125 eth_mac->exact_addr = 1;
Sergunb 0:8918a71cdbe9 126
Sergunb 0:8918a71cdbe9 127 //Default duplex mode
Sergunb 0:8918a71cdbe9 128 eth_mac->full_duplex = 0;
Sergunb 0:8918a71cdbe9 129
Sergunb 0:8918a71cdbe9 130 //Automatic padding and CRC generation
Sergunb 0:8918a71cdbe9 131 eth_mac->no_padding = 0;
Sergunb 0:8918a71cdbe9 132 eth_mac->crc_disable = 0;
Sergunb 0:8918a71cdbe9 133
Sergunb 0:8918a71cdbe9 134 //Set the maximum frame length
Sergunb 0:8918a71cdbe9 135 eth_mac->max_frame_size = 1518;
Sergunb 0:8918a71cdbe9 136
Sergunb 0:8918a71cdbe9 137 //Set transmit and receive thresholds
Sergunb 0:8918a71cdbe9 138 eth_tx->tx_threshold = 0;
Sergunb 0:8918a71cdbe9 139 eth_rx->rx_threshold = 0;
Sergunb 0:8918a71cdbe9 140
Sergunb 0:8918a71cdbe9 141 //Disable indefinite deferral
Sergunb 0:8918a71cdbe9 142 eth_mac->indefinite_deferral = 0;
Sergunb 0:8918a71cdbe9 143 //Number of attempts to transmit a frame before aborting
Sergunb 0:8918a71cdbe9 144 eth_mac->max_deferral = 15;
Sergunb 0:8918a71cdbe9 145
Sergunb 0:8918a71cdbe9 146 //Use default collision window (112 half-octets)
Sergunb 0:8918a71cdbe9 147 eth_mac->collision_window = 111;
Sergunb 0:8918a71cdbe9 148 //Maximum Number of Collisions
Sergunb 0:8918a71cdbe9 149 eth_mac->max_collision = 15;
Sergunb 0:8918a71cdbe9 150
Sergunb 0:8918a71cdbe9 151 //Automatic backoff on collision
Sergunb 0:8918a71cdbe9 152 eth_mac->no_backoff = 0;
Sergunb 0:8918a71cdbe9 153
Sergunb 0:8918a71cdbe9 154 //Use the default interframe gap (24 half-octets or 96 bits)
Sergunb 0:8918a71cdbe9 155 eth_mac->interframe_gap = 23;
Sergunb 0:8918a71cdbe9 156
Sergunb 0:8918a71cdbe9 157 //Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 158 aps3EthInitDmaDesc(interface);
Sergunb 0:8918a71cdbe9 159
Sergunb 0:8918a71cdbe9 160 //Configure TX interrupts
Sergunb 0:8918a71cdbe9 161 eth_tx->tx_irq_mask = TX_IRQ_MASK_MEMORY_AVAILABLE;
Sergunb 0:8918a71cdbe9 162 //Configure RX interrupts
Sergunb 0:8918a71cdbe9 163 eth_rx->rx_irq_mask = RX_IRQ_MASK_FRAME_READY;
Sergunb 0:8918a71cdbe9 164
Sergunb 0:8918a71cdbe9 165 //Configure TX interrupt priority
Sergunb 0:8918a71cdbe9 166 irq[IRQ_ETH_TX].ipl = APS3_ETH_IRQ_PRIORITY;
Sergunb 0:8918a71cdbe9 167 //Configure RX interrupt priority
Sergunb 0:8918a71cdbe9 168 irq[IRQ_ETH_RX].ipl = APS3_ETH_IRQ_PRIORITY;
Sergunb 0:8918a71cdbe9 169
Sergunb 0:8918a71cdbe9 170 //Enable transmission and reception
Sergunb 0:8918a71cdbe9 171 eth_tx->tx_enable = 1;
Sergunb 0:8918a71cdbe9 172 eth_rx->rx_enable = 1;
Sergunb 0:8918a71cdbe9 173
Sergunb 0:8918a71cdbe9 174 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 175 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 176
Sergunb 0:8918a71cdbe9 177 //Successful initialization
Sergunb 0:8918a71cdbe9 178 return NO_ERROR;
Sergunb 0:8918a71cdbe9 179 }
Sergunb 0:8918a71cdbe9 180
Sergunb 0:8918a71cdbe9 181
Sergunb 0:8918a71cdbe9 182 /**
Sergunb 0:8918a71cdbe9 183 * @brief Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 184 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 185 **/
Sergunb 0:8918a71cdbe9 186
Sergunb 0:8918a71cdbe9 187 void aps3EthInitDmaDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 188 {
Sergunb 0:8918a71cdbe9 189 uint_t i;
Sergunb 0:8918a71cdbe9 190
Sergunb 0:8918a71cdbe9 191 //Initialize TX DMA descriptor list
Sergunb 0:8918a71cdbe9 192 for(i = 0; i < APS3_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 193 {
Sergunb 0:8918a71cdbe9 194 //Transmit buffer address
Sergunb 0:8918a71cdbe9 195 txDmaDesc[i].addr = (uint32_t) txBuffer + (APS3_ETH_TX_BUFFER_SIZE * i);
Sergunb 0:8918a71cdbe9 196 //Transmit buffer size
Sergunb 0:8918a71cdbe9 197 txDmaDesc[i].size = 0;
Sergunb 0:8918a71cdbe9 198 //Transmit status
Sergunb 0:8918a71cdbe9 199 txDmaDesc[i].status = 0;
Sergunb 0:8918a71cdbe9 200 }
Sergunb 0:8918a71cdbe9 201
Sergunb 0:8918a71cdbe9 202 //Initialize RX DMA descriptor list
Sergunb 0:8918a71cdbe9 203 for(i = 0; i < APS3_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 204 {
Sergunb 0:8918a71cdbe9 205 //Receive buffer address
Sergunb 0:8918a71cdbe9 206 rxDmaDesc[i].addr = (uint32_t) rxBuffer + (APS3_ETH_RX_BUFFER_SIZE * i);
Sergunb 0:8918a71cdbe9 207 //Receive buffer size
Sergunb 0:8918a71cdbe9 208 rxDmaDesc[i].size = 0;
Sergunb 0:8918a71cdbe9 209 //Receive status
Sergunb 0:8918a71cdbe9 210 rxDmaDesc[i].status = 0;
Sergunb 0:8918a71cdbe9 211 }
Sergunb 0:8918a71cdbe9 212
Sergunb 0:8918a71cdbe9 213 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 214 eth_tx->tx_desc_base_addr = (uint32_t) txDmaDesc;
Sergunb 0:8918a71cdbe9 215 //Number of TX descriptors
Sergunb 0:8918a71cdbe9 216 eth_tx->tx_desc_number = APS3_ETH_TX_BUFFER_COUNT - 1;
Sergunb 0:8918a71cdbe9 217
Sergunb 0:8918a71cdbe9 218 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 219 eth_rx->rx_desc_base_addr = (uint32_t) rxDmaDesc;
Sergunb 0:8918a71cdbe9 220 //Number of RX descriptors
Sergunb 0:8918a71cdbe9 221 eth_rx->rx_desc_number = APS3_ETH_RX_BUFFER_COUNT - 1;
Sergunb 0:8918a71cdbe9 222 }
Sergunb 0:8918a71cdbe9 223
Sergunb 0:8918a71cdbe9 224
Sergunb 0:8918a71cdbe9 225 /**
Sergunb 0:8918a71cdbe9 226 * @brief Cortus APS3 Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 227 *
Sergunb 0:8918a71cdbe9 228 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 229 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 230 *
Sergunb 0:8918a71cdbe9 231 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 232 **/
Sergunb 0:8918a71cdbe9 233
Sergunb 0:8918a71cdbe9 234 void aps3EthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 235 {
Sergunb 0:8918a71cdbe9 236 //Handle periodic operations
Sergunb 0:8918a71cdbe9 237 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 238 }
Sergunb 0:8918a71cdbe9 239
Sergunb 0:8918a71cdbe9 240
Sergunb 0:8918a71cdbe9 241 /**
Sergunb 0:8918a71cdbe9 242 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 243 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 244 **/
Sergunb 0:8918a71cdbe9 245
Sergunb 0:8918a71cdbe9 246 void aps3EthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 247 {
Sergunb 0:8918a71cdbe9 248 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 249 irq[IRQ_ETH_TX].ien = 1;
Sergunb 0:8918a71cdbe9 250 irq[IRQ_ETH_RX].ien = 1;
Sergunb 0:8918a71cdbe9 251 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 252 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 253 }
Sergunb 0:8918a71cdbe9 254
Sergunb 0:8918a71cdbe9 255
Sergunb 0:8918a71cdbe9 256 /**
Sergunb 0:8918a71cdbe9 257 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 258 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 259 **/
Sergunb 0:8918a71cdbe9 260
Sergunb 0:8918a71cdbe9 261 void aps3EthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 262 {
Sergunb 0:8918a71cdbe9 263 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 264 irq[IRQ_ETH_TX].ien = 0;
Sergunb 0:8918a71cdbe9 265 irq[IRQ_ETH_RX].ien = 0;
Sergunb 0:8918a71cdbe9 266 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 267 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 268 }
Sergunb 0:8918a71cdbe9 269
Sergunb 0:8918a71cdbe9 270
Sergunb 0:8918a71cdbe9 271 /**
Sergunb 0:8918a71cdbe9 272 * @brief Ethernet MAC transmit interrupt service routine
Sergunb 0:8918a71cdbe9 273 **/
Sergunb 0:8918a71cdbe9 274
Sergunb 0:8918a71cdbe9 275 void aps3EthTxIrqHandler(void)
Sergunb 0:8918a71cdbe9 276 {
Sergunb 0:8918a71cdbe9 277 bool_t flag;
Sergunb 0:8918a71cdbe9 278
Sergunb 0:8918a71cdbe9 279 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 280 osEnterIsr();
Sergunb 0:8918a71cdbe9 281
Sergunb 0:8918a71cdbe9 282 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 283 flag = FALSE;
Sergunb 0:8918a71cdbe9 284
Sergunb 0:8918a71cdbe9 285 //Check interrupt flag
Sergunb 0:8918a71cdbe9 286 if(eth_tx->tx_status & TX_IRQ_MASK_MEMORY_AVAILABLE)
Sergunb 0:8918a71cdbe9 287 {
Sergunb 0:8918a71cdbe9 288 //Disable TX interrupts
Sergunb 0:8918a71cdbe9 289 eth_tx->tx_irq_mask = 0;
Sergunb 0:8918a71cdbe9 290
Sergunb 0:8918a71cdbe9 291 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 292 if(!(eth_tx->tx_desc_status))
Sergunb 0:8918a71cdbe9 293 {
Sergunb 0:8918a71cdbe9 294 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 295 flag = osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 296 }
Sergunb 0:8918a71cdbe9 297 }
Sergunb 0:8918a71cdbe9 298
Sergunb 0:8918a71cdbe9 299 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 300 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 301 }
Sergunb 0:8918a71cdbe9 302
Sergunb 0:8918a71cdbe9 303
Sergunb 0:8918a71cdbe9 304 /**
Sergunb 0:8918a71cdbe9 305 * @brief Ethernet MAC receive interrupt service routine
Sergunb 0:8918a71cdbe9 306 **/
Sergunb 0:8918a71cdbe9 307
Sergunb 0:8918a71cdbe9 308 void aps3EthRxIrqHandler(void)
Sergunb 0:8918a71cdbe9 309 {
Sergunb 0:8918a71cdbe9 310 bool_t flag;
Sergunb 0:8918a71cdbe9 311
Sergunb 0:8918a71cdbe9 312 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 313 osEnterIsr();
Sergunb 0:8918a71cdbe9 314
Sergunb 0:8918a71cdbe9 315 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 316 flag = FALSE;
Sergunb 0:8918a71cdbe9 317
Sergunb 0:8918a71cdbe9 318 //Disable RX interrupts
Sergunb 0:8918a71cdbe9 319 eth_rx->rx_irq_mask = 0;
Sergunb 0:8918a71cdbe9 320
Sergunb 0:8918a71cdbe9 321 //Set event flag
Sergunb 0:8918a71cdbe9 322 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 323 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 324 flag = osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 325
Sergunb 0:8918a71cdbe9 326 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 327 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 328 }
Sergunb 0:8918a71cdbe9 329
Sergunb 0:8918a71cdbe9 330
Sergunb 0:8918a71cdbe9 331 /**
Sergunb 0:8918a71cdbe9 332 * @brief Cortus APS3 Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 333 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 334 **/
Sergunb 0:8918a71cdbe9 335
Sergunb 0:8918a71cdbe9 336 void aps3EthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 337 {
Sergunb 0:8918a71cdbe9 338 error_t error;
Sergunb 0:8918a71cdbe9 339
Sergunb 0:8918a71cdbe9 340 //A packet has been received?
Sergunb 0:8918a71cdbe9 341 if(eth_rx->rx_status & RX_IRQ_MASK_FRAME_READY)
Sergunb 0:8918a71cdbe9 342 {
Sergunb 0:8918a71cdbe9 343 //Process all pending packets
Sergunb 0:8918a71cdbe9 344 do
Sergunb 0:8918a71cdbe9 345 {
Sergunb 0:8918a71cdbe9 346 //Read incoming packet
Sergunb 0:8918a71cdbe9 347 error = aps3EthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 348
Sergunb 0:8918a71cdbe9 349 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 350 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 351 }
Sergunb 0:8918a71cdbe9 352
Sergunb 0:8918a71cdbe9 353 //Re-enable RX interrupts
Sergunb 0:8918a71cdbe9 354 eth_rx->rx_irq_mask = RX_IRQ_MASK_FRAME_READY;
Sergunb 0:8918a71cdbe9 355 }
Sergunb 0:8918a71cdbe9 356
Sergunb 0:8918a71cdbe9 357
Sergunb 0:8918a71cdbe9 358 /**
Sergunb 0:8918a71cdbe9 359 * @brief Send a packet
Sergunb 0:8918a71cdbe9 360 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 361 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 362 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 363 * @return Error code
Sergunb 0:8918a71cdbe9 364 **/
Sergunb 0:8918a71cdbe9 365
Sergunb 0:8918a71cdbe9 366 error_t aps3EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 367 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 368 {
Sergunb 0:8918a71cdbe9 369 uint_t i;
Sergunb 0:8918a71cdbe9 370 size_t length;
Sergunb 0:8918a71cdbe9 371
Sergunb 0:8918a71cdbe9 372 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 373 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 374
Sergunb 0:8918a71cdbe9 375 //Check the frame length
Sergunb 0:8918a71cdbe9 376 if(length > APS3_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 377 {
Sergunb 0:8918a71cdbe9 378 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 379 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 380 //Report an error
Sergunb 0:8918a71cdbe9 381 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 382 }
Sergunb 0:8918a71cdbe9 383
Sergunb 0:8918a71cdbe9 384 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 385 if(eth_tx->tx_desc_status)
Sergunb 0:8918a71cdbe9 386 {
Sergunb 0:8918a71cdbe9 387 //Re-enable TX interrupts
Sergunb 0:8918a71cdbe9 388 eth_tx->tx_irq_mask = TX_IRQ_MASK_MEMORY_AVAILABLE;
Sergunb 0:8918a71cdbe9 389 //Report an error
Sergunb 0:8918a71cdbe9 390 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 391 }
Sergunb 0:8918a71cdbe9 392
Sergunb 0:8918a71cdbe9 393 //Get the index of the current descriptor
Sergunb 0:8918a71cdbe9 394 i = eth_tx->tx_desc_produce;
Sergunb 0:8918a71cdbe9 395
Sergunb 0:8918a71cdbe9 396 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 397 netBufferRead((uint8_t *) txDmaDesc[i].addr, buffer, offset, length);
Sergunb 0:8918a71cdbe9 398 //Write the number of bytes to send
Sergunb 0:8918a71cdbe9 399 txDmaDesc[i].size = length;
Sergunb 0:8918a71cdbe9 400
Sergunb 0:8918a71cdbe9 401 //Start transmission
Sergunb 0:8918a71cdbe9 402 eth_tx->tx_sw_done = 1;
Sergunb 0:8918a71cdbe9 403
Sergunb 0:8918a71cdbe9 404 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 405 if(!eth_tx->tx_desc_status)
Sergunb 0:8918a71cdbe9 406 {
Sergunb 0:8918a71cdbe9 407 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 408 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 409 }
Sergunb 0:8918a71cdbe9 410 else
Sergunb 0:8918a71cdbe9 411 {
Sergunb 0:8918a71cdbe9 412 //Re-enable TX interrupts
Sergunb 0:8918a71cdbe9 413 eth_tx->tx_irq_mask = TX_IRQ_MASK_MEMORY_AVAILABLE;
Sergunb 0:8918a71cdbe9 414 }
Sergunb 0:8918a71cdbe9 415
Sergunb 0:8918a71cdbe9 416 //Data successfully written
Sergunb 0:8918a71cdbe9 417 return NO_ERROR;
Sergunb 0:8918a71cdbe9 418 }
Sergunb 0:8918a71cdbe9 419
Sergunb 0:8918a71cdbe9 420
Sergunb 0:8918a71cdbe9 421 /**
Sergunb 0:8918a71cdbe9 422 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 423 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 424 * @return Error code
Sergunb 0:8918a71cdbe9 425 **/
Sergunb 0:8918a71cdbe9 426
Sergunb 0:8918a71cdbe9 427 error_t aps3EthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 428 {
Sergunb 0:8918a71cdbe9 429 error_t error;
Sergunb 0:8918a71cdbe9 430 uint_t i;
Sergunb 0:8918a71cdbe9 431 size_t n;
Sergunb 0:8918a71cdbe9 432
Sergunb 0:8918a71cdbe9 433 //The current buffer is available for reading?
Sergunb 0:8918a71cdbe9 434 if(!(eth_rx->rx_desc_status))
Sergunb 0:8918a71cdbe9 435 {
Sergunb 0:8918a71cdbe9 436 //Point to the current descriptor
Sergunb 0:8918a71cdbe9 437 i = eth_rx->rx_desc_consume;
Sergunb 0:8918a71cdbe9 438
Sergunb 0:8918a71cdbe9 439 //Make sure no error occurred
Sergunb 0:8918a71cdbe9 440 if(!(rxDmaDesc[i].status & RX_DESC_RECEIVE_ERROR))
Sergunb 0:8918a71cdbe9 441 {
Sergunb 0:8918a71cdbe9 442 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 443 n = rxDmaDesc[i].size;
Sergunb 0:8918a71cdbe9 444 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 445 n = MIN(n, APS3_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 446
Sergunb 0:8918a71cdbe9 447 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 448 nicProcessPacket(interface, (uint8_t *) rxDmaDesc[i].addr, n);
Sergunb 0:8918a71cdbe9 449
Sergunb 0:8918a71cdbe9 450 //Valid packet received
Sergunb 0:8918a71cdbe9 451 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 452 }
Sergunb 0:8918a71cdbe9 453 else
Sergunb 0:8918a71cdbe9 454 {
Sergunb 0:8918a71cdbe9 455 //The received packet contains an error
Sergunb 0:8918a71cdbe9 456 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 457 }
Sergunb 0:8918a71cdbe9 458
Sergunb 0:8918a71cdbe9 459 //The frame has been has been processed by the software
Sergunb 0:8918a71cdbe9 460 //and is no longer needed
Sergunb 0:8918a71cdbe9 461 eth_rx->rx_sw_done = 1;
Sergunb 0:8918a71cdbe9 462 }
Sergunb 0:8918a71cdbe9 463 else
Sergunb 0:8918a71cdbe9 464 {
Sergunb 0:8918a71cdbe9 465 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 466 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 467 }
Sergunb 0:8918a71cdbe9 468
Sergunb 0:8918a71cdbe9 469 //Return status code
Sergunb 0:8918a71cdbe9 470 return error;
Sergunb 0:8918a71cdbe9 471 }
Sergunb 0:8918a71cdbe9 472
Sergunb 0:8918a71cdbe9 473
Sergunb 0:8918a71cdbe9 474 /**
Sergunb 0:8918a71cdbe9 475 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 476 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 477 * @return Error code
Sergunb 0:8918a71cdbe9 478 **/
Sergunb 0:8918a71cdbe9 479
Sergunb 0:8918a71cdbe9 480 error_t aps3EthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 481 {
Sergunb 0:8918a71cdbe9 482 uint_t i;
Sergunb 0:8918a71cdbe9 483 uint_t k;
Sergunb 0:8918a71cdbe9 484 uint32_t crc;
Sergunb 0:8918a71cdbe9 485 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 486 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 487
Sergunb 0:8918a71cdbe9 488 //Debug message
Sergunb 0:8918a71cdbe9 489 TRACE_DEBUG("Updating Cortus APS3 hash table...\r\n");
Sergunb 0:8918a71cdbe9 490
Sergunb 0:8918a71cdbe9 491 //Clear hash table
Sergunb 0:8918a71cdbe9 492 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 493 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 494
Sergunb 0:8918a71cdbe9 495 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 496 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 497 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 498 {
Sergunb 0:8918a71cdbe9 499 //Point to the current entry
Sergunb 0:8918a71cdbe9 500 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 501
Sergunb 0:8918a71cdbe9 502 //Valid entry?
Sergunb 0:8918a71cdbe9 503 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 504 {
Sergunb 0:8918a71cdbe9 505 //Compute CRC over the current MAC address
Sergunb 0:8918a71cdbe9 506 crc = aps3EthCalcCrc(&entry->addr, sizeof(MacAddr));
Sergunb 0:8918a71cdbe9 507 //Calculate the corresponding index in the table
Sergunb 0:8918a71cdbe9 508 k = (crc >> 23) & 0x3F;
Sergunb 0:8918a71cdbe9 509 //Update hash table contents
Sergunb 0:8918a71cdbe9 510 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 511 }
Sergunb 0:8918a71cdbe9 512 }
Sergunb 0:8918a71cdbe9 513
Sergunb 0:8918a71cdbe9 514 //Disable transmission and reception
Sergunb 0:8918a71cdbe9 515 eth_tx->tx_enable = 0;
Sergunb 0:8918a71cdbe9 516 eth_rx->rx_enable = 0;
Sergunb 0:8918a71cdbe9 517
Sergunb 0:8918a71cdbe9 518 //Write the hash table
Sergunb 0:8918a71cdbe9 519 eth_mac->hash_filter_low = hashTable[0];
Sergunb 0:8918a71cdbe9 520 eth_mac->hash_filter_high = hashTable[1];
Sergunb 0:8918a71cdbe9 521
Sergunb 0:8918a71cdbe9 522 //Debug message
Sergunb 0:8918a71cdbe9 523 TRACE_DEBUG(" hash_filter_low = %08" PRIX32 "\r\n", hashTable[0]);
Sergunb 0:8918a71cdbe9 524 TRACE_DEBUG(" hash_filter_high = %08" PRIX32 "\r\n", hashTable[1]);
Sergunb 0:8918a71cdbe9 525
Sergunb 0:8918a71cdbe9 526 //Re-enable transmission and reception
Sergunb 0:8918a71cdbe9 527 eth_tx->tx_enable = 1;
Sergunb 0:8918a71cdbe9 528 eth_rx->rx_enable = 1;
Sergunb 0:8918a71cdbe9 529
Sergunb 0:8918a71cdbe9 530 //Successful processing
Sergunb 0:8918a71cdbe9 531 return NO_ERROR;
Sergunb 0:8918a71cdbe9 532 }
Sergunb 0:8918a71cdbe9 533
Sergunb 0:8918a71cdbe9 534
Sergunb 0:8918a71cdbe9 535 /**
Sergunb 0:8918a71cdbe9 536 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 537 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 538 * @return Error code
Sergunb 0:8918a71cdbe9 539 **/
Sergunb 0:8918a71cdbe9 540
Sergunb 0:8918a71cdbe9 541 error_t aps3EthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 542 {
Sergunb 0:8918a71cdbe9 543 //Disable transmission and reception
Sergunb 0:8918a71cdbe9 544 eth_tx->tx_enable = 0;
Sergunb 0:8918a71cdbe9 545 eth_rx->rx_enable = 0;
Sergunb 0:8918a71cdbe9 546
Sergunb 0:8918a71cdbe9 547 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 548 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 549 eth_mac->full_duplex = 1;
Sergunb 0:8918a71cdbe9 550 else
Sergunb 0:8918a71cdbe9 551 eth_mac->full_duplex = 0;
Sergunb 0:8918a71cdbe9 552
Sergunb 0:8918a71cdbe9 553 //Re-enable transmission and reception
Sergunb 0:8918a71cdbe9 554 eth_tx->tx_enable = 1;
Sergunb 0:8918a71cdbe9 555 eth_rx->rx_enable = 1;
Sergunb 0:8918a71cdbe9 556
Sergunb 0:8918a71cdbe9 557 //Successful processing
Sergunb 0:8918a71cdbe9 558 return NO_ERROR;
Sergunb 0:8918a71cdbe9 559 }
Sergunb 0:8918a71cdbe9 560
Sergunb 0:8918a71cdbe9 561
Sergunb 0:8918a71cdbe9 562 /**
Sergunb 0:8918a71cdbe9 563 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 564 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 565 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 566 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 567 **/
Sergunb 0:8918a71cdbe9 568
Sergunb 0:8918a71cdbe9 569 void aps3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 570 {
Sergunb 0:8918a71cdbe9 571 //Wait for the MII management module to be ready
Sergunb 0:8918a71cdbe9 572 while(!eth_miim->miim_status);
Sergunb 0:8918a71cdbe9 573
Sergunb 0:8918a71cdbe9 574 //PHY address
Sergunb 0:8918a71cdbe9 575 eth_miim->miim_phy_addr = phyAddr;
Sergunb 0:8918a71cdbe9 576 //Register address
Sergunb 0:8918a71cdbe9 577 eth_miim->miim_phy_register_addr = regAddr;
Sergunb 0:8918a71cdbe9 578 //Data to be written in the PHY register
Sergunb 0:8918a71cdbe9 579 eth_miim->miim_data = data;
Sergunb 0:8918a71cdbe9 580
Sergunb 0:8918a71cdbe9 581 //Start a write operation
Sergunb 0:8918a71cdbe9 582 eth_miim->miim_read_write = 0;
Sergunb 0:8918a71cdbe9 583 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 584 while(!eth_miim->miim_status);
Sergunb 0:8918a71cdbe9 585 }
Sergunb 0:8918a71cdbe9 586
Sergunb 0:8918a71cdbe9 587
Sergunb 0:8918a71cdbe9 588 /**
Sergunb 0:8918a71cdbe9 589 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 590 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 591 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 592 * @return Register value
Sergunb 0:8918a71cdbe9 593 **/
Sergunb 0:8918a71cdbe9 594
Sergunb 0:8918a71cdbe9 595 uint16_t aps3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 596 {
Sergunb 0:8918a71cdbe9 597 //Wait for the MII management module to be ready
Sergunb 0:8918a71cdbe9 598 while(!eth_miim->miim_status);
Sergunb 0:8918a71cdbe9 599
Sergunb 0:8918a71cdbe9 600 //PHY address
Sergunb 0:8918a71cdbe9 601 eth_miim->miim_phy_addr = phyAddr;
Sergunb 0:8918a71cdbe9 602 //Register address
Sergunb 0:8918a71cdbe9 603 eth_miim->miim_phy_register_addr = regAddr;
Sergunb 0:8918a71cdbe9 604
Sergunb 0:8918a71cdbe9 605 //Start a read operation
Sergunb 0:8918a71cdbe9 606 eth_miim->miim_read_write = 1;
Sergunb 0:8918a71cdbe9 607 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 608 while(!eth_miim->miim_status);
Sergunb 0:8918a71cdbe9 609
Sergunb 0:8918a71cdbe9 610 //Return PHY register contents
Sergunb 0:8918a71cdbe9 611 return eth_miim->miim_data;
Sergunb 0:8918a71cdbe9 612 }
Sergunb 0:8918a71cdbe9 613
Sergunb 0:8918a71cdbe9 614
Sergunb 0:8918a71cdbe9 615 /**
Sergunb 0:8918a71cdbe9 616 * @brief CRC calculation
Sergunb 0:8918a71cdbe9 617 * @param[in] data Pointer to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 618 * @param[in] length Number of bytes to process
Sergunb 0:8918a71cdbe9 619 * @return Resulting CRC value
Sergunb 0:8918a71cdbe9 620 **/
Sergunb 0:8918a71cdbe9 621
Sergunb 0:8918a71cdbe9 622 uint32_t aps3EthCalcCrc(const void *data, size_t length)
Sergunb 0:8918a71cdbe9 623 {
Sergunb 0:8918a71cdbe9 624 uint_t i;
Sergunb 0:8918a71cdbe9 625 uint_t j;
Sergunb 0:8918a71cdbe9 626
Sergunb 0:8918a71cdbe9 627 //Point to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 628 const uint8_t *p = (uint8_t *) data;
Sergunb 0:8918a71cdbe9 629 //CRC preset value
Sergunb 0:8918a71cdbe9 630 uint32_t crc = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 631
Sergunb 0:8918a71cdbe9 632 //Loop through data
Sergunb 0:8918a71cdbe9 633 for(i = 0; i < length; i++)
Sergunb 0:8918a71cdbe9 634 {
Sergunb 0:8918a71cdbe9 635 //Update CRC value
Sergunb 0:8918a71cdbe9 636 crc ^= p[i];
Sergunb 0:8918a71cdbe9 637
Sergunb 0:8918a71cdbe9 638 //The message is processed bit by bit
Sergunb 0:8918a71cdbe9 639 for(j = 0; j < 8; j++)
Sergunb 0:8918a71cdbe9 640 {
Sergunb 0:8918a71cdbe9 641 //Update CRC value
Sergunb 0:8918a71cdbe9 642 if(crc & 0x00000001)
Sergunb 0:8918a71cdbe9 643 crc = (crc >> 1) ^ 0xEDB88320;
Sergunb 0:8918a71cdbe9 644 else
Sergunb 0:8918a71cdbe9 645 crc = crc >> 1;
Sergunb 0:8918a71cdbe9 646 }
Sergunb 0:8918a71cdbe9 647 }
Sergunb 0:8918a71cdbe9 648
Sergunb 0:8918a71cdbe9 649 //Return CRC value
Sergunb 0:8918a71cdbe9 650 return ~crc;
Sergunb 0:8918a71cdbe9 651 }
Sergunb 0:8918a71cdbe9 652