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cyclone_tcp/drivers/zynq7000_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file zynq7000_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief Zynq-7000 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include <limits.h>
Sergunb 0:8918a71cdbe9 34 #include "xemacps_hw.h"
Sergunb 0:8918a71cdbe9 35 #include "xscugic.h"
Sergunb 0:8918a71cdbe9 36 #include "xil_misc_psreset_api.h"
Sergunb 0:8918a71cdbe9 37 #include "core/net.h"
Sergunb 0:8918a71cdbe9 38 #include "drivers/zynq7000_eth.h"
Sergunb 0:8918a71cdbe9 39 #include "debug.h"
Sergunb 0:8918a71cdbe9 40
Sergunb 0:8918a71cdbe9 41 //Underlying network interface
Sergunb 0:8918a71cdbe9 42 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 43
Sergunb 0:8918a71cdbe9 44 //GIC instance
Sergunb 0:8918a71cdbe9 45 extern XScuGic ZYNQ7000_ETH_GIC_INSTANCE;
Sergunb 0:8918a71cdbe9 46
Sergunb 0:8918a71cdbe9 47 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 48 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 49
Sergunb 0:8918a71cdbe9 50 //TX buffer
Sergunb 0:8918a71cdbe9 51 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 52 #pragma location = ".ram_no_cache"
Sergunb 0:8918a71cdbe9 53 static uint8_t txBuffer[ZYNQ7000_ETH_TX_BUFFER_COUNT][ZYNQ7000_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 54 //RX buffer
Sergunb 0:8918a71cdbe9 55 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 56 #pragma location = ".ram_no_cache"
Sergunb 0:8918a71cdbe9 57 static uint8_t rxBuffer[ZYNQ7000_ETH_RX_BUFFER_COUNT][ZYNQ7000_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 58 //TX buffer descriptors
Sergunb 0:8918a71cdbe9 59 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 60 #pragma location = ".ram_no_cache"
Sergunb 0:8918a71cdbe9 61 static Zynq7000TxBufferDesc txBufferDesc[ZYNQ7000_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 62 //RX buffer descriptors
Sergunb 0:8918a71cdbe9 63 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 64 #pragma location = ".ram_no_cache"
Sergunb 0:8918a71cdbe9 65 static Zynq7000RxBufferDesc rxBufferDesc[ZYNQ7000_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 66
Sergunb 0:8918a71cdbe9 67 //Keil MDK-ARM or GCC compiler?
Sergunb 0:8918a71cdbe9 68 #else
Sergunb 0:8918a71cdbe9 69
Sergunb 0:8918a71cdbe9 70 //TX buffer
Sergunb 0:8918a71cdbe9 71 static uint8_t txBuffer[ZYNQ7000_ETH_TX_BUFFER_COUNT][ZYNQ7000_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 72 __attribute__((aligned(8), __section__(".ram_no_cache")));
Sergunb 0:8918a71cdbe9 73 //RX buffer
Sergunb 0:8918a71cdbe9 74 static uint8_t rxBuffer[ZYNQ7000_ETH_RX_BUFFER_COUNT][ZYNQ7000_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 75 __attribute__((aligned(8), __section__(".ram_no_cache")));
Sergunb 0:8918a71cdbe9 76 //TX buffer descriptors
Sergunb 0:8918a71cdbe9 77 static Zynq7000TxBufferDesc txBufferDesc[ZYNQ7000_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 78 __attribute__((aligned(4), __section__(".ram_no_cache")));
Sergunb 0:8918a71cdbe9 79 //RX buffer descriptors
Sergunb 0:8918a71cdbe9 80 static Zynq7000RxBufferDesc rxBufferDesc[ZYNQ7000_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 81 __attribute__((aligned(4), __section__(".ram_no_cache")));
Sergunb 0:8918a71cdbe9 82
Sergunb 0:8918a71cdbe9 83 #endif
Sergunb 0:8918a71cdbe9 84
Sergunb 0:8918a71cdbe9 85 //TX buffer index
Sergunb 0:8918a71cdbe9 86 static uint_t txBufferIndex;
Sergunb 0:8918a71cdbe9 87 //RX buffer index
Sergunb 0:8918a71cdbe9 88 static uint_t rxBufferIndex;
Sergunb 0:8918a71cdbe9 89
Sergunb 0:8918a71cdbe9 90
Sergunb 0:8918a71cdbe9 91 /**
Sergunb 0:8918a71cdbe9 92 * @brief Zynq-7000 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 93 **/
Sergunb 0:8918a71cdbe9 94
Sergunb 0:8918a71cdbe9 95 const NicDriver zynq7000EthDriver =
Sergunb 0:8918a71cdbe9 96 {
Sergunb 0:8918a71cdbe9 97 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 98 ETH_MTU,
Sergunb 0:8918a71cdbe9 99 zynq7000EthInit,
Sergunb 0:8918a71cdbe9 100 zynq7000EthTick,
Sergunb 0:8918a71cdbe9 101 zynq7000EthEnableIrq,
Sergunb 0:8918a71cdbe9 102 zynq7000EthDisableIrq,
Sergunb 0:8918a71cdbe9 103 zynq7000EthEventHandler,
Sergunb 0:8918a71cdbe9 104 zynq7000EthSendPacket,
Sergunb 0:8918a71cdbe9 105 zynq7000EthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 106 zynq7000EthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 107 zynq7000EthWritePhyReg,
Sergunb 0:8918a71cdbe9 108 zynq7000EthReadPhyReg,
Sergunb 0:8918a71cdbe9 109 TRUE,
Sergunb 0:8918a71cdbe9 110 TRUE,
Sergunb 0:8918a71cdbe9 111 TRUE,
Sergunb 0:8918a71cdbe9 112 FALSE
Sergunb 0:8918a71cdbe9 113 };
Sergunb 0:8918a71cdbe9 114
Sergunb 0:8918a71cdbe9 115
Sergunb 0:8918a71cdbe9 116 /**
Sergunb 0:8918a71cdbe9 117 * @brief Zynq-7000 Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 118 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 119 * @return Error code
Sergunb 0:8918a71cdbe9 120 **/
Sergunb 0:8918a71cdbe9 121
Sergunb 0:8918a71cdbe9 122 error_t zynq7000EthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 123 {
Sergunb 0:8918a71cdbe9 124 error_t error;
Sergunb 0:8918a71cdbe9 125 volatile uint32_t temp;
Sergunb 0:8918a71cdbe9 126
Sergunb 0:8918a71cdbe9 127 //Debug message
Sergunb 0:8918a71cdbe9 128 TRACE_INFO("Initializing Zynq-7000 Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 129
Sergunb 0:8918a71cdbe9 130 //Save underlying network interface
Sergunb 0:8918a71cdbe9 131 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 132
Sergunb 0:8918a71cdbe9 133 //Unlock SLCR
Sergunb 0:8918a71cdbe9 134 XSLCR_UNLOCK = XSLCR_UNLOCK_KEY_VALUE;
Sergunb 0:8918a71cdbe9 135
Sergunb 0:8918a71cdbe9 136 //Configure Ethernet controller reference clock
Sergunb 0:8918a71cdbe9 137 temp = XSLCR_GEM0_CLK_CTRL_CLKACT_MASK;
Sergunb 0:8918a71cdbe9 138 temp |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 << 20) & XSLCR_GEM0_CLK_CTRL_DIV1_MASK;
Sergunb 0:8918a71cdbe9 139 temp |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 << 8) & XSLCR_GEM0_CLK_CTRL_DIV0_MASK;
Sergunb 0:8918a71cdbe9 140 XSLCR_GEM0_CLK_CTRL = temp;
Sergunb 0:8918a71cdbe9 141
Sergunb 0:8918a71cdbe9 142 //Enable Ethernet controller RX clock
Sergunb 0:8918a71cdbe9 143 XSLCR_GEM0_RCLK_CTRL = XSLCR_GEM0_RCLK_CTRL_CLKACT_MASK;
Sergunb 0:8918a71cdbe9 144
Sergunb 0:8918a71cdbe9 145 //Lock SLCR
Sergunb 0:8918a71cdbe9 146 XSLCR_LOCK = XSLCR_LOCK_KEY_VALUE;
Sergunb 0:8918a71cdbe9 147
Sergunb 0:8918a71cdbe9 148 //Clear network control register
Sergunb 0:8918a71cdbe9 149 XEMACPS_NWCTRL = 0;
Sergunb 0:8918a71cdbe9 150 //Clear statistics registers
Sergunb 0:8918a71cdbe9 151 XEMACPS_NWCTRL |= XEMACPS_NWCTRL_STATCLR_MASK;
Sergunb 0:8918a71cdbe9 152
Sergunb 0:8918a71cdbe9 153 //Configure MDC clock speed
Sergunb 0:8918a71cdbe9 154 XEMACPS_NWCFG = (MDC_DIV_224 << XEMACPS_NWCFG_MDC_SHIFT_MASK) | XEMACPS_NWCFG_MDCCLKDIV_MASK;
Sergunb 0:8918a71cdbe9 155 //Enable management port (MDC and MDIO)
Sergunb 0:8918a71cdbe9 156 XEMACPS_NWCTRL |= XEMACPS_NWCTRL_MDEN_MASK;
Sergunb 0:8918a71cdbe9 157
Sergunb 0:8918a71cdbe9 158 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 159 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 160 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 161 if(error)
Sergunb 0:8918a71cdbe9 162 return error;
Sergunb 0:8918a71cdbe9 163
Sergunb 0:8918a71cdbe9 164 //Set the MAC address
Sergunb 0:8918a71cdbe9 165 XEMACPS_LADDR1L = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 166 XEMACPS_LADDR1H = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 167
Sergunb 0:8918a71cdbe9 168 //Configure the receive filter
Sergunb 0:8918a71cdbe9 169 XEMACPS_NWCFG |= XEMACPS_NWCFG_UCASTHASHEN_MASK | XEMACPS_NWCFG_MCASTHASHEN_MASK;
Sergunb 0:8918a71cdbe9 170
Sergunb 0:8918a71cdbe9 171 //Initialize hash table
Sergunb 0:8918a71cdbe9 172 XEMACPS_HASHL = 0;
Sergunb 0:8918a71cdbe9 173 XEMACPS_HASHH = 0;
Sergunb 0:8918a71cdbe9 174
Sergunb 0:8918a71cdbe9 175 //Initialize buffer descriptors
Sergunb 0:8918a71cdbe9 176 zynq7000EthInitBufferDesc(interface);
Sergunb 0:8918a71cdbe9 177
Sergunb 0:8918a71cdbe9 178 //Set RX buffer size
Sergunb 0:8918a71cdbe9 179 temp = ((ZYNQ7000_ETH_RX_BUFFER_SIZE / 64) << XEMACPS_DMACR_RXBUF_SHIFT) &
Sergunb 0:8918a71cdbe9 180 XEMACPS_DMACR_RXBUF_MASK;
Sergunb 0:8918a71cdbe9 181
Sergunb 0:8918a71cdbe9 182 //Use full configured addressable space for transmit and receive packet buffers
Sergunb 0:8918a71cdbe9 183 temp |= XEMACPS_DMACR_TXSIZE_MASK | XEMACPS_DMACR_RXSIZE_MASK;
Sergunb 0:8918a71cdbe9 184 //Select the burst length for DMA data operations
Sergunb 0:8918a71cdbe9 185 temp |= XEMACPS_DMACR_INCR16_AHB_BURST;
Sergunb 0:8918a71cdbe9 186 //Set DMA configuration register
Sergunb 0:8918a71cdbe9 187 XEMACPS_DMACR = temp;
Sergunb 0:8918a71cdbe9 188
Sergunb 0:8918a71cdbe9 189 //Clear transmit status register
Sergunb 0:8918a71cdbe9 190 XEMACPS_TXSR = XEMACPS_TXSR_TXCOMPL_MASK | XEMACPS_TXSR_TXGO_MASK |
Sergunb 0:8918a71cdbe9 191 XEMACPS_TXSR_ERROR_MASK;
Sergunb 0:8918a71cdbe9 192
Sergunb 0:8918a71cdbe9 193 //Clear receive status register
Sergunb 0:8918a71cdbe9 194 XEMACPS_RXSR = XEMACPS_RXSR_FRAMERX_MASK | XEMACPS_RXSR_ERROR_MASK;
Sergunb 0:8918a71cdbe9 195
Sergunb 0:8918a71cdbe9 196 //First disable all interrupts
Sergunb 0:8918a71cdbe9 197 XEMACPS_IDR = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 198
Sergunb 0:8918a71cdbe9 199 //Only the desired ones are enabled
Sergunb 0:8918a71cdbe9 200 XEMACPS_IER = XEMACPS_IXR_HRESPNOK_MASK | XEMACPS_IXR_RXOVR_MASK |
Sergunb 0:8918a71cdbe9 201 XEMACPS_IXR_TXCOMPL_MASK | XEMACPS_IXR_TXEXH_MASK | XEMACPS_IXR_RETRY_MASK |
Sergunb 0:8918a71cdbe9 202 XEMACPS_IXR_URUN_MASK | XEMACPS_IXR_RXUSED_MASK | XEMACPS_IXR_FRAMERX_MASK;
Sergunb 0:8918a71cdbe9 203
Sergunb 0:8918a71cdbe9 204 //Read interrupt status register to clear any pending interrupt
Sergunb 0:8918a71cdbe9 205 temp = XEMACPS_ISR;
Sergunb 0:8918a71cdbe9 206
Sergunb 0:8918a71cdbe9 207 //Register interrupt handler
Sergunb 0:8918a71cdbe9 208 XScuGic_Connect(&ZYNQ7000_ETH_GIC_INSTANCE, XPS_GEM0_INT_ID,
Sergunb 0:8918a71cdbe9 209 (Xil_InterruptHandler) zynq7000EthIrqHandler, interface);
Sergunb 0:8918a71cdbe9 210
Sergunb 0:8918a71cdbe9 211 //Configure interrupt priority
Sergunb 0:8918a71cdbe9 212 XScuGic_SetPriorityTriggerType(&ZYNQ7000_ETH_GIC_INSTANCE,
Sergunb 0:8918a71cdbe9 213 XPS_GEM0_INT_ID, ZYNQ7000_ETH_IRQ_PRIORITY, 1);
Sergunb 0:8918a71cdbe9 214
Sergunb 0:8918a71cdbe9 215 //Enable the transmitter and the receiver
Sergunb 0:8918a71cdbe9 216 XEMACPS_NWCTRL |= XEMACPS_NWCTRL_TXEN_MASK | XEMACPS_NWCTRL_RXEN_MASK;
Sergunb 0:8918a71cdbe9 217
Sergunb 0:8918a71cdbe9 218 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 219 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 220
Sergunb 0:8918a71cdbe9 221 //Successful initialization
Sergunb 0:8918a71cdbe9 222 return NO_ERROR;
Sergunb 0:8918a71cdbe9 223 }
Sergunb 0:8918a71cdbe9 224
Sergunb 0:8918a71cdbe9 225
Sergunb 0:8918a71cdbe9 226 /**
Sergunb 0:8918a71cdbe9 227 * @brief Initialize buffer descriptors
Sergunb 0:8918a71cdbe9 228 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 229 **/
Sergunb 0:8918a71cdbe9 230
Sergunb 0:8918a71cdbe9 231 void zynq7000EthInitBufferDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 232 {
Sergunb 0:8918a71cdbe9 233 uint_t i;
Sergunb 0:8918a71cdbe9 234 uint32_t address;
Sergunb 0:8918a71cdbe9 235
Sergunb 0:8918a71cdbe9 236 //Initialize TX buffer descriptors
Sergunb 0:8918a71cdbe9 237 for(i = 0; i < ZYNQ7000_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 238 {
Sergunb 0:8918a71cdbe9 239 //Calculate the address of the current TX buffer
Sergunb 0:8918a71cdbe9 240 address = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 241 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 242 txBufferDesc[i].address = address;
Sergunb 0:8918a71cdbe9 243 //Initialize status field
Sergunb 0:8918a71cdbe9 244 txBufferDesc[i].status = XEMACPS_TX_USED;
Sergunb 0:8918a71cdbe9 245 }
Sergunb 0:8918a71cdbe9 246
Sergunb 0:8918a71cdbe9 247 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 248 txBufferDesc[i - 1].status |= XEMACPS_TX_WRAP;
Sergunb 0:8918a71cdbe9 249 //Initialize TX buffer index
Sergunb 0:8918a71cdbe9 250 txBufferIndex = 0;
Sergunb 0:8918a71cdbe9 251
Sergunb 0:8918a71cdbe9 252 //Initialize RX buffer descriptors
Sergunb 0:8918a71cdbe9 253 for(i = 0; i < ZYNQ7000_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 254 {
Sergunb 0:8918a71cdbe9 255 //Calculate the address of the current RX buffer
Sergunb 0:8918a71cdbe9 256 address = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 257 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 258 rxBufferDesc[i].address = address & XEMACPS_RX_ADDRESS;
Sergunb 0:8918a71cdbe9 259 //Clear status field
Sergunb 0:8918a71cdbe9 260 rxBufferDesc[i].status = 0;
Sergunb 0:8918a71cdbe9 261 }
Sergunb 0:8918a71cdbe9 262
Sergunb 0:8918a71cdbe9 263 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 264 rxBufferDesc[i - 1].address |= XEMACPS_RX_WRAP;
Sergunb 0:8918a71cdbe9 265 //Initialize RX buffer index
Sergunb 0:8918a71cdbe9 266 rxBufferIndex = 0;
Sergunb 0:8918a71cdbe9 267
Sergunb 0:8918a71cdbe9 268 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 269 XEMACPS_TXQBASE = (uint32_t) txBufferDesc;
Sergunb 0:8918a71cdbe9 270 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 271 XEMACPS_RXQBASE = (uint32_t) rxBufferDesc;
Sergunb 0:8918a71cdbe9 272 }
Sergunb 0:8918a71cdbe9 273
Sergunb 0:8918a71cdbe9 274
Sergunb 0:8918a71cdbe9 275 /**
Sergunb 0:8918a71cdbe9 276 * @brief Zynq-7000 Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 277 *
Sergunb 0:8918a71cdbe9 278 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 279 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 280 *
Sergunb 0:8918a71cdbe9 281 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 282 **/
Sergunb 0:8918a71cdbe9 283
Sergunb 0:8918a71cdbe9 284 void zynq7000EthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 285 {
Sergunb 0:8918a71cdbe9 286 //Handle periodic operations
Sergunb 0:8918a71cdbe9 287 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 288 }
Sergunb 0:8918a71cdbe9 289
Sergunb 0:8918a71cdbe9 290
Sergunb 0:8918a71cdbe9 291 /**
Sergunb 0:8918a71cdbe9 292 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 293 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 294 **/
Sergunb 0:8918a71cdbe9 295
Sergunb 0:8918a71cdbe9 296 void zynq7000EthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 297 {
Sergunb 0:8918a71cdbe9 298 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 299 XScuGic_Enable(&ZYNQ7000_ETH_GIC_INSTANCE, XPS_GEM0_INT_ID);
Sergunb 0:8918a71cdbe9 300 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 301 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 302 }
Sergunb 0:8918a71cdbe9 303
Sergunb 0:8918a71cdbe9 304
Sergunb 0:8918a71cdbe9 305 /**
Sergunb 0:8918a71cdbe9 306 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 307 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 308 **/
Sergunb 0:8918a71cdbe9 309
Sergunb 0:8918a71cdbe9 310 void zynq7000EthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 311 {
Sergunb 0:8918a71cdbe9 312 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 313 XScuGic_Disable(&ZYNQ7000_ETH_GIC_INSTANCE, XPS_GEM0_INT_ID);
Sergunb 0:8918a71cdbe9 314 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 315 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 316 }
Sergunb 0:8918a71cdbe9 317
Sergunb 0:8918a71cdbe9 318
Sergunb 0:8918a71cdbe9 319 /**
Sergunb 0:8918a71cdbe9 320 * @brief Zynq-7000 Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 321 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 322 **/
Sergunb 0:8918a71cdbe9 323
Sergunb 0:8918a71cdbe9 324 void zynq7000EthIrqHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 325 {
Sergunb 0:8918a71cdbe9 326 bool_t flag;
Sergunb 0:8918a71cdbe9 327 volatile uint32_t isr;
Sergunb 0:8918a71cdbe9 328 volatile uint32_t tsr;
Sergunb 0:8918a71cdbe9 329 volatile uint32_t rsr;
Sergunb 0:8918a71cdbe9 330
Sergunb 0:8918a71cdbe9 331 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 332 osEnterIsr();
Sergunb 0:8918a71cdbe9 333
Sergunb 0:8918a71cdbe9 334 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 335 flag = FALSE;
Sergunb 0:8918a71cdbe9 336
Sergunb 0:8918a71cdbe9 337 //Each time the software reads XEMACPS_ISR, it has to check the
Sergunb 0:8918a71cdbe9 338 //contents of XEMACPS_TXSR, XEMACPS_RXSR
Sergunb 0:8918a71cdbe9 339 isr = XEMACPS_ISR;
Sergunb 0:8918a71cdbe9 340 tsr = XEMACPS_TXSR;
Sergunb 0:8918a71cdbe9 341 rsr = XEMACPS_RXSR;
Sergunb 0:8918a71cdbe9 342
Sergunb 0:8918a71cdbe9 343 //Clear interrupt flags
Sergunb 0:8918a71cdbe9 344 XEMACPS_ISR = isr;
Sergunb 0:8918a71cdbe9 345
Sergunb 0:8918a71cdbe9 346 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 347 if(tsr & (XEMACPS_TXSR_TXCOMPL_MASK | XEMACPS_TXSR_TXGO_MASK | XEMACPS_TXSR_ERROR_MASK))
Sergunb 0:8918a71cdbe9 348 {
Sergunb 0:8918a71cdbe9 349 //Only clear TSR flags that are currently set
Sergunb 0:8918a71cdbe9 350 XEMACPS_TXSR = tsr;
Sergunb 0:8918a71cdbe9 351
Sergunb 0:8918a71cdbe9 352 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 353 if(txBufferDesc[txBufferIndex].status & XEMACPS_TX_USED)
Sergunb 0:8918a71cdbe9 354 {
Sergunb 0:8918a71cdbe9 355 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 356 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 357 }
Sergunb 0:8918a71cdbe9 358 }
Sergunb 0:8918a71cdbe9 359
Sergunb 0:8918a71cdbe9 360 //A packet has been received?
Sergunb 0:8918a71cdbe9 361 if(rsr & (XEMACPS_RXSR_FRAMERX_MASK | XEMACPS_RXSR_ERROR_MASK))
Sergunb 0:8918a71cdbe9 362 {
Sergunb 0:8918a71cdbe9 363 //Set event flag
Sergunb 0:8918a71cdbe9 364 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 365 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 366 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 367 }
Sergunb 0:8918a71cdbe9 368
Sergunb 0:8918a71cdbe9 369 //Flush packet if the receive buffer not available
Sergunb 0:8918a71cdbe9 370 if (isr & XEMACPS_IXR_RXUSED_MASK)
Sergunb 0:8918a71cdbe9 371 XEMACPS_NWCTRL |= XEMACPS_NWCTRL_FLUSH_DPRAM_MASK;
Sergunb 0:8918a71cdbe9 372
Sergunb 0:8918a71cdbe9 373 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 374 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 375 }
Sergunb 0:8918a71cdbe9 376
Sergunb 0:8918a71cdbe9 377
Sergunb 0:8918a71cdbe9 378 /**
Sergunb 0:8918a71cdbe9 379 * @brief Zynq-7000 Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 380 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 381 **/
Sergunb 0:8918a71cdbe9 382
Sergunb 0:8918a71cdbe9 383 void zynq7000EthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 384 {
Sergunb 0:8918a71cdbe9 385 error_t error;
Sergunb 0:8918a71cdbe9 386 uint32_t rsr;
Sergunb 0:8918a71cdbe9 387
Sergunb 0:8918a71cdbe9 388 //Read receive status
Sergunb 0:8918a71cdbe9 389 rsr = XEMACPS_RXSR;
Sergunb 0:8918a71cdbe9 390
Sergunb 0:8918a71cdbe9 391 //Packet received?
Sergunb 0:8918a71cdbe9 392 if(rsr & (XEMACPS_RXSR_FRAMERX_MASK | XEMACPS_RXSR_ERROR_MASK))
Sergunb 0:8918a71cdbe9 393 {
Sergunb 0:8918a71cdbe9 394 //Only clear RSR flags that are currently set
Sergunb 0:8918a71cdbe9 395 XEMACPS_RXSR = rsr;
Sergunb 0:8918a71cdbe9 396
Sergunb 0:8918a71cdbe9 397 //Process all pending packets
Sergunb 0:8918a71cdbe9 398 do
Sergunb 0:8918a71cdbe9 399 {
Sergunb 0:8918a71cdbe9 400 //Read incoming packet
Sergunb 0:8918a71cdbe9 401 error = zynq7000EthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 402
Sergunb 0:8918a71cdbe9 403 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 404 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 405 }
Sergunb 0:8918a71cdbe9 406 }
Sergunb 0:8918a71cdbe9 407
Sergunb 0:8918a71cdbe9 408
Sergunb 0:8918a71cdbe9 409 /**
Sergunb 0:8918a71cdbe9 410 * @brief Send a packet
Sergunb 0:8918a71cdbe9 411 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 412 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 413 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 414 * @return Error code
Sergunb 0:8918a71cdbe9 415 **/
Sergunb 0:8918a71cdbe9 416
Sergunb 0:8918a71cdbe9 417 error_t zynq7000EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 418 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 419 {
Sergunb 0:8918a71cdbe9 420 static uint8_t temp[ZYNQ7000_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 421 size_t length;
Sergunb 0:8918a71cdbe9 422
Sergunb 0:8918a71cdbe9 423 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 424 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 425
Sergunb 0:8918a71cdbe9 426 //Check the frame length
Sergunb 0:8918a71cdbe9 427 if(length > ZYNQ7000_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 428 {
Sergunb 0:8918a71cdbe9 429 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 430 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 431 //Report an error
Sergunb 0:8918a71cdbe9 432 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 433 }
Sergunb 0:8918a71cdbe9 434
Sergunb 0:8918a71cdbe9 435 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 436 if(!(txBufferDesc[txBufferIndex].status & XEMACPS_TX_USED))
Sergunb 0:8918a71cdbe9 437 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 438
Sergunb 0:8918a71cdbe9 439 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 440 netBufferRead(temp, buffer, offset, length);
Sergunb 0:8918a71cdbe9 441 memcpy(txBuffer[txBufferIndex], temp, length);
Sergunb 0:8918a71cdbe9 442
Sergunb 0:8918a71cdbe9 443 //Set the necessary flags in the descriptor entry
Sergunb 0:8918a71cdbe9 444 if(txBufferIndex < (ZYNQ7000_ETH_TX_BUFFER_COUNT - 1))
Sergunb 0:8918a71cdbe9 445 {
Sergunb 0:8918a71cdbe9 446 //Write the status word
Sergunb 0:8918a71cdbe9 447 txBufferDesc[txBufferIndex].status =
Sergunb 0:8918a71cdbe9 448 XEMACPS_TX_LAST | (length & XEMACPS_TX_LENGTH);
Sergunb 0:8918a71cdbe9 449
Sergunb 0:8918a71cdbe9 450 //Point to the next buffer
Sergunb 0:8918a71cdbe9 451 txBufferIndex++;
Sergunb 0:8918a71cdbe9 452 }
Sergunb 0:8918a71cdbe9 453 else
Sergunb 0:8918a71cdbe9 454 {
Sergunb 0:8918a71cdbe9 455 //Write the status word
Sergunb 0:8918a71cdbe9 456 txBufferDesc[txBufferIndex].status = XEMACPS_TX_WRAP |
Sergunb 0:8918a71cdbe9 457 XEMACPS_TX_LAST | (length & XEMACPS_TX_LENGTH);
Sergunb 0:8918a71cdbe9 458
Sergunb 0:8918a71cdbe9 459 //Wrap around
Sergunb 0:8918a71cdbe9 460 txBufferIndex = 0;
Sergunb 0:8918a71cdbe9 461 }
Sergunb 0:8918a71cdbe9 462
Sergunb 0:8918a71cdbe9 463 //Set the STARTTX bit to initiate transmission
Sergunb 0:8918a71cdbe9 464 XEMACPS_NWCTRL |= XEMACPS_NWCTRL_STARTTX_MASK;
Sergunb 0:8918a71cdbe9 465
Sergunb 0:8918a71cdbe9 466 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 467 if(txBufferDesc[txBufferIndex].status & XEMACPS_TX_USED)
Sergunb 0:8918a71cdbe9 468 {
Sergunb 0:8918a71cdbe9 469 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 470 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 471 }
Sergunb 0:8918a71cdbe9 472
Sergunb 0:8918a71cdbe9 473 //Successful processing
Sergunb 0:8918a71cdbe9 474 return NO_ERROR;
Sergunb 0:8918a71cdbe9 475 }
Sergunb 0:8918a71cdbe9 476
Sergunb 0:8918a71cdbe9 477
Sergunb 0:8918a71cdbe9 478 /**
Sergunb 0:8918a71cdbe9 479 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 480 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 481 * @return Error code
Sergunb 0:8918a71cdbe9 482 **/
Sergunb 0:8918a71cdbe9 483
Sergunb 0:8918a71cdbe9 484 error_t zynq7000EthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 485 {
Sergunb 0:8918a71cdbe9 486 static uint8_t temp[ETH_MAX_FRAME_SIZE];
Sergunb 0:8918a71cdbe9 487 error_t error;
Sergunb 0:8918a71cdbe9 488 uint_t i;
Sergunb 0:8918a71cdbe9 489 uint_t j;
Sergunb 0:8918a71cdbe9 490 uint_t sofIndex;
Sergunb 0:8918a71cdbe9 491 uint_t eofIndex;
Sergunb 0:8918a71cdbe9 492 size_t n;
Sergunb 0:8918a71cdbe9 493 size_t size;
Sergunb 0:8918a71cdbe9 494 size_t length;
Sergunb 0:8918a71cdbe9 495
Sergunb 0:8918a71cdbe9 496 //Initialize SOF and EOF indices
Sergunb 0:8918a71cdbe9 497 sofIndex = UINT_MAX;
Sergunb 0:8918a71cdbe9 498 eofIndex = UINT_MAX;
Sergunb 0:8918a71cdbe9 499
Sergunb 0:8918a71cdbe9 500 //Search for SOF and EOF flags
Sergunb 0:8918a71cdbe9 501 for(i = 0; i < ZYNQ7000_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 502 {
Sergunb 0:8918a71cdbe9 503 //Point to the current entry
Sergunb 0:8918a71cdbe9 504 j = rxBufferIndex + i;
Sergunb 0:8918a71cdbe9 505
Sergunb 0:8918a71cdbe9 506 //Wrap around to the beginning of the buffer if necessary
Sergunb 0:8918a71cdbe9 507 if(j >= ZYNQ7000_ETH_RX_BUFFER_COUNT)
Sergunb 0:8918a71cdbe9 508 j -= ZYNQ7000_ETH_RX_BUFFER_COUNT;
Sergunb 0:8918a71cdbe9 509
Sergunb 0:8918a71cdbe9 510 //No more entries to process?
Sergunb 0:8918a71cdbe9 511 if(!(rxBufferDesc[j].address & XEMACPS_RX_OWNERSHIP))
Sergunb 0:8918a71cdbe9 512 {
Sergunb 0:8918a71cdbe9 513 //Stop processing
Sergunb 0:8918a71cdbe9 514 break;
Sergunb 0:8918a71cdbe9 515 }
Sergunb 0:8918a71cdbe9 516 //A valid SOF has been found?
Sergunb 0:8918a71cdbe9 517 if(rxBufferDesc[j].status & XEMACPS_RX_SOF)
Sergunb 0:8918a71cdbe9 518 {
Sergunb 0:8918a71cdbe9 519 //Save the position of the SOF
Sergunb 0:8918a71cdbe9 520 sofIndex = i;
Sergunb 0:8918a71cdbe9 521 }
Sergunb 0:8918a71cdbe9 522 //A valid EOF has been found?
Sergunb 0:8918a71cdbe9 523 if((rxBufferDesc[j].status & XEMACPS_RX_EOF) && sofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 524 {
Sergunb 0:8918a71cdbe9 525 //Save the position of the EOF
Sergunb 0:8918a71cdbe9 526 eofIndex = i;
Sergunb 0:8918a71cdbe9 527 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 528 size = rxBufferDesc[j].status & XEMACPS_RX_LENGTH;
Sergunb 0:8918a71cdbe9 529 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 530 size = MIN(size, ETH_MAX_FRAME_SIZE);
Sergunb 0:8918a71cdbe9 531 //Stop processing since we have reached the end of the frame
Sergunb 0:8918a71cdbe9 532 break;
Sergunb 0:8918a71cdbe9 533 }
Sergunb 0:8918a71cdbe9 534 }
Sergunb 0:8918a71cdbe9 535
Sergunb 0:8918a71cdbe9 536 //Determine the number of entries to process
Sergunb 0:8918a71cdbe9 537 if(eofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 538 j = eofIndex + 1;
Sergunb 0:8918a71cdbe9 539 else if(sofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 540 j = sofIndex;
Sergunb 0:8918a71cdbe9 541 else
Sergunb 0:8918a71cdbe9 542 j = i;
Sergunb 0:8918a71cdbe9 543
Sergunb 0:8918a71cdbe9 544 //Total number of bytes that have been copied from the receive buffer
Sergunb 0:8918a71cdbe9 545 length = 0;
Sergunb 0:8918a71cdbe9 546
Sergunb 0:8918a71cdbe9 547 //Process incoming frame
Sergunb 0:8918a71cdbe9 548 for(i = 0; i < j; i++)
Sergunb 0:8918a71cdbe9 549 {
Sergunb 0:8918a71cdbe9 550 //Any data to copy from current buffer?
Sergunb 0:8918a71cdbe9 551 if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
Sergunb 0:8918a71cdbe9 552 {
Sergunb 0:8918a71cdbe9 553 //Calculate the number of bytes to read at a time
Sergunb 0:8918a71cdbe9 554 n = MIN(size, ZYNQ7000_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 555 //Copy data from receive buffer
Sergunb 0:8918a71cdbe9 556 memcpy(temp + length, rxBuffer[rxBufferIndex], n);
Sergunb 0:8918a71cdbe9 557 //Update byte counters
Sergunb 0:8918a71cdbe9 558 length += n;
Sergunb 0:8918a71cdbe9 559 size -= n;
Sergunb 0:8918a71cdbe9 560 }
Sergunb 0:8918a71cdbe9 561
Sergunb 0:8918a71cdbe9 562 //Mark the current buffer as free
Sergunb 0:8918a71cdbe9 563 rxBufferDesc[rxBufferIndex].address &= ~XEMACPS_RX_OWNERSHIP;
Sergunb 0:8918a71cdbe9 564
Sergunb 0:8918a71cdbe9 565 //Point to the following entry
Sergunb 0:8918a71cdbe9 566 rxBufferIndex++;
Sergunb 0:8918a71cdbe9 567
Sergunb 0:8918a71cdbe9 568 //Wrap around to the beginning of the buffer if necessary
Sergunb 0:8918a71cdbe9 569 if(rxBufferIndex >= ZYNQ7000_ETH_RX_BUFFER_COUNT)
Sergunb 0:8918a71cdbe9 570 rxBufferIndex = 0;
Sergunb 0:8918a71cdbe9 571 }
Sergunb 0:8918a71cdbe9 572
Sergunb 0:8918a71cdbe9 573 //Any packet to process?
Sergunb 0:8918a71cdbe9 574 if(length > 0)
Sergunb 0:8918a71cdbe9 575 {
Sergunb 0:8918a71cdbe9 576 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 577 nicProcessPacket(interface, temp, length);
Sergunb 0:8918a71cdbe9 578 //Valid packet received
Sergunb 0:8918a71cdbe9 579 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 580 }
Sergunb 0:8918a71cdbe9 581 else
Sergunb 0:8918a71cdbe9 582 {
Sergunb 0:8918a71cdbe9 583 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 584 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 585 }
Sergunb 0:8918a71cdbe9 586
Sergunb 0:8918a71cdbe9 587 //Return status code
Sergunb 0:8918a71cdbe9 588 return error;
Sergunb 0:8918a71cdbe9 589 }
Sergunb 0:8918a71cdbe9 590
Sergunb 0:8918a71cdbe9 591
Sergunb 0:8918a71cdbe9 592 /**
Sergunb 0:8918a71cdbe9 593 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 594 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 595 * @return Error code
Sergunb 0:8918a71cdbe9 596 **/
Sergunb 0:8918a71cdbe9 597
Sergunb 0:8918a71cdbe9 598 error_t zynq7000EthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 599 {
Sergunb 0:8918a71cdbe9 600 uint_t i;
Sergunb 0:8918a71cdbe9 601 uint_t k;
Sergunb 0:8918a71cdbe9 602 uint8_t *p;
Sergunb 0:8918a71cdbe9 603 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 604 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 605
Sergunb 0:8918a71cdbe9 606 //Debug message
Sergunb 0:8918a71cdbe9 607 TRACE_DEBUG("Updating Zynq-7000 hash table...\r\n");
Sergunb 0:8918a71cdbe9 608
Sergunb 0:8918a71cdbe9 609 //Clear hash table
Sergunb 0:8918a71cdbe9 610 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 611 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 612
Sergunb 0:8918a71cdbe9 613 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 614 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 615 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 616 {
Sergunb 0:8918a71cdbe9 617 //Point to the current entry
Sergunb 0:8918a71cdbe9 618 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 619
Sergunb 0:8918a71cdbe9 620 //Valid entry?
Sergunb 0:8918a71cdbe9 621 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 622 {
Sergunb 0:8918a71cdbe9 623 //Point to the MAC address
Sergunb 0:8918a71cdbe9 624 p = entry->addr.b;
Sergunb 0:8918a71cdbe9 625
Sergunb 0:8918a71cdbe9 626 //Apply the hash function
Sergunb 0:8918a71cdbe9 627 k = (p[0] >> 6) ^ p[0];
Sergunb 0:8918a71cdbe9 628 k ^= (p[1] >> 4) ^ (p[1] << 2);
Sergunb 0:8918a71cdbe9 629 k ^= (p[2] >> 2) ^ (p[2] << 4);
Sergunb 0:8918a71cdbe9 630 k ^= (p[3] >> 6) ^ p[3];
Sergunb 0:8918a71cdbe9 631 k ^= (p[4] >> 4) ^ (p[4] << 2);
Sergunb 0:8918a71cdbe9 632 k ^= (p[5] >> 2) ^ (p[5] << 4);
Sergunb 0:8918a71cdbe9 633
Sergunb 0:8918a71cdbe9 634 //The hash value is reduced to a 6-bit index
Sergunb 0:8918a71cdbe9 635 k &= 0x3F;
Sergunb 0:8918a71cdbe9 636
Sergunb 0:8918a71cdbe9 637 //Update hash table contents
Sergunb 0:8918a71cdbe9 638 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 639 }
Sergunb 0:8918a71cdbe9 640 }
Sergunb 0:8918a71cdbe9 641
Sergunb 0:8918a71cdbe9 642 //Write the hash table
Sergunb 0:8918a71cdbe9 643 XEMACPS_HASHL = hashTable[0];
Sergunb 0:8918a71cdbe9 644 XEMACPS_HASHH = hashTable[1];
Sergunb 0:8918a71cdbe9 645
Sergunb 0:8918a71cdbe9 646 //Debug message
Sergunb 0:8918a71cdbe9 647 TRACE_DEBUG(" HASHL = %08" PRIX32 "\r\n", XEMACPS_HASHL);
Sergunb 0:8918a71cdbe9 648 TRACE_DEBUG(" HASHH = %08" PRIX32 "\r\n", XEMACPS_HASHH);
Sergunb 0:8918a71cdbe9 649
Sergunb 0:8918a71cdbe9 650 //Successful processing
Sergunb 0:8918a71cdbe9 651 return NO_ERROR;
Sergunb 0:8918a71cdbe9 652 }
Sergunb 0:8918a71cdbe9 653
Sergunb 0:8918a71cdbe9 654
Sergunb 0:8918a71cdbe9 655 /**
Sergunb 0:8918a71cdbe9 656 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 657 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 658 * @return Error code
Sergunb 0:8918a71cdbe9 659 **/
Sergunb 0:8918a71cdbe9 660
Sergunb 0:8918a71cdbe9 661 error_t zynq7000EthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 662 {
Sergunb 0:8918a71cdbe9 663 uint32_t config;
Sergunb 0:8918a71cdbe9 664 uint32_t clockCtrl;
Sergunb 0:8918a71cdbe9 665
Sergunb 0:8918a71cdbe9 666 //Read network configuration register
Sergunb 0:8918a71cdbe9 667 config = XEMACPS_NWCFG;
Sergunb 0:8918a71cdbe9 668
Sergunb 0:8918a71cdbe9 669 //Read clock control register
Sergunb 0:8918a71cdbe9 670 clockCtrl = XSLCR_GEM0_CLK_CTRL;
Sergunb 0:8918a71cdbe9 671 clockCtrl &= ~(XSLCR_GEM0_CLK_CTRL_DIV1_MASK | XSLCR_GEM0_CLK_CTRL_DIV0_MASK);
Sergunb 0:8918a71cdbe9 672
Sergunb 0:8918a71cdbe9 673 //1000BASE-T operation mode?
Sergunb 0:8918a71cdbe9 674 if(interface->linkSpeed == NIC_LINK_SPEED_1GBPS)
Sergunb 0:8918a71cdbe9 675 {
Sergunb 0:8918a71cdbe9 676 //Update network configuration
Sergunb 0:8918a71cdbe9 677 config |= XEMACPS_NWCFG_1000_MASK;
Sergunb 0:8918a71cdbe9 678 config &= ~XEMACPS_NWCFG_100_MASK;
Sergunb 0:8918a71cdbe9 679
Sergunb 0:8918a71cdbe9 680 //Update clock configuration
Sergunb 0:8918a71cdbe9 681 clockCtrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 << 20) & XSLCR_GEM0_CLK_CTRL_DIV1_MASK;
Sergunb 0:8918a71cdbe9 682 clockCtrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 << 8) & XSLCR_GEM0_CLK_CTRL_DIV0_MASK;
Sergunb 0:8918a71cdbe9 683 }
Sergunb 0:8918a71cdbe9 684 //100BASE-TX operation mode?
Sergunb 0:8918a71cdbe9 685 else if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
Sergunb 0:8918a71cdbe9 686 {
Sergunb 0:8918a71cdbe9 687 //Update network configuration
Sergunb 0:8918a71cdbe9 688 config &= ~XEMACPS_NWCFG_1000_MASK;
Sergunb 0:8918a71cdbe9 689 config |= XEMACPS_NWCFG_100_MASK;
Sergunb 0:8918a71cdbe9 690
Sergunb 0:8918a71cdbe9 691 //Update clock configuration
Sergunb 0:8918a71cdbe9 692 clockCtrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 << 20) & XSLCR_GEM0_CLK_CTRL_DIV1_MASK;
Sergunb 0:8918a71cdbe9 693 clockCtrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 << 8) & XSLCR_GEM0_CLK_CTRL_DIV0_MASK;
Sergunb 0:8918a71cdbe9 694 }
Sergunb 0:8918a71cdbe9 695 //10BASE-T operation mode?
Sergunb 0:8918a71cdbe9 696 else
Sergunb 0:8918a71cdbe9 697 {
Sergunb 0:8918a71cdbe9 698 //Update network configuration
Sergunb 0:8918a71cdbe9 699 config &= ~XEMACPS_NWCFG_1000_MASK;
Sergunb 0:8918a71cdbe9 700 config &= ~XEMACPS_NWCFG_100_MASK;
Sergunb 0:8918a71cdbe9 701
Sergunb 0:8918a71cdbe9 702 //Update clock configuration
Sergunb 0:8918a71cdbe9 703 clockCtrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 << 20) & XSLCR_GEM0_CLK_CTRL_DIV1_MASK;
Sergunb 0:8918a71cdbe9 704 clockCtrl |= (XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 << 8) & XSLCR_GEM0_CLK_CTRL_DIV0_MASK;
Sergunb 0:8918a71cdbe9 705 }
Sergunb 0:8918a71cdbe9 706
Sergunb 0:8918a71cdbe9 707 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 708 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 709 config |= XEMACPS_NWCFG_FDEN_MASK;
Sergunb 0:8918a71cdbe9 710 else
Sergunb 0:8918a71cdbe9 711 config &= ~XEMACPS_NWCFG_FDEN_MASK;
Sergunb 0:8918a71cdbe9 712
Sergunb 0:8918a71cdbe9 713 //Write network configuration register
Sergunb 0:8918a71cdbe9 714 XEMACPS_NWCFG = config;
Sergunb 0:8918a71cdbe9 715
Sergunb 0:8918a71cdbe9 716 //Unlock SLCR
Sergunb 0:8918a71cdbe9 717 XSLCR_UNLOCK = XSLCR_UNLOCK_KEY_VALUE;
Sergunb 0:8918a71cdbe9 718 //Write clock control register
Sergunb 0:8918a71cdbe9 719 XSLCR_GEM0_CLK_CTRL = clockCtrl;
Sergunb 0:8918a71cdbe9 720 //Lock SLCR
Sergunb 0:8918a71cdbe9 721 XSLCR_LOCK = XSLCR_LOCK_KEY_VALUE;
Sergunb 0:8918a71cdbe9 722
Sergunb 0:8918a71cdbe9 723 //Successful processing
Sergunb 0:8918a71cdbe9 724 return NO_ERROR;
Sergunb 0:8918a71cdbe9 725 }
Sergunb 0:8918a71cdbe9 726
Sergunb 0:8918a71cdbe9 727
Sergunb 0:8918a71cdbe9 728 /**
Sergunb 0:8918a71cdbe9 729 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 730 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 731 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 732 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 733 **/
Sergunb 0:8918a71cdbe9 734
Sergunb 0:8918a71cdbe9 735 void zynq7000EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 736 {
Sergunb 0:8918a71cdbe9 737 uint32_t value;
Sergunb 0:8918a71cdbe9 738
Sergunb 0:8918a71cdbe9 739 //Set up a write operation
Sergunb 0:8918a71cdbe9 740 value = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_W_MASK;
Sergunb 0:8918a71cdbe9 741 //PHY address
Sergunb 0:8918a71cdbe9 742 value |= (phyAddr << 23) & XEMACPS_PHYMNTNC_ADDR_MASK;
Sergunb 0:8918a71cdbe9 743 //Register address
Sergunb 0:8918a71cdbe9 744 value |= (regAddr << 18) & XEMACPS_PHYMNTNC_REG_MASK;
Sergunb 0:8918a71cdbe9 745 //Register value
Sergunb 0:8918a71cdbe9 746 value |= data & XEMACPS_PHYMNTNC_DATA_MASK;
Sergunb 0:8918a71cdbe9 747
Sergunb 0:8918a71cdbe9 748 //Start a write operation
Sergunb 0:8918a71cdbe9 749 XEMACPS_PHYMNTNC = value;
Sergunb 0:8918a71cdbe9 750 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 751 while(!(XEMACPS_NWSR & XEMACPS_NWSR_MDIOIDLE_MASK));
Sergunb 0:8918a71cdbe9 752 }
Sergunb 0:8918a71cdbe9 753
Sergunb 0:8918a71cdbe9 754
Sergunb 0:8918a71cdbe9 755 /**
Sergunb 0:8918a71cdbe9 756 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 757 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 758 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 759 * @return Register value
Sergunb 0:8918a71cdbe9 760 **/
Sergunb 0:8918a71cdbe9 761
Sergunb 0:8918a71cdbe9 762 uint16_t zynq7000EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 763 {
Sergunb 0:8918a71cdbe9 764 uint32_t value;
Sergunb 0:8918a71cdbe9 765
Sergunb 0:8918a71cdbe9 766 //Set up a read operation
Sergunb 0:8918a71cdbe9 767 value = XEMACPS_PHYMNTNC_OP_MASK | XEMACPS_PHYMNTNC_OP_R_MASK;
Sergunb 0:8918a71cdbe9 768 //PHY address
Sergunb 0:8918a71cdbe9 769 value |= (phyAddr << 23) & XEMACPS_PHYMNTNC_ADDR_MASK;
Sergunb 0:8918a71cdbe9 770 //Register address
Sergunb 0:8918a71cdbe9 771 value |= (regAddr << 18) & XEMACPS_PHYMNTNC_REG_MASK;
Sergunb 0:8918a71cdbe9 772
Sergunb 0:8918a71cdbe9 773 //Start a read operation
Sergunb 0:8918a71cdbe9 774 XEMACPS_PHYMNTNC = value;
Sergunb 0:8918a71cdbe9 775 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 776 while(!(XEMACPS_NWSR & XEMACPS_NWSR_MDIOIDLE_MASK));
Sergunb 0:8918a71cdbe9 777
Sergunb 0:8918a71cdbe9 778 //Return PHY register contents
Sergunb 0:8918a71cdbe9 779 return XEMACPS_PHYMNTNC & XEMACPS_PHYMNTNC_DATA_MASK;
Sergunb 0:8918a71cdbe9 780 }
Sergunb 0:8918a71cdbe9 781