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cyclone_tcp/drivers/xmc4500_eth.h@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file xmc4500_eth.h
Sergunb 0:8918a71cdbe9 3 * @brief Infineon XMC4500 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 #ifndef _XMC4500_ETH_H
Sergunb 0:8918a71cdbe9 30 #define _XMC4500_ETH_H
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "core/nic.h"
Sergunb 0:8918a71cdbe9 34
Sergunb 0:8918a71cdbe9 35 //Number of TX buffers
Sergunb 0:8918a71cdbe9 36 #ifndef XMC4500_ETH_TX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 37 #define XMC4500_ETH_TX_BUFFER_COUNT 3
Sergunb 0:8918a71cdbe9 38 #elif (XMC4500_ETH_TX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 39 #error XMC4500_ETH_TX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 40 #endif
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //TX buffer size
Sergunb 0:8918a71cdbe9 43 #ifndef XMC4500_ETH_TX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 44 #define XMC4500_ETH_TX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 45 #elif (XMC4500_ETH_TX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 46 #error XMC4500_ETH_TX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 47 #endif
Sergunb 0:8918a71cdbe9 48
Sergunb 0:8918a71cdbe9 49 //Number of RX buffers
Sergunb 0:8918a71cdbe9 50 #ifndef XMC4500_ETH_RX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 51 #define XMC4500_ETH_RX_BUFFER_COUNT 6
Sergunb 0:8918a71cdbe9 52 #elif (XMC4500_ETH_RX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 53 #error XMC4500_ETH_RX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 54 #endif
Sergunb 0:8918a71cdbe9 55
Sergunb 0:8918a71cdbe9 56 //RX buffer size
Sergunb 0:8918a71cdbe9 57 #ifndef XMC4500_ETH_RX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 58 #define XMC4500_ETH_RX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 59 #elif (XMC4500_ETH_RX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 60 #error XMC4500_ETH_RX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 61 #endif
Sergunb 0:8918a71cdbe9 62
Sergunb 0:8918a71cdbe9 63 //Interrupt priority grouping
Sergunb 0:8918a71cdbe9 64 #ifndef XMC4500_ETH_IRQ_PRIORITY_GROUPING
Sergunb 0:8918a71cdbe9 65 #define XMC4500_ETH_IRQ_PRIORITY_GROUPING 1
Sergunb 0:8918a71cdbe9 66 #elif (XMC4500_ETH_IRQ_PRIORITY_GROUPING < 0)
Sergunb 0:8918a71cdbe9 67 #error XMC4500_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
Sergunb 0:8918a71cdbe9 68 #endif
Sergunb 0:8918a71cdbe9 69
Sergunb 0:8918a71cdbe9 70 //Ethernet interrupt group priority
Sergunb 0:8918a71cdbe9 71 #ifndef XMC4500_ETH_IRQ_GROUP_PRIORITY
Sergunb 0:8918a71cdbe9 72 #define XMC4500_ETH_IRQ_GROUP_PRIORITY 48
Sergunb 0:8918a71cdbe9 73 #elif (XMC4500_ETH_IRQ_GROUP_PRIORITY < 0)
Sergunb 0:8918a71cdbe9 74 #error XMC4500_ETH_IRQ_GROUP_PRIORITY parameter is not valid
Sergunb 0:8918a71cdbe9 75 #endif
Sergunb 0:8918a71cdbe9 76
Sergunb 0:8918a71cdbe9 77 //Ethernet interrupt subpriority
Sergunb 0:8918a71cdbe9 78 #ifndef XMC4500_ETH_IRQ_SUB_PRIORITY
Sergunb 0:8918a71cdbe9 79 #define XMC4500_ETH_IRQ_SUB_PRIORITY 0
Sergunb 0:8918a71cdbe9 80 #elif (XMC4500_ETH_IRQ_SUB_PRIORITY < 0)
Sergunb 0:8918a71cdbe9 81 #error XMC4500_ETH_IRQ_SUB_PRIORITY parameter is not valid
Sergunb 0:8918a71cdbe9 82 #endif
Sergunb 0:8918a71cdbe9 83
Sergunb 0:8918a71cdbe9 84 //ETH0_CON
Sergunb 0:8918a71cdbe9 85 #define ETH_CON_MDIO_A (0 << ETH_CON_MDIO_Pos)
Sergunb 0:8918a71cdbe9 86 #define ETH_CON_MDIO_B (1 << ETH_CON_MDIO_Pos)
Sergunb 0:8918a71cdbe9 87 #define ETH_CON_MDIO_C (2 << ETH_CON_MDIO_Pos)
Sergunb 0:8918a71cdbe9 88 #define ETH_CON_MDIO_D (3 << ETH_CON_MDIO_Pos)
Sergunb 0:8918a71cdbe9 89
Sergunb 0:8918a71cdbe9 90 #define ETH_CON_CLK_TX_A (0 << ETH_CON_CLK_TX_Pos)
Sergunb 0:8918a71cdbe9 91 #define ETH_CON_CLK_TX_B (1 << ETH_CON_CLK_TX_Pos)
Sergunb 0:8918a71cdbe9 92 #define ETH_CON_CLK_TX_C (2 << ETH_CON_CLK_TX_Pos)
Sergunb 0:8918a71cdbe9 93 #define ETH_CON_CLK_TX_D (3 << ETH_CON_CLK_TX_Pos)
Sergunb 0:8918a71cdbe9 94
Sergunb 0:8918a71cdbe9 95 #define ETH_CON_COL_A (0 << ETH_CON_COL_Pos)
Sergunb 0:8918a71cdbe9 96 #define ETH_CON_COL_B (1 << ETH_CON_COL_Pos)
Sergunb 0:8918a71cdbe9 97 #define ETH_CON_COL_C (2 << ETH_CON_COL_Pos)
Sergunb 0:8918a71cdbe9 98 #define ETH_CON_COL_D (3 << ETH_CON_COL_Pos)
Sergunb 0:8918a71cdbe9 99
Sergunb 0:8918a71cdbe9 100 #define ETH_CON_RXER_A (0 << ETH_CON_RXER_Pos)
Sergunb 0:8918a71cdbe9 101 #define ETH_CON_RXER_B (1 << ETH_CON_RXER_Pos)
Sergunb 0:8918a71cdbe9 102 #define ETH_CON_RXER_C (2 << ETH_CON_RXER_Pos)
Sergunb 0:8918a71cdbe9 103 #define ETH_CON_RXER_D (3 << ETH_CON_RXER_Pos)
Sergunb 0:8918a71cdbe9 104
Sergunb 0:8918a71cdbe9 105 #define ETH_CON_CRS_A (0 << ETH_CON_CRS_Pos)
Sergunb 0:8918a71cdbe9 106 #define ETH_CON_CRS_B (1 << ETH_CON_CRS_Pos)
Sergunb 0:8918a71cdbe9 107 #define ETH_CON_CRS_C (2 << ETH_CON_CRS_Pos)
Sergunb 0:8918a71cdbe9 108 #define ETH_CON_CRS_D (3 << ETH_CON_CRS_Pos)
Sergunb 0:8918a71cdbe9 109
Sergunb 0:8918a71cdbe9 110 #define ETH_CON_CRS_DV_A (0 << ETH_CON_CRS_DV_Pos)
Sergunb 0:8918a71cdbe9 111 #define ETH_CON_CRS_DV_B (1 << ETH_CON_CRS_DV_Pos)
Sergunb 0:8918a71cdbe9 112 #define ETH_CON_CRS_DV_C (2 << ETH_CON_CRS_DV_Pos)
Sergunb 0:8918a71cdbe9 113 #define ETH_CON_CRS_DV_D (3 << ETH_CON_CRS_DV_Pos)
Sergunb 0:8918a71cdbe9 114
Sergunb 0:8918a71cdbe9 115 #define ETH_CON_CLK_RMII_A (0 << ETH_CON_CLK_RMII_Pos)
Sergunb 0:8918a71cdbe9 116 #define ETH_CON_CLK_RMII_B (1 << ETH_CON_CLK_RMII_Pos)
Sergunb 0:8918a71cdbe9 117 #define ETH_CON_CLK_RMII_C (2 << ETH_CON_CLK_RMII_Pos)
Sergunb 0:8918a71cdbe9 118 #define ETH_CON_CLK_RMII_D (3 << ETH_CON_CLK_RMII_Pos)
Sergunb 0:8918a71cdbe9 119
Sergunb 0:8918a71cdbe9 120 #define ETH_CON_RXD3_A (0 << ETH_CON_RXD3_Pos)
Sergunb 0:8918a71cdbe9 121 #define ETH_CON_RXD3_B (1 << ETH_CON_RXD3_Pos)
Sergunb 0:8918a71cdbe9 122 #define ETH_CON_RXD3_C (2 << ETH_CON_RXD3_Pos)
Sergunb 0:8918a71cdbe9 123 #define ETH_CON_RXD3_D (3 << ETH_CON_RXD3_Pos)
Sergunb 0:8918a71cdbe9 124
Sergunb 0:8918a71cdbe9 125 #define ETH_CON_RXD2_A (0 << ETH_CON_RXD2_Pos)
Sergunb 0:8918a71cdbe9 126 #define ETH_CON_RXD2_B (1 << ETH_CON_RXD2_Pos)
Sergunb 0:8918a71cdbe9 127 #define ETH_CON_RXD2_C (2 << ETH_CON_RXD2_Pos)
Sergunb 0:8918a71cdbe9 128 #define ETH_CON_RXD2_D (3 << ETH_CON_RXD2_Pos)
Sergunb 0:8918a71cdbe9 129
Sergunb 0:8918a71cdbe9 130 #define ETH_CON_RXD1_A (0 << ETH_CON_RXD1_Pos)
Sergunb 0:8918a71cdbe9 131 #define ETH_CON_RXD1_B (1 << ETH_CON_RXD1_Pos)
Sergunb 0:8918a71cdbe9 132 #define ETH_CON_RXD1_C (2 << ETH_CON_RXD1_Pos)
Sergunb 0:8918a71cdbe9 133 #define ETH_CON_RXD1_D (3 << ETH_CON_RXD1_Pos)
Sergunb 0:8918a71cdbe9 134
Sergunb 0:8918a71cdbe9 135 #define ETH_CON_RXD0_A (0 << ETH_CON_RXD0_Pos)
Sergunb 0:8918a71cdbe9 136 #define ETH_CON_RXD0_B (1 << ETH_CON_RXD0_Pos)
Sergunb 0:8918a71cdbe9 137 #define ETH_CON_RXD0_C (2 << ETH_CON_RXD0_Pos)
Sergunb 0:8918a71cdbe9 138 #define ETH_CON_RXD0_D (3 << ETH_CON_RXD0_Pos)
Sergunb 0:8918a71cdbe9 139
Sergunb 0:8918a71cdbe9 140 //ETH0_MAC_CONFIGURATION register
Sergunb 0:8918a71cdbe9 141 #define ETH_MAC_CONFIGURATION_RESERVED15_Msk (1 << 15)
Sergunb 0:8918a71cdbe9 142
Sergunb 0:8918a71cdbe9 143 //ETH0_GMII_ADDRESS register
Sergunb 0:8918a71cdbe9 144 #define ETH_GMII_ADDRESS_CR_DIV42 (0 << ETH_GMII_ADDRESS_CR_Pos)
Sergunb 0:8918a71cdbe9 145 #define ETH_GMII_ADDRESS_CR_DIV62 (1 << ETH_GMII_ADDRESS_CR_Pos)
Sergunb 0:8918a71cdbe9 146 #define ETH_GMII_ADDRESS_CR_DIV16 (2 << ETH_GMII_ADDRESS_CR_Pos)
Sergunb 0:8918a71cdbe9 147 #define ETH_GMII_ADDRESS_CR_DIV26 (3 << ETH_GMII_ADDRESS_CR_Pos)
Sergunb 0:8918a71cdbe9 148 #define ETH_GMII_ADDRESS_CR_DIV102 (4 << ETH_GMII_ADDRESS_CR_Pos)
Sergunb 0:8918a71cdbe9 149 #define ETH_GMII_ADDRESS_CR_DIV124 (5 << ETH_GMII_ADDRESS_CR_Pos)
Sergunb 0:8918a71cdbe9 150
Sergunb 0:8918a71cdbe9 151 //ETH0_BUS_MODE register
Sergunb 0:8918a71cdbe9 152 #define ETH_BUS_MODE_RPBL_1 (1 << ETH_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 153 #define ETH_BUS_MODE_RPBL_2 (2 << ETH_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 154 #define ETH_BUS_MODE_RPBL_4 (4 << ETH_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 155 #define ETH_BUS_MODE_RPBL_8 (8 << ETH_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 156 #define ETH_BUS_MODE_RPBL_16 (16 << ETH_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 157 #define ETH_BUS_MODE_RPBL_32 (32 << ETH_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 158
Sergunb 0:8918a71cdbe9 159 #define ETH_BUS_MODE_PR_1_1 (0 << ETH_BUS_MODE_PR_Pos)
Sergunb 0:8918a71cdbe9 160 #define ETH_BUS_MODE_PR_2_1 (1 << ETH_BUS_MODE_PR_Pos)
Sergunb 0:8918a71cdbe9 161 #define ETH_BUS_MODE_PR_3_1 (2 << ETH_BUS_MODE_PR_Pos)
Sergunb 0:8918a71cdbe9 162 #define ETH_BUS_MODE_PR_4_1 (3 << ETH_BUS_MODE_PR_Pos)
Sergunb 0:8918a71cdbe9 163
Sergunb 0:8918a71cdbe9 164 #define ETH_BUS_MODE_PBL_1 (1 << ETH_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 165 #define ETH_BUS_MODE_PBL_2 (2 << ETH_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 166 #define ETH_BUS_MODE_PBL_4 (4 << ETH_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 167 #define ETH_BUS_MODE_PBL_8 (8 << ETH_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 168 #define ETH_BUS_MODE_PBL_16 (16 << ETH_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 169 #define ETH_BUS_MODE_PBL_32 (32 << ETH_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 170
Sergunb 0:8918a71cdbe9 171 //Transmit DMA descriptor flags
Sergunb 0:8918a71cdbe9 172 #define ETH_TDES0_OWN 0x80000000
Sergunb 0:8918a71cdbe9 173 #define ETH_TDES0_IC 0x40000000
Sergunb 0:8918a71cdbe9 174 #define ETH_TDES0_LS 0x20000000
Sergunb 0:8918a71cdbe9 175 #define ETH_TDES0_FS 0x10000000
Sergunb 0:8918a71cdbe9 176 #define ETH_TDES0_DC 0x08000000
Sergunb 0:8918a71cdbe9 177 #define ETH_TDES0_DP 0x04000000
Sergunb 0:8918a71cdbe9 178 #define ETH_TDES0_TTSE 0x02000000
Sergunb 0:8918a71cdbe9 179 #define ETH_TDES0_CIC 0x00C00000
Sergunb 0:8918a71cdbe9 180 #define ETH_TDES0_TER 0x00200000
Sergunb 0:8918a71cdbe9 181 #define ETH_TDES0_TCH 0x00100000
Sergunb 0:8918a71cdbe9 182 #define ETH_TDES0_TTSS 0x00020000
Sergunb 0:8918a71cdbe9 183 #define ETH_TDES0_IHE 0x00010000
Sergunb 0:8918a71cdbe9 184 #define ETH_TDES0_ES 0x00008000
Sergunb 0:8918a71cdbe9 185 #define ETH_TDES0_JT 0x00004000
Sergunb 0:8918a71cdbe9 186 #define ETH_TDES0_FF 0x00002000
Sergunb 0:8918a71cdbe9 187 #define ETH_TDES0_IPE 0x00001000
Sergunb 0:8918a71cdbe9 188 #define ETH_TDES0_LCA 0x00000800
Sergunb 0:8918a71cdbe9 189 #define ETH_TDES0_NC 0x00000400
Sergunb 0:8918a71cdbe9 190 #define ETH_TDES0_LCO 0x00000200
Sergunb 0:8918a71cdbe9 191 #define ETH_TDES0_EC 0x00000100
Sergunb 0:8918a71cdbe9 192 #define ETH_TDES0_VF 0x00000080
Sergunb 0:8918a71cdbe9 193 #define ETH_TDES0_CC 0x00000078
Sergunb 0:8918a71cdbe9 194 #define ETH_TDES0_ED 0x00000004
Sergunb 0:8918a71cdbe9 195 #define ETH_TDES0_UF 0x00000002
Sergunb 0:8918a71cdbe9 196 #define ETH_TDES0_DB 0x00000001
Sergunb 0:8918a71cdbe9 197 #define ETH_TDES1_TBS2 0x1FFF0000
Sergunb 0:8918a71cdbe9 198 #define ETH_TDES1_TBS1 0x00001FFF
Sergunb 0:8918a71cdbe9 199 #define ETH_TDES2_TBAP1 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 200 #define ETH_TDES3_TBAP2 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 201
Sergunb 0:8918a71cdbe9 202 //Receive DMA descriptor flags
Sergunb 0:8918a71cdbe9 203 #define ETH_RDES0_OWN 0x80000000
Sergunb 0:8918a71cdbe9 204 #define ETH_RDES0_AFM 0x40000000
Sergunb 0:8918a71cdbe9 205 #define ETH_RDES0_FL 0x3FFF0000
Sergunb 0:8918a71cdbe9 206 #define ETH_RDES0_ES 0x00008000
Sergunb 0:8918a71cdbe9 207 #define ETH_RDES0_DE 0x00004000
Sergunb 0:8918a71cdbe9 208 #define ETH_RDES0_SAF 0x00002000
Sergunb 0:8918a71cdbe9 209 #define ETH_RDES0_LE 0x00001000
Sergunb 0:8918a71cdbe9 210 #define ETH_RDES0_OE 0x00000800
Sergunb 0:8918a71cdbe9 211 #define ETH_RDES0_VLAN 0x00000400
Sergunb 0:8918a71cdbe9 212 #define ETH_RDES0_FS 0x00000200
Sergunb 0:8918a71cdbe9 213 #define ETH_RDES0_LS 0x00000100
Sergunb 0:8918a71cdbe9 214 #define ETH_RDES0_IPCE_GF 0x00000080
Sergunb 0:8918a71cdbe9 215 #define ETH_RDES0_LCO 0x00000040
Sergunb 0:8918a71cdbe9 216 #define ETH_RDES0_FT 0x00000020
Sergunb 0:8918a71cdbe9 217 #define ETH_RDES0_RWT 0x00000010
Sergunb 0:8918a71cdbe9 218 #define ETH_RDES0_RE 0x00000008
Sergunb 0:8918a71cdbe9 219 #define ETH_RDES0_DBE 0x00000004
Sergunb 0:8918a71cdbe9 220 #define ETH_RDES0_CE 0x00000002
Sergunb 0:8918a71cdbe9 221 #define ETH_RDES0_PCE 0x00000001
Sergunb 0:8918a71cdbe9 222 #define ETH_RDES1_DIC 0x80000000
Sergunb 0:8918a71cdbe9 223 #define ETH_RDES1_RBS2 0x1FFF0000
Sergunb 0:8918a71cdbe9 224 #define ETH_RDES1_RER 0x00008000
Sergunb 0:8918a71cdbe9 225 #define ETH_RDES1_RCH 0x00004000
Sergunb 0:8918a71cdbe9 226 #define ETH_RDES1_RBS1 0x00001FFF
Sergunb 0:8918a71cdbe9 227 #define ETH_RDES2_RBAP1 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 228 #define ETH_RDES3_RBAP2 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 229
Sergunb 0:8918a71cdbe9 230
Sergunb 0:8918a71cdbe9 231 /**
Sergunb 0:8918a71cdbe9 232 * @brief Transmit DMA descriptor
Sergunb 0:8918a71cdbe9 233 **/
Sergunb 0:8918a71cdbe9 234
Sergunb 0:8918a71cdbe9 235 typedef struct
Sergunb 0:8918a71cdbe9 236 {
Sergunb 0:8918a71cdbe9 237 uint32_t tdes0;
Sergunb 0:8918a71cdbe9 238 uint32_t tdes1;
Sergunb 0:8918a71cdbe9 239 uint32_t tdes2;
Sergunb 0:8918a71cdbe9 240 uint32_t tdes3;
Sergunb 0:8918a71cdbe9 241 } Xmc4500TxDmaDesc;
Sergunb 0:8918a71cdbe9 242
Sergunb 0:8918a71cdbe9 243
Sergunb 0:8918a71cdbe9 244 /**
Sergunb 0:8918a71cdbe9 245 * @brief Receive DMA descriptor
Sergunb 0:8918a71cdbe9 246 **/
Sergunb 0:8918a71cdbe9 247
Sergunb 0:8918a71cdbe9 248 typedef struct
Sergunb 0:8918a71cdbe9 249 {
Sergunb 0:8918a71cdbe9 250 uint32_t rdes0;
Sergunb 0:8918a71cdbe9 251 uint32_t rdes1;
Sergunb 0:8918a71cdbe9 252 uint32_t rdes2;
Sergunb 0:8918a71cdbe9 253 uint32_t rdes3;
Sergunb 0:8918a71cdbe9 254 } Xmc4500RxDmaDesc;
Sergunb 0:8918a71cdbe9 255
Sergunb 0:8918a71cdbe9 256
Sergunb 0:8918a71cdbe9 257 //XMC4500 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 258 extern const NicDriver xmc4500EthDriver;
Sergunb 0:8918a71cdbe9 259
Sergunb 0:8918a71cdbe9 260 //XMC4500 Ethernet MAC related functions
Sergunb 0:8918a71cdbe9 261 error_t xmc4500EthInit(NetInterface *interface);
Sergunb 0:8918a71cdbe9 262 void xmc4500EthInitGpio(NetInterface *interface);
Sergunb 0:8918a71cdbe9 263 void xmc4500EthInitDmaDesc(NetInterface *interface);
Sergunb 0:8918a71cdbe9 264
Sergunb 0:8918a71cdbe9 265 void xmc4500EthTick(NetInterface *interface);
Sergunb 0:8918a71cdbe9 266
Sergunb 0:8918a71cdbe9 267 void xmc4500EthEnableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 268 void xmc4500EthDisableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 269 void xmc4500EthEventHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 270
Sergunb 0:8918a71cdbe9 271 error_t xmc4500EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 272 const NetBuffer *buffer, size_t offset);
Sergunb 0:8918a71cdbe9 273
Sergunb 0:8918a71cdbe9 274 error_t xmc4500EthReceivePacket(NetInterface *interface);
Sergunb 0:8918a71cdbe9 275
Sergunb 0:8918a71cdbe9 276 error_t xmc4500EthSetMulticastFilter(NetInterface *interface);
Sergunb 0:8918a71cdbe9 277 error_t xmc4500EthUpdateMacConfig(NetInterface *interface);
Sergunb 0:8918a71cdbe9 278
Sergunb 0:8918a71cdbe9 279 void xmc4500EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
Sergunb 0:8918a71cdbe9 280 uint16_t xmc4500EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
Sergunb 0:8918a71cdbe9 281
Sergunb 0:8918a71cdbe9 282 uint32_t xmc4500EthCalcCrc(const void *data, size_t length);
Sergunb 0:8918a71cdbe9 283
Sergunb 0:8918a71cdbe9 284 #endif
Sergunb 0:8918a71cdbe9 285