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cyclone_tcp/drivers/tm4c129_eth.h@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

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Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file tm4c129_eth.h
Sergunb 0:8918a71cdbe9 3 * @brief Tiva TM4C129 Ethernet controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 #ifndef _TM4C129_ETH_H
Sergunb 0:8918a71cdbe9 30 #define _TM4C129_ETH_H
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "core/nic.h"
Sergunb 0:8918a71cdbe9 34
Sergunb 0:8918a71cdbe9 35 //Number of TX buffers
Sergunb 0:8918a71cdbe9 36 #ifndef TM4C129_ETH_TX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 37 #define TM4C129_ETH_TX_BUFFER_COUNT 3
Sergunb 0:8918a71cdbe9 38 #elif (TM4C129_ETH_TX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 39 #error TM4C129_ETH_TX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 40 #endif
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //TX buffer size
Sergunb 0:8918a71cdbe9 43 #ifndef TM4C129_ETH_TX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 44 #define TM4C129_ETH_TX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 45 #elif (TM4C129_ETH_TX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 46 #error TM4C129_ETH_TX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 47 #endif
Sergunb 0:8918a71cdbe9 48
Sergunb 0:8918a71cdbe9 49 //Number of RX buffers
Sergunb 0:8918a71cdbe9 50 #ifndef TM4C129_ETH_RX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 51 #define TM4C129_ETH_RX_BUFFER_COUNT 6
Sergunb 0:8918a71cdbe9 52 #elif (TM4C129_ETH_RX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 53 #error TM4C129_ETH_RX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 54 #endif
Sergunb 0:8918a71cdbe9 55
Sergunb 0:8918a71cdbe9 56 //RX buffer size
Sergunb 0:8918a71cdbe9 57 #ifndef TM4C129_ETH_RX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 58 #define TM4C129_ETH_RX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 59 #elif (TM4C129_ETH_RX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 60 #error TM4C129_ETH_RX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 61 #endif
Sergunb 0:8918a71cdbe9 62
Sergunb 0:8918a71cdbe9 63 //Interrupt priority grouping
Sergunb 0:8918a71cdbe9 64 #ifndef TM4C129_ETH_IRQ_PRIORITY_GROUPING
Sergunb 0:8918a71cdbe9 65 #define TM4C129_ETH_IRQ_PRIORITY_GROUPING 3
Sergunb 0:8918a71cdbe9 66 #elif (TM4C129_ETH_IRQ_PRIORITY_GROUPING < 0)
Sergunb 0:8918a71cdbe9 67 #error TM4C129_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
Sergunb 0:8918a71cdbe9 68 #endif
Sergunb 0:8918a71cdbe9 69
Sergunb 0:8918a71cdbe9 70 //Ethernet interrupt priority
Sergunb 0:8918a71cdbe9 71 #ifndef TM4C129_ETH_IRQ_PRIORITY
Sergunb 0:8918a71cdbe9 72 #define TM4C129_ETH_IRQ_PRIORITY 192
Sergunb 0:8918a71cdbe9 73 #elif (TM4C129_ETH_IRQ_PRIORITY < 0)
Sergunb 0:8918a71cdbe9 74 #error TM4C129_ETH_IRQ_PRIORITY parameter is not valid
Sergunb 0:8918a71cdbe9 75 #endif
Sergunb 0:8918a71cdbe9 76
Sergunb 0:8918a71cdbe9 77 //DMABUSMOD register
Sergunb 0:8918a71cdbe9 78 #define EMAC_DMABUSMOD_RPBL_1 (1 << EMAC_DMABUSMOD_RPBL_S)
Sergunb 0:8918a71cdbe9 79 #define EMAC_DMABUSMOD_RPBL_2 (2 << EMAC_DMABUSMOD_RPBL_S)
Sergunb 0:8918a71cdbe9 80 #define EMAC_DMABUSMOD_RPBL_4 (4 << EMAC_DMABUSMOD_RPBL_S)
Sergunb 0:8918a71cdbe9 81 #define EMAC_DMABUSMOD_RPBL_8 (8 << EMAC_DMABUSMOD_RPBL_S)
Sergunb 0:8918a71cdbe9 82 #define EMAC_DMABUSMOD_RPBL_16 (16 << EMAC_DMABUSMOD_RPBL_S)
Sergunb 0:8918a71cdbe9 83 #define EMAC_DMABUSMOD_RPBL_32 (32 << EMAC_DMABUSMOD_RPBL_S)
Sergunb 0:8918a71cdbe9 84
Sergunb 0:8918a71cdbe9 85 #define EMAC_DMABUSMOD_PR_1_1 (0 << EMAC_DMABUSMOD_PR_S)
Sergunb 0:8918a71cdbe9 86 #define EMAC_DMABUSMOD_PR_2_1 (1 << EMAC_DMABUSMOD_PR_S)
Sergunb 0:8918a71cdbe9 87 #define EMAC_DMABUSMOD_PR_3_1 (2 << EMAC_DMABUSMOD_PR_S)
Sergunb 0:8918a71cdbe9 88 #define EMAC_DMABUSMOD_PR_4_1 (3 << EMAC_DMABUSMOD_PR_S)
Sergunb 0:8918a71cdbe9 89
Sergunb 0:8918a71cdbe9 90 #define EMAC_DMABUSMOD_PBL_1 (1 << EMAC_DMABUSMOD_PBL_S)
Sergunb 0:8918a71cdbe9 91 #define EMAC_DMABUSMOD_PBL_2 (2 << EMAC_DMABUSMOD_PBL_S)
Sergunb 0:8918a71cdbe9 92 #define EMAC_DMABUSMOD_PBL_4 (4 << EMAC_DMABUSMOD_PBL_S)
Sergunb 0:8918a71cdbe9 93 #define EMAC_DMABUSMOD_PBL_8 (8 << EMAC_DMABUSMOD_PBL_S)
Sergunb 0:8918a71cdbe9 94 #define EMAC_DMABUSMOD_PBL_16 (16 << EMAC_DMABUSMOD_PBL_S)
Sergunb 0:8918a71cdbe9 95 #define EMAC_DMABUSMOD_PBL_32 (32 << EMAC_DMABUSMOD_PBL_S)
Sergunb 0:8918a71cdbe9 96
Sergunb 0:8918a71cdbe9 97 //Transmit DMA descriptor flags
Sergunb 0:8918a71cdbe9 98 #define EMAC_TDES0_OWN 0x80000000
Sergunb 0:8918a71cdbe9 99 #define EMAC_TDES0_IC 0x40000000
Sergunb 0:8918a71cdbe9 100 #define EMAC_TDES0_LS 0x20000000
Sergunb 0:8918a71cdbe9 101 #define EMAC_TDES0_FS 0x10000000
Sergunb 0:8918a71cdbe9 102 #define EMAC_TDES0_DC 0x08000000
Sergunb 0:8918a71cdbe9 103 #define EMAC_TDES0_DP 0x04000000
Sergunb 0:8918a71cdbe9 104 #define EMAC_TDES0_TTSE 0x02000000
Sergunb 0:8918a71cdbe9 105 #define EMAC_TDES0_CRCR 0x01000000
Sergunb 0:8918a71cdbe9 106 #define EMAC_TDES0_CIC 0x00C00000
Sergunb 0:8918a71cdbe9 107 #define EMAC_TDES0_TER 0x00200000
Sergunb 0:8918a71cdbe9 108 #define EMAC_TDES0_TCH 0x00100000
Sergunb 0:8918a71cdbe9 109 #define EMAC_TDES0_VLIC 0x000C0000
Sergunb 0:8918a71cdbe9 110 #define EMAC_TDES0_TTSS 0x00020000
Sergunb 0:8918a71cdbe9 111 #define EMAC_TDES0_IHE 0x00010000
Sergunb 0:8918a71cdbe9 112 #define EMAC_TDES0_ES 0x00008000
Sergunb 0:8918a71cdbe9 113 #define EMAC_TDES0_JT 0x00004000
Sergunb 0:8918a71cdbe9 114 #define EMAC_TDES0_FF 0x00002000
Sergunb 0:8918a71cdbe9 115 #define EMAC_TDES0_IPE 0x00001000
Sergunb 0:8918a71cdbe9 116 #define EMAC_TDES0_LCA 0x00000800
Sergunb 0:8918a71cdbe9 117 #define EMAC_TDES0_NC 0x00000400
Sergunb 0:8918a71cdbe9 118 #define EMAC_TDES0_LCO 0x00000200
Sergunb 0:8918a71cdbe9 119 #define EMAC_TDES0_EC 0x00000100
Sergunb 0:8918a71cdbe9 120 #define EMAC_TDES0_VF 0x00000080
Sergunb 0:8918a71cdbe9 121 #define EMAC_TDES0_CC 0x00000078
Sergunb 0:8918a71cdbe9 122 #define EMAC_TDES0_ED 0x00000004
Sergunb 0:8918a71cdbe9 123 #define EMAC_TDES0_UF 0x00000002
Sergunb 0:8918a71cdbe9 124 #define EMAC_TDES0_DB 0x00000001
Sergunb 0:8918a71cdbe9 125 #define EMAC_TDES1_SAIC 0xE0000000
Sergunb 0:8918a71cdbe9 126 #define EMAC_TDES1_TBS2 0x1FFF0000
Sergunb 0:8918a71cdbe9 127 #define EMAC_TDES1_TBS1 0x00001FFF
Sergunb 0:8918a71cdbe9 128 #define EMAC_TDES2_TBAP1 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 129 #define EMAC_TDES3_TBAP2 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 130 #define EMAC_TDES6_TTSL 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 131 #define EMAC_TDES7_TTSH 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 132
Sergunb 0:8918a71cdbe9 133 //Receive DMA descriptor flags
Sergunb 0:8918a71cdbe9 134 #define EMAC_RDES0_OWN 0x80000000
Sergunb 0:8918a71cdbe9 135 #define EMAC_RDES0_AFM 0x40000000
Sergunb 0:8918a71cdbe9 136 #define EMAC_RDES0_FL 0x3FFF0000
Sergunb 0:8918a71cdbe9 137 #define EMAC_RDES0_ES 0x00008000
Sergunb 0:8918a71cdbe9 138 #define EMAC_RDES0_DE 0x00004000
Sergunb 0:8918a71cdbe9 139 #define EMAC_RDES0_SAF 0x00002000
Sergunb 0:8918a71cdbe9 140 #define EMAC_RDES0_LE 0x00001000
Sergunb 0:8918a71cdbe9 141 #define EMAC_RDES0_OE 0x00000800
Sergunb 0:8918a71cdbe9 142 #define EMAC_RDES0_VLAN 0x00000400
Sergunb 0:8918a71cdbe9 143 #define EMAC_RDES0_FS 0x00000200
Sergunb 0:8918a71cdbe9 144 #define EMAC_RDES0_LS 0x00000100
Sergunb 0:8918a71cdbe9 145 #define EMAC_RDES0_TSA_GF 0x00000080
Sergunb 0:8918a71cdbe9 146 #define EMAC_RDES0_LCO 0x00000040
Sergunb 0:8918a71cdbe9 147 #define EMAC_RDES0_FT 0x00000020
Sergunb 0:8918a71cdbe9 148 #define EMAC_RDES0_RWT 0x00000010
Sergunb 0:8918a71cdbe9 149 #define EMAC_RDES0_RE 0x00000008
Sergunb 0:8918a71cdbe9 150 #define EMAC_RDES0_DBE 0x00000004
Sergunb 0:8918a71cdbe9 151 #define EMAC_RDES0_CE 0x00000002
Sergunb 0:8918a71cdbe9 152 #define EMAC_RDES0_ESA 0x00000001
Sergunb 0:8918a71cdbe9 153 #define EMAC_RDES1_DIC 0x80000000
Sergunb 0:8918a71cdbe9 154 #define EMAC_RDES1_RBS2 0x1FFF0000
Sergunb 0:8918a71cdbe9 155 #define EMAC_RDES1_RER 0x00008000
Sergunb 0:8918a71cdbe9 156 #define EMAC_RDES1_RCH 0x00004000
Sergunb 0:8918a71cdbe9 157 #define EMAC_RDES1_RBS1 0x00001FFF
Sergunb 0:8918a71cdbe9 158 #define EMAC_RDES2_RBAP1 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 159 #define EMAC_RDES3_RBAP2 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 160 #define EMAC_RDES4_TSD 0x00004000
Sergunb 0:8918a71cdbe9 161 #define EMAC_RDES4_PV 0x00002000
Sergunb 0:8918a71cdbe9 162 #define EMAC_RDES4_PFT 0x00001000
Sergunb 0:8918a71cdbe9 163 #define EMAC_RDES4_PMT 0x00000F00
Sergunb 0:8918a71cdbe9 164 #define EMAC_RDES4_IPV6PR 0x00000080
Sergunb 0:8918a71cdbe9 165 #define EMAC_RDES4_IPV4PR 0x00000040
Sergunb 0:8918a71cdbe9 166 #define EMAC_RDES4_IPCB 0x00000020
Sergunb 0:8918a71cdbe9 167 #define EMAC_RDES4_IPPE 0x00000010
Sergunb 0:8918a71cdbe9 168 #define EMAC_RDES4_IPHE 0x00000008
Sergunb 0:8918a71cdbe9 169 #define EMAC_RDES4_IPPT 0x00000007
Sergunb 0:8918a71cdbe9 170 #define EMAC_RDES6_RTSL 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 171 #define EMAC_RDES7_RTSH 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 172
Sergunb 0:8918a71cdbe9 173
Sergunb 0:8918a71cdbe9 174 /**
Sergunb 0:8918a71cdbe9 175 * @brief Enhanced TX DMA descriptor
Sergunb 0:8918a71cdbe9 176 **/
Sergunb 0:8918a71cdbe9 177
Sergunb 0:8918a71cdbe9 178 typedef struct
Sergunb 0:8918a71cdbe9 179 {
Sergunb 0:8918a71cdbe9 180 uint32_t tdes0;
Sergunb 0:8918a71cdbe9 181 uint32_t tdes1;
Sergunb 0:8918a71cdbe9 182 uint32_t tdes2;
Sergunb 0:8918a71cdbe9 183 uint32_t tdes3;
Sergunb 0:8918a71cdbe9 184 uint32_t tdes4;
Sergunb 0:8918a71cdbe9 185 uint32_t tdes5;
Sergunb 0:8918a71cdbe9 186 uint32_t tdes6;
Sergunb 0:8918a71cdbe9 187 uint32_t tdes7;
Sergunb 0:8918a71cdbe9 188 } Tm4c129TxDmaDesc;
Sergunb 0:8918a71cdbe9 189
Sergunb 0:8918a71cdbe9 190
Sergunb 0:8918a71cdbe9 191 /**
Sergunb 0:8918a71cdbe9 192 * @brief Enhanced RX DMA descriptor
Sergunb 0:8918a71cdbe9 193 **/
Sergunb 0:8918a71cdbe9 194
Sergunb 0:8918a71cdbe9 195 typedef struct
Sergunb 0:8918a71cdbe9 196 {
Sergunb 0:8918a71cdbe9 197 uint32_t rdes0;
Sergunb 0:8918a71cdbe9 198 uint32_t rdes1;
Sergunb 0:8918a71cdbe9 199 uint32_t rdes2;
Sergunb 0:8918a71cdbe9 200 uint32_t rdes3;
Sergunb 0:8918a71cdbe9 201 uint32_t rdes4;
Sergunb 0:8918a71cdbe9 202 uint32_t rdes5;
Sergunb 0:8918a71cdbe9 203 uint32_t rdes6;
Sergunb 0:8918a71cdbe9 204 uint32_t rdes7;
Sergunb 0:8918a71cdbe9 205 } Tm4c129RxDmaDesc;
Sergunb 0:8918a71cdbe9 206
Sergunb 0:8918a71cdbe9 207
Sergunb 0:8918a71cdbe9 208 //TM4C129 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 209 extern const NicDriver tm4c129EthDriver;
Sergunb 0:8918a71cdbe9 210
Sergunb 0:8918a71cdbe9 211 //TM4C129 Ethernet MAC related functions
Sergunb 0:8918a71cdbe9 212 error_t tm4c129EthInit(NetInterface *interface);
Sergunb 0:8918a71cdbe9 213 void tm4c129EthInitGpio(NetInterface *interface);
Sergunb 0:8918a71cdbe9 214 void tm4c129EthInitDmaDesc(NetInterface *interface);
Sergunb 0:8918a71cdbe9 215
Sergunb 0:8918a71cdbe9 216 void tm4c129EthTick(NetInterface *interface);
Sergunb 0:8918a71cdbe9 217
Sergunb 0:8918a71cdbe9 218 void tm4c129EthEnableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 219 void tm4c129EthDisableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 220 void tm4c129EthEventHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 221
Sergunb 0:8918a71cdbe9 222 error_t tm4c129EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 223 const NetBuffer *buffer, size_t offset);
Sergunb 0:8918a71cdbe9 224
Sergunb 0:8918a71cdbe9 225 error_t tm4c129EthReceivePacket(NetInterface *interface);
Sergunb 0:8918a71cdbe9 226
Sergunb 0:8918a71cdbe9 227 error_t tm4c129EthSetMulticastFilter(NetInterface *interface);
Sergunb 0:8918a71cdbe9 228
Sergunb 0:8918a71cdbe9 229 void tm4c129EthWritePhyReg(uint8_t regAddr, uint16_t data);
Sergunb 0:8918a71cdbe9 230 uint16_t tm4c129EthReadPhyReg(uint8_t regAddr);
Sergunb 0:8918a71cdbe9 231 void tm4c129EthDumpPhyReg(void);
Sergunb 0:8918a71cdbe9 232
Sergunb 0:8918a71cdbe9 233 uint32_t tm4c129EthCalcCrc(const void *data, size_t length);
Sergunb 0:8918a71cdbe9 234
Sergunb 0:8918a71cdbe9 235 #endif
Sergunb 0:8918a71cdbe9 236