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cyclone_tcp/drivers/str912_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file str912_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief STR9 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "91x_lib.h"
Sergunb 0:8918a71cdbe9 34 #include "core/net.h"
Sergunb 0:8918a71cdbe9 35 #include "drivers/str912_eth.h"
Sergunb 0:8918a71cdbe9 36 #include "debug.h"
Sergunb 0:8918a71cdbe9 37
Sergunb 0:8918a71cdbe9 38 //Underlying network interface
Sergunb 0:8918a71cdbe9 39 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 40
Sergunb 0:8918a71cdbe9 41 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 42 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 43
Sergunb 0:8918a71cdbe9 44 //Transmit buffer
Sergunb 0:8918a71cdbe9 45 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 46 static uint8_t txBuffer[STR912_ETH_TX_BUFFER_COUNT][STR912_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 47 //Receive buffer
Sergunb 0:8918a71cdbe9 48 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 49 static uint8_t rxBuffer[STR912_ETH_RX_BUFFER_COUNT][STR912_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 50 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 51 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 52 static Str912TxDmaDesc txDmaDesc[STR912_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 53 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 54 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 55 static Str912RxDmaDesc rxDmaDesc[STR912_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 56
Sergunb 0:8918a71cdbe9 57 //Keil MDK-ARM or GCC compiler?
Sergunb 0:8918a71cdbe9 58 #else
Sergunb 0:8918a71cdbe9 59
Sergunb 0:8918a71cdbe9 60 //Transmit buffer
Sergunb 0:8918a71cdbe9 61 static uint8_t txBuffer[STR912_ETH_TX_BUFFER_COUNT][STR912_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 62 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 63 //Receive buffer
Sergunb 0:8918a71cdbe9 64 static uint8_t rxBuffer[STR912_ETH_RX_BUFFER_COUNT][STR912_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 65 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 66 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 67 static Str912TxDmaDesc txDmaDesc[STR912_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 68 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 69 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 70 static Str912RxDmaDesc rxDmaDesc[STR912_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 71 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 72
Sergunb 0:8918a71cdbe9 73 #endif
Sergunb 0:8918a71cdbe9 74
Sergunb 0:8918a71cdbe9 75 //Pointer to the current TX DMA descriptor
Sergunb 0:8918a71cdbe9 76 static Str912TxDmaDesc *txCurDmaDesc;
Sergunb 0:8918a71cdbe9 77 //Pointer to the current RX DMA descriptor
Sergunb 0:8918a71cdbe9 78 static Str912RxDmaDesc *rxCurDmaDesc;
Sergunb 0:8918a71cdbe9 79
Sergunb 0:8918a71cdbe9 80
Sergunb 0:8918a71cdbe9 81 /**
Sergunb 0:8918a71cdbe9 82 * @brief STR912 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 83 **/
Sergunb 0:8918a71cdbe9 84
Sergunb 0:8918a71cdbe9 85 const NicDriver str912EthDriver =
Sergunb 0:8918a71cdbe9 86 {
Sergunb 0:8918a71cdbe9 87 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 88 ETH_MTU,
Sergunb 0:8918a71cdbe9 89 str912EthInit,
Sergunb 0:8918a71cdbe9 90 str912EthTick,
Sergunb 0:8918a71cdbe9 91 str912EthEnableIrq,
Sergunb 0:8918a71cdbe9 92 str912EthDisableIrq,
Sergunb 0:8918a71cdbe9 93 str912EthEventHandler,
Sergunb 0:8918a71cdbe9 94 str912EthSendPacket,
Sergunb 0:8918a71cdbe9 95 str912EthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 96 str912EthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 97 str912EthWritePhyReg,
Sergunb 0:8918a71cdbe9 98 str912EthReadPhyReg,
Sergunb 0:8918a71cdbe9 99 TRUE,
Sergunb 0:8918a71cdbe9 100 TRUE,
Sergunb 0:8918a71cdbe9 101 TRUE,
Sergunb 0:8918a71cdbe9 102 FALSE
Sergunb 0:8918a71cdbe9 103 };
Sergunb 0:8918a71cdbe9 104
Sergunb 0:8918a71cdbe9 105
Sergunb 0:8918a71cdbe9 106 /**
Sergunb 0:8918a71cdbe9 107 * @brief STR912 Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 108 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 109 * @return Error code
Sergunb 0:8918a71cdbe9 110 **/
Sergunb 0:8918a71cdbe9 111
Sergunb 0:8918a71cdbe9 112 error_t str912EthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 113 {
Sergunb 0:8918a71cdbe9 114 error_t error;
Sergunb 0:8918a71cdbe9 115
Sergunb 0:8918a71cdbe9 116 //Debug message
Sergunb 0:8918a71cdbe9 117 TRACE_INFO("Initializing STR912 Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 118
Sergunb 0:8918a71cdbe9 119 //Save underlying network interface
Sergunb 0:8918a71cdbe9 120 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 121
Sergunb 0:8918a71cdbe9 122 //GPIO configuration
Sergunb 0:8918a71cdbe9 123 str912EthInitGpio(interface);
Sergunb 0:8918a71cdbe9 124
Sergunb 0:8918a71cdbe9 125 //Enable Ethernet MAC clock
Sergunb 0:8918a71cdbe9 126 SCU_AHBPeriphClockConfig(__ENET, ENABLE);
Sergunb 0:8918a71cdbe9 127
Sergunb 0:8918a71cdbe9 128 //Reset Ethernet MAC peripheral
Sergunb 0:8918a71cdbe9 129 SCU_AHBPeriphReset(__ENET, ENABLE);
Sergunb 0:8918a71cdbe9 130 SCU_AHBPeriphReset(__ENET, DISABLE);
Sergunb 0:8918a71cdbe9 131
Sergunb 0:8918a71cdbe9 132 //MAC DMA software reset
Sergunb 0:8918a71cdbe9 133 ENET_DMA->SCR |= ENET_SCR_SRESET;
Sergunb 0:8918a71cdbe9 134 ENET_DMA->SCR &= ~ENET_SCR_SRESET;
Sergunb 0:8918a71cdbe9 135
Sergunb 0:8918a71cdbe9 136 //Use default MAC configuration
Sergunb 0:8918a71cdbe9 137 ENET_MAC->MCR = ENET_MCR_AFM_1 | ENET_MCR_RVFF |
Sergunb 0:8918a71cdbe9 138 ENET_MCR_BL_1 | ENET_MCR_DCE | ENET_MCR_RVBE;
Sergunb 0:8918a71cdbe9 139
Sergunb 0:8918a71cdbe9 140 //Adjust HCLK divider depending on system clock frequency
Sergunb 0:8918a71cdbe9 141 if(SCU_GetHCLKFreqValue() > 50000)
Sergunb 0:8918a71cdbe9 142 ENET_MAC->MCR |= ENET_MCR_PS_1;
Sergunb 0:8918a71cdbe9 143
Sergunb 0:8918a71cdbe9 144 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 145 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 146 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 147 if(error)
Sergunb 0:8918a71cdbe9 148 return error;
Sergunb 0:8918a71cdbe9 149
Sergunb 0:8918a71cdbe9 150 //Set the MAC address
Sergunb 0:8918a71cdbe9 151 ENET_MAC->MAL = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 152 ENET_MAC->MAH = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 153
Sergunb 0:8918a71cdbe9 154 //Initialize hash table
Sergunb 0:8918a71cdbe9 155 ENET_MAC->MCLA = 0;
Sergunb 0:8918a71cdbe9 156 ENET_MAC->MCHA = 0;
Sergunb 0:8918a71cdbe9 157
Sergunb 0:8918a71cdbe9 158 //DMA configuration
Sergunb 0:8918a71cdbe9 159 //ENET_DMA->SCR = 0;
Sergunb 0:8918a71cdbe9 160
Sergunb 0:8918a71cdbe9 161 //Force a DMA abort
Sergunb 0:8918a71cdbe9 162 ENET_DMA->TXSTR |= ENET_TXSTR_DMA_EN;
Sergunb 0:8918a71cdbe9 163 ENET_DMA->RXSTR |= ENET_RXSTR_DMA_EN;
Sergunb 0:8918a71cdbe9 164
Sergunb 0:8918a71cdbe9 165 //Set descriptor fetch delay
Sergunb 0:8918a71cdbe9 166 ENET_DMA->TXSTR = ENET_TXSTR_DFETCH_DLY_DEFAULT | ENET_TXSTR_UNDER_RUN;
Sergunb 0:8918a71cdbe9 167 ENET_DMA->RXSTR = ENET_RXSTR_DFETCH_DLY_DEFAULT;
Sergunb 0:8918a71cdbe9 168
Sergunb 0:8918a71cdbe9 169 //Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 170 str912EthInitDmaDesc(interface);
Sergunb 0:8918a71cdbe9 171
Sergunb 0:8918a71cdbe9 172 //Clear interrupt flags
Sergunb 0:8918a71cdbe9 173 ENET_DMA->ISR = ENET_ISR_TX_CURR_DONE | ENET_ISR_RX_CURR_DONE;
Sergunb 0:8918a71cdbe9 174 //Configure DMA interrupts as desired
Sergunb 0:8918a71cdbe9 175 ENET_DMA->IER = ENET_IER_TX_CURR_DONE_EN | ENET_IER_RX_CURR_DONE_EN;
Sergunb 0:8918a71cdbe9 176
Sergunb 0:8918a71cdbe9 177 //Configure Ethernet interrupt priority
Sergunb 0:8918a71cdbe9 178 VIC_Config(ENET_ITLine, VIC_IRQ, STR912_ETH_IRQ_PRIORITY);
Sergunb 0:8918a71cdbe9 179
Sergunb 0:8918a71cdbe9 180 //Enable MAC transmission and reception
Sergunb 0:8918a71cdbe9 181 ENET_MAC->MCR |= ENET_MCR_TE | ENET_MCR_RE;
Sergunb 0:8918a71cdbe9 182 //Instruct the DMA to poll the receive descriptor list
Sergunb 0:8918a71cdbe9 183 ENET_DMA->RXSTR |= ENET_RXSTR_START_FETCH;
Sergunb 0:8918a71cdbe9 184
Sergunb 0:8918a71cdbe9 185 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 186 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 187
Sergunb 0:8918a71cdbe9 188 //Successful initialization
Sergunb 0:8918a71cdbe9 189 return NO_ERROR;
Sergunb 0:8918a71cdbe9 190 }
Sergunb 0:8918a71cdbe9 191
Sergunb 0:8918a71cdbe9 192
Sergunb 0:8918a71cdbe9 193 //STR-E912 evaluation board?
Sergunb 0:8918a71cdbe9 194 #if defined(USE_STR_E912)
Sergunb 0:8918a71cdbe9 195
Sergunb 0:8918a71cdbe9 196 /**
Sergunb 0:8918a71cdbe9 197 * @brief GPIO configuration
Sergunb 0:8918a71cdbe9 198 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 199 **/
Sergunb 0:8918a71cdbe9 200
Sergunb 0:8918a71cdbe9 201 void str912EthInitGpio(NetInterface *interface)
Sergunb 0:8918a71cdbe9 202 {
Sergunb 0:8918a71cdbe9 203 GPIO_InitTypeDef GPIO_InitStructure;
Sergunb 0:8918a71cdbe9 204
Sergunb 0:8918a71cdbe9 205 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 206 SCU_APBPeriphClockConfig(__GPIO0, ENABLE);
Sergunb 0:8918a71cdbe9 207 SCU_APBPeriphClockConfig(__GPIO1, ENABLE);
Sergunb 0:8918a71cdbe9 208 SCU_APBPeriphClockConfig(__GPIO5, ENABLE);
Sergunb 0:8918a71cdbe9 209
Sergunb 0:8918a71cdbe9 210 //Enable MII_PHYCLK clock
Sergunb 0:8918a71cdbe9 211 SCU_PHYCLKConfig(ENABLE);
Sergunb 0:8918a71cdbe9 212
Sergunb 0:8918a71cdbe9 213 //Configure MII_TX_CLK (P0.0), MII_RXD0 (P0.2), MII_RXD1 (P0.3), MII_RXD2 (P0.4),
Sergunb 0:8918a71cdbe9 214 //MII_RXD3 (P0.5), MII_RX_CLK (P0.6) and MII_RX_DV (P0.7)
Sergunb 0:8918a71cdbe9 215 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_2 | GPIO_Pin_3 |
Sergunb 0:8918a71cdbe9 216 GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 217
Sergunb 0:8918a71cdbe9 218 GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
Sergunb 0:8918a71cdbe9 219 GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
Sergunb 0:8918a71cdbe9 220 GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1;
Sergunb 0:8918a71cdbe9 221 GPIO_Init(GPIO0, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 222
Sergunb 0:8918a71cdbe9 223 //Configure MII_RX_ER (P1.0), MII_COL (P1.5) and MII_CRS (P1.6)
Sergunb 0:8918a71cdbe9 224 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_5 | GPIO_Pin_6;
Sergunb 0:8918a71cdbe9 225 GPIO_InitStructure.GPIO_Direction = GPIO_PinInput;
Sergunb 0:8918a71cdbe9 226 GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
Sergunb 0:8918a71cdbe9 227 GPIO_InitStructure.GPIO_Alternate = GPIO_InputAlt1;
Sergunb 0:8918a71cdbe9 228 GPIO_Init(GPIO1, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 229
Sergunb 0:8918a71cdbe9 230 //Configure MII_TXD0 (P1.1), MII_TXD1 (P1.2), MII_TXD2 (P1.3),
Sergunb 0:8918a71cdbe9 231 //MII_TXD3 (P1.4) and MII_MDC (P1.7)
Sergunb 0:8918a71cdbe9 232 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 |
Sergunb 0:8918a71cdbe9 233 GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 234
Sergunb 0:8918a71cdbe9 235 GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
Sergunb 0:8918a71cdbe9 236 GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
Sergunb 0:8918a71cdbe9 237 GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
Sergunb 0:8918a71cdbe9 238 GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2;
Sergunb 0:8918a71cdbe9 239 GPIO_Init(GPIO1, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 240
Sergunb 0:8918a71cdbe9 241 //Configure MII_PHYCLK (P5.2) and MII_TX_EN (P5.3)
Sergunb 0:8918a71cdbe9 242 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3;
Sergunb 0:8918a71cdbe9 243 GPIO_InitStructure.GPIO_Direction = GPIO_PinOutput;
Sergunb 0:8918a71cdbe9 244 GPIO_InitStructure.GPIO_Type = GPIO_Type_PushPull;
Sergunb 0:8918a71cdbe9 245 GPIO_InitStructure.GPIO_IPInputConnected = GPIO_IPInputConnected_Disable;
Sergunb 0:8918a71cdbe9 246 GPIO_InitStructure.GPIO_Alternate = GPIO_OutputAlt2;
Sergunb 0:8918a71cdbe9 247 GPIO_Init(GPIO5, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 248 }
Sergunb 0:8918a71cdbe9 249
Sergunb 0:8918a71cdbe9 250 #endif
Sergunb 0:8918a71cdbe9 251
Sergunb 0:8918a71cdbe9 252
Sergunb 0:8918a71cdbe9 253 /**
Sergunb 0:8918a71cdbe9 254 * @brief Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 255 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 256 **/
Sergunb 0:8918a71cdbe9 257
Sergunb 0:8918a71cdbe9 258 void str912EthInitDmaDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 259 {
Sergunb 0:8918a71cdbe9 260 uint_t i;
Sergunb 0:8918a71cdbe9 261
Sergunb 0:8918a71cdbe9 262 //Initialize TX DMA descriptor list
Sergunb 0:8918a71cdbe9 263 for(i = 0; i < STR912_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 264 {
Sergunb 0:8918a71cdbe9 265 //Control word
Sergunb 0:8918a71cdbe9 266 txDmaDesc[i].ctrl = ENET_TDES_CTRL_NXT_EN;
Sergunb 0:8918a71cdbe9 267 //Transmit buffer address
Sergunb 0:8918a71cdbe9 268 txDmaDesc[i].start = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 269 //Next descriptor address
Sergunb 0:8918a71cdbe9 270 txDmaDesc[i].next = (uint32_t) &txDmaDesc[i + 1] | ENET_TDES_NEXT_NPOL_EN;
Sergunb 0:8918a71cdbe9 271 //Status word
Sergunb 0:8918a71cdbe9 272 txDmaDesc[i].status = 0;
Sergunb 0:8918a71cdbe9 273 }
Sergunb 0:8918a71cdbe9 274
Sergunb 0:8918a71cdbe9 275 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 276 txDmaDesc[i - 1].next = (uint32_t) &txDmaDesc[0] | ENET_TDES_NEXT_NPOL_EN;
Sergunb 0:8918a71cdbe9 277 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 278 txCurDmaDesc = &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 279
Sergunb 0:8918a71cdbe9 280 //Initialize RX DMA descriptor list
Sergunb 0:8918a71cdbe9 281 for(i = 0; i < STR912_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 282 {
Sergunb 0:8918a71cdbe9 283 //Control word
Sergunb 0:8918a71cdbe9 284 rxDmaDesc[i].ctrl = ENET_RDES_CTRL_NXT_EN | STR912_ETH_RX_BUFFER_SIZE;
Sergunb 0:8918a71cdbe9 285 //Receive buffer address
Sergunb 0:8918a71cdbe9 286 rxDmaDesc[i].start = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 287 //Next descriptor address
Sergunb 0:8918a71cdbe9 288 rxDmaDesc[i].next = (uint32_t) &rxDmaDesc[i + 1] | ENET_RDES_NEXT_NPOL_EN;
Sergunb 0:8918a71cdbe9 289 //Status word
Sergunb 0:8918a71cdbe9 290 rxDmaDesc[i].status = ENET_RDES_STATUS_VALID;
Sergunb 0:8918a71cdbe9 291 }
Sergunb 0:8918a71cdbe9 292
Sergunb 0:8918a71cdbe9 293 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 294 rxDmaDesc[i - 1].next = (uint32_t) &rxDmaDesc[0] | ENET_RDES_NEXT_NPOL_EN;
Sergunb 0:8918a71cdbe9 295 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 296 rxCurDmaDesc = &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 297
Sergunb 0:8918a71cdbe9 298 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 299 ENET_DMA->TXNDAR = (uint32_t) txDmaDesc | ENET_TDES_NEXT_NPOL_EN;
Sergunb 0:8918a71cdbe9 300 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 301 ENET_DMA->RXNDAR = (uint32_t) rxDmaDesc | ENET_RDES_NEXT_NPOL_EN;
Sergunb 0:8918a71cdbe9 302 }
Sergunb 0:8918a71cdbe9 303
Sergunb 0:8918a71cdbe9 304
Sergunb 0:8918a71cdbe9 305 /**
Sergunb 0:8918a71cdbe9 306 * @brief STR912 Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 307 *
Sergunb 0:8918a71cdbe9 308 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 309 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 310 *
Sergunb 0:8918a71cdbe9 311 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 312 **/
Sergunb 0:8918a71cdbe9 313
Sergunb 0:8918a71cdbe9 314 void str912EthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 315 {
Sergunb 0:8918a71cdbe9 316 //Handle periodic operations
Sergunb 0:8918a71cdbe9 317 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 318 }
Sergunb 0:8918a71cdbe9 319
Sergunb 0:8918a71cdbe9 320
Sergunb 0:8918a71cdbe9 321 /**
Sergunb 0:8918a71cdbe9 322 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 323 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 324 **/
Sergunb 0:8918a71cdbe9 325
Sergunb 0:8918a71cdbe9 326 void str912EthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 327 {
Sergunb 0:8918a71cdbe9 328 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 329 VIC_ITCmd(ENET_ITLine, ENABLE);
Sergunb 0:8918a71cdbe9 330 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 331 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 332 }
Sergunb 0:8918a71cdbe9 333
Sergunb 0:8918a71cdbe9 334
Sergunb 0:8918a71cdbe9 335 /**
Sergunb 0:8918a71cdbe9 336 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 337 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 338 **/
Sergunb 0:8918a71cdbe9 339
Sergunb 0:8918a71cdbe9 340 void str912EthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 341 {
Sergunb 0:8918a71cdbe9 342 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 343 VIC_ITCmd(ENET_ITLine, DISABLE);
Sergunb 0:8918a71cdbe9 344 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 345 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 346 }
Sergunb 0:8918a71cdbe9 347
Sergunb 0:8918a71cdbe9 348
Sergunb 0:8918a71cdbe9 349 /**
Sergunb 0:8918a71cdbe9 350 * @brief STR912 Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 351 **/
Sergunb 0:8918a71cdbe9 352
Sergunb 0:8918a71cdbe9 353 void ENET_IRQHandler(void)
Sergunb 0:8918a71cdbe9 354 {
Sergunb 0:8918a71cdbe9 355 bool_t flag;
Sergunb 0:8918a71cdbe9 356 uint32_t status;
Sergunb 0:8918a71cdbe9 357
Sergunb 0:8918a71cdbe9 358 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 359 osEnterIsr();
Sergunb 0:8918a71cdbe9 360
Sergunb 0:8918a71cdbe9 361 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 362 flag = FALSE;
Sergunb 0:8918a71cdbe9 363
Sergunb 0:8918a71cdbe9 364 //Read DMA status register
Sergunb 0:8918a71cdbe9 365 status = ENET_DMA->ISR;
Sergunb 0:8918a71cdbe9 366
Sergunb 0:8918a71cdbe9 367 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 368 if(status & ENET_ISR_TX_CURR_DONE)
Sergunb 0:8918a71cdbe9 369 {
Sergunb 0:8918a71cdbe9 370 //Clear TX_CURR_DONE interrupt flag
Sergunb 0:8918a71cdbe9 371 ENET_DMA->ISR = ENET_ISR_TX_CURR_DONE;
Sergunb 0:8918a71cdbe9 372
Sergunb 0:8918a71cdbe9 373 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 374 if(!(txCurDmaDesc->status & ENET_TDES_STATUS_VALID))
Sergunb 0:8918a71cdbe9 375 {
Sergunb 0:8918a71cdbe9 376 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 377 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 378 }
Sergunb 0:8918a71cdbe9 379 }
Sergunb 0:8918a71cdbe9 380
Sergunb 0:8918a71cdbe9 381 //A packet has been received?
Sergunb 0:8918a71cdbe9 382 if(status & ENET_ISR_RX_CURR_DONE)
Sergunb 0:8918a71cdbe9 383 {
Sergunb 0:8918a71cdbe9 384 //Disable RX_CURR_DONE interrupt
Sergunb 0:8918a71cdbe9 385 ENET_DMA->IER &= ~ENET_IER_RX_CURR_DONE_EN;
Sergunb 0:8918a71cdbe9 386
Sergunb 0:8918a71cdbe9 387 //Set event flag
Sergunb 0:8918a71cdbe9 388 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 389 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 390 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 391 }
Sergunb 0:8918a71cdbe9 392
Sergunb 0:8918a71cdbe9 393 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 394 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 395 }
Sergunb 0:8918a71cdbe9 396
Sergunb 0:8918a71cdbe9 397
Sergunb 0:8918a71cdbe9 398 /**
Sergunb 0:8918a71cdbe9 399 * @brief STR912 Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 400 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 401 **/
Sergunb 0:8918a71cdbe9 402
Sergunb 0:8918a71cdbe9 403 void str912EthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 404 {
Sergunb 0:8918a71cdbe9 405 error_t error;
Sergunb 0:8918a71cdbe9 406
Sergunb 0:8918a71cdbe9 407 //Packet received?
Sergunb 0:8918a71cdbe9 408 if(ENET_DMA->ISR & ENET_ISR_RX_CURR_DONE)
Sergunb 0:8918a71cdbe9 409 {
Sergunb 0:8918a71cdbe9 410 //Clear interrupt flag
Sergunb 0:8918a71cdbe9 411 ENET_DMA->ISR = ENET_ISR_RX_CURR_DONE;
Sergunb 0:8918a71cdbe9 412
Sergunb 0:8918a71cdbe9 413 //Process all pending packets
Sergunb 0:8918a71cdbe9 414 do
Sergunb 0:8918a71cdbe9 415 {
Sergunb 0:8918a71cdbe9 416 //Read incoming packet
Sergunb 0:8918a71cdbe9 417 error = str912EthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 418
Sergunb 0:8918a71cdbe9 419 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 420 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 421 }
Sergunb 0:8918a71cdbe9 422
Sergunb 0:8918a71cdbe9 423 //Re-enable DMA interrupts
Sergunb 0:8918a71cdbe9 424 ENET_DMA->IER = ENET_IER_TX_CURR_DONE_EN | ENET_IER_RX_CURR_DONE_EN;
Sergunb 0:8918a71cdbe9 425 }
Sergunb 0:8918a71cdbe9 426
Sergunb 0:8918a71cdbe9 427
Sergunb 0:8918a71cdbe9 428 /**
Sergunb 0:8918a71cdbe9 429 * @brief Send a packet
Sergunb 0:8918a71cdbe9 430 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 431 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 432 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 433 * @return Error code
Sergunb 0:8918a71cdbe9 434 **/
Sergunb 0:8918a71cdbe9 435
Sergunb 0:8918a71cdbe9 436 error_t str912EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 437 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 438 {
Sergunb 0:8918a71cdbe9 439 size_t length;
Sergunb 0:8918a71cdbe9 440
Sergunb 0:8918a71cdbe9 441 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 442 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 443
Sergunb 0:8918a71cdbe9 444 //Check the frame length
Sergunb 0:8918a71cdbe9 445 if(length > STR912_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 446 {
Sergunb 0:8918a71cdbe9 447 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 448 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 449 //Report an error
Sergunb 0:8918a71cdbe9 450 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 451 }
Sergunb 0:8918a71cdbe9 452
Sergunb 0:8918a71cdbe9 453 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 454 if(txCurDmaDesc->status & ENET_TDES_STATUS_VALID)
Sergunb 0:8918a71cdbe9 455 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 456
Sergunb 0:8918a71cdbe9 457 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 458 netBufferRead((uint8_t *) (txCurDmaDesc->start & ENET_TDES_START_ADDR),
Sergunb 0:8918a71cdbe9 459 buffer, offset, length);
Sergunb 0:8918a71cdbe9 460
Sergunb 0:8918a71cdbe9 461 //Write the number of bytes to send
Sergunb 0:8918a71cdbe9 462 txCurDmaDesc->ctrl = ENET_TDES_CTRL_NXT_EN | length;
Sergunb 0:8918a71cdbe9 463 //Give the ownership of the descriptor to the DMA
Sergunb 0:8918a71cdbe9 464 txCurDmaDesc->status = ENET_TDES_STATUS_VALID;
Sergunb 0:8918a71cdbe9 465
Sergunb 0:8918a71cdbe9 466 //Instruct the DMA to poll the transmit descriptor list
Sergunb 0:8918a71cdbe9 467 ENET_DMA->TXSTR |= ENET_TXSTR_START_FETCH;
Sergunb 0:8918a71cdbe9 468
Sergunb 0:8918a71cdbe9 469 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 470 txCurDmaDesc = (Str912TxDmaDesc *) (txCurDmaDesc->next & ENET_TDES_NEXT_ADDR);
Sergunb 0:8918a71cdbe9 471
Sergunb 0:8918a71cdbe9 472 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 473 if(!(txCurDmaDesc->status & ENET_TDES_STATUS_VALID))
Sergunb 0:8918a71cdbe9 474 {
Sergunb 0:8918a71cdbe9 475 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 476 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 477 }
Sergunb 0:8918a71cdbe9 478
Sergunb 0:8918a71cdbe9 479 //Data successfully written
Sergunb 0:8918a71cdbe9 480 return NO_ERROR;
Sergunb 0:8918a71cdbe9 481 }
Sergunb 0:8918a71cdbe9 482
Sergunb 0:8918a71cdbe9 483
Sergunb 0:8918a71cdbe9 484 /**
Sergunb 0:8918a71cdbe9 485 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 486 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 487 * @return Error code
Sergunb 0:8918a71cdbe9 488 **/
Sergunb 0:8918a71cdbe9 489
Sergunb 0:8918a71cdbe9 490 error_t str912EthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 491 {
Sergunb 0:8918a71cdbe9 492 error_t error;
Sergunb 0:8918a71cdbe9 493 size_t n;
Sergunb 0:8918a71cdbe9 494 uint8_t *p;
Sergunb 0:8918a71cdbe9 495
Sergunb 0:8918a71cdbe9 496 //The current buffer is available for reading?
Sergunb 0:8918a71cdbe9 497 if(!(rxCurDmaDesc->status & ENET_RDES_STATUS_VALID))
Sergunb 0:8918a71cdbe9 498 {
Sergunb 0:8918a71cdbe9 499 //Make sure no error occurred
Sergunb 0:8918a71cdbe9 500 if(!(rxCurDmaDesc->status & ENET_RDES_STATUS_ERROR))
Sergunb 0:8918a71cdbe9 501 {
Sergunb 0:8918a71cdbe9 502 //Point to the received frame
Sergunb 0:8918a71cdbe9 503 p = (uint8_t *) (rxCurDmaDesc->start & ENET_RDES_START_ADDR);
Sergunb 0:8918a71cdbe9 504
Sergunb 0:8918a71cdbe9 505 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 506 n = rxCurDmaDesc->status & ENET_RDES_STATUS_FL;
Sergunb 0:8918a71cdbe9 507 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 508 n = MIN(n, STR912_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 509
Sergunb 0:8918a71cdbe9 510 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 511 nicProcessPacket(interface, p, n);
Sergunb 0:8918a71cdbe9 512
Sergunb 0:8918a71cdbe9 513 //Valid packet received
Sergunb 0:8918a71cdbe9 514 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 515 }
Sergunb 0:8918a71cdbe9 516 else
Sergunb 0:8918a71cdbe9 517 {
Sergunb 0:8918a71cdbe9 518 //The received packet contains an error
Sergunb 0:8918a71cdbe9 519 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 520 }
Sergunb 0:8918a71cdbe9 521
Sergunb 0:8918a71cdbe9 522 //Give the ownership of the descriptor back to the DMA
Sergunb 0:8918a71cdbe9 523 rxCurDmaDesc->status = ENET_RDES_STATUS_VALID;
Sergunb 0:8918a71cdbe9 524 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 525 rxCurDmaDesc = (Str912RxDmaDesc *) (rxCurDmaDesc->next & ENET_RDES_NEXT_ADDR);
Sergunb 0:8918a71cdbe9 526 }
Sergunb 0:8918a71cdbe9 527 else
Sergunb 0:8918a71cdbe9 528 {
Sergunb 0:8918a71cdbe9 529 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 530 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 531 }
Sergunb 0:8918a71cdbe9 532
Sergunb 0:8918a71cdbe9 533 //Instruct the DMA to poll the receive descriptor list
Sergunb 0:8918a71cdbe9 534 ENET_DMA->RXSTR |= ENET_RXSTR_START_FETCH;
Sergunb 0:8918a71cdbe9 535
Sergunb 0:8918a71cdbe9 536 //Return status code
Sergunb 0:8918a71cdbe9 537 return error;
Sergunb 0:8918a71cdbe9 538 }
Sergunb 0:8918a71cdbe9 539
Sergunb 0:8918a71cdbe9 540
Sergunb 0:8918a71cdbe9 541 /**
Sergunb 0:8918a71cdbe9 542 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 543 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 544 * @return Error code
Sergunb 0:8918a71cdbe9 545 **/
Sergunb 0:8918a71cdbe9 546
Sergunb 0:8918a71cdbe9 547 error_t str912EthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 548 {
Sergunb 0:8918a71cdbe9 549 uint_t i;
Sergunb 0:8918a71cdbe9 550 uint_t k;
Sergunb 0:8918a71cdbe9 551 uint32_t crc;
Sergunb 0:8918a71cdbe9 552 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 553 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 554
Sergunb 0:8918a71cdbe9 555 //Debug message
Sergunb 0:8918a71cdbe9 556 TRACE_DEBUG("Updating STR912 hash table...\r\n");
Sergunb 0:8918a71cdbe9 557
Sergunb 0:8918a71cdbe9 558 //Clear hash table
Sergunb 0:8918a71cdbe9 559 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 560 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 561
Sergunb 0:8918a71cdbe9 562 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 563 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 564 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 565 {
Sergunb 0:8918a71cdbe9 566 //Point to the current entry
Sergunb 0:8918a71cdbe9 567 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 568
Sergunb 0:8918a71cdbe9 569 //Valid entry?
Sergunb 0:8918a71cdbe9 570 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 571 {
Sergunb 0:8918a71cdbe9 572 //Compute CRC over the current MAC address
Sergunb 0:8918a71cdbe9 573 crc = str912EthCalcCrc(&entry->addr, sizeof(MacAddr));
Sergunb 0:8918a71cdbe9 574
Sergunb 0:8918a71cdbe9 575 //The upper 6 bits in the CRC register are used to index the
Sergunb 0:8918a71cdbe9 576 //contents of the hash table
Sergunb 0:8918a71cdbe9 577 k = (crc >> 26) & 0x3F;
Sergunb 0:8918a71cdbe9 578
Sergunb 0:8918a71cdbe9 579 //Update hash table contents
Sergunb 0:8918a71cdbe9 580 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 581 }
Sergunb 0:8918a71cdbe9 582 }
Sergunb 0:8918a71cdbe9 583
Sergunb 0:8918a71cdbe9 584 //Write the hash table
Sergunb 0:8918a71cdbe9 585 ENET_MAC->MCLA = hashTable[0];
Sergunb 0:8918a71cdbe9 586 ENET_MAC->MCHA = hashTable[1];
Sergunb 0:8918a71cdbe9 587
Sergunb 0:8918a71cdbe9 588 //Debug message
Sergunb 0:8918a71cdbe9 589 TRACE_DEBUG(" ENET_MCLA = %08" PRIX32 "\r\n", ENET_MAC->MCLA);
Sergunb 0:8918a71cdbe9 590 TRACE_DEBUG(" ENET_MCHA = %08" PRIX32 "\r\n", ENET_MAC->MCHA);
Sergunb 0:8918a71cdbe9 591
Sergunb 0:8918a71cdbe9 592 //Successful processing
Sergunb 0:8918a71cdbe9 593 return NO_ERROR;
Sergunb 0:8918a71cdbe9 594 }
Sergunb 0:8918a71cdbe9 595
Sergunb 0:8918a71cdbe9 596
Sergunb 0:8918a71cdbe9 597 /**
Sergunb 0:8918a71cdbe9 598 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 599 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 600 * @return Error code
Sergunb 0:8918a71cdbe9 601 **/
Sergunb 0:8918a71cdbe9 602
Sergunb 0:8918a71cdbe9 603 error_t str912EthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 604 {
Sergunb 0:8918a71cdbe9 605 uint32_t config;
Sergunb 0:8918a71cdbe9 606
Sergunb 0:8918a71cdbe9 607 //Read current MAC configuration
Sergunb 0:8918a71cdbe9 608 config = ENET_MAC->MCR;
Sergunb 0:8918a71cdbe9 609
Sergunb 0:8918a71cdbe9 610 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 611 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 612 {
Sergunb 0:8918a71cdbe9 613 //Full-duplex mode
Sergunb 0:8918a71cdbe9 614 config |= ENET_MCR_FDM;
Sergunb 0:8918a71cdbe9 615 //Enable the reception path during transmission
Sergunb 0:8918a71cdbe9 616 config &= ~ENET_MCR_DRO;
Sergunb 0:8918a71cdbe9 617 }
Sergunb 0:8918a71cdbe9 618 else
Sergunb 0:8918a71cdbe9 619 {
Sergunb 0:8918a71cdbe9 620 //Half-duplex mode
Sergunb 0:8918a71cdbe9 621 config &= ~ENET_MCR_FDM;
Sergunb 0:8918a71cdbe9 622 //Disable the reception path during transmission
Sergunb 0:8918a71cdbe9 623 config |= ENET_MCR_DRO;
Sergunb 0:8918a71cdbe9 624 }
Sergunb 0:8918a71cdbe9 625
Sergunb 0:8918a71cdbe9 626 //Update MAC configuration register
Sergunb 0:8918a71cdbe9 627 ENET_MAC->MCR = config;
Sergunb 0:8918a71cdbe9 628
Sergunb 0:8918a71cdbe9 629 //Successful processing
Sergunb 0:8918a71cdbe9 630 return NO_ERROR;
Sergunb 0:8918a71cdbe9 631 }
Sergunb 0:8918a71cdbe9 632
Sergunb 0:8918a71cdbe9 633
Sergunb 0:8918a71cdbe9 634 /**
Sergunb 0:8918a71cdbe9 635 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 636 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 637 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 638 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 639 **/
Sergunb 0:8918a71cdbe9 640
Sergunb 0:8918a71cdbe9 641 void str912EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 642 {
Sergunb 0:8918a71cdbe9 643 uint32_t value;
Sergunb 0:8918a71cdbe9 644
Sergunb 0:8918a71cdbe9 645 //Set up a write operation
Sergunb 0:8918a71cdbe9 646 value = ENET_MIIA_WR | ENET_MIIA_BUSY;
Sergunb 0:8918a71cdbe9 647 //PHY address
Sergunb 0:8918a71cdbe9 648 value |= (phyAddr << 11) & ENET_MIIA_PADDR;
Sergunb 0:8918a71cdbe9 649 //Register address
Sergunb 0:8918a71cdbe9 650 value |= (regAddr << 6) & ENET_MIIA_RADDR;
Sergunb 0:8918a71cdbe9 651
Sergunb 0:8918a71cdbe9 652 //Data to be written in the PHY register
Sergunb 0:8918a71cdbe9 653 ENET_MAC->MIID = data & ENET_MIID_RDATA;
Sergunb 0:8918a71cdbe9 654
Sergunb 0:8918a71cdbe9 655 //Start a write operation
Sergunb 0:8918a71cdbe9 656 ENET_MAC->MIIA = value;
Sergunb 0:8918a71cdbe9 657 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 658 while(ENET_MAC->MIIA & ENET_MIIA_BUSY);
Sergunb 0:8918a71cdbe9 659 }
Sergunb 0:8918a71cdbe9 660
Sergunb 0:8918a71cdbe9 661
Sergunb 0:8918a71cdbe9 662 /**
Sergunb 0:8918a71cdbe9 663 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 664 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 665 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 666 * @return Register value
Sergunb 0:8918a71cdbe9 667 **/
Sergunb 0:8918a71cdbe9 668
Sergunb 0:8918a71cdbe9 669 uint16_t str912EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 670 {
Sergunb 0:8918a71cdbe9 671 uint32_t value;
Sergunb 0:8918a71cdbe9 672
Sergunb 0:8918a71cdbe9 673 //Set up a read operation
Sergunb 0:8918a71cdbe9 674 value = ENET_MIIA_BUSY;
Sergunb 0:8918a71cdbe9 675 //PHY address
Sergunb 0:8918a71cdbe9 676 value |= (phyAddr << 11) & ENET_MIIA_PADDR;
Sergunb 0:8918a71cdbe9 677 //Register address
Sergunb 0:8918a71cdbe9 678 value |= (regAddr << 6) & ENET_MIIA_RADDR;
Sergunb 0:8918a71cdbe9 679
Sergunb 0:8918a71cdbe9 680 //Start a read operation
Sergunb 0:8918a71cdbe9 681 ENET_MAC->MIIA = value;
Sergunb 0:8918a71cdbe9 682 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 683 while(ENET_MAC->MIIA & ENET_MIIA_BUSY);
Sergunb 0:8918a71cdbe9 684
Sergunb 0:8918a71cdbe9 685 //Return PHY register contents
Sergunb 0:8918a71cdbe9 686 return ENET_MAC->MIID & ENET_MIID_RDATA;
Sergunb 0:8918a71cdbe9 687 }
Sergunb 0:8918a71cdbe9 688
Sergunb 0:8918a71cdbe9 689
Sergunb 0:8918a71cdbe9 690 /**
Sergunb 0:8918a71cdbe9 691 * @brief CRC calculation
Sergunb 0:8918a71cdbe9 692 * @param[in] data Pointer to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 693 * @param[in] length Number of bytes to process
Sergunb 0:8918a71cdbe9 694 * @return Resulting CRC value
Sergunb 0:8918a71cdbe9 695 **/
Sergunb 0:8918a71cdbe9 696
Sergunb 0:8918a71cdbe9 697 uint32_t str912EthCalcCrc(const void *data, size_t length)
Sergunb 0:8918a71cdbe9 698 {
Sergunb 0:8918a71cdbe9 699 uint_t i;
Sergunb 0:8918a71cdbe9 700 uint_t j;
Sergunb 0:8918a71cdbe9 701
Sergunb 0:8918a71cdbe9 702 //Point to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 703 const uint8_t *p = (uint8_t *) data;
Sergunb 0:8918a71cdbe9 704 //CRC preset value
Sergunb 0:8918a71cdbe9 705 uint32_t crc = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 706
Sergunb 0:8918a71cdbe9 707 //Loop through data
Sergunb 0:8918a71cdbe9 708 for(i = 0; i < length; i++)
Sergunb 0:8918a71cdbe9 709 {
Sergunb 0:8918a71cdbe9 710 //The message is processed bit by bit
Sergunb 0:8918a71cdbe9 711 for(j = 0; j < 8; j++)
Sergunb 0:8918a71cdbe9 712 {
Sergunb 0:8918a71cdbe9 713 //Update CRC value
Sergunb 0:8918a71cdbe9 714 if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
Sergunb 0:8918a71cdbe9 715 crc = (crc << 1) ^ 0x04C11DB7;
Sergunb 0:8918a71cdbe9 716 else
Sergunb 0:8918a71cdbe9 717 crc = crc << 1;
Sergunb 0:8918a71cdbe9 718 }
Sergunb 0:8918a71cdbe9 719 }
Sergunb 0:8918a71cdbe9 720
Sergunb 0:8918a71cdbe9 721 //Return CRC value
Sergunb 0:8918a71cdbe9 722 return crc;
Sergunb 0:8918a71cdbe9 723 }
Sergunb 0:8918a71cdbe9 724