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cyclone_tcp/drivers/stm32f4x7_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file stm32f4x7_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief STM32F407/417/427/437 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "stm32f4xx.h"
Sergunb 0:8918a71cdbe9 34 #include "core/net.h"
Sergunb 0:8918a71cdbe9 35 #include "drivers/stm32f4x7_eth.h"
Sergunb 0:8918a71cdbe9 36 #include "debug.h"
Sergunb 0:8918a71cdbe9 37
Sergunb 0:8918a71cdbe9 38 //Underlying network interface
Sergunb 0:8918a71cdbe9 39 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 40
Sergunb 0:8918a71cdbe9 41 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 42 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 43
Sergunb 0:8918a71cdbe9 44 //Transmit buffer
Sergunb 0:8918a71cdbe9 45 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 46 static uint8_t txBuffer[STM32F4X7_ETH_TX_BUFFER_COUNT][STM32F4X7_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 47 //Receive buffer
Sergunb 0:8918a71cdbe9 48 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 49 static uint8_t rxBuffer[STM32F4X7_ETH_RX_BUFFER_COUNT][STM32F4X7_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 50 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 51 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 52 static Stm32f4x7TxDmaDesc txDmaDesc[STM32F4X7_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 53 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 54 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 55 static Stm32f4x7RxDmaDesc rxDmaDesc[STM32F4X7_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 56
Sergunb 0:8918a71cdbe9 57 //Keil MDK-ARM or GCC compiler?
Sergunb 0:8918a71cdbe9 58 #else
Sergunb 0:8918a71cdbe9 59
Sergunb 0:8918a71cdbe9 60 //Transmit buffer
Sergunb 0:8918a71cdbe9 61 static uint8_t txBuffer[STM32F4X7_ETH_TX_BUFFER_COUNT][STM32F4X7_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 62 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 63 //Receive buffer
Sergunb 0:8918a71cdbe9 64 static uint8_t rxBuffer[STM32F4X7_ETH_RX_BUFFER_COUNT][STM32F4X7_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 65 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 66 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 67 static Stm32f4x7TxDmaDesc txDmaDesc[STM32F4X7_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 68 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 69 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 70 static Stm32f4x7RxDmaDesc rxDmaDesc[STM32F4X7_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 71 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 72
Sergunb 0:8918a71cdbe9 73 #endif
Sergunb 0:8918a71cdbe9 74
Sergunb 0:8918a71cdbe9 75 //Pointer to the current TX DMA descriptor
Sergunb 0:8918a71cdbe9 76 static Stm32f4x7TxDmaDesc *txCurDmaDesc;
Sergunb 0:8918a71cdbe9 77 //Pointer to the current RX DMA descriptor
Sergunb 0:8918a71cdbe9 78 static Stm32f4x7RxDmaDesc *rxCurDmaDesc;
Sergunb 0:8918a71cdbe9 79
Sergunb 0:8918a71cdbe9 80
Sergunb 0:8918a71cdbe9 81 /**
Sergunb 0:8918a71cdbe9 82 * @brief STM32F407/417/427/437 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 83 **/
Sergunb 0:8918a71cdbe9 84
Sergunb 0:8918a71cdbe9 85 const NicDriver stm32f4x7EthDriver =
Sergunb 0:8918a71cdbe9 86 {
Sergunb 0:8918a71cdbe9 87 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 88 ETH_MTU,
Sergunb 0:8918a71cdbe9 89 stm32f4x7EthInit,
Sergunb 0:8918a71cdbe9 90 stm32f4x7EthTick,
Sergunb 0:8918a71cdbe9 91 stm32f4x7EthEnableIrq,
Sergunb 0:8918a71cdbe9 92 stm32f4x7EthDisableIrq,
Sergunb 0:8918a71cdbe9 93 stm32f4x7EthEventHandler,
Sergunb 0:8918a71cdbe9 94 stm32f4x7EthSendPacket,
Sergunb 0:8918a71cdbe9 95 stm32f4x7EthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 96 stm32f4x7EthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 97 stm32f4x7EthWritePhyReg,
Sergunb 0:8918a71cdbe9 98 stm32f4x7EthReadPhyReg,
Sergunb 0:8918a71cdbe9 99 TRUE,
Sergunb 0:8918a71cdbe9 100 TRUE,
Sergunb 0:8918a71cdbe9 101 TRUE,
Sergunb 0:8918a71cdbe9 102 FALSE
Sergunb 0:8918a71cdbe9 103 };
Sergunb 0:8918a71cdbe9 104
Sergunb 0:8918a71cdbe9 105
Sergunb 0:8918a71cdbe9 106 /**
Sergunb 0:8918a71cdbe9 107 * @brief STM32F407/417/427/437 Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 108 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 109 * @return Error code
Sergunb 0:8918a71cdbe9 110 **/
Sergunb 0:8918a71cdbe9 111
Sergunb 0:8918a71cdbe9 112 error_t stm32f4x7EthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 113 {
Sergunb 0:8918a71cdbe9 114 error_t error;
Sergunb 0:8918a71cdbe9 115
Sergunb 0:8918a71cdbe9 116 //Debug message
Sergunb 0:8918a71cdbe9 117 TRACE_INFO("Initializing STM32F4x7 Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 118
Sergunb 0:8918a71cdbe9 119 //Save underlying network interface
Sergunb 0:8918a71cdbe9 120 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 121
Sergunb 0:8918a71cdbe9 122 //GPIO configuration
Sergunb 0:8918a71cdbe9 123 stm32f4x7EthInitGpio(interface);
Sergunb 0:8918a71cdbe9 124
Sergunb 0:8918a71cdbe9 125 #if defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 126 //Enable Ethernet MAC clock
Sergunb 0:8918a71cdbe9 127 __HAL_RCC_ETHMAC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 128 __HAL_RCC_ETHMACTX_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 129 __HAL_RCC_ETHMACRX_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 130
Sergunb 0:8918a71cdbe9 131 //Reset Ethernet MAC peripheral
Sergunb 0:8918a71cdbe9 132 __HAL_RCC_ETHMAC_FORCE_RESET();
Sergunb 0:8918a71cdbe9 133 __HAL_RCC_ETHMAC_RELEASE_RESET();
Sergunb 0:8918a71cdbe9 134
Sergunb 0:8918a71cdbe9 135 #elif defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 136 //Enable Ethernet MAC clock
Sergunb 0:8918a71cdbe9 137 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC |
Sergunb 0:8918a71cdbe9 138 RCC_AHB1Periph_ETH_MAC_Tx | RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
Sergunb 0:8918a71cdbe9 139
Sergunb 0:8918a71cdbe9 140 //Reset Ethernet MAC peripheral
Sergunb 0:8918a71cdbe9 141 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
Sergunb 0:8918a71cdbe9 142 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
Sergunb 0:8918a71cdbe9 143 #endif
Sergunb 0:8918a71cdbe9 144
Sergunb 0:8918a71cdbe9 145 //Perform a software reset
Sergunb 0:8918a71cdbe9 146 ETH->DMABMR |= ETH_DMABMR_SR;
Sergunb 0:8918a71cdbe9 147 //Wait for the reset to complete
Sergunb 0:8918a71cdbe9 148 while(ETH->DMABMR & ETH_DMABMR_SR);
Sergunb 0:8918a71cdbe9 149
Sergunb 0:8918a71cdbe9 150 //Adjust MDC clock range depending on HCLK frequency
Sergunb 0:8918a71cdbe9 151 ETH->MACMIIAR = ETH_MACMIIAR_CR_Div102;
Sergunb 0:8918a71cdbe9 152
Sergunb 0:8918a71cdbe9 153 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 154 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 155 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 156 if(error)
Sergunb 0:8918a71cdbe9 157 return error;
Sergunb 0:8918a71cdbe9 158
Sergunb 0:8918a71cdbe9 159 //Use default MAC configuration
Sergunb 0:8918a71cdbe9 160 ETH->MACCR = ETH_MACCR_ROD;
Sergunb 0:8918a71cdbe9 161
Sergunb 0:8918a71cdbe9 162 //Set the MAC address
Sergunb 0:8918a71cdbe9 163 ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 164 ETH->MACA0HR = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 165
Sergunb 0:8918a71cdbe9 166 //Initialize hash table
Sergunb 0:8918a71cdbe9 167 ETH->MACHTLR = 0;
Sergunb 0:8918a71cdbe9 168 ETH->MACHTHR = 0;
Sergunb 0:8918a71cdbe9 169
Sergunb 0:8918a71cdbe9 170 //Configure the receive filter
Sergunb 0:8918a71cdbe9 171 ETH->MACFFR = ETH_MACFFR_HPF | ETH_MACFFR_HM;
Sergunb 0:8918a71cdbe9 172 //Disable flow control
Sergunb 0:8918a71cdbe9 173 ETH->MACFCR = 0;
Sergunb 0:8918a71cdbe9 174 //Enable store and forward mode
Sergunb 0:8918a71cdbe9 175 ETH->DMAOMR = ETH_DMAOMR_RSF | ETH_DMAOMR_TSF;
Sergunb 0:8918a71cdbe9 176
Sergunb 0:8918a71cdbe9 177 //Configure DMA bus mode
Sergunb 0:8918a71cdbe9 178 ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_USP | ETH_DMABMR_RDP_1Beat |
Sergunb 0:8918a71cdbe9 179 ETH_DMABMR_RTPR_1_1 | ETH_DMABMR_PBL_1Beat | ETH_DMABMR_EDE;
Sergunb 0:8918a71cdbe9 180
Sergunb 0:8918a71cdbe9 181 //Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 182 stm32f4x7EthInitDmaDesc(interface);
Sergunb 0:8918a71cdbe9 183
Sergunb 0:8918a71cdbe9 184 //Prevent interrupts from being generated when the transmit statistic
Sergunb 0:8918a71cdbe9 185 //counters reach half their maximum value
Sergunb 0:8918a71cdbe9 186 ETH->MMCTIMR = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | ETH_MMCTIMR_TGFSCM;
Sergunb 0:8918a71cdbe9 187
Sergunb 0:8918a71cdbe9 188 //Prevent interrupts from being generated when the receive statistic
Sergunb 0:8918a71cdbe9 189 //counters reach half their maximum value
Sergunb 0:8918a71cdbe9 190 ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM;
Sergunb 0:8918a71cdbe9 191
Sergunb 0:8918a71cdbe9 192 //Disable MAC interrupts
Sergunb 0:8918a71cdbe9 193 ETH->MACIMR = ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM;
Sergunb 0:8918a71cdbe9 194 //Enable the desired DMA interrupts
Sergunb 0:8918a71cdbe9 195 ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
Sergunb 0:8918a71cdbe9 196
Sergunb 0:8918a71cdbe9 197 //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
Sergunb 0:8918a71cdbe9 198 NVIC_SetPriorityGrouping(STM32F4X7_ETH_IRQ_PRIORITY_GROUPING);
Sergunb 0:8918a71cdbe9 199
Sergunb 0:8918a71cdbe9 200 //Configure Ethernet interrupt priority
Sergunb 0:8918a71cdbe9 201 NVIC_SetPriority(ETH_IRQn, NVIC_EncodePriority(STM32F4X7_ETH_IRQ_PRIORITY_GROUPING,
Sergunb 0:8918a71cdbe9 202 STM32F4X7_ETH_IRQ_GROUP_PRIORITY, STM32F4X7_ETH_IRQ_SUB_PRIORITY));
Sergunb 0:8918a71cdbe9 203
Sergunb 0:8918a71cdbe9 204 //Enable MAC transmission and reception
Sergunb 0:8918a71cdbe9 205 ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
Sergunb 0:8918a71cdbe9 206 //Enable DMA transmission and reception
Sergunb 0:8918a71cdbe9 207 ETH->DMAOMR |= ETH_DMAOMR_ST | ETH_DMAOMR_SR;
Sergunb 0:8918a71cdbe9 208
Sergunb 0:8918a71cdbe9 209 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 210 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 211
Sergunb 0:8918a71cdbe9 212 //Successful initialization
Sergunb 0:8918a71cdbe9 213 return NO_ERROR;
Sergunb 0:8918a71cdbe9 214 }
Sergunb 0:8918a71cdbe9 215
Sergunb 0:8918a71cdbe9 216
Sergunb 0:8918a71cdbe9 217 //STM3240G-EVAL, STM32F4-DISCOVERY, MCBSTM32F400, STM32-E407
Sergunb 0:8918a71cdbe9 218 //or STM-P407 evaluation board?
Sergunb 0:8918a71cdbe9 219 #if defined(USE_STM324xG_EVAL) || defined(USE_STM32F4_DISCOVERY) || \
Sergunb 0:8918a71cdbe9 220 defined(USE_MCBSTM32F400) || defined(USE_STM32_E407) || defined(USE_STM32_P407)
Sergunb 0:8918a71cdbe9 221
Sergunb 0:8918a71cdbe9 222 /**
Sergunb 0:8918a71cdbe9 223 * @brief GPIO configuration
Sergunb 0:8918a71cdbe9 224 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 225 **/
Sergunb 0:8918a71cdbe9 226
Sergunb 0:8918a71cdbe9 227 void stm32f4x7EthInitGpio(NetInterface *interface)
Sergunb 0:8918a71cdbe9 228 {
Sergunb 0:8918a71cdbe9 229 GPIO_InitTypeDef GPIO_InitStructure;
Sergunb 0:8918a71cdbe9 230
Sergunb 0:8918a71cdbe9 231 //STM3240G-EVAL evaluation board?
Sergunb 0:8918a71cdbe9 232 #if defined(USE_STM324xG_EVAL) && defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 233 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 234 __HAL_RCC_SYSCFG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 235
Sergunb 0:8918a71cdbe9 236 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 237 __HAL_RCC_GPIOA_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 238 __HAL_RCC_GPIOB_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 239 __HAL_RCC_GPIOC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 240 __HAL_RCC_GPIOG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 241 __HAL_RCC_GPIOH_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 242 __HAL_RCC_GPIOI_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 243
Sergunb 0:8918a71cdbe9 244 //Configure MCO1 (PA8) as an output
Sergunb 0:8918a71cdbe9 245 GPIO_InitStructure.Pin = GPIO_PIN_8;
Sergunb 0:8918a71cdbe9 246 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 247 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 248 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 249 GPIO_InitStructure.Alternate = GPIO_AF0_MCO;
Sergunb 0:8918a71cdbe9 250 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 251
Sergunb 0:8918a71cdbe9 252 //Configure MCO1 pin to output the HSE clock (25MHz)
Sergunb 0:8918a71cdbe9 253 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1);
Sergunb 0:8918a71cdbe9 254
Sergunb 0:8918a71cdbe9 255 //Select MII interface mode
Sergunb 0:8918a71cdbe9 256 SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL;
Sergunb 0:8918a71cdbe9 257
Sergunb 0:8918a71cdbe9 258 //Configure MII pins
Sergunb 0:8918a71cdbe9 259 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 260 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 261 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 262 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
Sergunb 0:8918a71cdbe9 263
Sergunb 0:8918a71cdbe9 264 //Configure ETH_MII_RX_CLK (PA1), ETH_MDIO (PA2) and ETH_MII_RX_DV (PA7)
Sergunb 0:8918a71cdbe9 265 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 266 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 267
Sergunb 0:8918a71cdbe9 268 //Configure ETH_PPS_OUT (PB5) and ETH_MII_TXD3 (PB8)
Sergunb 0:8918a71cdbe9 269 GPIO_InitStructure.Pin = GPIO_PIN_5 | GPIO_PIN_8;
Sergunb 0:8918a71cdbe9 270 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 271
Sergunb 0:8918a71cdbe9 272 //Configure ETH_MDC (PC1), ETH_MII_TXD2 (PC2), ETH_MII_TX_CLK (PC3),
Sergunb 0:8918a71cdbe9 273 //ETH_MII_RXD0 (PC4) and ETH_MII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 274 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
Sergunb 0:8918a71cdbe9 275 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 276
Sergunb 0:8918a71cdbe9 277 //Configure ETH_MII_TX_EN (PG11), ETH_MII_TXD0 (PG13) and ETH_MII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 278 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
Sergunb 0:8918a71cdbe9 279 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 280
Sergunb 0:8918a71cdbe9 281 //Configure ETH_MII_CRS (PH2), ETH_MII_COL (PH3), ETH_MII_RXD2 (PH6) and ETH_MII_RXD3 (PH7)
Sergunb 0:8918a71cdbe9 282 GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_6 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 283 HAL_GPIO_Init(GPIOH, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 284
Sergunb 0:8918a71cdbe9 285 //Configure ETH_MII_RX_ER (PI10)
Sergunb 0:8918a71cdbe9 286 GPIO_InitStructure.Pin = GPIO_PIN_10;
Sergunb 0:8918a71cdbe9 287 HAL_GPIO_Init(GPIOI, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 288
Sergunb 0:8918a71cdbe9 289 #elif defined(USE_STM324xG_EVAL) && defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 290 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 291 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
Sergunb 0:8918a71cdbe9 292
Sergunb 0:8918a71cdbe9 293 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 294 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
Sergunb 0:8918a71cdbe9 295 RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG |
Sergunb 0:8918a71cdbe9 296 RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI, ENABLE);
Sergunb 0:8918a71cdbe9 297
Sergunb 0:8918a71cdbe9 298 //Configure MCO1 (PA8) as an output
Sergunb 0:8918a71cdbe9 299 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
Sergunb 0:8918a71cdbe9 300 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
Sergunb 0:8918a71cdbe9 301 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
Sergunb 0:8918a71cdbe9 302 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
Sergunb 0:8918a71cdbe9 303 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
Sergunb 0:8918a71cdbe9 304 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 305
Sergunb 0:8918a71cdbe9 306 //Configure MCO1 pin to output the HSE clock (25MHz)
Sergunb 0:8918a71cdbe9 307 RCC_MCO1Config(RCC_MCO1Source_HSE, RCC_MCO1Div_1);
Sergunb 0:8918a71cdbe9 308
Sergunb 0:8918a71cdbe9 309 //Select MII interface mode
Sergunb 0:8918a71cdbe9 310 SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_MII);
Sergunb 0:8918a71cdbe9 311
Sergunb 0:8918a71cdbe9 312 //Configure ETH_MII_RX_CLK (PA1), ETH_MDIO (PA2) and ETH_MII_RX_DV (PA7)
Sergunb 0:8918a71cdbe9 313 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 314 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 315 GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 316 GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 317 GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 318
Sergunb 0:8918a71cdbe9 319 //Configure ETH_PPS_OUT (PB5) and ETH_MII_TXD3 (PB8)
Sergunb 0:8918a71cdbe9 320 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8;
Sergunb 0:8918a71cdbe9 321 GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 322 GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 323 GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 324
Sergunb 0:8918a71cdbe9 325 //Configure ETH_MDC (PC1), ETH_MII_TXD2 (PC2), ETH_MII_TX_CLK (PC3),
Sergunb 0:8918a71cdbe9 326 //ETH_MII_RXD0 (PC4) and ETH_MII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 327 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
Sergunb 0:8918a71cdbe9 328 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 329 GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 330 GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 331 GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 332 GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 333 GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 334
Sergunb 0:8918a71cdbe9 335 //Configure ETH_MII_TX_EN (PG11), ETH_MII_TXD0 (PG13) and ETH_MII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 336 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14;
Sergunb 0:8918a71cdbe9 337 GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 338 GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 339 GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 340 GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 341
Sergunb 0:8918a71cdbe9 342 //Configure ETH_MII_CRS (PH2), ETH_MII_COL (PH3), ETH_MII_RXD2 (PH6) and ETH_MII_RXD3 (PH7)
Sergunb 0:8918a71cdbe9 343 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 344 GPIO_Init(GPIOH, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 345 GPIO_PinAFConfig(GPIOH, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 346 GPIO_PinAFConfig(GPIOH, GPIO_PinSource3, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 347 GPIO_PinAFConfig(GPIOH, GPIO_PinSource6, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 348 GPIO_PinAFConfig(GPIOH, GPIO_PinSource7, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 349
Sergunb 0:8918a71cdbe9 350 //Configure ETH_MII_RX_ER (PI10)
Sergunb 0:8918a71cdbe9 351 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
Sergunb 0:8918a71cdbe9 352 GPIO_Init(GPIOI, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 353 GPIO_PinAFConfig(GPIOI, GPIO_PinSource10, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 354
Sergunb 0:8918a71cdbe9 355 //STM32F4-DISCOVERY evaluation board?
Sergunb 0:8918a71cdbe9 356 #elif defined(USE_STM32F4_DISCOVERY) && defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 357 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 358 __HAL_RCC_SYSCFG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 359
Sergunb 0:8918a71cdbe9 360 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 361 __HAL_RCC_GPIOA_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 362 __HAL_RCC_GPIOB_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 363 __HAL_RCC_GPIOC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 364
Sergunb 0:8918a71cdbe9 365 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 366 SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
Sergunb 0:8918a71cdbe9 367
Sergunb 0:8918a71cdbe9 368 //Configure RMII pins
Sergunb 0:8918a71cdbe9 369 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 370 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 371 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 372 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
Sergunb 0:8918a71cdbe9 373
Sergunb 0:8918a71cdbe9 374 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 375 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 376 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 377
Sergunb 0:8918a71cdbe9 378 //Configure ETH_RMII_TX_EN (PB11), ETH_RMII_TXD0 (PB12) and ETH_RMII_TXD1 (PB13)
Sergunb 0:8918a71cdbe9 379 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
Sergunb 0:8918a71cdbe9 380 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 381
Sergunb 0:8918a71cdbe9 382 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 383 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
Sergunb 0:8918a71cdbe9 384 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 385
Sergunb 0:8918a71cdbe9 386 #elif defined(USE_STM32F4_DISCOVERY) && defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 387 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 388 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
Sergunb 0:8918a71cdbe9 389
Sergunb 0:8918a71cdbe9 390 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 391 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA |
Sergunb 0:8918a71cdbe9 392 RCC_AHB1Periph_GPIOB | RCC_AHB1Periph_GPIOC, ENABLE);
Sergunb 0:8918a71cdbe9 393
Sergunb 0:8918a71cdbe9 394 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 395 SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
Sergunb 0:8918a71cdbe9 396
Sergunb 0:8918a71cdbe9 397 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 398 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 399 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
Sergunb 0:8918a71cdbe9 400 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
Sergunb 0:8918a71cdbe9 401 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
Sergunb 0:8918a71cdbe9 402 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
Sergunb 0:8918a71cdbe9 403 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 404 GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 405 GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 406 GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 407
Sergunb 0:8918a71cdbe9 408 //Configure ETH_RMII_TX_EN (PB11), ETH_RMII_TXD0 (PB12) and ETH_RMII_TXD1 (PB13)
Sergunb 0:8918a71cdbe9 409 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
Sergunb 0:8918a71cdbe9 410 GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 411 GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 412 GPIO_PinAFConfig(GPIOB, GPIO_PinSource12, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 413 GPIO_PinAFConfig(GPIOB, GPIO_PinSource13, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 414
Sergunb 0:8918a71cdbe9 415 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 416 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
Sergunb 0:8918a71cdbe9 417 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 418 GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 419 GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 420 GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 421
Sergunb 0:8918a71cdbe9 422 //MCBSTM32F400 evaluation board?
Sergunb 0:8918a71cdbe9 423 #elif defined(USE_MCBSTM32F400) && defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 424 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 425 __HAL_RCC_SYSCFG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 426
Sergunb 0:8918a71cdbe9 427 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 428 __HAL_RCC_GPIOA_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 429 __HAL_RCC_GPIOC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 430 __HAL_RCC_GPIOG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 431
Sergunb 0:8918a71cdbe9 432 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 433 SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
Sergunb 0:8918a71cdbe9 434
Sergunb 0:8918a71cdbe9 435 //Configure RMII pins
Sergunb 0:8918a71cdbe9 436 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 437 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 438 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 439 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
Sergunb 0:8918a71cdbe9 440
Sergunb 0:8918a71cdbe9 441 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 442 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 443 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 444
Sergunb 0:8918a71cdbe9 445 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 446 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
Sergunb 0:8918a71cdbe9 447 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 448
Sergunb 0:8918a71cdbe9 449 //Configure ETH_RMII_TX_EN (PG11), ETH_RMII_TXD0 (PG13) and ETH_RMII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 450 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
Sergunb 0:8918a71cdbe9 451 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 452
Sergunb 0:8918a71cdbe9 453 #elif defined(USE_MCBSTM32F400) && defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 454 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 455 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
Sergunb 0:8918a71cdbe9 456
Sergunb 0:8918a71cdbe9 457 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 458 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA |
Sergunb 0:8918a71cdbe9 459 RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE);
Sergunb 0:8918a71cdbe9 460
Sergunb 0:8918a71cdbe9 461 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 462 SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
Sergunb 0:8918a71cdbe9 463
Sergunb 0:8918a71cdbe9 464 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 465 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 466 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
Sergunb 0:8918a71cdbe9 467 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
Sergunb 0:8918a71cdbe9 468 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
Sergunb 0:8918a71cdbe9 469 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
Sergunb 0:8918a71cdbe9 470 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 471 GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 472 GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 473 GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 474
Sergunb 0:8918a71cdbe9 475 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 476 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
Sergunb 0:8918a71cdbe9 477 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 478 GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 479 GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 480 GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 481
Sergunb 0:8918a71cdbe9 482 //Configure ETH_RMII_TX_EN (PG11), ETH_RMII_TXD0 (PG13) and ETH_RMII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 483 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14;
Sergunb 0:8918a71cdbe9 484 GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 485 GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 486 GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 487 GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 488
Sergunb 0:8918a71cdbe9 489 //STM32-E407 evaluation board?
Sergunb 0:8918a71cdbe9 490 #elif defined(USE_STM32_E407) && defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 491 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 492 __HAL_RCC_SYSCFG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 493
Sergunb 0:8918a71cdbe9 494 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 495 __HAL_RCC_GPIOA_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 496 __HAL_RCC_GPIOC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 497 __HAL_RCC_GPIOG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 498
Sergunb 0:8918a71cdbe9 499 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 500 SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
Sergunb 0:8918a71cdbe9 501
Sergunb 0:8918a71cdbe9 502 //Configure RMII pins
Sergunb 0:8918a71cdbe9 503 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 504 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 505 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 506 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
Sergunb 0:8918a71cdbe9 507
Sergunb 0:8918a71cdbe9 508 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 509 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 510 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 511
Sergunb 0:8918a71cdbe9 512 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 513 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
Sergunb 0:8918a71cdbe9 514 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 515
Sergunb 0:8918a71cdbe9 516 //Configure ETH_RMII_TX_EN (PG11), ETH_RMII_TXD0 (PG13) and ETH_RMII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 517 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
Sergunb 0:8918a71cdbe9 518 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 519
Sergunb 0:8918a71cdbe9 520 //Configure PHY_RST (PG6)
Sergunb 0:8918a71cdbe9 521 GPIO_InitStructure.GPIO_Pin = Pin = GPIO_PIN_6;
Sergunb 0:8918a71cdbe9 522 GPIO_InitStructure.Mode = GPIO_MODE_OUTPUT_PP;
Sergunb 0:8918a71cdbe9 523 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 524 GPIO_InitStructure.Speed = GPIO_SPEED_LOW;
Sergunb 0:8918a71cdbe9 525 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 526
Sergunb 0:8918a71cdbe9 527 //Reset PHY transceiver
Sergunb 0:8918a71cdbe9 528 HAL_GPIO_WritePin(GPIOG, GPIO_PIN_6, GPIO_PIN_RESET);
Sergunb 0:8918a71cdbe9 529 sleep(10);
Sergunb 0:8918a71cdbe9 530
Sergunb 0:8918a71cdbe9 531 //Take the PHY transceiver out of reset
Sergunb 0:8918a71cdbe9 532 HAL_GPIO_WritePin(GPIOG, GPIO_PIN_6, GPIO_PIN_SET);
Sergunb 0:8918a71cdbe9 533 sleep(10);
Sergunb 0:8918a71cdbe9 534
Sergunb 0:8918a71cdbe9 535 #elif defined(USE_STM32_E407) && defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 536 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 537 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
Sergunb 0:8918a71cdbe9 538
Sergunb 0:8918a71cdbe9 539 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 540 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA |
Sergunb 0:8918a71cdbe9 541 RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE);
Sergunb 0:8918a71cdbe9 542
Sergunb 0:8918a71cdbe9 543 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 544 SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
Sergunb 0:8918a71cdbe9 545
Sergunb 0:8918a71cdbe9 546 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 547 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 548 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
Sergunb 0:8918a71cdbe9 549 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
Sergunb 0:8918a71cdbe9 550 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
Sergunb 0:8918a71cdbe9 551 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
Sergunb 0:8918a71cdbe9 552 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 553 GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 554 GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 555 GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 556
Sergunb 0:8918a71cdbe9 557 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 558 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
Sergunb 0:8918a71cdbe9 559 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 560 GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 561 GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 562 GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 563
Sergunb 0:8918a71cdbe9 564 //Configure ETH_RMII_TX_EN (PG11), ETH_RMII_TXD0 (PG13) and ETH_RMII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 565 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14;
Sergunb 0:8918a71cdbe9 566 GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 567 GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 568 GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 569 GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 570
Sergunb 0:8918a71cdbe9 571 //Configure PHY_RST (PG6)
Sergunb 0:8918a71cdbe9 572 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
Sergunb 0:8918a71cdbe9 573 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 574 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_OUT;
Sergunb 0:8918a71cdbe9 575 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
Sergunb 0:8918a71cdbe9 576 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
Sergunb 0:8918a71cdbe9 577 GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 578
Sergunb 0:8918a71cdbe9 579 //Reset PHY transceiver
Sergunb 0:8918a71cdbe9 580 GPIO_ResetBits(GPIOG, GPIO_Pin_6);
Sergunb 0:8918a71cdbe9 581 sleep(10);
Sergunb 0:8918a71cdbe9 582
Sergunb 0:8918a71cdbe9 583 //Take the PHY transceiver out of reset
Sergunb 0:8918a71cdbe9 584 GPIO_SetBits(GPIOG, GPIO_Pin_6);
Sergunb 0:8918a71cdbe9 585 sleep(10);
Sergunb 0:8918a71cdbe9 586
Sergunb 0:8918a71cdbe9 587 //STM32-P407 evaluation board?
Sergunb 0:8918a71cdbe9 588 #elif defined(USE_STM32_P407) && defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 589 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 590 __HAL_RCC_SYSCFG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 591
Sergunb 0:8918a71cdbe9 592 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 593 __HAL_RCC_GPIOA_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 594 __HAL_RCC_GPIOB_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 595 __HAL_RCC_GPIOC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 596 __HAL_RCC_GPIOG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 597
Sergunb 0:8918a71cdbe9 598 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 599 SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
Sergunb 0:8918a71cdbe9 600
Sergunb 0:8918a71cdbe9 601 //Configure RMII pins
Sergunb 0:8918a71cdbe9 602 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 603 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 604 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 605 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
Sergunb 0:8918a71cdbe9 606
Sergunb 0:8918a71cdbe9 607 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 608 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 609 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 610
Sergunb 0:8918a71cdbe9 611 //Configure ETH_RMII_TX_EN (PB11)
Sergunb 0:8918a71cdbe9 612 GPIO_InitStructure.Pin = GPIO_PIN_11;
Sergunb 0:8918a71cdbe9 613 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 614
Sergunb 0:8918a71cdbe9 615 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 616 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
Sergunb 0:8918a71cdbe9 617 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 618
Sergunb 0:8918a71cdbe9 619 //Configure ETH_RMII_TXD0 (PG13) and ETH_RMII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 620 GPIO_InitStructure.Pin = GPIO_PIN_13 | GPIO_PIN_14;
Sergunb 0:8918a71cdbe9 621 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 622
Sergunb 0:8918a71cdbe9 623 #elif defined(USE_STM32_P407) && defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 624 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 625 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
Sergunb 0:8918a71cdbe9 626
Sergunb 0:8918a71cdbe9 627 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 628 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
Sergunb 0:8918a71cdbe9 629 RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE);
Sergunb 0:8918a71cdbe9 630
Sergunb 0:8918a71cdbe9 631 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 632 SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
Sergunb 0:8918a71cdbe9 633
Sergunb 0:8918a71cdbe9 634 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 635 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 636 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
Sergunb 0:8918a71cdbe9 637 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
Sergunb 0:8918a71cdbe9 638 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
Sergunb 0:8918a71cdbe9 639 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
Sergunb 0:8918a71cdbe9 640 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 641 GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 642 GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 643 GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 644
Sergunb 0:8918a71cdbe9 645 //Configure ETH_RMII_TX_EN (PB11)
Sergunb 0:8918a71cdbe9 646 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11;
Sergunb 0:8918a71cdbe9 647 GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 648 GPIO_PinAFConfig(GPIOB, GPIO_PinSource11, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 649
Sergunb 0:8918a71cdbe9 650 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 651 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
Sergunb 0:8918a71cdbe9 652 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 653 GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 654 GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 655 GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 656
Sergunb 0:8918a71cdbe9 657 //Configure ETH_RMII_TXD0 (PG13) and ETH_RMII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 658 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13 | GPIO_Pin_14;
Sergunb 0:8918a71cdbe9 659 GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 660 GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 661 GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 662 #endif
Sergunb 0:8918a71cdbe9 663 }
Sergunb 0:8918a71cdbe9 664
Sergunb 0:8918a71cdbe9 665 #endif
Sergunb 0:8918a71cdbe9 666
Sergunb 0:8918a71cdbe9 667
Sergunb 0:8918a71cdbe9 668 /**
Sergunb 0:8918a71cdbe9 669 * @brief Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 670 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 671 **/
Sergunb 0:8918a71cdbe9 672
Sergunb 0:8918a71cdbe9 673 void stm32f4x7EthInitDmaDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 674 {
Sergunb 0:8918a71cdbe9 675 uint_t i;
Sergunb 0:8918a71cdbe9 676
Sergunb 0:8918a71cdbe9 677 //Initialize TX DMA descriptor list
Sergunb 0:8918a71cdbe9 678 for(i = 0; i < STM32F4X7_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 679 {
Sergunb 0:8918a71cdbe9 680 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 681 txDmaDesc[i].tdes0 = ETH_TDES0_IC | ETH_TDES0_TCH;
Sergunb 0:8918a71cdbe9 682 //Initialize transmit buffer size
Sergunb 0:8918a71cdbe9 683 txDmaDesc[i].tdes1 = 0;
Sergunb 0:8918a71cdbe9 684 //Transmit buffer address
Sergunb 0:8918a71cdbe9 685 txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 686 //Next descriptor address
Sergunb 0:8918a71cdbe9 687 txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 688 //Reserved fields
Sergunb 0:8918a71cdbe9 689 txDmaDesc[i].tdes4 = 0;
Sergunb 0:8918a71cdbe9 690 txDmaDesc[i].tdes5 = 0;
Sergunb 0:8918a71cdbe9 691 //Transmit frame time stamp
Sergunb 0:8918a71cdbe9 692 txDmaDesc[i].tdes6 = 0;
Sergunb 0:8918a71cdbe9 693 txDmaDesc[i].tdes7 = 0;
Sergunb 0:8918a71cdbe9 694 }
Sergunb 0:8918a71cdbe9 695
Sergunb 0:8918a71cdbe9 696 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 697 txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 698 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 699 txCurDmaDesc = &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 700
Sergunb 0:8918a71cdbe9 701 //Initialize RX DMA descriptor list
Sergunb 0:8918a71cdbe9 702 for(i = 0; i < STM32F4X7_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 703 {
Sergunb 0:8918a71cdbe9 704 //The descriptor is initially owned by the DMA
Sergunb 0:8918a71cdbe9 705 rxDmaDesc[i].rdes0 = ETH_RDES0_OWN;
Sergunb 0:8918a71cdbe9 706 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 707 rxDmaDesc[i].rdes1 = ETH_RDES1_RCH | (STM32F4X7_ETH_RX_BUFFER_SIZE & ETH_RDES1_RBS1);
Sergunb 0:8918a71cdbe9 708 //Receive buffer address
Sergunb 0:8918a71cdbe9 709 rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 710 //Next descriptor address
Sergunb 0:8918a71cdbe9 711 rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 712 //Extended status
Sergunb 0:8918a71cdbe9 713 rxDmaDesc[i].rdes4 = 0;
Sergunb 0:8918a71cdbe9 714 //Reserved field
Sergunb 0:8918a71cdbe9 715 rxDmaDesc[i].rdes5 = 0;
Sergunb 0:8918a71cdbe9 716 //Receive frame time stamp
Sergunb 0:8918a71cdbe9 717 rxDmaDesc[i].rdes6 = 0;
Sergunb 0:8918a71cdbe9 718 rxDmaDesc[i].rdes7 = 0;
Sergunb 0:8918a71cdbe9 719 }
Sergunb 0:8918a71cdbe9 720
Sergunb 0:8918a71cdbe9 721 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 722 rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 723 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 724 rxCurDmaDesc = &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 725
Sergunb 0:8918a71cdbe9 726 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 727 ETH->DMATDLAR = (uint32_t) txDmaDesc;
Sergunb 0:8918a71cdbe9 728 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 729 ETH->DMARDLAR = (uint32_t) rxDmaDesc;
Sergunb 0:8918a71cdbe9 730 }
Sergunb 0:8918a71cdbe9 731
Sergunb 0:8918a71cdbe9 732
Sergunb 0:8918a71cdbe9 733 /**
Sergunb 0:8918a71cdbe9 734 * @brief STM32F407/417/427/437 Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 735 *
Sergunb 0:8918a71cdbe9 736 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 737 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 738 *
Sergunb 0:8918a71cdbe9 739 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 740 **/
Sergunb 0:8918a71cdbe9 741
Sergunb 0:8918a71cdbe9 742 void stm32f4x7EthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 743 {
Sergunb 0:8918a71cdbe9 744 //Handle periodic operations
Sergunb 0:8918a71cdbe9 745 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 746 }
Sergunb 0:8918a71cdbe9 747
Sergunb 0:8918a71cdbe9 748
Sergunb 0:8918a71cdbe9 749 /**
Sergunb 0:8918a71cdbe9 750 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 751 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 752 **/
Sergunb 0:8918a71cdbe9 753
Sergunb 0:8918a71cdbe9 754 void stm32f4x7EthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 755 {
Sergunb 0:8918a71cdbe9 756 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 757 NVIC_EnableIRQ(ETH_IRQn);
Sergunb 0:8918a71cdbe9 758 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 759 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 760 }
Sergunb 0:8918a71cdbe9 761
Sergunb 0:8918a71cdbe9 762
Sergunb 0:8918a71cdbe9 763 /**
Sergunb 0:8918a71cdbe9 764 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 765 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 766 **/
Sergunb 0:8918a71cdbe9 767
Sergunb 0:8918a71cdbe9 768 void stm32f4x7EthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 769 {
Sergunb 0:8918a71cdbe9 770 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 771 NVIC_DisableIRQ(ETH_IRQn);
Sergunb 0:8918a71cdbe9 772 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 773 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 774 }
Sergunb 0:8918a71cdbe9 775
Sergunb 0:8918a71cdbe9 776
Sergunb 0:8918a71cdbe9 777 /**
Sergunb 0:8918a71cdbe9 778 * @brief STM32F407/417/427/437 Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 779 **/
Sergunb 0:8918a71cdbe9 780
Sergunb 0:8918a71cdbe9 781 void ETH_IRQHandler(void)
Sergunb 0:8918a71cdbe9 782 {
Sergunb 0:8918a71cdbe9 783 bool_t flag;
Sergunb 0:8918a71cdbe9 784 uint32_t status;
Sergunb 0:8918a71cdbe9 785
Sergunb 0:8918a71cdbe9 786 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 787 osEnterIsr();
Sergunb 0:8918a71cdbe9 788
Sergunb 0:8918a71cdbe9 789 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 790 flag = FALSE;
Sergunb 0:8918a71cdbe9 791
Sergunb 0:8918a71cdbe9 792 //Read DMA status register
Sergunb 0:8918a71cdbe9 793 status = ETH->DMASR;
Sergunb 0:8918a71cdbe9 794
Sergunb 0:8918a71cdbe9 795 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 796 if(status & ETH_DMASR_TS)
Sergunb 0:8918a71cdbe9 797 {
Sergunb 0:8918a71cdbe9 798 //Clear TS interrupt flag
Sergunb 0:8918a71cdbe9 799 ETH->DMASR = ETH_DMASR_TS;
Sergunb 0:8918a71cdbe9 800
Sergunb 0:8918a71cdbe9 801 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 802 if(!(txCurDmaDesc->tdes0 & ETH_TDES0_OWN))
Sergunb 0:8918a71cdbe9 803 {
Sergunb 0:8918a71cdbe9 804 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 805 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 806 }
Sergunb 0:8918a71cdbe9 807 }
Sergunb 0:8918a71cdbe9 808
Sergunb 0:8918a71cdbe9 809 //A packet has been received?
Sergunb 0:8918a71cdbe9 810 if(status & ETH_DMASR_RS)
Sergunb 0:8918a71cdbe9 811 {
Sergunb 0:8918a71cdbe9 812 //Disable RIE interrupt
Sergunb 0:8918a71cdbe9 813 ETH->DMAIER &= ~ETH_DMAIER_RIE;
Sergunb 0:8918a71cdbe9 814
Sergunb 0:8918a71cdbe9 815 //Set event flag
Sergunb 0:8918a71cdbe9 816 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 817 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 818 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 819 }
Sergunb 0:8918a71cdbe9 820
Sergunb 0:8918a71cdbe9 821 //Clear NIS interrupt flag
Sergunb 0:8918a71cdbe9 822 ETH->DMASR = ETH_DMASR_NIS;
Sergunb 0:8918a71cdbe9 823
Sergunb 0:8918a71cdbe9 824 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 825 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 826 }
Sergunb 0:8918a71cdbe9 827
Sergunb 0:8918a71cdbe9 828
Sergunb 0:8918a71cdbe9 829 /**
Sergunb 0:8918a71cdbe9 830 * @brief STM32F407/417/427/437 Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 831 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 832 **/
Sergunb 0:8918a71cdbe9 833
Sergunb 0:8918a71cdbe9 834 void stm32f4x7EthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 835 {
Sergunb 0:8918a71cdbe9 836 error_t error;
Sergunb 0:8918a71cdbe9 837
Sergunb 0:8918a71cdbe9 838 //Packet received?
Sergunb 0:8918a71cdbe9 839 if(ETH->DMASR & ETH_DMASR_RS)
Sergunb 0:8918a71cdbe9 840 {
Sergunb 0:8918a71cdbe9 841 //Clear interrupt flag
Sergunb 0:8918a71cdbe9 842 ETH->DMASR = ETH_DMASR_RS;
Sergunb 0:8918a71cdbe9 843
Sergunb 0:8918a71cdbe9 844 //Process all pending packets
Sergunb 0:8918a71cdbe9 845 do
Sergunb 0:8918a71cdbe9 846 {
Sergunb 0:8918a71cdbe9 847 //Read incoming packet
Sergunb 0:8918a71cdbe9 848 error = stm32f4x7EthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 849
Sergunb 0:8918a71cdbe9 850 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 851 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 852 }
Sergunb 0:8918a71cdbe9 853
Sergunb 0:8918a71cdbe9 854 //Re-enable DMA interrupts
Sergunb 0:8918a71cdbe9 855 ETH->DMAIER |= ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
Sergunb 0:8918a71cdbe9 856 }
Sergunb 0:8918a71cdbe9 857
Sergunb 0:8918a71cdbe9 858
Sergunb 0:8918a71cdbe9 859 /**
Sergunb 0:8918a71cdbe9 860 * @brief Send a packet
Sergunb 0:8918a71cdbe9 861 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 862 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 863 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 864 * @return Error code
Sergunb 0:8918a71cdbe9 865 **/
Sergunb 0:8918a71cdbe9 866
Sergunb 0:8918a71cdbe9 867 error_t stm32f4x7EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 868 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 869 {
Sergunb 0:8918a71cdbe9 870 size_t length;
Sergunb 0:8918a71cdbe9 871
Sergunb 0:8918a71cdbe9 872 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 873 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 874
Sergunb 0:8918a71cdbe9 875 //Check the frame length
Sergunb 0:8918a71cdbe9 876 if(length > STM32F4X7_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 877 {
Sergunb 0:8918a71cdbe9 878 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 879 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 880 //Report an error
Sergunb 0:8918a71cdbe9 881 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 882 }
Sergunb 0:8918a71cdbe9 883
Sergunb 0:8918a71cdbe9 884 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 885 if(txCurDmaDesc->tdes0 & ETH_TDES0_OWN)
Sergunb 0:8918a71cdbe9 886 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 887
Sergunb 0:8918a71cdbe9 888 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 889 netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
Sergunb 0:8918a71cdbe9 890
Sergunb 0:8918a71cdbe9 891 //Write the number of bytes to send
Sergunb 0:8918a71cdbe9 892 txCurDmaDesc->tdes1 = length & ETH_TDES1_TBS1;
Sergunb 0:8918a71cdbe9 893 //Set LS and FS flags as the data fits in a single buffer
Sergunb 0:8918a71cdbe9 894 txCurDmaDesc->tdes0 |= ETH_TDES0_LS | ETH_TDES0_FS;
Sergunb 0:8918a71cdbe9 895 //Give the ownership of the descriptor to the DMA
Sergunb 0:8918a71cdbe9 896 txCurDmaDesc->tdes0 |= ETH_TDES0_OWN;
Sergunb 0:8918a71cdbe9 897
Sergunb 0:8918a71cdbe9 898 //Clear TBUS flag to resume processing
Sergunb 0:8918a71cdbe9 899 ETH->DMASR = ETH_DMASR_TBUS;
Sergunb 0:8918a71cdbe9 900 //Instruct the DMA to poll the transmit descriptor list
Sergunb 0:8918a71cdbe9 901 ETH->DMATPDR = 0;
Sergunb 0:8918a71cdbe9 902
Sergunb 0:8918a71cdbe9 903 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 904 txCurDmaDesc = (Stm32f4x7TxDmaDesc *) txCurDmaDesc->tdes3;
Sergunb 0:8918a71cdbe9 905
Sergunb 0:8918a71cdbe9 906 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 907 if(!(txCurDmaDesc->tdes0 & ETH_TDES0_OWN))
Sergunb 0:8918a71cdbe9 908 {
Sergunb 0:8918a71cdbe9 909 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 910 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 911 }
Sergunb 0:8918a71cdbe9 912
Sergunb 0:8918a71cdbe9 913 //Data successfully written
Sergunb 0:8918a71cdbe9 914 return NO_ERROR;
Sergunb 0:8918a71cdbe9 915 }
Sergunb 0:8918a71cdbe9 916
Sergunb 0:8918a71cdbe9 917
Sergunb 0:8918a71cdbe9 918 /**
Sergunb 0:8918a71cdbe9 919 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 920 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 921 * @return Error code
Sergunb 0:8918a71cdbe9 922 **/
Sergunb 0:8918a71cdbe9 923
Sergunb 0:8918a71cdbe9 924 error_t stm32f4x7EthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 925 {
Sergunb 0:8918a71cdbe9 926 error_t error;
Sergunb 0:8918a71cdbe9 927 size_t n;
Sergunb 0:8918a71cdbe9 928
Sergunb 0:8918a71cdbe9 929 //The current buffer is available for reading?
Sergunb 0:8918a71cdbe9 930 if(!(rxCurDmaDesc->rdes0 & ETH_RDES0_OWN))
Sergunb 0:8918a71cdbe9 931 {
Sergunb 0:8918a71cdbe9 932 //FS and LS flags should be set
Sergunb 0:8918a71cdbe9 933 if((rxCurDmaDesc->rdes0 & ETH_RDES0_FS) && (rxCurDmaDesc->rdes0 & ETH_RDES0_LS))
Sergunb 0:8918a71cdbe9 934 {
Sergunb 0:8918a71cdbe9 935 //Make sure no error occurred
Sergunb 0:8918a71cdbe9 936 if(!(rxCurDmaDesc->rdes0 & ETH_RDES0_ES))
Sergunb 0:8918a71cdbe9 937 {
Sergunb 0:8918a71cdbe9 938 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 939 n = (rxCurDmaDesc->rdes0 & ETH_RDES0_FL) >> 16;
Sergunb 0:8918a71cdbe9 940 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 941 n = MIN(n, STM32F4X7_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 942
Sergunb 0:8918a71cdbe9 943 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 944 nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n);
Sergunb 0:8918a71cdbe9 945
Sergunb 0:8918a71cdbe9 946 //Valid packet received
Sergunb 0:8918a71cdbe9 947 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 948 }
Sergunb 0:8918a71cdbe9 949 else
Sergunb 0:8918a71cdbe9 950 {
Sergunb 0:8918a71cdbe9 951 //The received packet contains an error
Sergunb 0:8918a71cdbe9 952 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 953 }
Sergunb 0:8918a71cdbe9 954 }
Sergunb 0:8918a71cdbe9 955 else
Sergunb 0:8918a71cdbe9 956 {
Sergunb 0:8918a71cdbe9 957 //The packet is not valid
Sergunb 0:8918a71cdbe9 958 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 959 }
Sergunb 0:8918a71cdbe9 960
Sergunb 0:8918a71cdbe9 961 //Give the ownership of the descriptor back to the DMA
Sergunb 0:8918a71cdbe9 962 rxCurDmaDesc->rdes0 = ETH_RDES0_OWN;
Sergunb 0:8918a71cdbe9 963 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 964 rxCurDmaDesc = (Stm32f4x7RxDmaDesc *) rxCurDmaDesc->rdes3;
Sergunb 0:8918a71cdbe9 965 }
Sergunb 0:8918a71cdbe9 966 else
Sergunb 0:8918a71cdbe9 967 {
Sergunb 0:8918a71cdbe9 968 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 969 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 970 }
Sergunb 0:8918a71cdbe9 971
Sergunb 0:8918a71cdbe9 972 //Clear RBUS flag to resume processing
Sergunb 0:8918a71cdbe9 973 ETH->DMASR = ETH_DMASR_RBUS;
Sergunb 0:8918a71cdbe9 974 //Instruct the DMA to poll the receive descriptor list
Sergunb 0:8918a71cdbe9 975 ETH->DMARPDR = 0;
Sergunb 0:8918a71cdbe9 976
Sergunb 0:8918a71cdbe9 977 //Return status code
Sergunb 0:8918a71cdbe9 978 return error;
Sergunb 0:8918a71cdbe9 979 }
Sergunb 0:8918a71cdbe9 980
Sergunb 0:8918a71cdbe9 981
Sergunb 0:8918a71cdbe9 982 /**
Sergunb 0:8918a71cdbe9 983 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 984 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 985 * @return Error code
Sergunb 0:8918a71cdbe9 986 **/
Sergunb 0:8918a71cdbe9 987
Sergunb 0:8918a71cdbe9 988 error_t stm32f4x7EthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 989 {
Sergunb 0:8918a71cdbe9 990 uint_t i;
Sergunb 0:8918a71cdbe9 991 uint_t k;
Sergunb 0:8918a71cdbe9 992 uint32_t crc;
Sergunb 0:8918a71cdbe9 993 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 994 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 995
Sergunb 0:8918a71cdbe9 996 //Debug message
Sergunb 0:8918a71cdbe9 997 TRACE_DEBUG("Updating STM32F4x7 hash table...\r\n");
Sergunb 0:8918a71cdbe9 998
Sergunb 0:8918a71cdbe9 999 //Clear hash table
Sergunb 0:8918a71cdbe9 1000 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 1001 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 1002
Sergunb 0:8918a71cdbe9 1003 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 1004 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 1005 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 1006 {
Sergunb 0:8918a71cdbe9 1007 //Point to the current entry
Sergunb 0:8918a71cdbe9 1008 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 1009
Sergunb 0:8918a71cdbe9 1010 //Valid entry?
Sergunb 0:8918a71cdbe9 1011 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 1012 {
Sergunb 0:8918a71cdbe9 1013 //Compute CRC over the current MAC address
Sergunb 0:8918a71cdbe9 1014 crc = stm32f4x7EthCalcCrc(&entry->addr, sizeof(MacAddr));
Sergunb 0:8918a71cdbe9 1015
Sergunb 0:8918a71cdbe9 1016 //The upper 6 bits in the CRC register are used to index the
Sergunb 0:8918a71cdbe9 1017 //contents of the hash table
Sergunb 0:8918a71cdbe9 1018 k = (crc >> 26) & 0x3F;
Sergunb 0:8918a71cdbe9 1019
Sergunb 0:8918a71cdbe9 1020 //Update hash table contents
Sergunb 0:8918a71cdbe9 1021 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 1022 }
Sergunb 0:8918a71cdbe9 1023 }
Sergunb 0:8918a71cdbe9 1024
Sergunb 0:8918a71cdbe9 1025 //Write the hash table
Sergunb 0:8918a71cdbe9 1026 ETH->MACHTLR = hashTable[0];
Sergunb 0:8918a71cdbe9 1027 ETH->MACHTHR = hashTable[1];
Sergunb 0:8918a71cdbe9 1028
Sergunb 0:8918a71cdbe9 1029 //Debug message
Sergunb 0:8918a71cdbe9 1030 TRACE_DEBUG(" MACHTLR = %08" PRIX32 "\r\n", ETH->MACHTLR);
Sergunb 0:8918a71cdbe9 1031 TRACE_DEBUG(" MACHTHR = %08" PRIX32 "\r\n", ETH->MACHTHR);
Sergunb 0:8918a71cdbe9 1032
Sergunb 0:8918a71cdbe9 1033 //Successful processing
Sergunb 0:8918a71cdbe9 1034 return NO_ERROR;
Sergunb 0:8918a71cdbe9 1035 }
Sergunb 0:8918a71cdbe9 1036
Sergunb 0:8918a71cdbe9 1037
Sergunb 0:8918a71cdbe9 1038 /**
Sergunb 0:8918a71cdbe9 1039 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 1040 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 1041 * @return Error code
Sergunb 0:8918a71cdbe9 1042 **/
Sergunb 0:8918a71cdbe9 1043
Sergunb 0:8918a71cdbe9 1044 error_t stm32f4x7EthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 1045 {
Sergunb 0:8918a71cdbe9 1046 uint32_t config;
Sergunb 0:8918a71cdbe9 1047
Sergunb 0:8918a71cdbe9 1048 //Read current MAC configuration
Sergunb 0:8918a71cdbe9 1049 config = ETH->MACCR;
Sergunb 0:8918a71cdbe9 1050
Sergunb 0:8918a71cdbe9 1051 //10BASE-T or 100BASE-TX operation mode?
Sergunb 0:8918a71cdbe9 1052 if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
Sergunb 0:8918a71cdbe9 1053 config |= ETH_MACCR_FES;
Sergunb 0:8918a71cdbe9 1054 else
Sergunb 0:8918a71cdbe9 1055 config &= ~ETH_MACCR_FES;
Sergunb 0:8918a71cdbe9 1056
Sergunb 0:8918a71cdbe9 1057 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 1058 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 1059 config |= ETH_MACCR_DM;
Sergunb 0:8918a71cdbe9 1060 else
Sergunb 0:8918a71cdbe9 1061 config &= ~ETH_MACCR_DM;
Sergunb 0:8918a71cdbe9 1062
Sergunb 0:8918a71cdbe9 1063 //Update MAC configuration register
Sergunb 0:8918a71cdbe9 1064 ETH->MACCR = config;
Sergunb 0:8918a71cdbe9 1065
Sergunb 0:8918a71cdbe9 1066 //Successful processing
Sergunb 0:8918a71cdbe9 1067 return NO_ERROR;
Sergunb 0:8918a71cdbe9 1068 }
Sergunb 0:8918a71cdbe9 1069
Sergunb 0:8918a71cdbe9 1070
Sergunb 0:8918a71cdbe9 1071 /**
Sergunb 0:8918a71cdbe9 1072 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 1073 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 1074 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 1075 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 1076 **/
Sergunb 0:8918a71cdbe9 1077
Sergunb 0:8918a71cdbe9 1078 void stm32f4x7EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 1079 {
Sergunb 0:8918a71cdbe9 1080 uint32_t value;
Sergunb 0:8918a71cdbe9 1081
Sergunb 0:8918a71cdbe9 1082 //Take care not to alter MDC clock configuration
Sergunb 0:8918a71cdbe9 1083 value = ETH->MACMIIAR & ETH_MACMIIAR_CR;
Sergunb 0:8918a71cdbe9 1084 //Set up a write operation
Sergunb 0:8918a71cdbe9 1085 value |= ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
Sergunb 0:8918a71cdbe9 1086 //PHY address
Sergunb 0:8918a71cdbe9 1087 value |= (phyAddr << 11) & ETH_MACMIIAR_PA;
Sergunb 0:8918a71cdbe9 1088 //Register address
Sergunb 0:8918a71cdbe9 1089 value |= (regAddr << 6) & ETH_MACMIIAR_MR;
Sergunb 0:8918a71cdbe9 1090
Sergunb 0:8918a71cdbe9 1091 //Data to be written in the PHY register
Sergunb 0:8918a71cdbe9 1092 ETH->MACMIIDR = data & ETH_MACMIIDR_MD;
Sergunb 0:8918a71cdbe9 1093
Sergunb 0:8918a71cdbe9 1094 //Start a write operation
Sergunb 0:8918a71cdbe9 1095 ETH->MACMIIAR = value;
Sergunb 0:8918a71cdbe9 1096 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 1097 while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
Sergunb 0:8918a71cdbe9 1098 }
Sergunb 0:8918a71cdbe9 1099
Sergunb 0:8918a71cdbe9 1100
Sergunb 0:8918a71cdbe9 1101 /**
Sergunb 0:8918a71cdbe9 1102 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 1103 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 1104 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 1105 * @return Register value
Sergunb 0:8918a71cdbe9 1106 **/
Sergunb 0:8918a71cdbe9 1107
Sergunb 0:8918a71cdbe9 1108 uint16_t stm32f4x7EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 1109 {
Sergunb 0:8918a71cdbe9 1110 uint32_t value;
Sergunb 0:8918a71cdbe9 1111
Sergunb 0:8918a71cdbe9 1112 //Take care not to alter MDC clock configuration
Sergunb 0:8918a71cdbe9 1113 value = ETH->MACMIIAR & ETH_MACMIIAR_CR;
Sergunb 0:8918a71cdbe9 1114 //Set up a read operation
Sergunb 0:8918a71cdbe9 1115 value |= ETH_MACMIIAR_MB;
Sergunb 0:8918a71cdbe9 1116 //PHY address
Sergunb 0:8918a71cdbe9 1117 value |= (phyAddr << 11) & ETH_MACMIIAR_PA;
Sergunb 0:8918a71cdbe9 1118 //Register address
Sergunb 0:8918a71cdbe9 1119 value |= (regAddr << 6) & ETH_MACMIIAR_MR;
Sergunb 0:8918a71cdbe9 1120
Sergunb 0:8918a71cdbe9 1121 //Start a read operation
Sergunb 0:8918a71cdbe9 1122 ETH->MACMIIAR = value;
Sergunb 0:8918a71cdbe9 1123 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 1124 while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
Sergunb 0:8918a71cdbe9 1125
Sergunb 0:8918a71cdbe9 1126 //Return PHY register contents
Sergunb 0:8918a71cdbe9 1127 return ETH->MACMIIDR & ETH_MACMIIDR_MD;
Sergunb 0:8918a71cdbe9 1128 }
Sergunb 0:8918a71cdbe9 1129
Sergunb 0:8918a71cdbe9 1130
Sergunb 0:8918a71cdbe9 1131 /**
Sergunb 0:8918a71cdbe9 1132 * @brief CRC calculation
Sergunb 0:8918a71cdbe9 1133 * @param[in] data Pointer to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 1134 * @param[in] length Number of bytes to process
Sergunb 0:8918a71cdbe9 1135 * @return Resulting CRC value
Sergunb 0:8918a71cdbe9 1136 **/
Sergunb 0:8918a71cdbe9 1137
Sergunb 0:8918a71cdbe9 1138 uint32_t stm32f4x7EthCalcCrc(const void *data, size_t length)
Sergunb 0:8918a71cdbe9 1139 {
Sergunb 0:8918a71cdbe9 1140 uint_t i;
Sergunb 0:8918a71cdbe9 1141 uint_t j;
Sergunb 0:8918a71cdbe9 1142
Sergunb 0:8918a71cdbe9 1143 //Point to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 1144 const uint8_t *p = (uint8_t *) data;
Sergunb 0:8918a71cdbe9 1145 //CRC preset value
Sergunb 0:8918a71cdbe9 1146 uint32_t crc = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 1147
Sergunb 0:8918a71cdbe9 1148 //Loop through data
Sergunb 0:8918a71cdbe9 1149 for(i = 0; i < length; i++)
Sergunb 0:8918a71cdbe9 1150 {
Sergunb 0:8918a71cdbe9 1151 //The message is processed bit by bit
Sergunb 0:8918a71cdbe9 1152 for(j = 0; j < 8; j++)
Sergunb 0:8918a71cdbe9 1153 {
Sergunb 0:8918a71cdbe9 1154 //Update CRC value
Sergunb 0:8918a71cdbe9 1155 if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
Sergunb 0:8918a71cdbe9 1156 crc = (crc << 1) ^ 0x04C11DB7;
Sergunb 0:8918a71cdbe9 1157 else
Sergunb 0:8918a71cdbe9 1158 crc = crc << 1;
Sergunb 0:8918a71cdbe9 1159 }
Sergunb 0:8918a71cdbe9 1160 }
Sergunb 0:8918a71cdbe9 1161
Sergunb 0:8918a71cdbe9 1162 //Return CRC value
Sergunb 0:8918a71cdbe9 1163 return ~crc;
Sergunb 0:8918a71cdbe9 1164 }
Sergunb 0:8918a71cdbe9 1165