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cyclone_tcp/drivers/stm32f2x7_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file stm32f2x7_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief STM32F207/217 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "stm32f2xx.h"
Sergunb 0:8918a71cdbe9 34 #include "core/net.h"
Sergunb 0:8918a71cdbe9 35 #include "drivers/stm32f2x7_eth.h"
Sergunb 0:8918a71cdbe9 36 #include "debug.h"
Sergunb 0:8918a71cdbe9 37
Sergunb 0:8918a71cdbe9 38 //Underlying network interface
Sergunb 0:8918a71cdbe9 39 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 40
Sergunb 0:8918a71cdbe9 41 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 42 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 43
Sergunb 0:8918a71cdbe9 44 //Transmit buffer
Sergunb 0:8918a71cdbe9 45 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 46 static uint8_t txBuffer[STM32F2X7_ETH_TX_BUFFER_COUNT][STM32F2X7_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 47 //Receive buffer
Sergunb 0:8918a71cdbe9 48 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 49 static uint8_t rxBuffer[STM32F2X7_ETH_RX_BUFFER_COUNT][STM32F2X7_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 50 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 51 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 52 static Stm32f2x7TxDmaDesc txDmaDesc[STM32F2X7_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 53 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 54 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 55 static Stm32f2x7RxDmaDesc rxDmaDesc[STM32F2X7_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 56
Sergunb 0:8918a71cdbe9 57 //Keil MDK-ARM or GCC compiler?
Sergunb 0:8918a71cdbe9 58 #else
Sergunb 0:8918a71cdbe9 59
Sergunb 0:8918a71cdbe9 60 //Transmit buffer
Sergunb 0:8918a71cdbe9 61 static uint8_t txBuffer[STM32F2X7_ETH_TX_BUFFER_COUNT][STM32F2X7_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 62 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 63 //Receive buffer
Sergunb 0:8918a71cdbe9 64 static uint8_t rxBuffer[STM32F2X7_ETH_RX_BUFFER_COUNT][STM32F2X7_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 65 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 66 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 67 static Stm32f2x7TxDmaDesc txDmaDesc[STM32F2X7_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 68 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 69 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 70 static Stm32f2x7RxDmaDesc rxDmaDesc[STM32F2X7_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 71 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 72
Sergunb 0:8918a71cdbe9 73 #endif
Sergunb 0:8918a71cdbe9 74
Sergunb 0:8918a71cdbe9 75 //Pointer to the current TX DMA descriptor
Sergunb 0:8918a71cdbe9 76 static Stm32f2x7TxDmaDesc *txCurDmaDesc;
Sergunb 0:8918a71cdbe9 77 //Pointer to the current RX DMA descriptor
Sergunb 0:8918a71cdbe9 78 static Stm32f2x7RxDmaDesc *rxCurDmaDesc;
Sergunb 0:8918a71cdbe9 79
Sergunb 0:8918a71cdbe9 80
Sergunb 0:8918a71cdbe9 81 /**
Sergunb 0:8918a71cdbe9 82 * @brief STM32F207/217 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 83 **/
Sergunb 0:8918a71cdbe9 84
Sergunb 0:8918a71cdbe9 85 const NicDriver stm32f2x7EthDriver =
Sergunb 0:8918a71cdbe9 86 {
Sergunb 0:8918a71cdbe9 87 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 88 ETH_MTU,
Sergunb 0:8918a71cdbe9 89 stm32f2x7EthInit,
Sergunb 0:8918a71cdbe9 90 stm32f2x7EthTick,
Sergunb 0:8918a71cdbe9 91 stm32f2x7EthEnableIrq,
Sergunb 0:8918a71cdbe9 92 stm32f2x7EthDisableIrq,
Sergunb 0:8918a71cdbe9 93 stm32f2x7EthEventHandler,
Sergunb 0:8918a71cdbe9 94 stm32f2x7EthSendPacket,
Sergunb 0:8918a71cdbe9 95 stm32f2x7EthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 96 stm32f2x7EthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 97 stm32f2x7EthWritePhyReg,
Sergunb 0:8918a71cdbe9 98 stm32f2x7EthReadPhyReg,
Sergunb 0:8918a71cdbe9 99 TRUE,
Sergunb 0:8918a71cdbe9 100 TRUE,
Sergunb 0:8918a71cdbe9 101 TRUE,
Sergunb 0:8918a71cdbe9 102 FALSE
Sergunb 0:8918a71cdbe9 103 };
Sergunb 0:8918a71cdbe9 104
Sergunb 0:8918a71cdbe9 105
Sergunb 0:8918a71cdbe9 106 /**
Sergunb 0:8918a71cdbe9 107 * @brief STM32F207/217 Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 108 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 109 * @return Error code
Sergunb 0:8918a71cdbe9 110 **/
Sergunb 0:8918a71cdbe9 111
Sergunb 0:8918a71cdbe9 112 error_t stm32f2x7EthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 113 {
Sergunb 0:8918a71cdbe9 114 error_t error;
Sergunb 0:8918a71cdbe9 115
Sergunb 0:8918a71cdbe9 116 //Debug message
Sergunb 0:8918a71cdbe9 117 TRACE_INFO("Initializing STM32F2x7 Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 118
Sergunb 0:8918a71cdbe9 119 //Save underlying network interface
Sergunb 0:8918a71cdbe9 120 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 121
Sergunb 0:8918a71cdbe9 122 //GPIO configuration
Sergunb 0:8918a71cdbe9 123 stm32f2x7EthInitGpio(interface);
Sergunb 0:8918a71cdbe9 124
Sergunb 0:8918a71cdbe9 125 #if defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 126 //Enable Ethernet MAC clock
Sergunb 0:8918a71cdbe9 127 __HAL_RCC_ETHMAC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 128 __HAL_RCC_ETHMACTX_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 129 __HAL_RCC_ETHMACRX_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 130
Sergunb 0:8918a71cdbe9 131 //Reset Ethernet MAC peripheral
Sergunb 0:8918a71cdbe9 132 __HAL_RCC_ETHMAC_FORCE_RESET();
Sergunb 0:8918a71cdbe9 133 __HAL_RCC_ETHMAC_RELEASE_RESET();
Sergunb 0:8918a71cdbe9 134
Sergunb 0:8918a71cdbe9 135 #elif defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 136 //Enable Ethernet MAC clock
Sergunb 0:8918a71cdbe9 137 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC |
Sergunb 0:8918a71cdbe9 138 RCC_AHB1Periph_ETH_MAC_Tx | RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);
Sergunb 0:8918a71cdbe9 139
Sergunb 0:8918a71cdbe9 140 //Reset Ethernet MAC peripheral
Sergunb 0:8918a71cdbe9 141 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, ENABLE);
Sergunb 0:8918a71cdbe9 142 RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_ETH_MAC, DISABLE);
Sergunb 0:8918a71cdbe9 143 #endif
Sergunb 0:8918a71cdbe9 144
Sergunb 0:8918a71cdbe9 145 //Perform a software reset
Sergunb 0:8918a71cdbe9 146 ETH->DMABMR |= ETH_DMABMR_SR;
Sergunb 0:8918a71cdbe9 147 //Wait for the reset to complete
Sergunb 0:8918a71cdbe9 148 while(ETH->DMABMR & ETH_DMABMR_SR);
Sergunb 0:8918a71cdbe9 149
Sergunb 0:8918a71cdbe9 150 //Adjust MDC clock range depending on HCLK frequency
Sergunb 0:8918a71cdbe9 151 ETH->MACMIIAR = ETH_MACMIIAR_CR_Div62;
Sergunb 0:8918a71cdbe9 152
Sergunb 0:8918a71cdbe9 153 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 154 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 155 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 156 if(error)
Sergunb 0:8918a71cdbe9 157 return error;
Sergunb 0:8918a71cdbe9 158
Sergunb 0:8918a71cdbe9 159 //Use default MAC configuration
Sergunb 0:8918a71cdbe9 160 ETH->MACCR = ETH_MACCR_ROD;
Sergunb 0:8918a71cdbe9 161
Sergunb 0:8918a71cdbe9 162 //Set the MAC address
Sergunb 0:8918a71cdbe9 163 ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 164 ETH->MACA0HR = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 165
Sergunb 0:8918a71cdbe9 166 //Initialize hash table
Sergunb 0:8918a71cdbe9 167 ETH->MACHTLR = 0;
Sergunb 0:8918a71cdbe9 168 ETH->MACHTHR = 0;
Sergunb 0:8918a71cdbe9 169
Sergunb 0:8918a71cdbe9 170 //Configure the receive filter
Sergunb 0:8918a71cdbe9 171 ETH->MACFFR = ETH_MACFFR_HPF | ETH_MACFFR_HM;
Sergunb 0:8918a71cdbe9 172 //Disable flow control
Sergunb 0:8918a71cdbe9 173 ETH->MACFCR = 0;
Sergunb 0:8918a71cdbe9 174 //Enable store and forward mode
Sergunb 0:8918a71cdbe9 175 ETH->DMAOMR = ETH_DMAOMR_RSF | ETH_DMAOMR_TSF;
Sergunb 0:8918a71cdbe9 176
Sergunb 0:8918a71cdbe9 177 //Configure DMA bus mode
Sergunb 0:8918a71cdbe9 178 ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_USP | ETH_DMABMR_RDP_1Beat |
Sergunb 0:8918a71cdbe9 179 ETH_DMABMR_RTPR_1_1 | ETH_DMABMR_PBL_1Beat | ETH_DMABMR_EDE;
Sergunb 0:8918a71cdbe9 180
Sergunb 0:8918a71cdbe9 181 //Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 182 stm32f2x7EthInitDmaDesc(interface);
Sergunb 0:8918a71cdbe9 183
Sergunb 0:8918a71cdbe9 184 //Prevent interrupts from being generated when the transmit statistic
Sergunb 0:8918a71cdbe9 185 //counters reach half their maximum value
Sergunb 0:8918a71cdbe9 186 ETH->MMCTIMR = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | ETH_MMCTIMR_TGFSCM;
Sergunb 0:8918a71cdbe9 187
Sergunb 0:8918a71cdbe9 188 //Prevent interrupts from being generated when the receive statistic
Sergunb 0:8918a71cdbe9 189 //counters reach half their maximum value
Sergunb 0:8918a71cdbe9 190 ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM;
Sergunb 0:8918a71cdbe9 191
Sergunb 0:8918a71cdbe9 192 //Disable MAC interrupts
Sergunb 0:8918a71cdbe9 193 ETH->MACIMR = ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM;
Sergunb 0:8918a71cdbe9 194 //Enable the desired DMA interrupts
Sergunb 0:8918a71cdbe9 195 ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
Sergunb 0:8918a71cdbe9 196
Sergunb 0:8918a71cdbe9 197 //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
Sergunb 0:8918a71cdbe9 198 NVIC_SetPriorityGrouping(STM32F2X7_ETH_IRQ_PRIORITY_GROUPING);
Sergunb 0:8918a71cdbe9 199
Sergunb 0:8918a71cdbe9 200 //Configure Ethernet interrupt priority
Sergunb 0:8918a71cdbe9 201 NVIC_SetPriority(ETH_IRQn, NVIC_EncodePriority(STM32F2X7_ETH_IRQ_PRIORITY_GROUPING,
Sergunb 0:8918a71cdbe9 202 STM32F2X7_ETH_IRQ_GROUP_PRIORITY, STM32F2X7_ETH_IRQ_SUB_PRIORITY));
Sergunb 0:8918a71cdbe9 203
Sergunb 0:8918a71cdbe9 204 //Enable MAC transmission and reception
Sergunb 0:8918a71cdbe9 205 ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
Sergunb 0:8918a71cdbe9 206 //Enable DMA transmission and reception
Sergunb 0:8918a71cdbe9 207 ETH->DMAOMR |= ETH_DMAOMR_ST | ETH_DMAOMR_SR;
Sergunb 0:8918a71cdbe9 208
Sergunb 0:8918a71cdbe9 209 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 210 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 211
Sergunb 0:8918a71cdbe9 212 //Successful initialization
Sergunb 0:8918a71cdbe9 213 return NO_ERROR;
Sergunb 0:8918a71cdbe9 214 }
Sergunb 0:8918a71cdbe9 215
Sergunb 0:8918a71cdbe9 216
Sergunb 0:8918a71cdbe9 217 //STM3220G-EVAL, MCBSTM32F200 or Nucleo-F207ZG evaluation board?
Sergunb 0:8918a71cdbe9 218 #if defined(USE_STM322xG_EVAL) || defined(USE_MCBSTM32F200) || \
Sergunb 0:8918a71cdbe9 219 defined(USE_STM32F2XX_NUCLEO_144)
Sergunb 0:8918a71cdbe9 220
Sergunb 0:8918a71cdbe9 221 /**
Sergunb 0:8918a71cdbe9 222 * @brief GPIO configuration
Sergunb 0:8918a71cdbe9 223 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 224 **/
Sergunb 0:8918a71cdbe9 225
Sergunb 0:8918a71cdbe9 226 void stm32f2x7EthInitGpio(NetInterface *interface)
Sergunb 0:8918a71cdbe9 227 {
Sergunb 0:8918a71cdbe9 228 GPIO_InitTypeDef GPIO_InitStructure;
Sergunb 0:8918a71cdbe9 229
Sergunb 0:8918a71cdbe9 230 //STM3220G-EVAL evaluation board?
Sergunb 0:8918a71cdbe9 231 #if defined(USE_STM322xG_EVAL) && defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 232 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 233 __HAL_RCC_SYSCFG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 234
Sergunb 0:8918a71cdbe9 235 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 236 __HAL_RCC_GPIOA_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 237 __HAL_RCC_GPIOB_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 238 __HAL_RCC_GPIOC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 239 __HAL_RCC_GPIOG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 240 __HAL_RCC_GPIOH_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 241 __HAL_RCC_GPIOI_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 242
Sergunb 0:8918a71cdbe9 243 //Configure MCO1 (PA8) as an output
Sergunb 0:8918a71cdbe9 244 GPIO_InitStructure.Pin = GPIO_PIN_8;
Sergunb 0:8918a71cdbe9 245 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 246 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 247 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 248 GPIO_InitStructure.Alternate = GPIO_AF0_MCO;
Sergunb 0:8918a71cdbe9 249 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 250
Sergunb 0:8918a71cdbe9 251 //Configure MCO1 pin to output the HSE clock (25MHz)
Sergunb 0:8918a71cdbe9 252 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1);
Sergunb 0:8918a71cdbe9 253
Sergunb 0:8918a71cdbe9 254 //Select MII interface mode
Sergunb 0:8918a71cdbe9 255 SYSCFG->PMC &= ~SYSCFG_PMC_MII_RMII_SEL;
Sergunb 0:8918a71cdbe9 256
Sergunb 0:8918a71cdbe9 257 //Configure MII pins
Sergunb 0:8918a71cdbe9 258 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 259 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 260 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 261 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
Sergunb 0:8918a71cdbe9 262
Sergunb 0:8918a71cdbe9 263 //Configure ETH_MII_RX_CLK (PA1), ETH_MDIO (PA2) and ETH_MII_RX_DV (PA7)
Sergunb 0:8918a71cdbe9 264 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 265 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 266
Sergunb 0:8918a71cdbe9 267 //Configure ETH_PPS_OUT (PB5) and ETH_MII_TXD3 (PB8)
Sergunb 0:8918a71cdbe9 268 GPIO_InitStructure.Pin = GPIO_PIN_5 | GPIO_PIN_8;
Sergunb 0:8918a71cdbe9 269 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 270
Sergunb 0:8918a71cdbe9 271 //Configure ETH_MDC (PC1), ETH_MII_TXD2 (PC2), ETH_MII_TX_CLK (PC3),
Sergunb 0:8918a71cdbe9 272 //ETH_MII_RXD0 (PC4) and ETH_MII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 273 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5;
Sergunb 0:8918a71cdbe9 274 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 275
Sergunb 0:8918a71cdbe9 276 //Configure ETH_MII_TX_EN (PG11), ETH_MII_TXD0 (PG13) and ETH_MII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 277 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
Sergunb 0:8918a71cdbe9 278 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 279
Sergunb 0:8918a71cdbe9 280 //Configure ETH_MII_CRS (PH2), ETH_MII_COL (PH3), ETH_MII_RXD2 (PH6) and ETH_MII_RXD3 (PH7)
Sergunb 0:8918a71cdbe9 281 GPIO_InitStructure.Pin = GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_6 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 282 HAL_GPIO_Init(GPIOH, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 283
Sergunb 0:8918a71cdbe9 284 //Configure ETH_MII_RX_ER (PI10)
Sergunb 0:8918a71cdbe9 285 GPIO_InitStructure.Pin = GPIO_PIN_10;
Sergunb 0:8918a71cdbe9 286 HAL_GPIO_Init(GPIOI, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 287
Sergunb 0:8918a71cdbe9 288 #elif defined(USE_STM322xG_EVAL) && defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 289 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 290 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
Sergunb 0:8918a71cdbe9 291
Sergunb 0:8918a71cdbe9 292 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 293 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA | RCC_AHB1Periph_GPIOB |
Sergunb 0:8918a71cdbe9 294 RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG |
Sergunb 0:8918a71cdbe9 295 RCC_AHB1Periph_GPIOH | RCC_AHB1Periph_GPIOI, ENABLE);
Sergunb 0:8918a71cdbe9 296
Sergunb 0:8918a71cdbe9 297 //Configure MCO1 (PA8) as an output
Sergunb 0:8918a71cdbe9 298 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
Sergunb 0:8918a71cdbe9 299 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
Sergunb 0:8918a71cdbe9 300 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
Sergunb 0:8918a71cdbe9 301 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
Sergunb 0:8918a71cdbe9 302 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
Sergunb 0:8918a71cdbe9 303 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 304
Sergunb 0:8918a71cdbe9 305 //Configure MCO1 pin to output the HSE clock (25MHz)
Sergunb 0:8918a71cdbe9 306 RCC_MCO1Config(RCC_MCO1Source_HSE, RCC_MCO1Div_1);
Sergunb 0:8918a71cdbe9 307
Sergunb 0:8918a71cdbe9 308 //Select MII interface mode
Sergunb 0:8918a71cdbe9 309 SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_MII);
Sergunb 0:8918a71cdbe9 310
Sergunb 0:8918a71cdbe9 311 //Configure ETH_MII_RX_CLK (PA1), ETH_MDIO (PA2) and ETH_MII_RX_DV (PA7)
Sergunb 0:8918a71cdbe9 312 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 313 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 314 GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 315 GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 316 GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 317
Sergunb 0:8918a71cdbe9 318 //Configure ETH_PPS_OUT (PB5) and ETH_MII_TXD3 (PB8)
Sergunb 0:8918a71cdbe9 319 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8;
Sergunb 0:8918a71cdbe9 320 GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 321 GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 322 GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 323
Sergunb 0:8918a71cdbe9 324 //Configure ETH_MDC (PC1), ETH_MII_TXD2 (PC2), ETH_MII_TX_CLK (PC3),
Sergunb 0:8918a71cdbe9 325 //ETH_MII_RXD0 (PC4) and ETH_MII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 326 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;
Sergunb 0:8918a71cdbe9 327 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 328 GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 329 GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 330 GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 331 GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 332 GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 333
Sergunb 0:8918a71cdbe9 334 //Configure ETH_MII_TX_EN (PG11), ETH_MII_TXD0 (PG13) and ETH_MII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 335 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14;
Sergunb 0:8918a71cdbe9 336 GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 337 GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 338 GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 339 GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 340
Sergunb 0:8918a71cdbe9 341 //Configure ETH_MII_CRS (PH2), ETH_MII_COL (PH3), ETH_MII_RXD2 (PH6) and ETH_MII_RXD3 (PH7)
Sergunb 0:8918a71cdbe9 342 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_6 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 343 GPIO_Init(GPIOH, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 344 GPIO_PinAFConfig(GPIOH, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 345 GPIO_PinAFConfig(GPIOH, GPIO_PinSource3, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 346 GPIO_PinAFConfig(GPIOH, GPIO_PinSource6, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 347 GPIO_PinAFConfig(GPIOH, GPIO_PinSource7, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 348
Sergunb 0:8918a71cdbe9 349 //Configure ETH_MII_RX_ER (PI10)
Sergunb 0:8918a71cdbe9 350 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
Sergunb 0:8918a71cdbe9 351 GPIO_Init(GPIOI, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 352 GPIO_PinAFConfig(GPIOI, GPIO_PinSource10, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 353
Sergunb 0:8918a71cdbe9 354 //MCBSTM32F200 evaluation board?
Sergunb 0:8918a71cdbe9 355 #elif defined(USE_MCBSTM32F200) && defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 356 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 357 __HAL_RCC_SYSCFG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 358
Sergunb 0:8918a71cdbe9 359 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 360 __HAL_RCC_GPIOA_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 361 __HAL_RCC_GPIOC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 362 __HAL_RCC_GPIOG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 363
Sergunb 0:8918a71cdbe9 364 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 365 SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
Sergunb 0:8918a71cdbe9 366
Sergunb 0:8918a71cdbe9 367 //Configure RMII pins
Sergunb 0:8918a71cdbe9 368 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 369 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 370 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 371 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
Sergunb 0:8918a71cdbe9 372
Sergunb 0:8918a71cdbe9 373 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 374 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 375 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 376
Sergunb 0:8918a71cdbe9 377 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 378 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
Sergunb 0:8918a71cdbe9 379 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 380
Sergunb 0:8918a71cdbe9 381 //Configure ETH_RMII_TX_EN (PG11), ETH_RMII_TXD0 (PG13) and ETH_RMII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 382 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13 | GPIO_PIN_14;
Sergunb 0:8918a71cdbe9 383 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 384
Sergunb 0:8918a71cdbe9 385 #elif defined(USE_MCBSTM32F200) && defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 386 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 387 RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
Sergunb 0:8918a71cdbe9 388
Sergunb 0:8918a71cdbe9 389 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 390 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA |
Sergunb 0:8918a71cdbe9 391 RCC_AHB1Periph_GPIOC | RCC_AHB1Periph_GPIOG, ENABLE);
Sergunb 0:8918a71cdbe9 392
Sergunb 0:8918a71cdbe9 393 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 394 SYSCFG_ETH_MediaInterfaceConfig(SYSCFG_ETH_MediaInterface_RMII);
Sergunb 0:8918a71cdbe9 395
Sergunb 0:8918a71cdbe9 396 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 397 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 398 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_100MHz;
Sergunb 0:8918a71cdbe9 399 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
Sergunb 0:8918a71cdbe9 400 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
Sergunb 0:8918a71cdbe9 401 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
Sergunb 0:8918a71cdbe9 402 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 403 GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 404 GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 405 GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 406
Sergunb 0:8918a71cdbe9 407 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 408 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_4 | GPIO_Pin_5;
Sergunb 0:8918a71cdbe9 409 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 410 GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 411 GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 412 GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 413
Sergunb 0:8918a71cdbe9 414 //Configure ETH_RMII_TX_EN (PG11), ETH_RMII_TXD0 (PG13) and ETH_RMII_TXD1 (PG14)
Sergunb 0:8918a71cdbe9 415 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_13 | GPIO_Pin_14;
Sergunb 0:8918a71cdbe9 416 GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 417 GPIO_PinAFConfig(GPIOG, GPIO_PinSource11, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 418 GPIO_PinAFConfig(GPIOG, GPIO_PinSource13, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 419 GPIO_PinAFConfig(GPIOG, GPIO_PinSource14, GPIO_AF_ETH);
Sergunb 0:8918a71cdbe9 420
Sergunb 0:8918a71cdbe9 421 //Nucleo-F207ZG evaluation board?
Sergunb 0:8918a71cdbe9 422 #elif defined(USE_STM32F2XX_NUCLEO_144)
Sergunb 0:8918a71cdbe9 423 //Enable SYSCFG clock
Sergunb 0:8918a71cdbe9 424 __HAL_RCC_SYSCFG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 425
Sergunb 0:8918a71cdbe9 426 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 427 __HAL_RCC_GPIOA_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 428 __HAL_RCC_GPIOB_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 429 __HAL_RCC_GPIOC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 430 __HAL_RCC_GPIOG_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 431
Sergunb 0:8918a71cdbe9 432 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 433 SYSCFG->PMC |= SYSCFG_PMC_MII_RMII_SEL;
Sergunb 0:8918a71cdbe9 434
Sergunb 0:8918a71cdbe9 435 //Configure RMII pins
Sergunb 0:8918a71cdbe9 436 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 437 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 438 GPIO_InitStructure.Speed = GPIO_SPEED_HIGH;
Sergunb 0:8918a71cdbe9 439 GPIO_InitStructure.Alternate = GPIO_AF11_ETH;
Sergunb 0:8918a71cdbe9 440
Sergunb 0:8918a71cdbe9 441 //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 442 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7;
Sergunb 0:8918a71cdbe9 443 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 444
Sergunb 0:8918a71cdbe9 445 //Configure ETH_RMII_TXD1 (PB13)
Sergunb 0:8918a71cdbe9 446 GPIO_InitStructure.Pin = GPIO_PIN_13;
Sergunb 0:8918a71cdbe9 447 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 448
Sergunb 0:8918a71cdbe9 449 //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 450 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5;
Sergunb 0:8918a71cdbe9 451 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 452
Sergunb 0:8918a71cdbe9 453 //Configure RMII_TX_EN (PG11), ETH_RMII_TXD0 (PG13)
Sergunb 0:8918a71cdbe9 454 GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_13;
Sergunb 0:8918a71cdbe9 455 HAL_GPIO_Init(GPIOG, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 456 #endif
Sergunb 0:8918a71cdbe9 457 }
Sergunb 0:8918a71cdbe9 458
Sergunb 0:8918a71cdbe9 459 #endif
Sergunb 0:8918a71cdbe9 460
Sergunb 0:8918a71cdbe9 461
Sergunb 0:8918a71cdbe9 462 /**
Sergunb 0:8918a71cdbe9 463 * @brief Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 464 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 465 **/
Sergunb 0:8918a71cdbe9 466
Sergunb 0:8918a71cdbe9 467 void stm32f2x7EthInitDmaDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 468 {
Sergunb 0:8918a71cdbe9 469 uint_t i;
Sergunb 0:8918a71cdbe9 470
Sergunb 0:8918a71cdbe9 471 //Initialize TX DMA descriptor list
Sergunb 0:8918a71cdbe9 472 for(i = 0; i < STM32F2X7_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 473 {
Sergunb 0:8918a71cdbe9 474 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 475 txDmaDesc[i].tdes0 = ETH_TDES0_IC | ETH_TDES0_TCH;
Sergunb 0:8918a71cdbe9 476 //Initialize transmit buffer size
Sergunb 0:8918a71cdbe9 477 txDmaDesc[i].tdes1 = 0;
Sergunb 0:8918a71cdbe9 478 //Transmit buffer address
Sergunb 0:8918a71cdbe9 479 txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 480 //Next descriptor address
Sergunb 0:8918a71cdbe9 481 txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 482 //Reserved fields
Sergunb 0:8918a71cdbe9 483 txDmaDesc[i].tdes4 = 0;
Sergunb 0:8918a71cdbe9 484 txDmaDesc[i].tdes5 = 0;
Sergunb 0:8918a71cdbe9 485 //Transmit frame time stamp
Sergunb 0:8918a71cdbe9 486 txDmaDesc[i].tdes6 = 0;
Sergunb 0:8918a71cdbe9 487 txDmaDesc[i].tdes7 = 0;
Sergunb 0:8918a71cdbe9 488 }
Sergunb 0:8918a71cdbe9 489
Sergunb 0:8918a71cdbe9 490 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 491 txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 492 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 493 txCurDmaDesc = &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 494
Sergunb 0:8918a71cdbe9 495 //Initialize RX DMA descriptor list
Sergunb 0:8918a71cdbe9 496 for(i = 0; i < STM32F2X7_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 497 {
Sergunb 0:8918a71cdbe9 498 //The descriptor is initially owned by the DMA
Sergunb 0:8918a71cdbe9 499 rxDmaDesc[i].rdes0 = ETH_RDES0_OWN;
Sergunb 0:8918a71cdbe9 500 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 501 rxDmaDesc[i].rdes1 = ETH_RDES1_RCH | (STM32F2X7_ETH_RX_BUFFER_SIZE & ETH_RDES1_RBS1);
Sergunb 0:8918a71cdbe9 502 //Receive buffer address
Sergunb 0:8918a71cdbe9 503 rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 504 //Next descriptor address
Sergunb 0:8918a71cdbe9 505 rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 506 //Extended status
Sergunb 0:8918a71cdbe9 507 rxDmaDesc[i].rdes4 = 0;
Sergunb 0:8918a71cdbe9 508 //Reserved field
Sergunb 0:8918a71cdbe9 509 rxDmaDesc[i].rdes5 = 0;
Sergunb 0:8918a71cdbe9 510 //Receive frame time stamp
Sergunb 0:8918a71cdbe9 511 rxDmaDesc[i].rdes6 = 0;
Sergunb 0:8918a71cdbe9 512 rxDmaDesc[i].rdes7 = 0;
Sergunb 0:8918a71cdbe9 513 }
Sergunb 0:8918a71cdbe9 514
Sergunb 0:8918a71cdbe9 515 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 516 rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 517 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 518 rxCurDmaDesc = &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 519
Sergunb 0:8918a71cdbe9 520 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 521 ETH->DMATDLAR = (uint32_t) txDmaDesc;
Sergunb 0:8918a71cdbe9 522 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 523 ETH->DMARDLAR = (uint32_t) rxDmaDesc;
Sergunb 0:8918a71cdbe9 524 }
Sergunb 0:8918a71cdbe9 525
Sergunb 0:8918a71cdbe9 526
Sergunb 0:8918a71cdbe9 527 /**
Sergunb 0:8918a71cdbe9 528 * @brief STM32F207/217 Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 529 *
Sergunb 0:8918a71cdbe9 530 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 531 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 532 *
Sergunb 0:8918a71cdbe9 533 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 534 **/
Sergunb 0:8918a71cdbe9 535
Sergunb 0:8918a71cdbe9 536 void stm32f2x7EthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 537 {
Sergunb 0:8918a71cdbe9 538 //Handle periodic operations
Sergunb 0:8918a71cdbe9 539 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 540 }
Sergunb 0:8918a71cdbe9 541
Sergunb 0:8918a71cdbe9 542
Sergunb 0:8918a71cdbe9 543 /**
Sergunb 0:8918a71cdbe9 544 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 545 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 546 **/
Sergunb 0:8918a71cdbe9 547
Sergunb 0:8918a71cdbe9 548 void stm32f2x7EthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 549 {
Sergunb 0:8918a71cdbe9 550 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 551 NVIC_EnableIRQ(ETH_IRQn);
Sergunb 0:8918a71cdbe9 552 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 553 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 554 }
Sergunb 0:8918a71cdbe9 555
Sergunb 0:8918a71cdbe9 556
Sergunb 0:8918a71cdbe9 557 /**
Sergunb 0:8918a71cdbe9 558 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 559 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 560 **/
Sergunb 0:8918a71cdbe9 561
Sergunb 0:8918a71cdbe9 562 void stm32f2x7EthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 563 {
Sergunb 0:8918a71cdbe9 564 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 565 NVIC_DisableIRQ(ETH_IRQn);
Sergunb 0:8918a71cdbe9 566 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 567 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 568 }
Sergunb 0:8918a71cdbe9 569
Sergunb 0:8918a71cdbe9 570
Sergunb 0:8918a71cdbe9 571 /**
Sergunb 0:8918a71cdbe9 572 * @brief STM32F207/217 Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 573 **/
Sergunb 0:8918a71cdbe9 574
Sergunb 0:8918a71cdbe9 575 void ETH_IRQHandler(void)
Sergunb 0:8918a71cdbe9 576 {
Sergunb 0:8918a71cdbe9 577 bool_t flag;
Sergunb 0:8918a71cdbe9 578 uint32_t status;
Sergunb 0:8918a71cdbe9 579
Sergunb 0:8918a71cdbe9 580 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 581 osEnterIsr();
Sergunb 0:8918a71cdbe9 582
Sergunb 0:8918a71cdbe9 583 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 584 flag = FALSE;
Sergunb 0:8918a71cdbe9 585
Sergunb 0:8918a71cdbe9 586 //Read DMA status register
Sergunb 0:8918a71cdbe9 587 status = ETH->DMASR;
Sergunb 0:8918a71cdbe9 588
Sergunb 0:8918a71cdbe9 589 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 590 if(status & ETH_DMASR_TS)
Sergunb 0:8918a71cdbe9 591 {
Sergunb 0:8918a71cdbe9 592 //Clear TS interrupt flag
Sergunb 0:8918a71cdbe9 593 ETH->DMASR = ETH_DMASR_TS;
Sergunb 0:8918a71cdbe9 594
Sergunb 0:8918a71cdbe9 595 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 596 if(!(txCurDmaDesc->tdes0 & ETH_TDES0_OWN))
Sergunb 0:8918a71cdbe9 597 {
Sergunb 0:8918a71cdbe9 598 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 599 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 600 }
Sergunb 0:8918a71cdbe9 601 }
Sergunb 0:8918a71cdbe9 602
Sergunb 0:8918a71cdbe9 603 //A packet has been received?
Sergunb 0:8918a71cdbe9 604 if(status & ETH_DMASR_RS)
Sergunb 0:8918a71cdbe9 605 {
Sergunb 0:8918a71cdbe9 606 //Disable RIE interrupt
Sergunb 0:8918a71cdbe9 607 ETH->DMAIER &= ~ETH_DMAIER_RIE;
Sergunb 0:8918a71cdbe9 608
Sergunb 0:8918a71cdbe9 609 //Set event flag
Sergunb 0:8918a71cdbe9 610 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 611 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 612 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 613 }
Sergunb 0:8918a71cdbe9 614
Sergunb 0:8918a71cdbe9 615 //Clear NIS interrupt flag
Sergunb 0:8918a71cdbe9 616 ETH->DMASR = ETH_DMASR_NIS;
Sergunb 0:8918a71cdbe9 617
Sergunb 0:8918a71cdbe9 618 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 619 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 620 }
Sergunb 0:8918a71cdbe9 621
Sergunb 0:8918a71cdbe9 622
Sergunb 0:8918a71cdbe9 623 /**
Sergunb 0:8918a71cdbe9 624 * @brief STM32F207/217 Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 625 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 626 **/
Sergunb 0:8918a71cdbe9 627
Sergunb 0:8918a71cdbe9 628 void stm32f2x7EthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 629 {
Sergunb 0:8918a71cdbe9 630 error_t error;
Sergunb 0:8918a71cdbe9 631
Sergunb 0:8918a71cdbe9 632 //Packet received?
Sergunb 0:8918a71cdbe9 633 if(ETH->DMASR & ETH_DMASR_RS)
Sergunb 0:8918a71cdbe9 634 {
Sergunb 0:8918a71cdbe9 635 //Clear interrupt flag
Sergunb 0:8918a71cdbe9 636 ETH->DMASR = ETH_DMASR_RS;
Sergunb 0:8918a71cdbe9 637
Sergunb 0:8918a71cdbe9 638 //Process all pending packets
Sergunb 0:8918a71cdbe9 639 do
Sergunb 0:8918a71cdbe9 640 {
Sergunb 0:8918a71cdbe9 641 //Read incoming packet
Sergunb 0:8918a71cdbe9 642 error = stm32f2x7EthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 643
Sergunb 0:8918a71cdbe9 644 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 645 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 646 }
Sergunb 0:8918a71cdbe9 647
Sergunb 0:8918a71cdbe9 648 //Re-enable DMA interrupts
Sergunb 0:8918a71cdbe9 649 ETH->DMAIER |= ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
Sergunb 0:8918a71cdbe9 650 }
Sergunb 0:8918a71cdbe9 651
Sergunb 0:8918a71cdbe9 652
Sergunb 0:8918a71cdbe9 653 /**
Sergunb 0:8918a71cdbe9 654 * @brief Send a packet
Sergunb 0:8918a71cdbe9 655 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 656 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 657 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 658 * @return Error code
Sergunb 0:8918a71cdbe9 659 **/
Sergunb 0:8918a71cdbe9 660
Sergunb 0:8918a71cdbe9 661 error_t stm32f2x7EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 662 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 663 {
Sergunb 0:8918a71cdbe9 664 size_t length;
Sergunb 0:8918a71cdbe9 665
Sergunb 0:8918a71cdbe9 666 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 667 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 668
Sergunb 0:8918a71cdbe9 669 //Check the frame length
Sergunb 0:8918a71cdbe9 670 if(length > STM32F2X7_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 671 {
Sergunb 0:8918a71cdbe9 672 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 673 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 674 //Report an error
Sergunb 0:8918a71cdbe9 675 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 676 }
Sergunb 0:8918a71cdbe9 677
Sergunb 0:8918a71cdbe9 678 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 679 if(txCurDmaDesc->tdes0 & ETH_TDES0_OWN)
Sergunb 0:8918a71cdbe9 680 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 681
Sergunb 0:8918a71cdbe9 682 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 683 netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
Sergunb 0:8918a71cdbe9 684
Sergunb 0:8918a71cdbe9 685 //Write the number of bytes to send
Sergunb 0:8918a71cdbe9 686 txCurDmaDesc->tdes1 = length & ETH_TDES1_TBS1;
Sergunb 0:8918a71cdbe9 687 //Set LS and FS flags as the data fits in a single buffer
Sergunb 0:8918a71cdbe9 688 txCurDmaDesc->tdes0 |= ETH_TDES0_LS | ETH_TDES0_FS;
Sergunb 0:8918a71cdbe9 689 //Give the ownership of the descriptor to the DMA
Sergunb 0:8918a71cdbe9 690 txCurDmaDesc->tdes0 |= ETH_TDES0_OWN;
Sergunb 0:8918a71cdbe9 691
Sergunb 0:8918a71cdbe9 692 //Clear TBUS flag to resume processing
Sergunb 0:8918a71cdbe9 693 ETH->DMASR = ETH_DMASR_TBUS;
Sergunb 0:8918a71cdbe9 694 //Instruct the DMA to poll the transmit descriptor list
Sergunb 0:8918a71cdbe9 695 ETH->DMATPDR = 0;
Sergunb 0:8918a71cdbe9 696
Sergunb 0:8918a71cdbe9 697 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 698 txCurDmaDesc = (Stm32f2x7TxDmaDesc *) txCurDmaDesc->tdes3;
Sergunb 0:8918a71cdbe9 699
Sergunb 0:8918a71cdbe9 700 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 701 if(!(txCurDmaDesc->tdes0 & ETH_TDES0_OWN))
Sergunb 0:8918a71cdbe9 702 {
Sergunb 0:8918a71cdbe9 703 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 704 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 705 }
Sergunb 0:8918a71cdbe9 706
Sergunb 0:8918a71cdbe9 707 //Data successfully written
Sergunb 0:8918a71cdbe9 708 return NO_ERROR;
Sergunb 0:8918a71cdbe9 709 }
Sergunb 0:8918a71cdbe9 710
Sergunb 0:8918a71cdbe9 711
Sergunb 0:8918a71cdbe9 712 /**
Sergunb 0:8918a71cdbe9 713 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 714 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 715 * @return Error code
Sergunb 0:8918a71cdbe9 716 **/
Sergunb 0:8918a71cdbe9 717
Sergunb 0:8918a71cdbe9 718 error_t stm32f2x7EthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 719 {
Sergunb 0:8918a71cdbe9 720 error_t error;
Sergunb 0:8918a71cdbe9 721 size_t n;
Sergunb 0:8918a71cdbe9 722
Sergunb 0:8918a71cdbe9 723 //The current buffer is available for reading?
Sergunb 0:8918a71cdbe9 724 if(!(rxCurDmaDesc->rdes0 & ETH_RDES0_OWN))
Sergunb 0:8918a71cdbe9 725 {
Sergunb 0:8918a71cdbe9 726 //FS and LS flags should be set
Sergunb 0:8918a71cdbe9 727 if((rxCurDmaDesc->rdes0 & ETH_RDES0_FS) && (rxCurDmaDesc->rdes0 & ETH_RDES0_LS))
Sergunb 0:8918a71cdbe9 728 {
Sergunb 0:8918a71cdbe9 729 //Make sure no error occurred
Sergunb 0:8918a71cdbe9 730 if(!(rxCurDmaDesc->rdes0 & ETH_RDES0_ES))
Sergunb 0:8918a71cdbe9 731 {
Sergunb 0:8918a71cdbe9 732 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 733 n = (rxCurDmaDesc->rdes0 & ETH_RDES0_FL) >> 16;
Sergunb 0:8918a71cdbe9 734 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 735 n = MIN(n, STM32F2X7_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 736
Sergunb 0:8918a71cdbe9 737 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 738 nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n);
Sergunb 0:8918a71cdbe9 739
Sergunb 0:8918a71cdbe9 740 //Valid packet received
Sergunb 0:8918a71cdbe9 741 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 742 }
Sergunb 0:8918a71cdbe9 743 else
Sergunb 0:8918a71cdbe9 744 {
Sergunb 0:8918a71cdbe9 745 //The received packet contains an error
Sergunb 0:8918a71cdbe9 746 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 747 }
Sergunb 0:8918a71cdbe9 748 }
Sergunb 0:8918a71cdbe9 749 else
Sergunb 0:8918a71cdbe9 750 {
Sergunb 0:8918a71cdbe9 751 //The packet is not valid
Sergunb 0:8918a71cdbe9 752 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 753 }
Sergunb 0:8918a71cdbe9 754
Sergunb 0:8918a71cdbe9 755 //Give the ownership of the descriptor back to the DMA
Sergunb 0:8918a71cdbe9 756 rxCurDmaDesc->rdes0 = ETH_RDES0_OWN;
Sergunb 0:8918a71cdbe9 757 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 758 rxCurDmaDesc = (Stm32f2x7RxDmaDesc *) rxCurDmaDesc->rdes3;
Sergunb 0:8918a71cdbe9 759 }
Sergunb 0:8918a71cdbe9 760 else
Sergunb 0:8918a71cdbe9 761 {
Sergunb 0:8918a71cdbe9 762 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 763 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 764 }
Sergunb 0:8918a71cdbe9 765
Sergunb 0:8918a71cdbe9 766 //Clear RBUS flag to resume processing
Sergunb 0:8918a71cdbe9 767 ETH->DMASR = ETH_DMASR_RBUS;
Sergunb 0:8918a71cdbe9 768 //Instruct the DMA to poll the receive descriptor list
Sergunb 0:8918a71cdbe9 769 ETH->DMARPDR = 0;
Sergunb 0:8918a71cdbe9 770
Sergunb 0:8918a71cdbe9 771 //Return status code
Sergunb 0:8918a71cdbe9 772 return error;
Sergunb 0:8918a71cdbe9 773 }
Sergunb 0:8918a71cdbe9 774
Sergunb 0:8918a71cdbe9 775
Sergunb 0:8918a71cdbe9 776 /**
Sergunb 0:8918a71cdbe9 777 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 778 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 779 * @return Error code
Sergunb 0:8918a71cdbe9 780 **/
Sergunb 0:8918a71cdbe9 781
Sergunb 0:8918a71cdbe9 782 error_t stm32f2x7EthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 783 {
Sergunb 0:8918a71cdbe9 784 uint_t i;
Sergunb 0:8918a71cdbe9 785 uint_t k;
Sergunb 0:8918a71cdbe9 786 uint32_t crc;
Sergunb 0:8918a71cdbe9 787 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 788 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 789
Sergunb 0:8918a71cdbe9 790 //Debug message
Sergunb 0:8918a71cdbe9 791 TRACE_DEBUG("Updating STM32F2x7 hash table...\r\n");
Sergunb 0:8918a71cdbe9 792
Sergunb 0:8918a71cdbe9 793 //Clear hash table
Sergunb 0:8918a71cdbe9 794 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 795 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 796
Sergunb 0:8918a71cdbe9 797 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 798 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 799 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 800 {
Sergunb 0:8918a71cdbe9 801 //Point to the current entry
Sergunb 0:8918a71cdbe9 802 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 803
Sergunb 0:8918a71cdbe9 804 //Valid entry?
Sergunb 0:8918a71cdbe9 805 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 806 {
Sergunb 0:8918a71cdbe9 807 //Compute CRC over the current MAC address
Sergunb 0:8918a71cdbe9 808 crc = stm32f2x7EthCalcCrc(&entry->addr, sizeof(MacAddr));
Sergunb 0:8918a71cdbe9 809
Sergunb 0:8918a71cdbe9 810 //The upper 6 bits in the CRC register are used to index the
Sergunb 0:8918a71cdbe9 811 //contents of the hash table
Sergunb 0:8918a71cdbe9 812 k = (crc >> 26) & 0x3F;
Sergunb 0:8918a71cdbe9 813
Sergunb 0:8918a71cdbe9 814 //Update hash table contents
Sergunb 0:8918a71cdbe9 815 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 816 }
Sergunb 0:8918a71cdbe9 817 }
Sergunb 0:8918a71cdbe9 818
Sergunb 0:8918a71cdbe9 819 //Write the hash table
Sergunb 0:8918a71cdbe9 820 ETH->MACHTLR = hashTable[0];
Sergunb 0:8918a71cdbe9 821 ETH->MACHTHR = hashTable[1];
Sergunb 0:8918a71cdbe9 822
Sergunb 0:8918a71cdbe9 823 //Debug message
Sergunb 0:8918a71cdbe9 824 TRACE_DEBUG(" MACHTLR = %08" PRIX32 "\r\n", ETH->MACHTLR);
Sergunb 0:8918a71cdbe9 825 TRACE_DEBUG(" MACHTHR = %08" PRIX32 "\r\n", ETH->MACHTHR);
Sergunb 0:8918a71cdbe9 826
Sergunb 0:8918a71cdbe9 827 //Successful processing
Sergunb 0:8918a71cdbe9 828 return NO_ERROR;
Sergunb 0:8918a71cdbe9 829 }
Sergunb 0:8918a71cdbe9 830
Sergunb 0:8918a71cdbe9 831
Sergunb 0:8918a71cdbe9 832 /**
Sergunb 0:8918a71cdbe9 833 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 834 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 835 * @return Error code
Sergunb 0:8918a71cdbe9 836 **/
Sergunb 0:8918a71cdbe9 837
Sergunb 0:8918a71cdbe9 838 error_t stm32f2x7EthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 839 {
Sergunb 0:8918a71cdbe9 840 uint32_t config;
Sergunb 0:8918a71cdbe9 841
Sergunb 0:8918a71cdbe9 842 //Read current MAC configuration
Sergunb 0:8918a71cdbe9 843 config = ETH->MACCR;
Sergunb 0:8918a71cdbe9 844
Sergunb 0:8918a71cdbe9 845 //10BASE-T or 100BASE-TX operation mode?
Sergunb 0:8918a71cdbe9 846 if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
Sergunb 0:8918a71cdbe9 847 config |= ETH_MACCR_FES;
Sergunb 0:8918a71cdbe9 848 else
Sergunb 0:8918a71cdbe9 849 config &= ~ETH_MACCR_FES;
Sergunb 0:8918a71cdbe9 850
Sergunb 0:8918a71cdbe9 851 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 852 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 853 config |= ETH_MACCR_DM;
Sergunb 0:8918a71cdbe9 854 else
Sergunb 0:8918a71cdbe9 855 config &= ~ETH_MACCR_DM;
Sergunb 0:8918a71cdbe9 856
Sergunb 0:8918a71cdbe9 857 //Update MAC configuration register
Sergunb 0:8918a71cdbe9 858 ETH->MACCR = config;
Sergunb 0:8918a71cdbe9 859
Sergunb 0:8918a71cdbe9 860 //Successful processing
Sergunb 0:8918a71cdbe9 861 return NO_ERROR;
Sergunb 0:8918a71cdbe9 862 }
Sergunb 0:8918a71cdbe9 863
Sergunb 0:8918a71cdbe9 864
Sergunb 0:8918a71cdbe9 865 /**
Sergunb 0:8918a71cdbe9 866 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 867 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 868 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 869 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 870 **/
Sergunb 0:8918a71cdbe9 871
Sergunb 0:8918a71cdbe9 872 void stm32f2x7EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 873 {
Sergunb 0:8918a71cdbe9 874 uint32_t value;
Sergunb 0:8918a71cdbe9 875
Sergunb 0:8918a71cdbe9 876 //Take care not to alter MDC clock configuration
Sergunb 0:8918a71cdbe9 877 value = ETH->MACMIIAR & ETH_MACMIIAR_CR;
Sergunb 0:8918a71cdbe9 878 //Set up a write operation
Sergunb 0:8918a71cdbe9 879 value |= ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
Sergunb 0:8918a71cdbe9 880 //PHY address
Sergunb 0:8918a71cdbe9 881 value |= (phyAddr << 11) & ETH_MACMIIAR_PA;
Sergunb 0:8918a71cdbe9 882 //Register address
Sergunb 0:8918a71cdbe9 883 value |= (regAddr << 6) & ETH_MACMIIAR_MR;
Sergunb 0:8918a71cdbe9 884
Sergunb 0:8918a71cdbe9 885 //Data to be written in the PHY register
Sergunb 0:8918a71cdbe9 886 ETH->MACMIIDR = data & ETH_MACMIIDR_MD;
Sergunb 0:8918a71cdbe9 887
Sergunb 0:8918a71cdbe9 888 //Start a write operation
Sergunb 0:8918a71cdbe9 889 ETH->MACMIIAR = value;
Sergunb 0:8918a71cdbe9 890 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 891 while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
Sergunb 0:8918a71cdbe9 892 }
Sergunb 0:8918a71cdbe9 893
Sergunb 0:8918a71cdbe9 894
Sergunb 0:8918a71cdbe9 895 /**
Sergunb 0:8918a71cdbe9 896 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 897 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 898 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 899 * @return Register value
Sergunb 0:8918a71cdbe9 900 **/
Sergunb 0:8918a71cdbe9 901
Sergunb 0:8918a71cdbe9 902 uint16_t stm32f2x7EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 903 {
Sergunb 0:8918a71cdbe9 904 uint32_t value;
Sergunb 0:8918a71cdbe9 905
Sergunb 0:8918a71cdbe9 906 //Take care not to alter MDC clock configuration
Sergunb 0:8918a71cdbe9 907 value = ETH->MACMIIAR & ETH_MACMIIAR_CR;
Sergunb 0:8918a71cdbe9 908 //Set up a read operation
Sergunb 0:8918a71cdbe9 909 value |= ETH_MACMIIAR_MB;
Sergunb 0:8918a71cdbe9 910 //PHY address
Sergunb 0:8918a71cdbe9 911 value |= (phyAddr << 11) & ETH_MACMIIAR_PA;
Sergunb 0:8918a71cdbe9 912 //Register address
Sergunb 0:8918a71cdbe9 913 value |= (regAddr << 6) & ETH_MACMIIAR_MR;
Sergunb 0:8918a71cdbe9 914
Sergunb 0:8918a71cdbe9 915 //Start a read operation
Sergunb 0:8918a71cdbe9 916 ETH->MACMIIAR = value;
Sergunb 0:8918a71cdbe9 917 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 918 while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
Sergunb 0:8918a71cdbe9 919
Sergunb 0:8918a71cdbe9 920 //Return PHY register contents
Sergunb 0:8918a71cdbe9 921 return ETH->MACMIIDR & ETH_MACMIIDR_MD;
Sergunb 0:8918a71cdbe9 922 }
Sergunb 0:8918a71cdbe9 923
Sergunb 0:8918a71cdbe9 924
Sergunb 0:8918a71cdbe9 925 /**
Sergunb 0:8918a71cdbe9 926 * @brief CRC calculation
Sergunb 0:8918a71cdbe9 927 * @param[in] data Pointer to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 928 * @param[in] length Number of bytes to process
Sergunb 0:8918a71cdbe9 929 * @return Resulting CRC value
Sergunb 0:8918a71cdbe9 930 **/
Sergunb 0:8918a71cdbe9 931
Sergunb 0:8918a71cdbe9 932 uint32_t stm32f2x7EthCalcCrc(const void *data, size_t length)
Sergunb 0:8918a71cdbe9 933 {
Sergunb 0:8918a71cdbe9 934 uint_t i;
Sergunb 0:8918a71cdbe9 935 uint_t j;
Sergunb 0:8918a71cdbe9 936
Sergunb 0:8918a71cdbe9 937 //Point to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 938 const uint8_t *p = (uint8_t *) data;
Sergunb 0:8918a71cdbe9 939 //CRC preset value
Sergunb 0:8918a71cdbe9 940 uint32_t crc = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 941
Sergunb 0:8918a71cdbe9 942 //Loop through data
Sergunb 0:8918a71cdbe9 943 for(i = 0; i < length; i++)
Sergunb 0:8918a71cdbe9 944 {
Sergunb 0:8918a71cdbe9 945 //The message is processed bit by bit
Sergunb 0:8918a71cdbe9 946 for(j = 0; j < 8; j++)
Sergunb 0:8918a71cdbe9 947 {
Sergunb 0:8918a71cdbe9 948 //Update CRC value
Sergunb 0:8918a71cdbe9 949 if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
Sergunb 0:8918a71cdbe9 950 crc = (crc << 1) ^ 0x04C11DB7;
Sergunb 0:8918a71cdbe9 951 else
Sergunb 0:8918a71cdbe9 952 crc = crc << 1;
Sergunb 0:8918a71cdbe9 953 }
Sergunb 0:8918a71cdbe9 954 }
Sergunb 0:8918a71cdbe9 955
Sergunb 0:8918a71cdbe9 956 //Return CRC value
Sergunb 0:8918a71cdbe9 957 return ~crc;
Sergunb 0:8918a71cdbe9 958 }
Sergunb 0:8918a71cdbe9 959