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cyclone_tcp/drivers/stm32f107_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file stm32f107_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief STM32F107 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #if defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 34 #include "stm32f1xx.h"
Sergunb 0:8918a71cdbe9 35 #elif defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 36 #include "stm32f10x.h"
Sergunb 0:8918a71cdbe9 37 #endif
Sergunb 0:8918a71cdbe9 38
Sergunb 0:8918a71cdbe9 39 #include "core/net.h"
Sergunb 0:8918a71cdbe9 40 #include "drivers/stm32f107_eth.h"
Sergunb 0:8918a71cdbe9 41 #include "debug.h"
Sergunb 0:8918a71cdbe9 42
Sergunb 0:8918a71cdbe9 43 //Underlying network interface
Sergunb 0:8918a71cdbe9 44 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 45
Sergunb 0:8918a71cdbe9 46 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 47 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 48
Sergunb 0:8918a71cdbe9 49 //Transmit buffer
Sergunb 0:8918a71cdbe9 50 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 51 static uint8_t txBuffer[STM32F107_ETH_TX_BUFFER_COUNT][STM32F107_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 52 //Receive buffer
Sergunb 0:8918a71cdbe9 53 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 54 static uint8_t rxBuffer[STM32F107_ETH_RX_BUFFER_COUNT][STM32F107_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 55 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 56 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 57 static Stm32f107TxDmaDesc txDmaDesc[STM32F107_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 58 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 59 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 60 static Stm32f107RxDmaDesc rxDmaDesc[STM32F107_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 61
Sergunb 0:8918a71cdbe9 62 //Keil MDK-ARM or GCC compiler?
Sergunb 0:8918a71cdbe9 63 #else
Sergunb 0:8918a71cdbe9 64
Sergunb 0:8918a71cdbe9 65 //Transmit buffer
Sergunb 0:8918a71cdbe9 66 static uint8_t txBuffer[STM32F107_ETH_TX_BUFFER_COUNT][STM32F107_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 67 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 68 //Receive buffer
Sergunb 0:8918a71cdbe9 69 static uint8_t rxBuffer[STM32F107_ETH_RX_BUFFER_COUNT][STM32F107_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 70 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 71 //Transmit DMA descriptors
Sergunb 0:8918a71cdbe9 72 static Stm32f107TxDmaDesc txDmaDesc[STM32F107_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 73 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 74 //Receive DMA descriptors
Sergunb 0:8918a71cdbe9 75 static Stm32f107RxDmaDesc rxDmaDesc[STM32F107_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 76 __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 77
Sergunb 0:8918a71cdbe9 78 #endif
Sergunb 0:8918a71cdbe9 79
Sergunb 0:8918a71cdbe9 80 //Pointer to the current TX DMA descriptor
Sergunb 0:8918a71cdbe9 81 static Stm32f107TxDmaDesc *txCurDmaDesc;
Sergunb 0:8918a71cdbe9 82 //Pointer to the current RX DMA descriptor
Sergunb 0:8918a71cdbe9 83 static Stm32f107RxDmaDesc *rxCurDmaDesc;
Sergunb 0:8918a71cdbe9 84
Sergunb 0:8918a71cdbe9 85
Sergunb 0:8918a71cdbe9 86 /**
Sergunb 0:8918a71cdbe9 87 * @brief STM32F107 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 88 **/
Sergunb 0:8918a71cdbe9 89
Sergunb 0:8918a71cdbe9 90 const NicDriver stm32f107EthDriver =
Sergunb 0:8918a71cdbe9 91 {
Sergunb 0:8918a71cdbe9 92 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 93 ETH_MTU,
Sergunb 0:8918a71cdbe9 94 stm32f107EthInit,
Sergunb 0:8918a71cdbe9 95 stm32f107EthTick,
Sergunb 0:8918a71cdbe9 96 stm32f107EthEnableIrq,
Sergunb 0:8918a71cdbe9 97 stm32f107EthDisableIrq,
Sergunb 0:8918a71cdbe9 98 stm32f107EthEventHandler,
Sergunb 0:8918a71cdbe9 99 stm32f107EthSendPacket,
Sergunb 0:8918a71cdbe9 100 stm32f107EthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 101 stm32f107EthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 102 stm32f107EthWritePhyReg,
Sergunb 0:8918a71cdbe9 103 stm32f107EthReadPhyReg,
Sergunb 0:8918a71cdbe9 104 TRUE,
Sergunb 0:8918a71cdbe9 105 TRUE,
Sergunb 0:8918a71cdbe9 106 TRUE,
Sergunb 0:8918a71cdbe9 107 FALSE
Sergunb 0:8918a71cdbe9 108 };
Sergunb 0:8918a71cdbe9 109
Sergunb 0:8918a71cdbe9 110
Sergunb 0:8918a71cdbe9 111 /**
Sergunb 0:8918a71cdbe9 112 * @brief STM32F107 Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 113 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 114 * @return Error code
Sergunb 0:8918a71cdbe9 115 **/
Sergunb 0:8918a71cdbe9 116
Sergunb 0:8918a71cdbe9 117 error_t stm32f107EthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 118 {
Sergunb 0:8918a71cdbe9 119 error_t error;
Sergunb 0:8918a71cdbe9 120
Sergunb 0:8918a71cdbe9 121 //Debug message
Sergunb 0:8918a71cdbe9 122 TRACE_INFO("Initializing STM32F107 Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 123
Sergunb 0:8918a71cdbe9 124 //Save underlying network interface
Sergunb 0:8918a71cdbe9 125 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 126
Sergunb 0:8918a71cdbe9 127 //GPIO configuration
Sergunb 0:8918a71cdbe9 128 stm32f107EthInitGpio(interface);
Sergunb 0:8918a71cdbe9 129
Sergunb 0:8918a71cdbe9 130 #if defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 131 //Enable Ethernet MAC clock
Sergunb 0:8918a71cdbe9 132 __HAL_RCC_ETHMAC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 133 __HAL_RCC_ETHMACTX_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 134 __HAL_RCC_ETHMACRX_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 135
Sergunb 0:8918a71cdbe9 136 //Reset Ethernet MAC peripheral
Sergunb 0:8918a71cdbe9 137 __HAL_RCC_ETHMAC_FORCE_RESET();
Sergunb 0:8918a71cdbe9 138 __HAL_RCC_ETHMAC_RELEASE_RESET();
Sergunb 0:8918a71cdbe9 139
Sergunb 0:8918a71cdbe9 140 #elif defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 141 //Enable Ethernet MAC clock
Sergunb 0:8918a71cdbe9 142 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_ETH_MAC |
Sergunb 0:8918a71cdbe9 143 RCC_AHBPeriph_ETH_MAC_Tx | RCC_AHBPeriph_ETH_MAC_Rx, ENABLE);
Sergunb 0:8918a71cdbe9 144
Sergunb 0:8918a71cdbe9 145 //Reset Ethernet MAC peripheral
Sergunb 0:8918a71cdbe9 146 RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE);
Sergunb 0:8918a71cdbe9 147 RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE);
Sergunb 0:8918a71cdbe9 148 #endif
Sergunb 0:8918a71cdbe9 149
Sergunb 0:8918a71cdbe9 150 //Perform a software reset
Sergunb 0:8918a71cdbe9 151 ETH->DMABMR |= ETH_DMABMR_SR;
Sergunb 0:8918a71cdbe9 152 //Wait for the reset to complete
Sergunb 0:8918a71cdbe9 153 while(ETH->DMABMR & ETH_DMABMR_SR);
Sergunb 0:8918a71cdbe9 154
Sergunb 0:8918a71cdbe9 155 //Adjust MDC clock range depending on HCLK frequency
Sergunb 0:8918a71cdbe9 156 #if defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 157 ETH->MACMIIAR = ETH_MACMIIAR_CR_DIV42;
Sergunb 0:8918a71cdbe9 158 #elif defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 159 ETH->MACMIIAR = ETH_MACMIIAR_CR_Div42;
Sergunb 0:8918a71cdbe9 160 #endif
Sergunb 0:8918a71cdbe9 161
Sergunb 0:8918a71cdbe9 162 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 163 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 164 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 165 if(error)
Sergunb 0:8918a71cdbe9 166 return error;
Sergunb 0:8918a71cdbe9 167
Sergunb 0:8918a71cdbe9 168 //Use default MAC configuration
Sergunb 0:8918a71cdbe9 169 ETH->MACCR = ETH_MACCR_ROD;
Sergunb 0:8918a71cdbe9 170
Sergunb 0:8918a71cdbe9 171 //Set the MAC address
Sergunb 0:8918a71cdbe9 172 ETH->MACA0LR = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 173 ETH->MACA0HR = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 174
Sergunb 0:8918a71cdbe9 175 //Initialize hash table
Sergunb 0:8918a71cdbe9 176 ETH->MACHTLR = 0;
Sergunb 0:8918a71cdbe9 177 ETH->MACHTHR = 0;
Sergunb 0:8918a71cdbe9 178
Sergunb 0:8918a71cdbe9 179 //Configure the receive filter
Sergunb 0:8918a71cdbe9 180 ETH->MACFFR = ETH_MACFFR_HPF | ETH_MACFFR_HM;
Sergunb 0:8918a71cdbe9 181 //Disable flow control
Sergunb 0:8918a71cdbe9 182 ETH->MACFCR = 0;
Sergunb 0:8918a71cdbe9 183 //Enable store and forward mode
Sergunb 0:8918a71cdbe9 184 ETH->DMAOMR = ETH_DMAOMR_RSF | ETH_DMAOMR_TSF;
Sergunb 0:8918a71cdbe9 185
Sergunb 0:8918a71cdbe9 186 //Configure DMA bus mode
Sergunb 0:8918a71cdbe9 187 ETH->DMABMR = ETH_DMABMR_AAB | ETH_DMABMR_USP | ETH_DMABMR_RDP_1Beat |
Sergunb 0:8918a71cdbe9 188 ETH_DMABMR_RTPR_1_1 | ETH_DMABMR_PBL_1Beat;
Sergunb 0:8918a71cdbe9 189
Sergunb 0:8918a71cdbe9 190 //Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 191 stm32f107EthInitDmaDesc(interface);
Sergunb 0:8918a71cdbe9 192
Sergunb 0:8918a71cdbe9 193 //Prevent interrupts from being generated when the transmit statistic
Sergunb 0:8918a71cdbe9 194 //counters reach half their maximum value
Sergunb 0:8918a71cdbe9 195 ETH->MMCTIMR = ETH_MMCTIMR_TGFM | ETH_MMCTIMR_TGFMSCM | ETH_MMCTIMR_TGFSCM;
Sergunb 0:8918a71cdbe9 196
Sergunb 0:8918a71cdbe9 197 //Prevent interrupts from being generated when the receive statistic
Sergunb 0:8918a71cdbe9 198 //counters reach half their maximum value
Sergunb 0:8918a71cdbe9 199 ETH->MMCRIMR = ETH_MMCRIMR_RGUFM | ETH_MMCRIMR_RFAEM | ETH_MMCRIMR_RFCEM;
Sergunb 0:8918a71cdbe9 200
Sergunb 0:8918a71cdbe9 201 //Disable MAC interrupts
Sergunb 0:8918a71cdbe9 202 ETH->MACIMR = ETH_MACIMR_TSTIM | ETH_MACIMR_PMTIM;
Sergunb 0:8918a71cdbe9 203 //Enable the desired DMA interrupts
Sergunb 0:8918a71cdbe9 204 ETH->DMAIER = ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
Sergunb 0:8918a71cdbe9 205
Sergunb 0:8918a71cdbe9 206 //Set priority grouping (4 bits for pre-emption priority, no bits for subpriority)
Sergunb 0:8918a71cdbe9 207 NVIC_SetPriorityGrouping(STM32F107_ETH_IRQ_PRIORITY_GROUPING);
Sergunb 0:8918a71cdbe9 208
Sergunb 0:8918a71cdbe9 209 //Configure Ethernet interrupt priority
Sergunb 0:8918a71cdbe9 210 NVIC_SetPriority(ETH_IRQn, NVIC_EncodePriority(STM32F107_ETH_IRQ_PRIORITY_GROUPING,
Sergunb 0:8918a71cdbe9 211 STM32F107_ETH_IRQ_GROUP_PRIORITY, STM32F107_ETH_IRQ_SUB_PRIORITY));
Sergunb 0:8918a71cdbe9 212
Sergunb 0:8918a71cdbe9 213 //Enable MAC transmission and reception
Sergunb 0:8918a71cdbe9 214 ETH->MACCR |= ETH_MACCR_TE | ETH_MACCR_RE;
Sergunb 0:8918a71cdbe9 215 //Enable DMA transmission and reception
Sergunb 0:8918a71cdbe9 216 ETH->DMAOMR |= ETH_DMAOMR_ST | ETH_DMAOMR_SR;
Sergunb 0:8918a71cdbe9 217
Sergunb 0:8918a71cdbe9 218 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 219 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 220
Sergunb 0:8918a71cdbe9 221 //Successful initialization
Sergunb 0:8918a71cdbe9 222 return NO_ERROR;
Sergunb 0:8918a71cdbe9 223 }
Sergunb 0:8918a71cdbe9 224
Sergunb 0:8918a71cdbe9 225
Sergunb 0:8918a71cdbe9 226 //STM3210C-EVAL or STM32-P107 evaluation board?
Sergunb 0:8918a71cdbe9 227 #if defined(USE_STM3210C_EVAL) || defined(USE_STM32_P107)
Sergunb 0:8918a71cdbe9 228
Sergunb 0:8918a71cdbe9 229 /**
Sergunb 0:8918a71cdbe9 230 * @brief GPIO configuration
Sergunb 0:8918a71cdbe9 231 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 232 **/
Sergunb 0:8918a71cdbe9 233
Sergunb 0:8918a71cdbe9 234 void stm32f107EthInitGpio(NetInterface *interface)
Sergunb 0:8918a71cdbe9 235 {
Sergunb 0:8918a71cdbe9 236 GPIO_InitTypeDef GPIO_InitStructure;
Sergunb 0:8918a71cdbe9 237
Sergunb 0:8918a71cdbe9 238 //STM3210C-EVAL evaluation board?
Sergunb 0:8918a71cdbe9 239 #if defined(USE_STM3210C_EVAL) && defined(USE_HAL_DRIVER)
Sergunb 0:8918a71cdbe9 240 //Enable AFIO clock
Sergunb 0:8918a71cdbe9 241 __HAL_RCC_AFIO_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 242
Sergunb 0:8918a71cdbe9 243 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 244 __HAL_RCC_GPIOA_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 245 __HAL_RCC_GPIOB_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 246 __HAL_RCC_GPIOC_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 247 __HAL_RCC_GPIOD_CLK_ENABLE();
Sergunb 0:8918a71cdbe9 248
Sergunb 0:8918a71cdbe9 249 //Configure MCO (PA8) as an output
Sergunb 0:8918a71cdbe9 250 GPIO_InitStructure.Pin = GPIO_PIN_8;
Sergunb 0:8918a71cdbe9 251 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 252 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 253 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
Sergunb 0:8918a71cdbe9 254 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 255
Sergunb 0:8918a71cdbe9 256 //Configure MCO pin to output the HSE clock (25MHz)
Sergunb 0:8918a71cdbe9 257 HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, 1);
Sergunb 0:8918a71cdbe9 258
Sergunb 0:8918a71cdbe9 259 //Select MII interface mode
Sergunb 0:8918a71cdbe9 260 __HAL_AFIO_ETH_MII();
Sergunb 0:8918a71cdbe9 261
Sergunb 0:8918a71cdbe9 262 //Configure MII_MDIO (PA2)
Sergunb 0:8918a71cdbe9 263 GPIO_InitStructure.Pin = GPIO_PIN_2;
Sergunb 0:8918a71cdbe9 264 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 265 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 266 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
Sergunb 0:8918a71cdbe9 267 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 268
Sergunb 0:8918a71cdbe9 269 //Configure MII_PPS_OUT (PB5), ETH_MII_TXD3 (PB8), MII_TX_EN (PB11),
Sergunb 0:8918a71cdbe9 270 //MII_TXD0 (PB12) and MII_TXD1 (PB13)
Sergunb 0:8918a71cdbe9 271 GPIO_InitStructure.Pin = GPIO_PIN_5 | GPIO_PIN_8 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13;
Sergunb 0:8918a71cdbe9 272 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 273 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 274 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
Sergunb 0:8918a71cdbe9 275 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 276
Sergunb 0:8918a71cdbe9 277 //Configure MII_MDC (PC1) and MII_TXD2 (PC2)
Sergunb 0:8918a71cdbe9 278 GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2;
Sergunb 0:8918a71cdbe9 279 GPIO_InitStructure.Mode = GPIO_MODE_AF_PP;
Sergunb 0:8918a71cdbe9 280 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 281 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
Sergunb 0:8918a71cdbe9 282 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 283
Sergunb 0:8918a71cdbe9 284 //Configure ETH_MII_CRS (PA0), ETH_MII_RX_CLK (PA1) and ETH_MII_COL (PA3)
Sergunb 0:8918a71cdbe9 285 GPIO_InitStructure.Pin = GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3;
Sergunb 0:8918a71cdbe9 286 GPIO_InitStructure.Mode = GPIO_MODE_AF_INPUT;
Sergunb 0:8918a71cdbe9 287 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 288 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
Sergunb 0:8918a71cdbe9 289 HAL_GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 290
Sergunb 0:8918a71cdbe9 291 //Configure ETH_MII_RX_ER (PB10)
Sergunb 0:8918a71cdbe9 292 GPIO_InitStructure.Pin = GPIO_PIN_10;
Sergunb 0:8918a71cdbe9 293 GPIO_InitStructure.Mode = GPIO_MODE_AF_INPUT;
Sergunb 0:8918a71cdbe9 294 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 295 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
Sergunb 0:8918a71cdbe9 296 HAL_GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 297
Sergunb 0:8918a71cdbe9 298 //Configure ETH_MII_TX_CLK (PC3)
Sergunb 0:8918a71cdbe9 299 GPIO_InitStructure.Pin = GPIO_PIN_3;
Sergunb 0:8918a71cdbe9 300 GPIO_InitStructure.Mode = GPIO_MODE_AF_INPUT;
Sergunb 0:8918a71cdbe9 301 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 302 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
Sergunb 0:8918a71cdbe9 303 HAL_GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 304
Sergunb 0:8918a71cdbe9 305 //Configure ETH_MII_RX_DV (PD8), ETH_MII_RXD0 (PD9), ETH_MII_RXD1 (PD10),
Sergunb 0:8918a71cdbe9 306 //ETH_MII_RXD2 (PD11) and ETH_MII_RXD3 (PD12)
Sergunb 0:8918a71cdbe9 307 GPIO_InitStructure.Pin = GPIO_PIN_8 | GPIO_PIN_9 | GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12;
Sergunb 0:8918a71cdbe9 308 GPIO_InitStructure.Mode = GPIO_MODE_AF_INPUT;
Sergunb 0:8918a71cdbe9 309 GPIO_InitStructure.Pull = GPIO_NOPULL;
Sergunb 0:8918a71cdbe9 310 GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_HIGH;
Sergunb 0:8918a71cdbe9 311 HAL_GPIO_Init(GPIOD, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 312
Sergunb 0:8918a71cdbe9 313 //Remap Ethernet pins
Sergunb 0:8918a71cdbe9 314 __HAL_AFIO_REMAP_ETH_ENABLE();
Sergunb 0:8918a71cdbe9 315
Sergunb 0:8918a71cdbe9 316 #elif defined(USE_STM3210C_EVAL) && defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 317 //Enable AFIO clock
Sergunb 0:8918a71cdbe9 318 RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
Sergunb 0:8918a71cdbe9 319
Sergunb 0:8918a71cdbe9 320 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 321 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB |
Sergunb 0:8918a71cdbe9 322 RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE);
Sergunb 0:8918a71cdbe9 323
Sergunb 0:8918a71cdbe9 324 //Configure MCO (PA8) as an output
Sergunb 0:8918a71cdbe9 325 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
Sergunb 0:8918a71cdbe9 326 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 327 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
Sergunb 0:8918a71cdbe9 328 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 329
Sergunb 0:8918a71cdbe9 330 //Configure MCO pin to output the HSE clock (25MHz)
Sergunb 0:8918a71cdbe9 331 RCC_MCOConfig(RCC_MCO_HSE);
Sergunb 0:8918a71cdbe9 332
Sergunb 0:8918a71cdbe9 333 //Select MII interface mode
Sergunb 0:8918a71cdbe9 334 GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
Sergunb 0:8918a71cdbe9 335
Sergunb 0:8918a71cdbe9 336 //Configure MII_MDIO (PA2)
Sergunb 0:8918a71cdbe9 337 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
Sergunb 0:8918a71cdbe9 338 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 339 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
Sergunb 0:8918a71cdbe9 340 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 341
Sergunb 0:8918a71cdbe9 342 //Configure MII_PPS_OUT (PB5), ETH_MII_TXD3 (PB8), MII_TX_EN (PB11),
Sergunb 0:8918a71cdbe9 343 //MII_TXD0 (PB12) and MII_TXD1 (PB13)
Sergunb 0:8918a71cdbe9 344 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
Sergunb 0:8918a71cdbe9 345 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 346 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
Sergunb 0:8918a71cdbe9 347 GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 348
Sergunb 0:8918a71cdbe9 349 //Configure MII_MDC (PC1) and MII_TXD2 (PC2)
Sergunb 0:8918a71cdbe9 350 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2;
Sergunb 0:8918a71cdbe9 351 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 352 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
Sergunb 0:8918a71cdbe9 353 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 354
Sergunb 0:8918a71cdbe9 355 //Configure ETH_MII_CRS (PA0), ETH_MII_RX_CLK (PA1) and ETH_MII_COL (PA3)
Sergunb 0:8918a71cdbe9 356 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_3;
Sergunb 0:8918a71cdbe9 357 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 358 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
Sergunb 0:8918a71cdbe9 359 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 360
Sergunb 0:8918a71cdbe9 361 //Configure ETH_MII_RX_ER (PB10)
Sergunb 0:8918a71cdbe9 362 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
Sergunb 0:8918a71cdbe9 363 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 364 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
Sergunb 0:8918a71cdbe9 365 GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 366
Sergunb 0:8918a71cdbe9 367 //Configure ETH_MII_TX_CLK (PC3)
Sergunb 0:8918a71cdbe9 368 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3;
Sergunb 0:8918a71cdbe9 369 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 370 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
Sergunb 0:8918a71cdbe9 371 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 372
Sergunb 0:8918a71cdbe9 373 //Configure ETH_MII_RX_DV (PD8), ETH_MII_RXD0 (PD9), ETH_MII_RXD1 (PD10),
Sergunb 0:8918a71cdbe9 374 //ETH_MII_RXD2 (PD11) and ETH_MII_RXD3 (PD12)
Sergunb 0:8918a71cdbe9 375 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12;
Sergunb 0:8918a71cdbe9 376 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 377 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
Sergunb 0:8918a71cdbe9 378 GPIO_Init(GPIOD, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 379
Sergunb 0:8918a71cdbe9 380 //Remap Ethernet pins
Sergunb 0:8918a71cdbe9 381 GPIO_PinRemapConfig(GPIO_Remap_ETH, ENABLE);
Sergunb 0:8918a71cdbe9 382
Sergunb 0:8918a71cdbe9 383 //STM32-P107 evaluation board?
Sergunb 0:8918a71cdbe9 384 #elif defined(USE_STM32_P107) && defined(USE_STDPERIPH_DRIVER)
Sergunb 0:8918a71cdbe9 385 //Enable AFIO clock
Sergunb 0:8918a71cdbe9 386 RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
Sergunb 0:8918a71cdbe9 387
Sergunb 0:8918a71cdbe9 388 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 389 RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA |
Sergunb 0:8918a71cdbe9 390 RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE);
Sergunb 0:8918a71cdbe9 391
Sergunb 0:8918a71cdbe9 392 //Configure MCO (PA8) as an output
Sergunb 0:8918a71cdbe9 393 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
Sergunb 0:8918a71cdbe9 394 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 395 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
Sergunb 0:8918a71cdbe9 396 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 397
Sergunb 0:8918a71cdbe9 398 //Configure PLL3 to output a 50MHz clock
Sergunb 0:8918a71cdbe9 399 RCC_PLL3Config(RCC_PLL3Mul_10);
Sergunb 0:8918a71cdbe9 400 //Enable PLL3
Sergunb 0:8918a71cdbe9 401 RCC_PLL3Cmd(ENABLE);
Sergunb 0:8918a71cdbe9 402
Sergunb 0:8918a71cdbe9 403 //Wait for the PLL3 to lock
Sergunb 0:8918a71cdbe9 404 while(RCC_GetFlagStatus(RCC_FLAG_PLL3RDY) == RESET);
Sergunb 0:8918a71cdbe9 405
Sergunb 0:8918a71cdbe9 406 //Configure MCO pin to output the PLL3 clock
Sergunb 0:8918a71cdbe9 407 RCC_MCOConfig(RCC_MCO_PLL3CLK);
Sergunb 0:8918a71cdbe9 408
Sergunb 0:8918a71cdbe9 409 //Select RMII interface mode
Sergunb 0:8918a71cdbe9 410 GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_RMII);
Sergunb 0:8918a71cdbe9 411
Sergunb 0:8918a71cdbe9 412 //Configure ETH_MDIO (PA2)
Sergunb 0:8918a71cdbe9 413 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
Sergunb 0:8918a71cdbe9 414 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 415 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
Sergunb 0:8918a71cdbe9 416 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 417
Sergunb 0:8918a71cdbe9 418 //Configure ETH_RMII_TX_EN (PB11), ETH_RMII_TXD0 (PB12) and ETH_RMII_TXD1 (PB13)
Sergunb 0:8918a71cdbe9 419 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13;
Sergunb 0:8918a71cdbe9 420 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 421 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
Sergunb 0:8918a71cdbe9 422 GPIO_Init(GPIOB, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 423
Sergunb 0:8918a71cdbe9 424 //Configure ETH_MDC (PC1)
Sergunb 0:8918a71cdbe9 425 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1;
Sergunb 0:8918a71cdbe9 426 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 427 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
Sergunb 0:8918a71cdbe9 428 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 429
Sergunb 0:8918a71cdbe9 430 //Configure ETH_RMII_REF_CLK (PA1) and ETH_RMII_CRS_DV (PA7)
Sergunb 0:8918a71cdbe9 431 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_7;
Sergunb 0:8918a71cdbe9 432 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 433 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
Sergunb 0:8918a71cdbe9 434 GPIO_Init(GPIOA, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 435
Sergunb 0:8918a71cdbe9 436 //Configure ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5)
Sergunb 0:8918a71cdbe9 437 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4 | GPIO_Pin_5;
Sergunb 0:8918a71cdbe9 438 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
Sergunb 0:8918a71cdbe9 439 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
Sergunb 0:8918a71cdbe9 440 GPIO_Init(GPIOC, &GPIO_InitStructure);
Sergunb 0:8918a71cdbe9 441
Sergunb 0:8918a71cdbe9 442 //Do not remap Ethernet pins
Sergunb 0:8918a71cdbe9 443 GPIO_PinRemapConfig(GPIO_Remap_ETH, DISABLE);
Sergunb 0:8918a71cdbe9 444 #endif
Sergunb 0:8918a71cdbe9 445 }
Sergunb 0:8918a71cdbe9 446
Sergunb 0:8918a71cdbe9 447 #endif
Sergunb 0:8918a71cdbe9 448
Sergunb 0:8918a71cdbe9 449
Sergunb 0:8918a71cdbe9 450 /**
Sergunb 0:8918a71cdbe9 451 * @brief Initialize DMA descriptor lists
Sergunb 0:8918a71cdbe9 452 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 453 **/
Sergunb 0:8918a71cdbe9 454
Sergunb 0:8918a71cdbe9 455 void stm32f107EthInitDmaDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 456 {
Sergunb 0:8918a71cdbe9 457 uint_t i;
Sergunb 0:8918a71cdbe9 458
Sergunb 0:8918a71cdbe9 459 //Initialize TX DMA descriptor list
Sergunb 0:8918a71cdbe9 460 for(i = 0; i < STM32F107_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 461 {
Sergunb 0:8918a71cdbe9 462 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 463 txDmaDesc[i].tdes0 = ETH_TDES0_IC | ETH_TDES0_TCH;
Sergunb 0:8918a71cdbe9 464 //Initialize transmit buffer size
Sergunb 0:8918a71cdbe9 465 txDmaDesc[i].tdes1 = 0;
Sergunb 0:8918a71cdbe9 466 //Transmit buffer address
Sergunb 0:8918a71cdbe9 467 txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 468 //Next descriptor address
Sergunb 0:8918a71cdbe9 469 txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 470 }
Sergunb 0:8918a71cdbe9 471
Sergunb 0:8918a71cdbe9 472 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 473 txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 474 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 475 txCurDmaDesc = &txDmaDesc[0];
Sergunb 0:8918a71cdbe9 476
Sergunb 0:8918a71cdbe9 477 //Initialize RX DMA descriptor list
Sergunb 0:8918a71cdbe9 478 for(i = 0; i < STM32F107_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 479 {
Sergunb 0:8918a71cdbe9 480 //The descriptor is initially owned by the DMA
Sergunb 0:8918a71cdbe9 481 rxDmaDesc[i].rdes0 = ETH_RDES0_OWN;
Sergunb 0:8918a71cdbe9 482 //Use chain structure rather than ring structure
Sergunb 0:8918a71cdbe9 483 rxDmaDesc[i].rdes1 = ETH_RDES1_RCH | (STM32F107_ETH_RX_BUFFER_SIZE & ETH_RDES1_RBS1);
Sergunb 0:8918a71cdbe9 484 //Receive buffer address
Sergunb 0:8918a71cdbe9 485 rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 486 //Next descriptor address
Sergunb 0:8918a71cdbe9 487 rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1];
Sergunb 0:8918a71cdbe9 488 }
Sergunb 0:8918a71cdbe9 489
Sergunb 0:8918a71cdbe9 490 //The last descriptor is chained to the first entry
Sergunb 0:8918a71cdbe9 491 rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 492 //Point to the very first descriptor
Sergunb 0:8918a71cdbe9 493 rxCurDmaDesc = &rxDmaDesc[0];
Sergunb 0:8918a71cdbe9 494
Sergunb 0:8918a71cdbe9 495 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 496 ETH->DMATDLAR = (uint32_t) txDmaDesc;
Sergunb 0:8918a71cdbe9 497 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 498 ETH->DMARDLAR = (uint32_t) rxDmaDesc;
Sergunb 0:8918a71cdbe9 499 }
Sergunb 0:8918a71cdbe9 500
Sergunb 0:8918a71cdbe9 501
Sergunb 0:8918a71cdbe9 502 /**
Sergunb 0:8918a71cdbe9 503 * @brief STM32F107 Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 504 *
Sergunb 0:8918a71cdbe9 505 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 506 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 507 *
Sergunb 0:8918a71cdbe9 508 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 509 **/
Sergunb 0:8918a71cdbe9 510
Sergunb 0:8918a71cdbe9 511 void stm32f107EthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 512 {
Sergunb 0:8918a71cdbe9 513 //Handle periodic operations
Sergunb 0:8918a71cdbe9 514 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 515 }
Sergunb 0:8918a71cdbe9 516
Sergunb 0:8918a71cdbe9 517
Sergunb 0:8918a71cdbe9 518 /**
Sergunb 0:8918a71cdbe9 519 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 520 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 521 **/
Sergunb 0:8918a71cdbe9 522
Sergunb 0:8918a71cdbe9 523 void stm32f107EthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 524 {
Sergunb 0:8918a71cdbe9 525 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 526 NVIC_EnableIRQ(ETH_IRQn);
Sergunb 0:8918a71cdbe9 527 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 528 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 529 }
Sergunb 0:8918a71cdbe9 530
Sergunb 0:8918a71cdbe9 531
Sergunb 0:8918a71cdbe9 532 /**
Sergunb 0:8918a71cdbe9 533 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 534 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 535 **/
Sergunb 0:8918a71cdbe9 536
Sergunb 0:8918a71cdbe9 537 void stm32f107EthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 538 {
Sergunb 0:8918a71cdbe9 539 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 540 NVIC_DisableIRQ(ETH_IRQn);
Sergunb 0:8918a71cdbe9 541 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 542 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 543 }
Sergunb 0:8918a71cdbe9 544
Sergunb 0:8918a71cdbe9 545
Sergunb 0:8918a71cdbe9 546 /**
Sergunb 0:8918a71cdbe9 547 * @brief STM32F107 Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 548 **/
Sergunb 0:8918a71cdbe9 549
Sergunb 0:8918a71cdbe9 550 void ETH_IRQHandler(void)
Sergunb 0:8918a71cdbe9 551 {
Sergunb 0:8918a71cdbe9 552 bool_t flag;
Sergunb 0:8918a71cdbe9 553 uint32_t status;
Sergunb 0:8918a71cdbe9 554
Sergunb 0:8918a71cdbe9 555 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 556 osEnterIsr();
Sergunb 0:8918a71cdbe9 557
Sergunb 0:8918a71cdbe9 558 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 559 flag = FALSE;
Sergunb 0:8918a71cdbe9 560
Sergunb 0:8918a71cdbe9 561 //Read DMA status register
Sergunb 0:8918a71cdbe9 562 status = ETH->DMASR;
Sergunb 0:8918a71cdbe9 563
Sergunb 0:8918a71cdbe9 564 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 565 if(status & ETH_DMASR_TS)
Sergunb 0:8918a71cdbe9 566 {
Sergunb 0:8918a71cdbe9 567 //Clear TS interrupt flag
Sergunb 0:8918a71cdbe9 568 ETH->DMASR = ETH_DMASR_TS;
Sergunb 0:8918a71cdbe9 569
Sergunb 0:8918a71cdbe9 570 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 571 if(!(txCurDmaDesc->tdes0 & ETH_TDES0_OWN))
Sergunb 0:8918a71cdbe9 572 {
Sergunb 0:8918a71cdbe9 573 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 574 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 575 }
Sergunb 0:8918a71cdbe9 576 }
Sergunb 0:8918a71cdbe9 577
Sergunb 0:8918a71cdbe9 578 //A packet has been received?
Sergunb 0:8918a71cdbe9 579 if(status & ETH_DMASR_RS)
Sergunb 0:8918a71cdbe9 580 {
Sergunb 0:8918a71cdbe9 581 //Disable RIE interrupt
Sergunb 0:8918a71cdbe9 582 ETH->DMAIER &= ~ETH_DMAIER_RIE;
Sergunb 0:8918a71cdbe9 583
Sergunb 0:8918a71cdbe9 584 //Set event flag
Sergunb 0:8918a71cdbe9 585 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 586 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 587 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 588 }
Sergunb 0:8918a71cdbe9 589
Sergunb 0:8918a71cdbe9 590 //Clear NIS interrupt flag
Sergunb 0:8918a71cdbe9 591 ETH->DMASR = ETH_DMASR_NIS;
Sergunb 0:8918a71cdbe9 592
Sergunb 0:8918a71cdbe9 593 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 594 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 595 }
Sergunb 0:8918a71cdbe9 596
Sergunb 0:8918a71cdbe9 597
Sergunb 0:8918a71cdbe9 598 /**
Sergunb 0:8918a71cdbe9 599 * @brief STM32F107 Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 600 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 601 **/
Sergunb 0:8918a71cdbe9 602
Sergunb 0:8918a71cdbe9 603 void stm32f107EthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 604 {
Sergunb 0:8918a71cdbe9 605 error_t error;
Sergunb 0:8918a71cdbe9 606
Sergunb 0:8918a71cdbe9 607 //Packet received?
Sergunb 0:8918a71cdbe9 608 if(ETH->DMASR & ETH_DMASR_RS)
Sergunb 0:8918a71cdbe9 609 {
Sergunb 0:8918a71cdbe9 610 //Clear interrupt flag
Sergunb 0:8918a71cdbe9 611 ETH->DMASR = ETH_DMASR_RS;
Sergunb 0:8918a71cdbe9 612
Sergunb 0:8918a71cdbe9 613 //Process all pending packets
Sergunb 0:8918a71cdbe9 614 do
Sergunb 0:8918a71cdbe9 615 {
Sergunb 0:8918a71cdbe9 616 //Read incoming packet
Sergunb 0:8918a71cdbe9 617 error = stm32f107EthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 618
Sergunb 0:8918a71cdbe9 619 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 620 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 621 }
Sergunb 0:8918a71cdbe9 622
Sergunb 0:8918a71cdbe9 623 //Re-enable DMA interrupts
Sergunb 0:8918a71cdbe9 624 ETH->DMAIER |= ETH_DMAIER_NISE | ETH_DMAIER_RIE | ETH_DMAIER_TIE;
Sergunb 0:8918a71cdbe9 625 }
Sergunb 0:8918a71cdbe9 626
Sergunb 0:8918a71cdbe9 627
Sergunb 0:8918a71cdbe9 628 /**
Sergunb 0:8918a71cdbe9 629 * @brief Send a packet
Sergunb 0:8918a71cdbe9 630 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 631 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 632 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 633 * @return Error code
Sergunb 0:8918a71cdbe9 634 **/
Sergunb 0:8918a71cdbe9 635
Sergunb 0:8918a71cdbe9 636 error_t stm32f107EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 637 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 638 {
Sergunb 0:8918a71cdbe9 639 size_t length;
Sergunb 0:8918a71cdbe9 640
Sergunb 0:8918a71cdbe9 641 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 642 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 643
Sergunb 0:8918a71cdbe9 644 //Check the frame length
Sergunb 0:8918a71cdbe9 645 if(length > STM32F107_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 646 {
Sergunb 0:8918a71cdbe9 647 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 648 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 649 //Report an error
Sergunb 0:8918a71cdbe9 650 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 651 }
Sergunb 0:8918a71cdbe9 652
Sergunb 0:8918a71cdbe9 653 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 654 if(txCurDmaDesc->tdes0 & ETH_TDES0_OWN)
Sergunb 0:8918a71cdbe9 655 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 656
Sergunb 0:8918a71cdbe9 657 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 658 netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length);
Sergunb 0:8918a71cdbe9 659
Sergunb 0:8918a71cdbe9 660 //Write the number of bytes to send
Sergunb 0:8918a71cdbe9 661 txCurDmaDesc->tdes1 = length & ETH_TDES1_TBS1;
Sergunb 0:8918a71cdbe9 662 //Set LS and FS flags as the data fits in a single buffer
Sergunb 0:8918a71cdbe9 663 txCurDmaDesc->tdes0 |= ETH_TDES0_LS | ETH_TDES0_FS;
Sergunb 0:8918a71cdbe9 664 //Give the ownership of the descriptor to the DMA
Sergunb 0:8918a71cdbe9 665 txCurDmaDesc->tdes0 |= ETH_TDES0_OWN;
Sergunb 0:8918a71cdbe9 666
Sergunb 0:8918a71cdbe9 667 //Clear TBUS flag to resume processing
Sergunb 0:8918a71cdbe9 668 ETH->DMASR = ETH_DMASR_TBUS;
Sergunb 0:8918a71cdbe9 669 //Instruct the DMA to poll the transmit descriptor list
Sergunb 0:8918a71cdbe9 670 ETH->DMATPDR = 0;
Sergunb 0:8918a71cdbe9 671
Sergunb 0:8918a71cdbe9 672 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 673 txCurDmaDesc = (Stm32f107TxDmaDesc *) txCurDmaDesc->tdes3;
Sergunb 0:8918a71cdbe9 674
Sergunb 0:8918a71cdbe9 675 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 676 if(!(txCurDmaDesc->tdes0 & ETH_TDES0_OWN))
Sergunb 0:8918a71cdbe9 677 {
Sergunb 0:8918a71cdbe9 678 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 679 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 680 }
Sergunb 0:8918a71cdbe9 681
Sergunb 0:8918a71cdbe9 682 //Data successfully written
Sergunb 0:8918a71cdbe9 683 return NO_ERROR;
Sergunb 0:8918a71cdbe9 684 }
Sergunb 0:8918a71cdbe9 685
Sergunb 0:8918a71cdbe9 686
Sergunb 0:8918a71cdbe9 687 /**
Sergunb 0:8918a71cdbe9 688 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 689 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 690 * @return Error code
Sergunb 0:8918a71cdbe9 691 **/
Sergunb 0:8918a71cdbe9 692
Sergunb 0:8918a71cdbe9 693 error_t stm32f107EthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 694 {
Sergunb 0:8918a71cdbe9 695 error_t error;
Sergunb 0:8918a71cdbe9 696 size_t n;
Sergunb 0:8918a71cdbe9 697
Sergunb 0:8918a71cdbe9 698 //The current buffer is available for reading?
Sergunb 0:8918a71cdbe9 699 if(!(rxCurDmaDesc->rdes0 & ETH_RDES0_OWN))
Sergunb 0:8918a71cdbe9 700 {
Sergunb 0:8918a71cdbe9 701 //FS and LS flags should be set
Sergunb 0:8918a71cdbe9 702 if((rxCurDmaDesc->rdes0 & ETH_RDES0_FS) && (rxCurDmaDesc->rdes0 & ETH_RDES0_LS))
Sergunb 0:8918a71cdbe9 703 {
Sergunb 0:8918a71cdbe9 704 //Make sure no error occurred
Sergunb 0:8918a71cdbe9 705 if(!(rxCurDmaDesc->rdes0 & ETH_RDES0_ES))
Sergunb 0:8918a71cdbe9 706 {
Sergunb 0:8918a71cdbe9 707 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 708 n = (rxCurDmaDesc->rdes0 & ETH_RDES0_FL) >> 16;
Sergunb 0:8918a71cdbe9 709 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 710 n = MIN(n, STM32F107_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 711
Sergunb 0:8918a71cdbe9 712 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 713 nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n);
Sergunb 0:8918a71cdbe9 714
Sergunb 0:8918a71cdbe9 715 //Valid packet received
Sergunb 0:8918a71cdbe9 716 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 717 }
Sergunb 0:8918a71cdbe9 718 else
Sergunb 0:8918a71cdbe9 719 {
Sergunb 0:8918a71cdbe9 720 //The received packet contains an error
Sergunb 0:8918a71cdbe9 721 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 722 }
Sergunb 0:8918a71cdbe9 723 }
Sergunb 0:8918a71cdbe9 724 else
Sergunb 0:8918a71cdbe9 725 {
Sergunb 0:8918a71cdbe9 726 //The packet is not valid
Sergunb 0:8918a71cdbe9 727 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 728 }
Sergunb 0:8918a71cdbe9 729
Sergunb 0:8918a71cdbe9 730 //Give the ownership of the descriptor back to the DMA
Sergunb 0:8918a71cdbe9 731 rxCurDmaDesc->rdes0 = ETH_RDES0_OWN;
Sergunb 0:8918a71cdbe9 732 //Point to the next descriptor in the list
Sergunb 0:8918a71cdbe9 733 rxCurDmaDesc = (Stm32f107RxDmaDesc *) rxCurDmaDesc->rdes3;
Sergunb 0:8918a71cdbe9 734 }
Sergunb 0:8918a71cdbe9 735 else
Sergunb 0:8918a71cdbe9 736 {
Sergunb 0:8918a71cdbe9 737 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 738 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 739 }
Sergunb 0:8918a71cdbe9 740
Sergunb 0:8918a71cdbe9 741 //Clear RBUS flag to resume processing
Sergunb 0:8918a71cdbe9 742 ETH->DMASR = ETH_DMASR_RBUS;
Sergunb 0:8918a71cdbe9 743 //Instruct the DMA to poll the receive descriptor list
Sergunb 0:8918a71cdbe9 744 ETH->DMARPDR = 0;
Sergunb 0:8918a71cdbe9 745
Sergunb 0:8918a71cdbe9 746 //Return status code
Sergunb 0:8918a71cdbe9 747 return error;
Sergunb 0:8918a71cdbe9 748 }
Sergunb 0:8918a71cdbe9 749
Sergunb 0:8918a71cdbe9 750
Sergunb 0:8918a71cdbe9 751 /**
Sergunb 0:8918a71cdbe9 752 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 753 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 754 * @return Error code
Sergunb 0:8918a71cdbe9 755 **/
Sergunb 0:8918a71cdbe9 756
Sergunb 0:8918a71cdbe9 757 error_t stm32f107EthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 758 {
Sergunb 0:8918a71cdbe9 759 uint_t i;
Sergunb 0:8918a71cdbe9 760 uint_t k;
Sergunb 0:8918a71cdbe9 761 uint32_t crc;
Sergunb 0:8918a71cdbe9 762 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 763 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 764
Sergunb 0:8918a71cdbe9 765 //Debug message
Sergunb 0:8918a71cdbe9 766 TRACE_DEBUG("Updating STM32F107 hash table...\r\n");
Sergunb 0:8918a71cdbe9 767
Sergunb 0:8918a71cdbe9 768 //Clear hash table
Sergunb 0:8918a71cdbe9 769 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 770 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 771
Sergunb 0:8918a71cdbe9 772 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 773 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 774 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 775 {
Sergunb 0:8918a71cdbe9 776 //Point to the current entry
Sergunb 0:8918a71cdbe9 777 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 778
Sergunb 0:8918a71cdbe9 779 //Valid entry?
Sergunb 0:8918a71cdbe9 780 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 781 {
Sergunb 0:8918a71cdbe9 782 //Compute CRC over the current MAC address
Sergunb 0:8918a71cdbe9 783 crc = stm32f107EthCalcCrc(&entry->addr, sizeof(MacAddr));
Sergunb 0:8918a71cdbe9 784
Sergunb 0:8918a71cdbe9 785 //The upper 6 bits in the CRC register are used to index the
Sergunb 0:8918a71cdbe9 786 //contents of the hash table
Sergunb 0:8918a71cdbe9 787 k = (crc >> 26) & 0x3F;
Sergunb 0:8918a71cdbe9 788
Sergunb 0:8918a71cdbe9 789 //Update hash table contents
Sergunb 0:8918a71cdbe9 790 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 791 }
Sergunb 0:8918a71cdbe9 792 }
Sergunb 0:8918a71cdbe9 793
Sergunb 0:8918a71cdbe9 794 //Write the hash table
Sergunb 0:8918a71cdbe9 795 ETH->MACHTLR = hashTable[0];
Sergunb 0:8918a71cdbe9 796 ETH->MACHTHR = hashTable[1];
Sergunb 0:8918a71cdbe9 797
Sergunb 0:8918a71cdbe9 798 //Debug message
Sergunb 0:8918a71cdbe9 799 TRACE_DEBUG(" MACHTLR = %08" PRIX32 "\r\n", ETH->MACHTLR);
Sergunb 0:8918a71cdbe9 800 TRACE_DEBUG(" MACHTHR = %08" PRIX32 "\r\n", ETH->MACHTHR);
Sergunb 0:8918a71cdbe9 801
Sergunb 0:8918a71cdbe9 802 //Successful processing
Sergunb 0:8918a71cdbe9 803 return NO_ERROR;
Sergunb 0:8918a71cdbe9 804 }
Sergunb 0:8918a71cdbe9 805
Sergunb 0:8918a71cdbe9 806
Sergunb 0:8918a71cdbe9 807 /**
Sergunb 0:8918a71cdbe9 808 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 809 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 810 * @return Error code
Sergunb 0:8918a71cdbe9 811 **/
Sergunb 0:8918a71cdbe9 812
Sergunb 0:8918a71cdbe9 813 error_t stm32f107EthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 814 {
Sergunb 0:8918a71cdbe9 815 uint32_t config ;
Sergunb 0:8918a71cdbe9 816
Sergunb 0:8918a71cdbe9 817 //Read current MAC configuration
Sergunb 0:8918a71cdbe9 818 config = ETH->MACCR;
Sergunb 0:8918a71cdbe9 819
Sergunb 0:8918a71cdbe9 820 //10BASE-T or 100BASE-TX operation mode?
Sergunb 0:8918a71cdbe9 821 if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
Sergunb 0:8918a71cdbe9 822 config |= ETH_MACCR_FES;
Sergunb 0:8918a71cdbe9 823 else
Sergunb 0:8918a71cdbe9 824 config &= ~ETH_MACCR_FES;
Sergunb 0:8918a71cdbe9 825
Sergunb 0:8918a71cdbe9 826 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 827 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 828 config |= ETH_MACCR_DM;
Sergunb 0:8918a71cdbe9 829 else
Sergunb 0:8918a71cdbe9 830 config &= ~ETH_MACCR_DM;
Sergunb 0:8918a71cdbe9 831
Sergunb 0:8918a71cdbe9 832 //Update MAC configuration register
Sergunb 0:8918a71cdbe9 833 ETH->MACCR = config;
Sergunb 0:8918a71cdbe9 834
Sergunb 0:8918a71cdbe9 835 //Successful processing
Sergunb 0:8918a71cdbe9 836 return NO_ERROR;
Sergunb 0:8918a71cdbe9 837 }
Sergunb 0:8918a71cdbe9 838
Sergunb 0:8918a71cdbe9 839
Sergunb 0:8918a71cdbe9 840 /**
Sergunb 0:8918a71cdbe9 841 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 842 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 843 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 844 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 845 **/
Sergunb 0:8918a71cdbe9 846
Sergunb 0:8918a71cdbe9 847 void stm32f107EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 848 {
Sergunb 0:8918a71cdbe9 849 uint32_t value;
Sergunb 0:8918a71cdbe9 850
Sergunb 0:8918a71cdbe9 851 //Take care not to alter MDC clock configuration
Sergunb 0:8918a71cdbe9 852 value = ETH->MACMIIAR & ETH_MACMIIAR_CR;
Sergunb 0:8918a71cdbe9 853 //Set up a write operation
Sergunb 0:8918a71cdbe9 854 value |= ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
Sergunb 0:8918a71cdbe9 855 //PHY address
Sergunb 0:8918a71cdbe9 856 value |= (phyAddr << 11) & ETH_MACMIIAR_PA;
Sergunb 0:8918a71cdbe9 857 //Register address
Sergunb 0:8918a71cdbe9 858 value |= (regAddr << 6) & ETH_MACMIIAR_MR;
Sergunb 0:8918a71cdbe9 859
Sergunb 0:8918a71cdbe9 860 //Data to be written in the PHY register
Sergunb 0:8918a71cdbe9 861 ETH->MACMIIDR = data & ETH_MACMIIDR_MD;
Sergunb 0:8918a71cdbe9 862
Sergunb 0:8918a71cdbe9 863 //Start a write operation
Sergunb 0:8918a71cdbe9 864 ETH->MACMIIAR = value;
Sergunb 0:8918a71cdbe9 865 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 866 while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
Sergunb 0:8918a71cdbe9 867 }
Sergunb 0:8918a71cdbe9 868
Sergunb 0:8918a71cdbe9 869
Sergunb 0:8918a71cdbe9 870 /**
Sergunb 0:8918a71cdbe9 871 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 872 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 873 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 874 * @return Register value
Sergunb 0:8918a71cdbe9 875 **/
Sergunb 0:8918a71cdbe9 876
Sergunb 0:8918a71cdbe9 877 uint16_t stm32f107EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 878 {
Sergunb 0:8918a71cdbe9 879 uint32_t value;
Sergunb 0:8918a71cdbe9 880
Sergunb 0:8918a71cdbe9 881 //Take care not to alter MDC clock configuration
Sergunb 0:8918a71cdbe9 882 value = ETH->MACMIIAR & ETH_MACMIIAR_CR;
Sergunb 0:8918a71cdbe9 883 //Set up a read operation
Sergunb 0:8918a71cdbe9 884 value |= ETH_MACMIIAR_MB;
Sergunb 0:8918a71cdbe9 885 //PHY address
Sergunb 0:8918a71cdbe9 886 value |= (phyAddr << 11) & ETH_MACMIIAR_PA;
Sergunb 0:8918a71cdbe9 887 //Register address
Sergunb 0:8918a71cdbe9 888 value |= (regAddr << 6) & ETH_MACMIIAR_MR;
Sergunb 0:8918a71cdbe9 889
Sergunb 0:8918a71cdbe9 890 //Start a read operation
Sergunb 0:8918a71cdbe9 891 ETH->MACMIIAR = value;
Sergunb 0:8918a71cdbe9 892 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 893 while(ETH->MACMIIAR & ETH_MACMIIAR_MB);
Sergunb 0:8918a71cdbe9 894
Sergunb 0:8918a71cdbe9 895 //Return PHY register contents
Sergunb 0:8918a71cdbe9 896 return ETH->MACMIIDR & ETH_MACMIIDR_MD;
Sergunb 0:8918a71cdbe9 897 }
Sergunb 0:8918a71cdbe9 898
Sergunb 0:8918a71cdbe9 899
Sergunb 0:8918a71cdbe9 900 /**
Sergunb 0:8918a71cdbe9 901 * @brief CRC calculation
Sergunb 0:8918a71cdbe9 902 * @param[in] data Pointer to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 903 * @param[in] length Number of bytes to process
Sergunb 0:8918a71cdbe9 904 * @return Resulting CRC value
Sergunb 0:8918a71cdbe9 905 **/
Sergunb 0:8918a71cdbe9 906
Sergunb 0:8918a71cdbe9 907 uint32_t stm32f107EthCalcCrc(const void *data, size_t length)
Sergunb 0:8918a71cdbe9 908 {
Sergunb 0:8918a71cdbe9 909 uint_t i;
Sergunb 0:8918a71cdbe9 910 uint_t j;
Sergunb 0:8918a71cdbe9 911
Sergunb 0:8918a71cdbe9 912 //Point to the data over which to calculate the CRC
Sergunb 0:8918a71cdbe9 913 const uint8_t *p = (uint8_t *) data;
Sergunb 0:8918a71cdbe9 914 //CRC preset value
Sergunb 0:8918a71cdbe9 915 uint32_t crc = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 916
Sergunb 0:8918a71cdbe9 917 //Loop through data
Sergunb 0:8918a71cdbe9 918 for(i = 0; i < length; i++)
Sergunb 0:8918a71cdbe9 919 {
Sergunb 0:8918a71cdbe9 920 //The message is processed bit by bit
Sergunb 0:8918a71cdbe9 921 for(j = 0; j < 8; j++)
Sergunb 0:8918a71cdbe9 922 {
Sergunb 0:8918a71cdbe9 923 //Update CRC value
Sergunb 0:8918a71cdbe9 924 if(((crc >> 31) ^ (p[i] >> j)) & 0x01)
Sergunb 0:8918a71cdbe9 925 crc = (crc << 1) ^ 0x04C11DB7;
Sergunb 0:8918a71cdbe9 926 else
Sergunb 0:8918a71cdbe9 927 crc = crc << 1;
Sergunb 0:8918a71cdbe9 928 }
Sergunb 0:8918a71cdbe9 929 }
Sergunb 0:8918a71cdbe9 930
Sergunb 0:8918a71cdbe9 931 //Return CRC value
Sergunb 0:8918a71cdbe9 932 return ~crc;
Sergunb 0:8918a71cdbe9 933 }
Sergunb 0:8918a71cdbe9 934