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cyclone_tcp/drivers/sama5d3_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

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Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file sama5d3_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief SAMA5D3 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include <limits.h>
Sergunb 0:8918a71cdbe9 34 #include "sama5d3x.h"
Sergunb 0:8918a71cdbe9 35 #include "core/net.h"
Sergunb 0:8918a71cdbe9 36 #include "drivers/sama5d3_eth.h"
Sergunb 0:8918a71cdbe9 37 #include "debug.h"
Sergunb 0:8918a71cdbe9 38
Sergunb 0:8918a71cdbe9 39 //Underlying network interface
Sergunb 0:8918a71cdbe9 40 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 43 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 44
Sergunb 0:8918a71cdbe9 45 //TX buffer
Sergunb 0:8918a71cdbe9 46 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 47 #pragma location = ".ram_no_cache"
Sergunb 0:8918a71cdbe9 48 static uint8_t txBuffer[SAMA5D3_ETH_TX_BUFFER_COUNT][SAMA5D3_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 49 //RX buffer
Sergunb 0:8918a71cdbe9 50 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 51 #pragma location = ".ram_no_cache"
Sergunb 0:8918a71cdbe9 52 static uint8_t rxBuffer[SAMA5D3_ETH_RX_BUFFER_COUNT][SAMA5D3_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 53 //TX buffer descriptors
Sergunb 0:8918a71cdbe9 54 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 55 #pragma location = ".ram_no_cache"
Sergunb 0:8918a71cdbe9 56 static Sama5d3TxBufferDesc txBufferDesc[SAMA5D3_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 57 //RX buffer descriptors
Sergunb 0:8918a71cdbe9 58 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 59 #pragma location = ".ram_no_cache"
Sergunb 0:8918a71cdbe9 60 static Sama5d3RxBufferDesc rxBufferDesc[SAMA5D3_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 61
Sergunb 0:8918a71cdbe9 62 //GCC compiler?
Sergunb 0:8918a71cdbe9 63 #else
Sergunb 0:8918a71cdbe9 64
Sergunb 0:8918a71cdbe9 65 //TX buffer
Sergunb 0:8918a71cdbe9 66 static uint8_t txBuffer[SAMA5D3_ETH_TX_BUFFER_COUNT][SAMA5D3_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 67 __attribute__((aligned(8), __section__(".ram_no_cache")));
Sergunb 0:8918a71cdbe9 68 //RX buffer
Sergunb 0:8918a71cdbe9 69 static uint8_t rxBuffer[SAMA5D3_ETH_RX_BUFFER_COUNT][SAMA5D3_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 70 __attribute__((aligned(8), __section__(".ram_no_cache")));
Sergunb 0:8918a71cdbe9 71 //TX buffer descriptors
Sergunb 0:8918a71cdbe9 72 static Sama5d3TxBufferDesc txBufferDesc[SAMA5D3_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 73 __attribute__((aligned(8), __section__(".ram_no_cache")));
Sergunb 0:8918a71cdbe9 74 //RX buffer descriptors
Sergunb 0:8918a71cdbe9 75 static Sama5d3RxBufferDesc rxBufferDesc[SAMA5D3_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 76 __attribute__((aligned(8), __section__(".ram_no_cache")));
Sergunb 0:8918a71cdbe9 77
Sergunb 0:8918a71cdbe9 78 #endif
Sergunb 0:8918a71cdbe9 79
Sergunb 0:8918a71cdbe9 80 //TX buffer index
Sergunb 0:8918a71cdbe9 81 static uint_t txBufferIndex;
Sergunb 0:8918a71cdbe9 82 //RX buffer index
Sergunb 0:8918a71cdbe9 83 static uint_t rxBufferIndex;
Sergunb 0:8918a71cdbe9 84
Sergunb 0:8918a71cdbe9 85
Sergunb 0:8918a71cdbe9 86 /**
Sergunb 0:8918a71cdbe9 87 * @brief SAMA5D3 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 88 **/
Sergunb 0:8918a71cdbe9 89
Sergunb 0:8918a71cdbe9 90 const NicDriver sama5d3EthDriver =
Sergunb 0:8918a71cdbe9 91 {
Sergunb 0:8918a71cdbe9 92 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 93 ETH_MTU,
Sergunb 0:8918a71cdbe9 94 sama5d3EthInit,
Sergunb 0:8918a71cdbe9 95 sama5d3EthTick,
Sergunb 0:8918a71cdbe9 96 sama5d3EthEnableIrq,
Sergunb 0:8918a71cdbe9 97 sama5d3EthDisableIrq,
Sergunb 0:8918a71cdbe9 98 sama5d3EthEventHandler,
Sergunb 0:8918a71cdbe9 99 sama5d3EthSendPacket,
Sergunb 0:8918a71cdbe9 100 sama5d3EthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 101 sama5d3EthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 102 sama5d3EthWritePhyReg,
Sergunb 0:8918a71cdbe9 103 sama5d3EthReadPhyReg,
Sergunb 0:8918a71cdbe9 104 TRUE,
Sergunb 0:8918a71cdbe9 105 TRUE,
Sergunb 0:8918a71cdbe9 106 TRUE,
Sergunb 0:8918a71cdbe9 107 FALSE
Sergunb 0:8918a71cdbe9 108 };
Sergunb 0:8918a71cdbe9 109
Sergunb 0:8918a71cdbe9 110
Sergunb 0:8918a71cdbe9 111 /**
Sergunb 0:8918a71cdbe9 112 * @brief SAMA5D3 Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 113 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 114 * @return Error code
Sergunb 0:8918a71cdbe9 115 **/
Sergunb 0:8918a71cdbe9 116
Sergunb 0:8918a71cdbe9 117 error_t sama5d3EthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 118 {
Sergunb 0:8918a71cdbe9 119 error_t error;
Sergunb 0:8918a71cdbe9 120 volatile uint32_t status;
Sergunb 0:8918a71cdbe9 121
Sergunb 0:8918a71cdbe9 122 //Debug message
Sergunb 0:8918a71cdbe9 123 TRACE_INFO("Initializing SAMA5D3 Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 124
Sergunb 0:8918a71cdbe9 125 //Save underlying network interface
Sergunb 0:8918a71cdbe9 126 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 127
Sergunb 0:8918a71cdbe9 128 //Enable EMAC peripheral clock
Sergunb 0:8918a71cdbe9 129 PMC->PMC_PCER1 = (1 << (ID_EMAC - 32));
Sergunb 0:8918a71cdbe9 130 //Enable IRQ controller peripheral clock
Sergunb 0:8918a71cdbe9 131 PMC->PMC_PCER1 = (1 << (ID_IRQ - 32));
Sergunb 0:8918a71cdbe9 132
Sergunb 0:8918a71cdbe9 133 //GPIO configuration
Sergunb 0:8918a71cdbe9 134 sama5d3EthInitGpio(interface);
Sergunb 0:8918a71cdbe9 135
Sergunb 0:8918a71cdbe9 136 //Configure MDC clock speed
Sergunb 0:8918a71cdbe9 137 EMAC->EMAC_NCFGR = EMAC_NCFGR_CLK_MCK_64;
Sergunb 0:8918a71cdbe9 138 //Enable management port (MDC and MDIO)
Sergunb 0:8918a71cdbe9 139 EMAC->EMAC_NCR |= EMAC_NCR_MPE;
Sergunb 0:8918a71cdbe9 140
Sergunb 0:8918a71cdbe9 141 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 142 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 143 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 144 if(error)
Sergunb 0:8918a71cdbe9 145 return error;
Sergunb 0:8918a71cdbe9 146
Sergunb 0:8918a71cdbe9 147 //Set the MAC address
Sergunb 0:8918a71cdbe9 148 EMAC->EMAC_SA[0].EMAC_SAxB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 149 EMAC->EMAC_SA[0].EMAC_SAxT = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 150
Sergunb 0:8918a71cdbe9 151 //Configure the receive filter
Sergunb 0:8918a71cdbe9 152 EMAC->EMAC_NCFGR |= EMAC_NCFGR_UNI | EMAC_NCFGR_MTI;
Sergunb 0:8918a71cdbe9 153
Sergunb 0:8918a71cdbe9 154 //Initialize hash table
Sergunb 0:8918a71cdbe9 155 EMAC->EMAC_HRB = 0;
Sergunb 0:8918a71cdbe9 156 EMAC->EMAC_HRT = 0;
Sergunb 0:8918a71cdbe9 157
Sergunb 0:8918a71cdbe9 158 //Initialize buffer descriptors
Sergunb 0:8918a71cdbe9 159 sama5d3EthInitBufferDesc(interface);
Sergunb 0:8918a71cdbe9 160
Sergunb 0:8918a71cdbe9 161 //Clear transmit status register
Sergunb 0:8918a71cdbe9 162 EMAC->EMAC_TSR = EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
Sergunb 0:8918a71cdbe9 163 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR;
Sergunb 0:8918a71cdbe9 164 //Clear receive status register
Sergunb 0:8918a71cdbe9 165 EMAC->EMAC_RSR = EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA;
Sergunb 0:8918a71cdbe9 166
Sergunb 0:8918a71cdbe9 167 //First disable all EMAC interrupts
Sergunb 0:8918a71cdbe9 168 EMAC->EMAC_IDR = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 169 //Only the desired ones are enabled
Sergunb 0:8918a71cdbe9 170 EMAC->EMAC_IER = EMAC_IER_ROVR | EMAC_IER_TCOMP | EMAC_IER_TXERR |
Sergunb 0:8918a71cdbe9 171 EMAC_IER_RLE | EMAC_IER_TUND | EMAC_IER_RXUBR | EMAC_IER_RCOMP;
Sergunb 0:8918a71cdbe9 172
Sergunb 0:8918a71cdbe9 173 //Read EMAC ISR register to clear any pending interrupt
Sergunb 0:8918a71cdbe9 174 status = EMAC->EMAC_ISR;
Sergunb 0:8918a71cdbe9 175
Sergunb 0:8918a71cdbe9 176 //Configure interrupt controller
Sergunb 0:8918a71cdbe9 177 AIC->AIC_SSR = ID_EMAC;
Sergunb 0:8918a71cdbe9 178 AIC->AIC_SMR = AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE | AIC_SMR_PRIOR(SAMA5D3_ETH_IRQ_PRIORITY);
Sergunb 0:8918a71cdbe9 179 AIC->AIC_SVR = (uint32_t) sama5d3EthIrqHandler;
Sergunb 0:8918a71cdbe9 180
Sergunb 0:8918a71cdbe9 181 //Enable the EMAC to transmit and receive data
Sergunb 0:8918a71cdbe9 182 EMAC->EMAC_NCR |= EMAC_NCR_TE | EMAC_NCR_RE;
Sergunb 0:8918a71cdbe9 183
Sergunb 0:8918a71cdbe9 184 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 185 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 186
Sergunb 0:8918a71cdbe9 187 //Successful initialization
Sergunb 0:8918a71cdbe9 188 return NO_ERROR;
Sergunb 0:8918a71cdbe9 189 }
Sergunb 0:8918a71cdbe9 190
Sergunb 0:8918a71cdbe9 191
Sergunb 0:8918a71cdbe9 192 //SAMA5D3-Xplained evaluation board?
Sergunb 0:8918a71cdbe9 193 #if defined(USE_SAMA5D3_XPLAINED)
Sergunb 0:8918a71cdbe9 194
Sergunb 0:8918a71cdbe9 195 /**
Sergunb 0:8918a71cdbe9 196 * @brief GPIO configuration
Sergunb 0:8918a71cdbe9 197 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 198 **/
Sergunb 0:8918a71cdbe9 199
Sergunb 0:8918a71cdbe9 200 void sama5d3EthInitGpio(NetInterface *interface)
Sergunb 0:8918a71cdbe9 201 {
Sergunb 0:8918a71cdbe9 202 //Enable PIO peripheral clock
Sergunb 0:8918a71cdbe9 203 PMC->PMC_PCER0 = (1 << ID_PIOC);
Sergunb 0:8918a71cdbe9 204
Sergunb 0:8918a71cdbe9 205 //Disable pull-up resistors on RMII pins
Sergunb 0:8918a71cdbe9 206 PIOC->PIO_PUDR = EMAC_RMII_MASK;
Sergunb 0:8918a71cdbe9 207 //Disable interrupts-on-change
Sergunb 0:8918a71cdbe9 208 PIOC->PIO_IDR = EMAC_RMII_MASK;
Sergunb 0:8918a71cdbe9 209 //Assign RMII pins to peripheral A function
Sergunb 0:8918a71cdbe9 210 PIOC->PIO_ABCDSR[0] &= ~EMAC_RMII_MASK;
Sergunb 0:8918a71cdbe9 211 PIOC->PIO_ABCDSR[1] &= ~EMAC_RMII_MASK;
Sergunb 0:8918a71cdbe9 212 //Disable the PIO from controlling the corresponding pins
Sergunb 0:8918a71cdbe9 213 PIOC->PIO_PDR = EMAC_RMII_MASK;
Sergunb 0:8918a71cdbe9 214
Sergunb 0:8918a71cdbe9 215 //Select RMII operation mode and enable transceiver clock
Sergunb 0:8918a71cdbe9 216 EMAC->EMAC_USRIO = EMAC_USRIO_CLKEN | EMAC_USRIO_RMII;
Sergunb 0:8918a71cdbe9 217 }
Sergunb 0:8918a71cdbe9 218
Sergunb 0:8918a71cdbe9 219 #endif
Sergunb 0:8918a71cdbe9 220
Sergunb 0:8918a71cdbe9 221
Sergunb 0:8918a71cdbe9 222 /**
Sergunb 0:8918a71cdbe9 223 * @brief Initialize buffer descriptors
Sergunb 0:8918a71cdbe9 224 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 225 **/
Sergunb 0:8918a71cdbe9 226
Sergunb 0:8918a71cdbe9 227 void sama5d3EthInitBufferDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 228 {
Sergunb 0:8918a71cdbe9 229 uint_t i;
Sergunb 0:8918a71cdbe9 230 uint32_t address;
Sergunb 0:8918a71cdbe9 231
Sergunb 0:8918a71cdbe9 232 //Initialize TX buffer descriptors
Sergunb 0:8918a71cdbe9 233 for(i = 0; i < SAMA5D3_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 234 {
Sergunb 0:8918a71cdbe9 235 //Calculate the address of the current TX buffer
Sergunb 0:8918a71cdbe9 236 address = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 237 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 238 txBufferDesc[i].address = address;
Sergunb 0:8918a71cdbe9 239 //Initialize status field
Sergunb 0:8918a71cdbe9 240 txBufferDesc[i].status = EMAC_TX_USED;
Sergunb 0:8918a71cdbe9 241 }
Sergunb 0:8918a71cdbe9 242
Sergunb 0:8918a71cdbe9 243 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 244 txBufferDesc[i - 1].status |= EMAC_TX_WRAP;
Sergunb 0:8918a71cdbe9 245 //Initialize TX buffer index
Sergunb 0:8918a71cdbe9 246 txBufferIndex = 0;
Sergunb 0:8918a71cdbe9 247
Sergunb 0:8918a71cdbe9 248 //Initialize RX buffer descriptors
Sergunb 0:8918a71cdbe9 249 for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 250 {
Sergunb 0:8918a71cdbe9 251 //Calculate the address of the current RX buffer
Sergunb 0:8918a71cdbe9 252 address = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 253 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 254 rxBufferDesc[i].address = address & EMAC_RX_ADDRESS;
Sergunb 0:8918a71cdbe9 255 //Clear status field
Sergunb 0:8918a71cdbe9 256 rxBufferDesc[i].status = 0;
Sergunb 0:8918a71cdbe9 257 }
Sergunb 0:8918a71cdbe9 258
Sergunb 0:8918a71cdbe9 259 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 260 rxBufferDesc[i - 1].address |= EMAC_RX_WRAP;
Sergunb 0:8918a71cdbe9 261 //Initialize RX buffer index
Sergunb 0:8918a71cdbe9 262 rxBufferIndex = 0;
Sergunb 0:8918a71cdbe9 263
Sergunb 0:8918a71cdbe9 264 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 265 EMAC->EMAC_TBQP = (uint32_t) txBufferDesc;
Sergunb 0:8918a71cdbe9 266 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 267 EMAC->EMAC_RBQP = (uint32_t) rxBufferDesc;
Sergunb 0:8918a71cdbe9 268 }
Sergunb 0:8918a71cdbe9 269
Sergunb 0:8918a71cdbe9 270
Sergunb 0:8918a71cdbe9 271 /**
Sergunb 0:8918a71cdbe9 272 * @brief SAMA5D3 Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 273 *
Sergunb 0:8918a71cdbe9 274 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 275 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 276 *
Sergunb 0:8918a71cdbe9 277 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 278 **/
Sergunb 0:8918a71cdbe9 279
Sergunb 0:8918a71cdbe9 280 void sama5d3EthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 281 {
Sergunb 0:8918a71cdbe9 282 //Handle periodic operations
Sergunb 0:8918a71cdbe9 283 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 284 }
Sergunb 0:8918a71cdbe9 285
Sergunb 0:8918a71cdbe9 286
Sergunb 0:8918a71cdbe9 287 /**
Sergunb 0:8918a71cdbe9 288 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 289 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 290 **/
Sergunb 0:8918a71cdbe9 291
Sergunb 0:8918a71cdbe9 292 void sama5d3EthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 293 {
Sergunb 0:8918a71cdbe9 294 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 295 AIC->AIC_SSR = ID_EMAC;
Sergunb 0:8918a71cdbe9 296 AIC->AIC_IECR = AIC_IECR_INTEN;
Sergunb 0:8918a71cdbe9 297 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 298 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 299 }
Sergunb 0:8918a71cdbe9 300
Sergunb 0:8918a71cdbe9 301
Sergunb 0:8918a71cdbe9 302 /**
Sergunb 0:8918a71cdbe9 303 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 304 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 305 **/
Sergunb 0:8918a71cdbe9 306
Sergunb 0:8918a71cdbe9 307 void sama5d3EthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 308 {
Sergunb 0:8918a71cdbe9 309 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 310 AIC->AIC_SSR = ID_EMAC;
Sergunb 0:8918a71cdbe9 311 AIC->AIC_IDCR = AIC_IDCR_INTD;
Sergunb 0:8918a71cdbe9 312 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 313 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 314 }
Sergunb 0:8918a71cdbe9 315
Sergunb 0:8918a71cdbe9 316
Sergunb 0:8918a71cdbe9 317 /**
Sergunb 0:8918a71cdbe9 318 * @brief SAMA5D3 Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 319 **/
Sergunb 0:8918a71cdbe9 320
Sergunb 0:8918a71cdbe9 321 void sama5d3EthIrqHandler(void)
Sergunb 0:8918a71cdbe9 322 {
Sergunb 0:8918a71cdbe9 323 bool_t flag;
Sergunb 0:8918a71cdbe9 324 volatile uint32_t isr;
Sergunb 0:8918a71cdbe9 325 volatile uint32_t tsr;
Sergunb 0:8918a71cdbe9 326 volatile uint32_t rsr;
Sergunb 0:8918a71cdbe9 327
Sergunb 0:8918a71cdbe9 328 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 329 osEnterIsr();
Sergunb 0:8918a71cdbe9 330
Sergunb 0:8918a71cdbe9 331 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 332 flag = FALSE;
Sergunb 0:8918a71cdbe9 333
Sergunb 0:8918a71cdbe9 334 //Each time the software reads EMAC_ISR, it has to check the
Sergunb 0:8918a71cdbe9 335 //contents of EMAC_TSR, EMAC_RSR and EMAC_NSR
Sergunb 0:8918a71cdbe9 336 isr = EMAC->EMAC_ISR;
Sergunb 0:8918a71cdbe9 337 tsr = EMAC->EMAC_TSR;
Sergunb 0:8918a71cdbe9 338 rsr = EMAC->EMAC_RSR;
Sergunb 0:8918a71cdbe9 339
Sergunb 0:8918a71cdbe9 340 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 341 if(tsr & (EMAC_TSR_UND | EMAC_TSR_COMP | EMAC_TSR_BEX |
Sergunb 0:8918a71cdbe9 342 EMAC_TSR_TGO | EMAC_TSR_RLES | EMAC_TSR_COL | EMAC_TSR_UBR))
Sergunb 0:8918a71cdbe9 343 {
Sergunb 0:8918a71cdbe9 344 //Only clear TSR flags that are currently set
Sergunb 0:8918a71cdbe9 345 EMAC->EMAC_TSR = tsr;
Sergunb 0:8918a71cdbe9 346
Sergunb 0:8918a71cdbe9 347 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 348 if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
Sergunb 0:8918a71cdbe9 349 {
Sergunb 0:8918a71cdbe9 350 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 351 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 352 }
Sergunb 0:8918a71cdbe9 353 }
Sergunb 0:8918a71cdbe9 354
Sergunb 0:8918a71cdbe9 355 //A packet has been received?
Sergunb 0:8918a71cdbe9 356 if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
Sergunb 0:8918a71cdbe9 357 {
Sergunb 0:8918a71cdbe9 358 //Set event flag
Sergunb 0:8918a71cdbe9 359 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 360 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 361 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 362 }
Sergunb 0:8918a71cdbe9 363
Sergunb 0:8918a71cdbe9 364 //Write AIC_EOICR register before exiting
Sergunb 0:8918a71cdbe9 365 AIC->AIC_EOICR = 0;
Sergunb 0:8918a71cdbe9 366
Sergunb 0:8918a71cdbe9 367 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 368 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 369 }
Sergunb 0:8918a71cdbe9 370
Sergunb 0:8918a71cdbe9 371
Sergunb 0:8918a71cdbe9 372 /**
Sergunb 0:8918a71cdbe9 373 * @brief SAMA5D3 Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 374 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 375 **/
Sergunb 0:8918a71cdbe9 376
Sergunb 0:8918a71cdbe9 377 void sama5d3EthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 378 {
Sergunb 0:8918a71cdbe9 379 error_t error;
Sergunb 0:8918a71cdbe9 380 uint32_t rsr;
Sergunb 0:8918a71cdbe9 381
Sergunb 0:8918a71cdbe9 382 //Read receive status
Sergunb 0:8918a71cdbe9 383 rsr = EMAC->EMAC_RSR;
Sergunb 0:8918a71cdbe9 384
Sergunb 0:8918a71cdbe9 385 //Packet received?
Sergunb 0:8918a71cdbe9 386 if(rsr & (EMAC_RSR_OVR | EMAC_RSR_REC | EMAC_RSR_BNA))
Sergunb 0:8918a71cdbe9 387 {
Sergunb 0:8918a71cdbe9 388 //Only clear RSR flags that are currently set
Sergunb 0:8918a71cdbe9 389 EMAC->EMAC_RSR = rsr;
Sergunb 0:8918a71cdbe9 390
Sergunb 0:8918a71cdbe9 391 //Process all pending packets
Sergunb 0:8918a71cdbe9 392 do
Sergunb 0:8918a71cdbe9 393 {
Sergunb 0:8918a71cdbe9 394 //Read incoming packet
Sergunb 0:8918a71cdbe9 395 error = sama5d3EthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 396
Sergunb 0:8918a71cdbe9 397 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 398 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 399 }
Sergunb 0:8918a71cdbe9 400 }
Sergunb 0:8918a71cdbe9 401
Sergunb 0:8918a71cdbe9 402
Sergunb 0:8918a71cdbe9 403 /**
Sergunb 0:8918a71cdbe9 404 * @brief Send a packet
Sergunb 0:8918a71cdbe9 405 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 406 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 407 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 408 * @return Error code
Sergunb 0:8918a71cdbe9 409 **/
Sergunb 0:8918a71cdbe9 410
Sergunb 0:8918a71cdbe9 411 error_t sama5d3EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 412 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 413 {
Sergunb 0:8918a71cdbe9 414 size_t length;
Sergunb 0:8918a71cdbe9 415
Sergunb 0:8918a71cdbe9 416 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 417 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 418
Sergunb 0:8918a71cdbe9 419 //Check the frame length
Sergunb 0:8918a71cdbe9 420 if(length > SAMA5D3_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 421 {
Sergunb 0:8918a71cdbe9 422 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 423 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 424 //Report an error
Sergunb 0:8918a71cdbe9 425 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 426 }
Sergunb 0:8918a71cdbe9 427
Sergunb 0:8918a71cdbe9 428 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 429 if(!(txBufferDesc[txBufferIndex].status & EMAC_TX_USED))
Sergunb 0:8918a71cdbe9 430 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 431
Sergunb 0:8918a71cdbe9 432 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 433 netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
Sergunb 0:8918a71cdbe9 434
Sergunb 0:8918a71cdbe9 435 //Set the necessary flags in the descriptor entry
Sergunb 0:8918a71cdbe9 436 if(txBufferIndex < (SAMA5D3_ETH_TX_BUFFER_COUNT - 1))
Sergunb 0:8918a71cdbe9 437 {
Sergunb 0:8918a71cdbe9 438 //Write the status word
Sergunb 0:8918a71cdbe9 439 txBufferDesc[txBufferIndex].status =
Sergunb 0:8918a71cdbe9 440 EMAC_TX_LAST | (length & EMAC_TX_LENGTH);
Sergunb 0:8918a71cdbe9 441
Sergunb 0:8918a71cdbe9 442 //Point to the next buffer
Sergunb 0:8918a71cdbe9 443 txBufferIndex++;
Sergunb 0:8918a71cdbe9 444 }
Sergunb 0:8918a71cdbe9 445 else
Sergunb 0:8918a71cdbe9 446 {
Sergunb 0:8918a71cdbe9 447 //Write the status word
Sergunb 0:8918a71cdbe9 448 txBufferDesc[txBufferIndex].status = EMAC_TX_WRAP |
Sergunb 0:8918a71cdbe9 449 EMAC_TX_LAST | (length & EMAC_TX_LENGTH);
Sergunb 0:8918a71cdbe9 450
Sergunb 0:8918a71cdbe9 451 //Wrap around
Sergunb 0:8918a71cdbe9 452 txBufferIndex = 0;
Sergunb 0:8918a71cdbe9 453 }
Sergunb 0:8918a71cdbe9 454
Sergunb 0:8918a71cdbe9 455 //Set the TSTART bit to initiate transmission
Sergunb 0:8918a71cdbe9 456 EMAC->EMAC_NCR |= EMAC_NCR_TSTART;
Sergunb 0:8918a71cdbe9 457
Sergunb 0:8918a71cdbe9 458 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 459 if(txBufferDesc[txBufferIndex].status & EMAC_TX_USED)
Sergunb 0:8918a71cdbe9 460 {
Sergunb 0:8918a71cdbe9 461 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 462 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 463 }
Sergunb 0:8918a71cdbe9 464
Sergunb 0:8918a71cdbe9 465 //Successful processing
Sergunb 0:8918a71cdbe9 466 return NO_ERROR;
Sergunb 0:8918a71cdbe9 467 }
Sergunb 0:8918a71cdbe9 468
Sergunb 0:8918a71cdbe9 469
Sergunb 0:8918a71cdbe9 470 /**
Sergunb 0:8918a71cdbe9 471 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 472 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 473 * @return Error code
Sergunb 0:8918a71cdbe9 474 **/
Sergunb 0:8918a71cdbe9 475
Sergunb 0:8918a71cdbe9 476 error_t sama5d3EthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 477 {
Sergunb 0:8918a71cdbe9 478 static uint8_t temp[ETH_MAX_FRAME_SIZE];
Sergunb 0:8918a71cdbe9 479 error_t error;
Sergunb 0:8918a71cdbe9 480 uint_t i;
Sergunb 0:8918a71cdbe9 481 uint_t j;
Sergunb 0:8918a71cdbe9 482 uint_t sofIndex;
Sergunb 0:8918a71cdbe9 483 uint_t eofIndex;
Sergunb 0:8918a71cdbe9 484 size_t n;
Sergunb 0:8918a71cdbe9 485 size_t size;
Sergunb 0:8918a71cdbe9 486 size_t length;
Sergunb 0:8918a71cdbe9 487
Sergunb 0:8918a71cdbe9 488 //Initialize SOF and EOF indices
Sergunb 0:8918a71cdbe9 489 sofIndex = UINT_MAX;
Sergunb 0:8918a71cdbe9 490 eofIndex = UINT_MAX;
Sergunb 0:8918a71cdbe9 491
Sergunb 0:8918a71cdbe9 492 //Search for SOF and EOF flags
Sergunb 0:8918a71cdbe9 493 for(i = 0; i < SAMA5D3_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 494 {
Sergunb 0:8918a71cdbe9 495 //Point to the current entry
Sergunb 0:8918a71cdbe9 496 j = rxBufferIndex + i;
Sergunb 0:8918a71cdbe9 497
Sergunb 0:8918a71cdbe9 498 //Wrap around to the beginning of the buffer if necessary
Sergunb 0:8918a71cdbe9 499 if(j >= SAMA5D3_ETH_RX_BUFFER_COUNT)
Sergunb 0:8918a71cdbe9 500 j -= SAMA5D3_ETH_RX_BUFFER_COUNT;
Sergunb 0:8918a71cdbe9 501
Sergunb 0:8918a71cdbe9 502 //No more entries to process?
Sergunb 0:8918a71cdbe9 503 if(!(rxBufferDesc[j].address & EMAC_RX_OWNERSHIP))
Sergunb 0:8918a71cdbe9 504 {
Sergunb 0:8918a71cdbe9 505 //Stop processing
Sergunb 0:8918a71cdbe9 506 break;
Sergunb 0:8918a71cdbe9 507 }
Sergunb 0:8918a71cdbe9 508 //A valid SOF has been found?
Sergunb 0:8918a71cdbe9 509 if(rxBufferDesc[j].status & EMAC_RX_SOF)
Sergunb 0:8918a71cdbe9 510 {
Sergunb 0:8918a71cdbe9 511 //Save the position of the SOF
Sergunb 0:8918a71cdbe9 512 sofIndex = i;
Sergunb 0:8918a71cdbe9 513 }
Sergunb 0:8918a71cdbe9 514 //A valid EOF has been found?
Sergunb 0:8918a71cdbe9 515 if((rxBufferDesc[j].status & EMAC_RX_EOF) && sofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 516 {
Sergunb 0:8918a71cdbe9 517 //Save the position of the EOF
Sergunb 0:8918a71cdbe9 518 eofIndex = i;
Sergunb 0:8918a71cdbe9 519 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 520 size = rxBufferDesc[j].status & EMAC_RX_LENGTH;
Sergunb 0:8918a71cdbe9 521 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 522 size = MIN(size, ETH_MAX_FRAME_SIZE);
Sergunb 0:8918a71cdbe9 523 //Stop processing since we have reached the end of the frame
Sergunb 0:8918a71cdbe9 524 break;
Sergunb 0:8918a71cdbe9 525 }
Sergunb 0:8918a71cdbe9 526 }
Sergunb 0:8918a71cdbe9 527
Sergunb 0:8918a71cdbe9 528 //Determine the number of entries to process
Sergunb 0:8918a71cdbe9 529 if(eofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 530 j = eofIndex + 1;
Sergunb 0:8918a71cdbe9 531 else if(sofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 532 j = sofIndex;
Sergunb 0:8918a71cdbe9 533 else
Sergunb 0:8918a71cdbe9 534 j = i;
Sergunb 0:8918a71cdbe9 535
Sergunb 0:8918a71cdbe9 536 //Total number of bytes that have been copied from the receive buffer
Sergunb 0:8918a71cdbe9 537 length = 0;
Sergunb 0:8918a71cdbe9 538
Sergunb 0:8918a71cdbe9 539 //Process incoming frame
Sergunb 0:8918a71cdbe9 540 for(i = 0; i < j; i++)
Sergunb 0:8918a71cdbe9 541 {
Sergunb 0:8918a71cdbe9 542 //Any data to copy from current buffer?
Sergunb 0:8918a71cdbe9 543 if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
Sergunb 0:8918a71cdbe9 544 {
Sergunb 0:8918a71cdbe9 545 //Calculate the number of bytes to read at a time
Sergunb 0:8918a71cdbe9 546 n = MIN(size, SAMA5D3_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 547 //Copy data from receive buffer
Sergunb 0:8918a71cdbe9 548 memcpy(temp + length, rxBuffer[rxBufferIndex], n);
Sergunb 0:8918a71cdbe9 549 //Update byte counters
Sergunb 0:8918a71cdbe9 550 length += n;
Sergunb 0:8918a71cdbe9 551 size -= n;
Sergunb 0:8918a71cdbe9 552 }
Sergunb 0:8918a71cdbe9 553
Sergunb 0:8918a71cdbe9 554 //Mark the current buffer as free
Sergunb 0:8918a71cdbe9 555 rxBufferDesc[rxBufferIndex].address &= ~EMAC_RX_OWNERSHIP;
Sergunb 0:8918a71cdbe9 556
Sergunb 0:8918a71cdbe9 557 //Point to the following entry
Sergunb 0:8918a71cdbe9 558 rxBufferIndex++;
Sergunb 0:8918a71cdbe9 559
Sergunb 0:8918a71cdbe9 560 //Wrap around to the beginning of the buffer if necessary
Sergunb 0:8918a71cdbe9 561 if(rxBufferIndex >= SAMA5D3_ETH_RX_BUFFER_COUNT)
Sergunb 0:8918a71cdbe9 562 rxBufferIndex = 0;
Sergunb 0:8918a71cdbe9 563 }
Sergunb 0:8918a71cdbe9 564
Sergunb 0:8918a71cdbe9 565 //Any packet to process?
Sergunb 0:8918a71cdbe9 566 if(length > 0)
Sergunb 0:8918a71cdbe9 567 {
Sergunb 0:8918a71cdbe9 568 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 569 nicProcessPacket(interface, temp, length);
Sergunb 0:8918a71cdbe9 570 //Valid packet received
Sergunb 0:8918a71cdbe9 571 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 572 }
Sergunb 0:8918a71cdbe9 573 else
Sergunb 0:8918a71cdbe9 574 {
Sergunb 0:8918a71cdbe9 575 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 576 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 577 }
Sergunb 0:8918a71cdbe9 578
Sergunb 0:8918a71cdbe9 579 //Return status code
Sergunb 0:8918a71cdbe9 580 return error;
Sergunb 0:8918a71cdbe9 581 }
Sergunb 0:8918a71cdbe9 582
Sergunb 0:8918a71cdbe9 583
Sergunb 0:8918a71cdbe9 584 /**
Sergunb 0:8918a71cdbe9 585 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 586 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 587 * @return Error code
Sergunb 0:8918a71cdbe9 588 **/
Sergunb 0:8918a71cdbe9 589
Sergunb 0:8918a71cdbe9 590 error_t sama5d3EthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 591 {
Sergunb 0:8918a71cdbe9 592 uint_t i;
Sergunb 0:8918a71cdbe9 593 uint_t k;
Sergunb 0:8918a71cdbe9 594 uint8_t *p;
Sergunb 0:8918a71cdbe9 595 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 596 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 597
Sergunb 0:8918a71cdbe9 598 //Debug message
Sergunb 0:8918a71cdbe9 599 TRACE_DEBUG("Updating SAMA5D3 hash table...\r\n");
Sergunb 0:8918a71cdbe9 600
Sergunb 0:8918a71cdbe9 601 //Clear hash table
Sergunb 0:8918a71cdbe9 602 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 603 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 604
Sergunb 0:8918a71cdbe9 605 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 606 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 607 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 608 {
Sergunb 0:8918a71cdbe9 609 //Point to the current entry
Sergunb 0:8918a71cdbe9 610 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 611
Sergunb 0:8918a71cdbe9 612 //Valid entry?
Sergunb 0:8918a71cdbe9 613 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 614 {
Sergunb 0:8918a71cdbe9 615 //Point to the MAC address
Sergunb 0:8918a71cdbe9 616 p = entry->addr.b;
Sergunb 0:8918a71cdbe9 617
Sergunb 0:8918a71cdbe9 618 //Apply the hash function
Sergunb 0:8918a71cdbe9 619 k = (p[0] >> 6) ^ p[0];
Sergunb 0:8918a71cdbe9 620 k ^= (p[1] >> 4) ^ (p[1] << 2);
Sergunb 0:8918a71cdbe9 621 k ^= (p[2] >> 2) ^ (p[2] << 4);
Sergunb 0:8918a71cdbe9 622 k ^= (p[3] >> 6) ^ p[3];
Sergunb 0:8918a71cdbe9 623 k ^= (p[4] >> 4) ^ (p[4] << 2);
Sergunb 0:8918a71cdbe9 624 k ^= (p[5] >> 2) ^ (p[5] << 4);
Sergunb 0:8918a71cdbe9 625
Sergunb 0:8918a71cdbe9 626 //The hash value is reduced to a 6-bit index
Sergunb 0:8918a71cdbe9 627 k &= 0x3F;
Sergunb 0:8918a71cdbe9 628
Sergunb 0:8918a71cdbe9 629 //Update hash table contents
Sergunb 0:8918a71cdbe9 630 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 631 }
Sergunb 0:8918a71cdbe9 632 }
Sergunb 0:8918a71cdbe9 633
Sergunb 0:8918a71cdbe9 634 //Write the hash table
Sergunb 0:8918a71cdbe9 635 EMAC->EMAC_HRB = hashTable[0];
Sergunb 0:8918a71cdbe9 636 EMAC->EMAC_HRT = hashTable[1];
Sergunb 0:8918a71cdbe9 637
Sergunb 0:8918a71cdbe9 638 //Debug message
Sergunb 0:8918a71cdbe9 639 TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", EMAC->EMAC_HRB);
Sergunb 0:8918a71cdbe9 640 TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", EMAC->EMAC_HRT);
Sergunb 0:8918a71cdbe9 641
Sergunb 0:8918a71cdbe9 642 //Successful processing
Sergunb 0:8918a71cdbe9 643 return NO_ERROR;
Sergunb 0:8918a71cdbe9 644 }
Sergunb 0:8918a71cdbe9 645
Sergunb 0:8918a71cdbe9 646
Sergunb 0:8918a71cdbe9 647 /**
Sergunb 0:8918a71cdbe9 648 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 649 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 650 * @return Error code
Sergunb 0:8918a71cdbe9 651 **/
Sergunb 0:8918a71cdbe9 652
Sergunb 0:8918a71cdbe9 653 error_t sama5d3EthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 654 {
Sergunb 0:8918a71cdbe9 655 uint32_t config;
Sergunb 0:8918a71cdbe9 656
Sergunb 0:8918a71cdbe9 657 //Read network configuration register
Sergunb 0:8918a71cdbe9 658 config = EMAC->EMAC_NCFGR;
Sergunb 0:8918a71cdbe9 659
Sergunb 0:8918a71cdbe9 660 //10BASE-T or 100BASE-TX operation mode?
Sergunb 0:8918a71cdbe9 661 if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
Sergunb 0:8918a71cdbe9 662 config |= EMAC_NCFGR_SPD;
Sergunb 0:8918a71cdbe9 663 else
Sergunb 0:8918a71cdbe9 664 config &= ~EMAC_NCFGR_SPD;
Sergunb 0:8918a71cdbe9 665
Sergunb 0:8918a71cdbe9 666 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 667 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 668 config |= EMAC_NCFGR_FD;
Sergunb 0:8918a71cdbe9 669 else
Sergunb 0:8918a71cdbe9 670 config &= ~EMAC_NCFGR_FD;
Sergunb 0:8918a71cdbe9 671
Sergunb 0:8918a71cdbe9 672 //Write configuration value back to NCFGR register
Sergunb 0:8918a71cdbe9 673 EMAC->EMAC_NCFGR = config;
Sergunb 0:8918a71cdbe9 674
Sergunb 0:8918a71cdbe9 675 //Successful processing
Sergunb 0:8918a71cdbe9 676 return NO_ERROR;
Sergunb 0:8918a71cdbe9 677 }
Sergunb 0:8918a71cdbe9 678
Sergunb 0:8918a71cdbe9 679
Sergunb 0:8918a71cdbe9 680 /**
Sergunb 0:8918a71cdbe9 681 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 682 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 683 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 684 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 685 **/
Sergunb 0:8918a71cdbe9 686
Sergunb 0:8918a71cdbe9 687 void sama5d3EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 688 {
Sergunb 0:8918a71cdbe9 689 uint32_t value;
Sergunb 0:8918a71cdbe9 690
Sergunb 0:8918a71cdbe9 691 //Set up a write operation
Sergunb 0:8918a71cdbe9 692 value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(1) | EMAC_MAN_CODE(2);
Sergunb 0:8918a71cdbe9 693 //PHY address
Sergunb 0:8918a71cdbe9 694 value |= EMAC_MAN_PHYA(phyAddr);
Sergunb 0:8918a71cdbe9 695 //Register address
Sergunb 0:8918a71cdbe9 696 value |= EMAC_MAN_REGA(regAddr);
Sergunb 0:8918a71cdbe9 697 //Register value
Sergunb 0:8918a71cdbe9 698 value |= EMAC_MAN_DATA(data);
Sergunb 0:8918a71cdbe9 699
Sergunb 0:8918a71cdbe9 700 //Start a write operation
Sergunb 0:8918a71cdbe9 701 EMAC->EMAC_MAN = value;
Sergunb 0:8918a71cdbe9 702 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 703 while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
Sergunb 0:8918a71cdbe9 704 }
Sergunb 0:8918a71cdbe9 705
Sergunb 0:8918a71cdbe9 706
Sergunb 0:8918a71cdbe9 707 /**
Sergunb 0:8918a71cdbe9 708 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 709 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 710 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 711 * @return Register value
Sergunb 0:8918a71cdbe9 712 **/
Sergunb 0:8918a71cdbe9 713
Sergunb 0:8918a71cdbe9 714 uint16_t sama5d3EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 715 {
Sergunb 0:8918a71cdbe9 716 uint32_t value;
Sergunb 0:8918a71cdbe9 717
Sergunb 0:8918a71cdbe9 718 //Set up a read operation
Sergunb 0:8918a71cdbe9 719 value = EMAC_MAN_SOF(1) | EMAC_MAN_RW(2) | EMAC_MAN_CODE(2);
Sergunb 0:8918a71cdbe9 720 //PHY address
Sergunb 0:8918a71cdbe9 721 value |= EMAC_MAN_PHYA(phyAddr);
Sergunb 0:8918a71cdbe9 722 //Register address
Sergunb 0:8918a71cdbe9 723 value |= EMAC_MAN_REGA(regAddr);
Sergunb 0:8918a71cdbe9 724
Sergunb 0:8918a71cdbe9 725 //Start a read operation
Sergunb 0:8918a71cdbe9 726 EMAC->EMAC_MAN = value;
Sergunb 0:8918a71cdbe9 727 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 728 while(!(EMAC->EMAC_NSR & EMAC_NSR_IDLE));
Sergunb 0:8918a71cdbe9 729
Sergunb 0:8918a71cdbe9 730 //Return PHY register contents
Sergunb 0:8918a71cdbe9 731 return EMAC->EMAC_MAN & EMAC_MAN_DATA_Msk;
Sergunb 0:8918a71cdbe9 732 }
Sergunb 0:8918a71cdbe9 733