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cyclone_tcp/drivers/sama5d2_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file sama5d2_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief SAMA5D2 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include <limits.h>
Sergunb 0:8918a71cdbe9 34 #include "chip.h"
Sergunb 0:8918a71cdbe9 35 #include "peripherals/aic.h"
Sergunb 0:8918a71cdbe9 36 #include "peripherals/pio.h"
Sergunb 0:8918a71cdbe9 37 #include "core/net.h"
Sergunb 0:8918a71cdbe9 38 #include "drivers/sama5d2_eth.h"
Sergunb 0:8918a71cdbe9 39 #include "debug.h"
Sergunb 0:8918a71cdbe9 40
Sergunb 0:8918a71cdbe9 41 //Underlying network interface
Sergunb 0:8918a71cdbe9 42 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 43
Sergunb 0:8918a71cdbe9 44 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 45 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 46
Sergunb 0:8918a71cdbe9 47 //TX buffer
Sergunb 0:8918a71cdbe9 48 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 49 #pragma location = ".region_ddr_nocache"
Sergunb 0:8918a71cdbe9 50 static uint8_t txBuffer[SAMA5D2_ETH_TX_BUFFER_COUNT][SAMA5D2_ETH_TX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 51 //RX buffer
Sergunb 0:8918a71cdbe9 52 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 53 #pragma location = ".region_ddr_nocache"
Sergunb 0:8918a71cdbe9 54 static uint8_t rxBuffer[SAMA5D2_ETH_RX_BUFFER_COUNT][SAMA5D2_ETH_RX_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 55 //TX buffer descriptors
Sergunb 0:8918a71cdbe9 56 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 57 #pragma location = ".region_ddr_nocache"
Sergunb 0:8918a71cdbe9 58 static Sama5d2TxBufferDesc txBufferDesc[SAMA5D2_ETH_TX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 59 //RX buffer descriptors
Sergunb 0:8918a71cdbe9 60 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 61 #pragma location = ".region_ddr_nocache"
Sergunb 0:8918a71cdbe9 62 static Sama5d2RxBufferDesc rxBufferDesc[SAMA5D2_ETH_RX_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 63
Sergunb 0:8918a71cdbe9 64 //Dummy TX buffer
Sergunb 0:8918a71cdbe9 65 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 66 #pragma location = ".region_ddr_nocache"
Sergunb 0:8918a71cdbe9 67 static uint8_t dummyTxBuffer[SAMA5D2_ETH_DUMMY_BUFFER_COUNT][SAMA5D2_ETH_DUMMY_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 68 //Dummy RX buffer
Sergunb 0:8918a71cdbe9 69 #pragma data_alignment = 8
Sergunb 0:8918a71cdbe9 70 #pragma location = ".region_ddr_nocache"
Sergunb 0:8918a71cdbe9 71 static uint8_t dummyRxBuffer[SAMA5D2_ETH_DUMMY_BUFFER_COUNT][SAMA5D2_ETH_DUMMY_BUFFER_SIZE];
Sergunb 0:8918a71cdbe9 72 //Dummy TX buffer descriptors
Sergunb 0:8918a71cdbe9 73 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 74 #pragma location = ".region_ddr_nocache"
Sergunb 0:8918a71cdbe9 75 static Sama5d2TxBufferDesc dummyTxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 76 //Dummy RX buffer descriptors
Sergunb 0:8918a71cdbe9 77 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 78 #pragma location = ".region_ddr_nocache"
Sergunb 0:8918a71cdbe9 79 static Sama5d2RxBufferDesc dummyRxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT];
Sergunb 0:8918a71cdbe9 80
Sergunb 0:8918a71cdbe9 81 //GCC compiler?
Sergunb 0:8918a71cdbe9 82 #else
Sergunb 0:8918a71cdbe9 83
Sergunb 0:8918a71cdbe9 84 //TX buffer
Sergunb 0:8918a71cdbe9 85 static uint8_t txBuffer[SAMA5D2_ETH_TX_BUFFER_COUNT][SAMA5D2_ETH_TX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 86 __attribute__((aligned(8), __section__(".region_ddr_nocache")));
Sergunb 0:8918a71cdbe9 87 //RX buffer
Sergunb 0:8918a71cdbe9 88 static uint8_t rxBuffer[SAMA5D2_ETH_RX_BUFFER_COUNT][SAMA5D2_ETH_RX_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 89 __attribute__((aligned(8), __section__(".region_ddr_nocache")));
Sergunb 0:8918a71cdbe9 90 //TX buffer descriptors
Sergunb 0:8918a71cdbe9 91 static Sama5d2TxBufferDesc txBufferDesc[SAMA5D2_ETH_TX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 92 __attribute__((aligned(4), __section__(".region_ddr_nocache")));
Sergunb 0:8918a71cdbe9 93 //RX buffer descriptors
Sergunb 0:8918a71cdbe9 94 static Sama5d2RxBufferDesc rxBufferDesc[SAMA5D2_ETH_RX_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 95 __attribute__((aligned(4), __section__(".region_ddr_nocache")));
Sergunb 0:8918a71cdbe9 96
Sergunb 0:8918a71cdbe9 97 //Dummy TX buffer
Sergunb 0:8918a71cdbe9 98 static uint8_t dummyTxBuffer[SAMA5D2_ETH_DUMMY_BUFFER_COUNT][SAMA5D2_ETH_DUMMY_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 99 __attribute__((aligned(8), __section__(".region_ddr_nocache")));
Sergunb 0:8918a71cdbe9 100 //Dummy RX buffer
Sergunb 0:8918a71cdbe9 101 static uint8_t dummyRxBuffer[SAMA5D2_ETH_DUMMY_BUFFER_COUNT][SAMA5D2_ETH_DUMMY_BUFFER_SIZE]
Sergunb 0:8918a71cdbe9 102 __attribute__((aligned(8), __section__(".region_ddr_nocache")));
Sergunb 0:8918a71cdbe9 103 //Dummy TX buffer descriptors
Sergunb 0:8918a71cdbe9 104 static Sama5d2TxBufferDesc dummyTxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 105 __attribute__((aligned(4), __section__(".region_ddr_nocache")));
Sergunb 0:8918a71cdbe9 106 //Dummy RX buffer descriptors
Sergunb 0:8918a71cdbe9 107 static Sama5d2RxBufferDesc dummyRxBufferDesc[SAMA5D2_ETH_DUMMY_BUFFER_COUNT]
Sergunb 0:8918a71cdbe9 108 __attribute__((aligned(4), __section__(".region_ddr_nocache")));
Sergunb 0:8918a71cdbe9 109
Sergunb 0:8918a71cdbe9 110 #endif
Sergunb 0:8918a71cdbe9 111
Sergunb 0:8918a71cdbe9 112 //TX buffer index
Sergunb 0:8918a71cdbe9 113 static uint_t txBufferIndex;
Sergunb 0:8918a71cdbe9 114 //RX buffer index
Sergunb 0:8918a71cdbe9 115 static uint_t rxBufferIndex;
Sergunb 0:8918a71cdbe9 116
Sergunb 0:8918a71cdbe9 117
Sergunb 0:8918a71cdbe9 118 /**
Sergunb 0:8918a71cdbe9 119 * @brief SAMA5D2 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 120 **/
Sergunb 0:8918a71cdbe9 121
Sergunb 0:8918a71cdbe9 122 const NicDriver sama5d2EthDriver =
Sergunb 0:8918a71cdbe9 123 {
Sergunb 0:8918a71cdbe9 124 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 125 ETH_MTU,
Sergunb 0:8918a71cdbe9 126 sama5d2EthInit,
Sergunb 0:8918a71cdbe9 127 sama5d2EthTick,
Sergunb 0:8918a71cdbe9 128 sama5d2EthEnableIrq,
Sergunb 0:8918a71cdbe9 129 sama5d2EthDisableIrq,
Sergunb 0:8918a71cdbe9 130 sama5d2EthEventHandler,
Sergunb 0:8918a71cdbe9 131 sama5d2EthSendPacket,
Sergunb 0:8918a71cdbe9 132 sama5d2EthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 133 sama5d2EthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 134 sama5d2EthWritePhyReg,
Sergunb 0:8918a71cdbe9 135 sama5d2EthReadPhyReg,
Sergunb 0:8918a71cdbe9 136 TRUE,
Sergunb 0:8918a71cdbe9 137 TRUE,
Sergunb 0:8918a71cdbe9 138 TRUE,
Sergunb 0:8918a71cdbe9 139 FALSE
Sergunb 0:8918a71cdbe9 140 };
Sergunb 0:8918a71cdbe9 141
Sergunb 0:8918a71cdbe9 142
Sergunb 0:8918a71cdbe9 143 /**
Sergunb 0:8918a71cdbe9 144 * @brief SAMA5D2 Ethernet MAC initialization
Sergunb 0:8918a71cdbe9 145 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 146 * @return Error code
Sergunb 0:8918a71cdbe9 147 **/
Sergunb 0:8918a71cdbe9 148
Sergunb 0:8918a71cdbe9 149 error_t sama5d2EthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 150 {
Sergunb 0:8918a71cdbe9 151 error_t error;
Sergunb 0:8918a71cdbe9 152 volatile uint32_t status;
Sergunb 0:8918a71cdbe9 153
Sergunb 0:8918a71cdbe9 154 //Debug message
Sergunb 0:8918a71cdbe9 155 TRACE_INFO("Initializing SAMA5D2 Ethernet MAC...\r\n");
Sergunb 0:8918a71cdbe9 156
Sergunb 0:8918a71cdbe9 157 //Save underlying network interface
Sergunb 0:8918a71cdbe9 158 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 159
Sergunb 0:8918a71cdbe9 160 //Enable GMAC peripheral clock
Sergunb 0:8918a71cdbe9 161 PMC->PMC_PCER0 = (1 << ID_GMAC0);
Sergunb 0:8918a71cdbe9 162
Sergunb 0:8918a71cdbe9 163 //GPIO configuration
Sergunb 0:8918a71cdbe9 164 sama5d2EthInitGpio(interface);
Sergunb 0:8918a71cdbe9 165
Sergunb 0:8918a71cdbe9 166 //Configure MDC clock speed
Sergunb 0:8918a71cdbe9 167 GMAC0->GMAC_NCFGR = GMAC_NCFGR_CLK_MCK_96;
Sergunb 0:8918a71cdbe9 168 //Enable management port (MDC and MDIO)
Sergunb 0:8918a71cdbe9 169 GMAC0->GMAC_NCR |= GMAC_NCR_MPE;
Sergunb 0:8918a71cdbe9 170
Sergunb 0:8918a71cdbe9 171 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 172 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 173 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 174 if(error)
Sergunb 0:8918a71cdbe9 175 return error;
Sergunb 0:8918a71cdbe9 176
Sergunb 0:8918a71cdbe9 177 //Set the MAC address
Sergunb 0:8918a71cdbe9 178 GMAC0->GMAC_SA[0].GMAC_SAB = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 179 GMAC0->GMAC_SA[0].GMAC_SAT = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 180
Sergunb 0:8918a71cdbe9 181 //Configure the receive filter
Sergunb 0:8918a71cdbe9 182 GMAC0->GMAC_NCFGR |= GMAC_NCFGR_UNIHEN | GMAC_NCFGR_MTIHEN;
Sergunb 0:8918a71cdbe9 183
Sergunb 0:8918a71cdbe9 184 //DMA configuration
Sergunb 0:8918a71cdbe9 185 GMAC0->GMAC_DCFGR = GMAC_DCFGR_DRBS(SAMA5D2_ETH_RX_BUFFER_SIZE / 64) |
Sergunb 0:8918a71cdbe9 186 GMAC_DCFGR_TXPBMS | GMAC_DCFGR_RXBMS_FULL | GMAC_DCFGR_FBLDO_INCR4;
Sergunb 0:8918a71cdbe9 187
Sergunb 0:8918a71cdbe9 188 GMAC0->GMAC_RBSRPQ[0] = GMAC_RBSRPQ_RBS(SAMA5D2_ETH_DUMMY_BUFFER_SIZE / 64);
Sergunb 0:8918a71cdbe9 189 GMAC0->GMAC_RBSRPQ[1] = GMAC_RBSRPQ_RBS(SAMA5D2_ETH_DUMMY_BUFFER_SIZE / 64);
Sergunb 0:8918a71cdbe9 190
Sergunb 0:8918a71cdbe9 191 //Initialize hash table
Sergunb 0:8918a71cdbe9 192 GMAC0->GMAC_HRB = 0;
Sergunb 0:8918a71cdbe9 193 GMAC0->GMAC_HRT = 0;
Sergunb 0:8918a71cdbe9 194
Sergunb 0:8918a71cdbe9 195 //Initialize buffer descriptors
Sergunb 0:8918a71cdbe9 196 sama5d2EthInitBufferDesc(interface);
Sergunb 0:8918a71cdbe9 197
Sergunb 0:8918a71cdbe9 198 //Clear transmit status register
Sergunb 0:8918a71cdbe9 199 GMAC0->GMAC_TSR = GMAC_TSR_HRESP | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
Sergunb 0:8918a71cdbe9 200 GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR;
Sergunb 0:8918a71cdbe9 201 //Clear receive status register
Sergunb 0:8918a71cdbe9 202 GMAC0->GMAC_RSR = GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA;
Sergunb 0:8918a71cdbe9 203
Sergunb 0:8918a71cdbe9 204 //First disable all GMAC interrupts
Sergunb 0:8918a71cdbe9 205 GMAC0->GMAC_IDR = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 206 GMAC0->GMAC_IDRPQ[0] = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 207 GMAC0->GMAC_IDRPQ[1] = 0xFFFFFFFF;
Sergunb 0:8918a71cdbe9 208
Sergunb 0:8918a71cdbe9 209 //Only the desired ones are enabled
Sergunb 0:8918a71cdbe9 210 GMAC0->GMAC_IER = GMAC_IER_HRESP | GMAC_IER_ROVR | GMAC_IER_TCOMP | GMAC_IER_TFC |
Sergunb 0:8918a71cdbe9 211 GMAC_IER_RLEX | GMAC_IER_TUR | GMAC_IER_RXUBR | GMAC_IER_RCOMP;
Sergunb 0:8918a71cdbe9 212
Sergunb 0:8918a71cdbe9 213 //Read GMAC ISR register to clear any pending interrupt
Sergunb 0:8918a71cdbe9 214 status = GMAC0->GMAC_ISR;
Sergunb 0:8918a71cdbe9 215
Sergunb 0:8918a71cdbe9 216 //Register interrupt handler
Sergunb 0:8918a71cdbe9 217 aic_set_source_vector(ID_GMAC0, sama5d2EthIrqHandler);
Sergunb 0:8918a71cdbe9 218
Sergunb 0:8918a71cdbe9 219 //Configure interrupt priority
Sergunb 0:8918a71cdbe9 220 aic_configure(ID_GMAC0, AIC_SMR_SRCTYPE_INT_LEVEL_SENSITIVE |
Sergunb 0:8918a71cdbe9 221 AIC_SMR_PRIOR(SAMA5D2_ETH_IRQ_PRIORITY));
Sergunb 0:8918a71cdbe9 222
Sergunb 0:8918a71cdbe9 223 //Enable the GMAC to transmit and receive data
Sergunb 0:8918a71cdbe9 224 GMAC0->GMAC_NCR |= GMAC_NCR_TXEN | GMAC_NCR_RXEN;
Sergunb 0:8918a71cdbe9 225
Sergunb 0:8918a71cdbe9 226 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 227 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 228
Sergunb 0:8918a71cdbe9 229 //Successful initialization
Sergunb 0:8918a71cdbe9 230 return NO_ERROR;
Sergunb 0:8918a71cdbe9 231 }
Sergunb 0:8918a71cdbe9 232
Sergunb 0:8918a71cdbe9 233
Sergunb 0:8918a71cdbe9 234 //SAMA5D2-Xplained-Ultra evaluation board?
Sergunb 0:8918a71cdbe9 235 #if defined(CONFIG_BOARD_SAMA5D2_XPLAINED)
Sergunb 0:8918a71cdbe9 236
Sergunb 0:8918a71cdbe9 237 /**
Sergunb 0:8918a71cdbe9 238 * @brief GPIO configuration
Sergunb 0:8918a71cdbe9 239 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 240 **/
Sergunb 0:8918a71cdbe9 241
Sergunb 0:8918a71cdbe9 242 void sama5d2EthInitGpio(NetInterface *interface)
Sergunb 0:8918a71cdbe9 243 {
Sergunb 0:8918a71cdbe9 244 struct _pin rmiiPins[] = PINS_GMAC_RMII_IOS3;
Sergunb 0:8918a71cdbe9 245
Sergunb 0:8918a71cdbe9 246 //Configure RMII pins
Sergunb 0:8918a71cdbe9 247 pio_configure(rmiiPins, arraysize(rmiiPins));
Sergunb 0:8918a71cdbe9 248
Sergunb 0:8918a71cdbe9 249 //Select RMII operation mode
Sergunb 0:8918a71cdbe9 250 GMAC0->GMAC_UR = GMAC_UR_RMII;
Sergunb 0:8918a71cdbe9 251 }
Sergunb 0:8918a71cdbe9 252
Sergunb 0:8918a71cdbe9 253 #endif
Sergunb 0:8918a71cdbe9 254
Sergunb 0:8918a71cdbe9 255
Sergunb 0:8918a71cdbe9 256 /**
Sergunb 0:8918a71cdbe9 257 * @brief Initialize buffer descriptors
Sergunb 0:8918a71cdbe9 258 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 259 **/
Sergunb 0:8918a71cdbe9 260
Sergunb 0:8918a71cdbe9 261 void sama5d2EthInitBufferDesc(NetInterface *interface)
Sergunb 0:8918a71cdbe9 262 {
Sergunb 0:8918a71cdbe9 263 uint_t i;
Sergunb 0:8918a71cdbe9 264 uint32_t address;
Sergunb 0:8918a71cdbe9 265
Sergunb 0:8918a71cdbe9 266 //Initialize TX buffer descriptors
Sergunb 0:8918a71cdbe9 267 for(i = 0; i < SAMA5D2_ETH_TX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 268 {
Sergunb 0:8918a71cdbe9 269 //Calculate the address of the current TX buffer
Sergunb 0:8918a71cdbe9 270 address = (uint32_t) txBuffer[i];
Sergunb 0:8918a71cdbe9 271 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 272 txBufferDesc[i].address = address;
Sergunb 0:8918a71cdbe9 273 //Initialize status field
Sergunb 0:8918a71cdbe9 274 txBufferDesc[i].status = GMAC_TX_USED;
Sergunb 0:8918a71cdbe9 275 }
Sergunb 0:8918a71cdbe9 276
Sergunb 0:8918a71cdbe9 277 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 278 txBufferDesc[i - 1].status |= GMAC_TX_WRAP;
Sergunb 0:8918a71cdbe9 279 //Initialize TX buffer index
Sergunb 0:8918a71cdbe9 280 txBufferIndex = 0;
Sergunb 0:8918a71cdbe9 281
Sergunb 0:8918a71cdbe9 282 //Initialize RX buffer descriptors
Sergunb 0:8918a71cdbe9 283 for(i = 0; i < SAMA5D2_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 284 {
Sergunb 0:8918a71cdbe9 285 //Calculate the address of the current RX buffer
Sergunb 0:8918a71cdbe9 286 address = (uint32_t) rxBuffer[i];
Sergunb 0:8918a71cdbe9 287 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 288 rxBufferDesc[i].address = address & GMAC_RX_ADDRESS;
Sergunb 0:8918a71cdbe9 289 //Clear status field
Sergunb 0:8918a71cdbe9 290 rxBufferDesc[i].status = 0;
Sergunb 0:8918a71cdbe9 291 }
Sergunb 0:8918a71cdbe9 292
Sergunb 0:8918a71cdbe9 293 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 294 rxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
Sergunb 0:8918a71cdbe9 295 //Initialize RX buffer index
Sergunb 0:8918a71cdbe9 296 rxBufferIndex = 0;
Sergunb 0:8918a71cdbe9 297
Sergunb 0:8918a71cdbe9 298 //Initialize dummy TX buffer descriptors
Sergunb 0:8918a71cdbe9 299 for(i = 0; i < SAMA5D2_ETH_DUMMY_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 300 {
Sergunb 0:8918a71cdbe9 301 //Calculate the address of the current TX buffer
Sergunb 0:8918a71cdbe9 302 address = (uint32_t) dummyTxBuffer[i];
Sergunb 0:8918a71cdbe9 303 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 304 dummyTxBufferDesc[i].address = address;
Sergunb 0:8918a71cdbe9 305 //Initialize status field
Sergunb 0:8918a71cdbe9 306 dummyTxBufferDesc[i].status = GMAC_TX_USED;
Sergunb 0:8918a71cdbe9 307 }
Sergunb 0:8918a71cdbe9 308
Sergunb 0:8918a71cdbe9 309 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 310 dummyTxBufferDesc[i - 1].status |= GMAC_TX_WRAP;
Sergunb 0:8918a71cdbe9 311
Sergunb 0:8918a71cdbe9 312 //Initialize dummy RX buffer descriptors
Sergunb 0:8918a71cdbe9 313 for(i = 0; i < SAMA5D2_ETH_DUMMY_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 314 {
Sergunb 0:8918a71cdbe9 315 //Calculate the address of the current RX buffer
Sergunb 0:8918a71cdbe9 316 address = (uint32_t) dummyRxBuffer[i];
Sergunb 0:8918a71cdbe9 317 //Write the address to the descriptor entry
Sergunb 0:8918a71cdbe9 318 dummyRxBufferDesc[i].address = (address & GMAC_RX_ADDRESS) | GMAC_RX_OWNERSHIP;
Sergunb 0:8918a71cdbe9 319 //Clear status field
Sergunb 0:8918a71cdbe9 320 dummyRxBufferDesc[i].status = 0;
Sergunb 0:8918a71cdbe9 321 }
Sergunb 0:8918a71cdbe9 322
Sergunb 0:8918a71cdbe9 323 //Mark the last descriptor entry with the wrap flag
Sergunb 0:8918a71cdbe9 324 dummyRxBufferDesc[i - 1].address |= GMAC_RX_WRAP;
Sergunb 0:8918a71cdbe9 325
Sergunb 0:8918a71cdbe9 326 //Start location of the TX descriptor list
Sergunb 0:8918a71cdbe9 327 GMAC0->GMAC_TBQB = (uint32_t) txBufferDesc;
Sergunb 0:8918a71cdbe9 328 GMAC0->GMAC_TBQBAPQ[0] = (uint32_t) dummyTxBufferDesc;
Sergunb 0:8918a71cdbe9 329 GMAC0->GMAC_TBQBAPQ[1] = (uint32_t) dummyTxBufferDesc;
Sergunb 0:8918a71cdbe9 330
Sergunb 0:8918a71cdbe9 331 //Start location of the RX descriptor list
Sergunb 0:8918a71cdbe9 332 GMAC0->GMAC_RBQB = (uint32_t) rxBufferDesc;
Sergunb 0:8918a71cdbe9 333 GMAC0->GMAC_RBQBAPQ[0] = (uint32_t) dummyRxBufferDesc;
Sergunb 0:8918a71cdbe9 334 GMAC0->GMAC_RBQBAPQ[1] = (uint32_t) dummyRxBufferDesc;
Sergunb 0:8918a71cdbe9 335 }
Sergunb 0:8918a71cdbe9 336
Sergunb 0:8918a71cdbe9 337
Sergunb 0:8918a71cdbe9 338 /**
Sergunb 0:8918a71cdbe9 339 * @brief SAMA5D2 Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 340 *
Sergunb 0:8918a71cdbe9 341 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 342 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 343 *
Sergunb 0:8918a71cdbe9 344 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 345 **/
Sergunb 0:8918a71cdbe9 346
Sergunb 0:8918a71cdbe9 347 void sama5d2EthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 348 {
Sergunb 0:8918a71cdbe9 349 //Handle periodic operations
Sergunb 0:8918a71cdbe9 350 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 351 }
Sergunb 0:8918a71cdbe9 352
Sergunb 0:8918a71cdbe9 353
Sergunb 0:8918a71cdbe9 354 /**
Sergunb 0:8918a71cdbe9 355 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 356 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 357 **/
Sergunb 0:8918a71cdbe9 358
Sergunb 0:8918a71cdbe9 359 void sama5d2EthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 360 {
Sergunb 0:8918a71cdbe9 361 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 362 aic_enable(ID_GMAC0);
Sergunb 0:8918a71cdbe9 363 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 364 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 365 }
Sergunb 0:8918a71cdbe9 366
Sergunb 0:8918a71cdbe9 367
Sergunb 0:8918a71cdbe9 368 /**
Sergunb 0:8918a71cdbe9 369 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 370 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 371 **/
Sergunb 0:8918a71cdbe9 372
Sergunb 0:8918a71cdbe9 373 void sama5d2EthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 374 {
Sergunb 0:8918a71cdbe9 375 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 376 aic_disable(ID_GMAC0);
Sergunb 0:8918a71cdbe9 377 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 378 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 379 }
Sergunb 0:8918a71cdbe9 380
Sergunb 0:8918a71cdbe9 381
Sergunb 0:8918a71cdbe9 382 /**
Sergunb 0:8918a71cdbe9 383 * @brief SAMA5D2 Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 384 **/
Sergunb 0:8918a71cdbe9 385
Sergunb 0:8918a71cdbe9 386 void sama5d2EthIrqHandler(void)
Sergunb 0:8918a71cdbe9 387 {
Sergunb 0:8918a71cdbe9 388 bool_t flag;
Sergunb 0:8918a71cdbe9 389 volatile uint32_t isr;
Sergunb 0:8918a71cdbe9 390 volatile uint32_t tsr;
Sergunb 0:8918a71cdbe9 391 volatile uint32_t rsr;
Sergunb 0:8918a71cdbe9 392
Sergunb 0:8918a71cdbe9 393 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 394 osEnterIsr();
Sergunb 0:8918a71cdbe9 395
Sergunb 0:8918a71cdbe9 396 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 397 flag = FALSE;
Sergunb 0:8918a71cdbe9 398
Sergunb 0:8918a71cdbe9 399 //Each time the software reads GMAC_ISR, it has to check the
Sergunb 0:8918a71cdbe9 400 //contents of GMAC_TSR, GMAC_RSR and GMAC_NSR
Sergunb 0:8918a71cdbe9 401 isr = GMAC0->GMAC_ISRPQ[0];
Sergunb 0:8918a71cdbe9 402 isr = GMAC0->GMAC_ISRPQ[1];
Sergunb 0:8918a71cdbe9 403 isr = GMAC0->GMAC_ISR;
Sergunb 0:8918a71cdbe9 404 tsr = GMAC0->GMAC_TSR;
Sergunb 0:8918a71cdbe9 405 rsr = GMAC0->GMAC_RSR;
Sergunb 0:8918a71cdbe9 406
Sergunb 0:8918a71cdbe9 407 //A packet has been transmitted?
Sergunb 0:8918a71cdbe9 408 if(tsr & (GMAC_TSR_HRESP | GMAC_TSR_TXCOMP | GMAC_TSR_TFC |
Sergunb 0:8918a71cdbe9 409 GMAC_TSR_TXGO | GMAC_TSR_RLE | GMAC_TSR_COL | GMAC_TSR_UBR))
Sergunb 0:8918a71cdbe9 410 {
Sergunb 0:8918a71cdbe9 411 //Only clear TSR flags that are currently set
Sergunb 0:8918a71cdbe9 412 GMAC0->GMAC_TSR = tsr;
Sergunb 0:8918a71cdbe9 413
Sergunb 0:8918a71cdbe9 414 //Check whether the TX buffer is available for writing
Sergunb 0:8918a71cdbe9 415 if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
Sergunb 0:8918a71cdbe9 416 {
Sergunb 0:8918a71cdbe9 417 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 418 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 419 }
Sergunb 0:8918a71cdbe9 420 }
Sergunb 0:8918a71cdbe9 421
Sergunb 0:8918a71cdbe9 422 //A packet has been received?
Sergunb 0:8918a71cdbe9 423 if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
Sergunb 0:8918a71cdbe9 424 {
Sergunb 0:8918a71cdbe9 425 //Set event flag
Sergunb 0:8918a71cdbe9 426 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 427 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 428 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 429 }
Sergunb 0:8918a71cdbe9 430
Sergunb 0:8918a71cdbe9 431 //Write AIC_EOICR register before exiting
Sergunb 0:8918a71cdbe9 432 AIC->AIC_EOICR = 0;
Sergunb 0:8918a71cdbe9 433
Sergunb 0:8918a71cdbe9 434 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 435 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 436 }
Sergunb 0:8918a71cdbe9 437
Sergunb 0:8918a71cdbe9 438
Sergunb 0:8918a71cdbe9 439 /**
Sergunb 0:8918a71cdbe9 440 * @brief SAMA5D2 Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 441 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 442 **/
Sergunb 0:8918a71cdbe9 443
Sergunb 0:8918a71cdbe9 444 void sama5d2EthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 445 {
Sergunb 0:8918a71cdbe9 446 error_t error;
Sergunb 0:8918a71cdbe9 447 uint32_t rsr;
Sergunb 0:8918a71cdbe9 448
Sergunb 0:8918a71cdbe9 449 //Read receive status
Sergunb 0:8918a71cdbe9 450 rsr = GMAC0->GMAC_RSR;
Sergunb 0:8918a71cdbe9 451
Sergunb 0:8918a71cdbe9 452 //Packet received?
Sergunb 0:8918a71cdbe9 453 if(rsr & (GMAC_RSR_HNO | GMAC_RSR_RXOVR | GMAC_RSR_REC | GMAC_RSR_BNA))
Sergunb 0:8918a71cdbe9 454 {
Sergunb 0:8918a71cdbe9 455 //Only clear RSR flags that are currently set
Sergunb 0:8918a71cdbe9 456 GMAC0->GMAC_RSR = rsr;
Sergunb 0:8918a71cdbe9 457
Sergunb 0:8918a71cdbe9 458 //Process all pending packets
Sergunb 0:8918a71cdbe9 459 do
Sergunb 0:8918a71cdbe9 460 {
Sergunb 0:8918a71cdbe9 461 //Read incoming packet
Sergunb 0:8918a71cdbe9 462 error = sama5d2EthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 463
Sergunb 0:8918a71cdbe9 464 //No more data in the receive buffer?
Sergunb 0:8918a71cdbe9 465 } while(error != ERROR_BUFFER_EMPTY);
Sergunb 0:8918a71cdbe9 466 }
Sergunb 0:8918a71cdbe9 467 }
Sergunb 0:8918a71cdbe9 468
Sergunb 0:8918a71cdbe9 469
Sergunb 0:8918a71cdbe9 470 /**
Sergunb 0:8918a71cdbe9 471 * @brief Send a packet
Sergunb 0:8918a71cdbe9 472 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 473 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 474 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 475 * @return Error code
Sergunb 0:8918a71cdbe9 476 **/
Sergunb 0:8918a71cdbe9 477
Sergunb 0:8918a71cdbe9 478 error_t sama5d2EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 479 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 480 {
Sergunb 0:8918a71cdbe9 481 size_t length;
Sergunb 0:8918a71cdbe9 482
Sergunb 0:8918a71cdbe9 483 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 484 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 485
Sergunb 0:8918a71cdbe9 486 //Check the frame length
Sergunb 0:8918a71cdbe9 487 if(length > SAMA5D2_ETH_TX_BUFFER_SIZE)
Sergunb 0:8918a71cdbe9 488 {
Sergunb 0:8918a71cdbe9 489 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 490 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 491 //Report an error
Sergunb 0:8918a71cdbe9 492 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 493 }
Sergunb 0:8918a71cdbe9 494
Sergunb 0:8918a71cdbe9 495 //Make sure the current buffer is available for writing
Sergunb 0:8918a71cdbe9 496 if(!(txBufferDesc[txBufferIndex].status & GMAC_TX_USED))
Sergunb 0:8918a71cdbe9 497 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 498
Sergunb 0:8918a71cdbe9 499 //Copy user data to the transmit buffer
Sergunb 0:8918a71cdbe9 500 netBufferRead(txBuffer[txBufferIndex], buffer, offset, length);
Sergunb 0:8918a71cdbe9 501
Sergunb 0:8918a71cdbe9 502 //Set the necessary flags in the descriptor entry
Sergunb 0:8918a71cdbe9 503 if(txBufferIndex < (SAMA5D2_ETH_TX_BUFFER_COUNT - 1))
Sergunb 0:8918a71cdbe9 504 {
Sergunb 0:8918a71cdbe9 505 //Write the status word
Sergunb 0:8918a71cdbe9 506 txBufferDesc[txBufferIndex].status =
Sergunb 0:8918a71cdbe9 507 GMAC_TX_LAST | (length & GMAC_TX_LENGTH);
Sergunb 0:8918a71cdbe9 508
Sergunb 0:8918a71cdbe9 509 //Point to the next buffer
Sergunb 0:8918a71cdbe9 510 txBufferIndex++;
Sergunb 0:8918a71cdbe9 511 }
Sergunb 0:8918a71cdbe9 512 else
Sergunb 0:8918a71cdbe9 513 {
Sergunb 0:8918a71cdbe9 514 //Write the status word
Sergunb 0:8918a71cdbe9 515 txBufferDesc[txBufferIndex].status = GMAC_TX_WRAP |
Sergunb 0:8918a71cdbe9 516 GMAC_TX_LAST | (length & GMAC_TX_LENGTH);
Sergunb 0:8918a71cdbe9 517
Sergunb 0:8918a71cdbe9 518 //Wrap around
Sergunb 0:8918a71cdbe9 519 txBufferIndex = 0;
Sergunb 0:8918a71cdbe9 520 }
Sergunb 0:8918a71cdbe9 521
Sergunb 0:8918a71cdbe9 522 //Data synchronization barrier
Sergunb 0:8918a71cdbe9 523 __DSB();
Sergunb 0:8918a71cdbe9 524
Sergunb 0:8918a71cdbe9 525 //Set the TSTART bit to initiate transmission
Sergunb 0:8918a71cdbe9 526 GMAC0->GMAC_NCR |= GMAC_NCR_TSTART;
Sergunb 0:8918a71cdbe9 527
Sergunb 0:8918a71cdbe9 528 //Check whether the next buffer is available for writing
Sergunb 0:8918a71cdbe9 529 if(txBufferDesc[txBufferIndex].status & GMAC_TX_USED)
Sergunb 0:8918a71cdbe9 530 {
Sergunb 0:8918a71cdbe9 531 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 532 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 533 }
Sergunb 0:8918a71cdbe9 534
Sergunb 0:8918a71cdbe9 535 //Successful processing
Sergunb 0:8918a71cdbe9 536 return NO_ERROR;
Sergunb 0:8918a71cdbe9 537 }
Sergunb 0:8918a71cdbe9 538
Sergunb 0:8918a71cdbe9 539
Sergunb 0:8918a71cdbe9 540 /**
Sergunb 0:8918a71cdbe9 541 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 542 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 543 * @return Error code
Sergunb 0:8918a71cdbe9 544 **/
Sergunb 0:8918a71cdbe9 545
Sergunb 0:8918a71cdbe9 546 error_t sama5d2EthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 547 {
Sergunb 0:8918a71cdbe9 548 static uint8_t temp[ETH_MAX_FRAME_SIZE];
Sergunb 0:8918a71cdbe9 549 error_t error;
Sergunb 0:8918a71cdbe9 550 uint_t i;
Sergunb 0:8918a71cdbe9 551 uint_t j;
Sergunb 0:8918a71cdbe9 552 uint_t sofIndex;
Sergunb 0:8918a71cdbe9 553 uint_t eofIndex;
Sergunb 0:8918a71cdbe9 554 size_t n;
Sergunb 0:8918a71cdbe9 555 size_t size;
Sergunb 0:8918a71cdbe9 556 size_t length;
Sergunb 0:8918a71cdbe9 557
Sergunb 0:8918a71cdbe9 558 //Initialize SOF and EOF indices
Sergunb 0:8918a71cdbe9 559 sofIndex = UINT_MAX;
Sergunb 0:8918a71cdbe9 560 eofIndex = UINT_MAX;
Sergunb 0:8918a71cdbe9 561
Sergunb 0:8918a71cdbe9 562 //Search for SOF and EOF flags
Sergunb 0:8918a71cdbe9 563 for(i = 0; i < SAMA5D2_ETH_RX_BUFFER_COUNT; i++)
Sergunb 0:8918a71cdbe9 564 {
Sergunb 0:8918a71cdbe9 565 //Point to the current entry
Sergunb 0:8918a71cdbe9 566 j = rxBufferIndex + i;
Sergunb 0:8918a71cdbe9 567
Sergunb 0:8918a71cdbe9 568 //Wrap around to the beginning of the buffer if necessary
Sergunb 0:8918a71cdbe9 569 if(j >= SAMA5D2_ETH_RX_BUFFER_COUNT)
Sergunb 0:8918a71cdbe9 570 j -= SAMA5D2_ETH_RX_BUFFER_COUNT;
Sergunb 0:8918a71cdbe9 571
Sergunb 0:8918a71cdbe9 572 //No more entries to process?
Sergunb 0:8918a71cdbe9 573 if(!(rxBufferDesc[j].address & GMAC_RX_OWNERSHIP))
Sergunb 0:8918a71cdbe9 574 {
Sergunb 0:8918a71cdbe9 575 //Stop processing
Sergunb 0:8918a71cdbe9 576 break;
Sergunb 0:8918a71cdbe9 577 }
Sergunb 0:8918a71cdbe9 578 //A valid SOF has been found?
Sergunb 0:8918a71cdbe9 579 if(rxBufferDesc[j].status & GMAC_RX_SOF)
Sergunb 0:8918a71cdbe9 580 {
Sergunb 0:8918a71cdbe9 581 //Save the position of the SOF
Sergunb 0:8918a71cdbe9 582 sofIndex = i;
Sergunb 0:8918a71cdbe9 583 }
Sergunb 0:8918a71cdbe9 584 //A valid EOF has been found?
Sergunb 0:8918a71cdbe9 585 if((rxBufferDesc[j].status & GMAC_RX_EOF) && sofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 586 {
Sergunb 0:8918a71cdbe9 587 //Save the position of the EOF
Sergunb 0:8918a71cdbe9 588 eofIndex = i;
Sergunb 0:8918a71cdbe9 589 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 590 size = rxBufferDesc[j].status & GMAC_RX_LENGTH;
Sergunb 0:8918a71cdbe9 591 //Limit the number of data to read
Sergunb 0:8918a71cdbe9 592 size = MIN(size, ETH_MAX_FRAME_SIZE);
Sergunb 0:8918a71cdbe9 593 //Stop processing since we have reached the end of the frame
Sergunb 0:8918a71cdbe9 594 break;
Sergunb 0:8918a71cdbe9 595 }
Sergunb 0:8918a71cdbe9 596 }
Sergunb 0:8918a71cdbe9 597
Sergunb 0:8918a71cdbe9 598 //Determine the number of entries to process
Sergunb 0:8918a71cdbe9 599 if(eofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 600 j = eofIndex + 1;
Sergunb 0:8918a71cdbe9 601 else if(sofIndex != UINT_MAX)
Sergunb 0:8918a71cdbe9 602 j = sofIndex;
Sergunb 0:8918a71cdbe9 603 else
Sergunb 0:8918a71cdbe9 604 j = i;
Sergunb 0:8918a71cdbe9 605
Sergunb 0:8918a71cdbe9 606 //Total number of bytes that have been copied from the receive buffer
Sergunb 0:8918a71cdbe9 607 length = 0;
Sergunb 0:8918a71cdbe9 608
Sergunb 0:8918a71cdbe9 609 //Process incoming frame
Sergunb 0:8918a71cdbe9 610 for(i = 0; i < j; i++)
Sergunb 0:8918a71cdbe9 611 {
Sergunb 0:8918a71cdbe9 612 //Any data to copy from current buffer?
Sergunb 0:8918a71cdbe9 613 if(eofIndex != UINT_MAX && i >= sofIndex && i <= eofIndex)
Sergunb 0:8918a71cdbe9 614 {
Sergunb 0:8918a71cdbe9 615 //Calculate the number of bytes to read at a time
Sergunb 0:8918a71cdbe9 616 n = MIN(size, SAMA5D2_ETH_RX_BUFFER_SIZE);
Sergunb 0:8918a71cdbe9 617 //Copy data from receive buffer
Sergunb 0:8918a71cdbe9 618 memcpy(temp + length, rxBuffer[rxBufferIndex], n);
Sergunb 0:8918a71cdbe9 619 //Update byte counters
Sergunb 0:8918a71cdbe9 620 length += n;
Sergunb 0:8918a71cdbe9 621 size -= n;
Sergunb 0:8918a71cdbe9 622 }
Sergunb 0:8918a71cdbe9 623
Sergunb 0:8918a71cdbe9 624 //Mark the current buffer as free
Sergunb 0:8918a71cdbe9 625 rxBufferDesc[rxBufferIndex].address &= ~GMAC_RX_OWNERSHIP;
Sergunb 0:8918a71cdbe9 626
Sergunb 0:8918a71cdbe9 627 //Point to the following entry
Sergunb 0:8918a71cdbe9 628 rxBufferIndex++;
Sergunb 0:8918a71cdbe9 629
Sergunb 0:8918a71cdbe9 630 //Wrap around to the beginning of the buffer if necessary
Sergunb 0:8918a71cdbe9 631 if(rxBufferIndex >= SAMA5D2_ETH_RX_BUFFER_COUNT)
Sergunb 0:8918a71cdbe9 632 rxBufferIndex = 0;
Sergunb 0:8918a71cdbe9 633 }
Sergunb 0:8918a71cdbe9 634
Sergunb 0:8918a71cdbe9 635 //Any packet to process?
Sergunb 0:8918a71cdbe9 636 if(length > 0)
Sergunb 0:8918a71cdbe9 637 {
Sergunb 0:8918a71cdbe9 638 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 639 nicProcessPacket(interface, temp, length);
Sergunb 0:8918a71cdbe9 640 //Valid packet received
Sergunb 0:8918a71cdbe9 641 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 642 }
Sergunb 0:8918a71cdbe9 643 else
Sergunb 0:8918a71cdbe9 644 {
Sergunb 0:8918a71cdbe9 645 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 646 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 647 }
Sergunb 0:8918a71cdbe9 648
Sergunb 0:8918a71cdbe9 649 //Return status code
Sergunb 0:8918a71cdbe9 650 return error;
Sergunb 0:8918a71cdbe9 651 }
Sergunb 0:8918a71cdbe9 652
Sergunb 0:8918a71cdbe9 653
Sergunb 0:8918a71cdbe9 654 /**
Sergunb 0:8918a71cdbe9 655 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 656 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 657 * @return Error code
Sergunb 0:8918a71cdbe9 658 **/
Sergunb 0:8918a71cdbe9 659
Sergunb 0:8918a71cdbe9 660 error_t sama5d2EthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 661 {
Sergunb 0:8918a71cdbe9 662 uint_t i;
Sergunb 0:8918a71cdbe9 663 uint_t k;
Sergunb 0:8918a71cdbe9 664 uint8_t *p;
Sergunb 0:8918a71cdbe9 665 uint32_t hashTable[2];
Sergunb 0:8918a71cdbe9 666 MacFilterEntry *entry;
Sergunb 0:8918a71cdbe9 667
Sergunb 0:8918a71cdbe9 668 //Debug message
Sergunb 0:8918a71cdbe9 669 TRACE_DEBUG("Updating SAMA5D2 hash table...\r\n");
Sergunb 0:8918a71cdbe9 670
Sergunb 0:8918a71cdbe9 671 //Clear hash table
Sergunb 0:8918a71cdbe9 672 hashTable[0] = 0;
Sergunb 0:8918a71cdbe9 673 hashTable[1] = 0;
Sergunb 0:8918a71cdbe9 674
Sergunb 0:8918a71cdbe9 675 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 676 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 677 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 678 {
Sergunb 0:8918a71cdbe9 679 //Point to the current entry
Sergunb 0:8918a71cdbe9 680 entry = &interface->macMulticastFilter[i];
Sergunb 0:8918a71cdbe9 681
Sergunb 0:8918a71cdbe9 682 //Valid entry?
Sergunb 0:8918a71cdbe9 683 if(entry->refCount > 0)
Sergunb 0:8918a71cdbe9 684 {
Sergunb 0:8918a71cdbe9 685 //Point to the MAC address
Sergunb 0:8918a71cdbe9 686 p = entry->addr.b;
Sergunb 0:8918a71cdbe9 687
Sergunb 0:8918a71cdbe9 688 //Apply the hash function
Sergunb 0:8918a71cdbe9 689 k = (p[0] >> 6) ^ p[0];
Sergunb 0:8918a71cdbe9 690 k ^= (p[1] >> 4) ^ (p[1] << 2);
Sergunb 0:8918a71cdbe9 691 k ^= (p[2] >> 2) ^ (p[2] << 4);
Sergunb 0:8918a71cdbe9 692 k ^= (p[3] >> 6) ^ p[3];
Sergunb 0:8918a71cdbe9 693 k ^= (p[4] >> 4) ^ (p[4] << 2);
Sergunb 0:8918a71cdbe9 694 k ^= (p[5] >> 2) ^ (p[5] << 4);
Sergunb 0:8918a71cdbe9 695
Sergunb 0:8918a71cdbe9 696 //The hash value is reduced to a 6-bit index
Sergunb 0:8918a71cdbe9 697 k &= 0x3F;
Sergunb 0:8918a71cdbe9 698
Sergunb 0:8918a71cdbe9 699 //Update hash table contents
Sergunb 0:8918a71cdbe9 700 hashTable[k / 32] |= (1 << (k % 32));
Sergunb 0:8918a71cdbe9 701 }
Sergunb 0:8918a71cdbe9 702 }
Sergunb 0:8918a71cdbe9 703
Sergunb 0:8918a71cdbe9 704 //Write the hash table
Sergunb 0:8918a71cdbe9 705 GMAC0->GMAC_HRB = hashTable[0];
Sergunb 0:8918a71cdbe9 706 GMAC0->GMAC_HRT = hashTable[1];
Sergunb 0:8918a71cdbe9 707
Sergunb 0:8918a71cdbe9 708 //Debug message
Sergunb 0:8918a71cdbe9 709 TRACE_DEBUG(" HRB = %08" PRIX32 "\r\n", GMAC0->GMAC_HRB);
Sergunb 0:8918a71cdbe9 710 TRACE_DEBUG(" HRT = %08" PRIX32 "\r\n", GMAC0->GMAC_HRT);
Sergunb 0:8918a71cdbe9 711
Sergunb 0:8918a71cdbe9 712 //Successful processing
Sergunb 0:8918a71cdbe9 713 return NO_ERROR;
Sergunb 0:8918a71cdbe9 714 }
Sergunb 0:8918a71cdbe9 715
Sergunb 0:8918a71cdbe9 716
Sergunb 0:8918a71cdbe9 717 /**
Sergunb 0:8918a71cdbe9 718 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 719 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 720 * @return Error code
Sergunb 0:8918a71cdbe9 721 **/
Sergunb 0:8918a71cdbe9 722
Sergunb 0:8918a71cdbe9 723 error_t sama5d2EthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 724 {
Sergunb 0:8918a71cdbe9 725 uint32_t config;
Sergunb 0:8918a71cdbe9 726
Sergunb 0:8918a71cdbe9 727 //Read network configuration register
Sergunb 0:8918a71cdbe9 728 config = GMAC0->GMAC_NCFGR;
Sergunb 0:8918a71cdbe9 729
Sergunb 0:8918a71cdbe9 730 //10BASE-T or 100BASE-TX operation mode?
Sergunb 0:8918a71cdbe9 731 if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS)
Sergunb 0:8918a71cdbe9 732 config |= GMAC_NCFGR_SPD;
Sergunb 0:8918a71cdbe9 733 else
Sergunb 0:8918a71cdbe9 734 config &= ~GMAC_NCFGR_SPD;
Sergunb 0:8918a71cdbe9 735
Sergunb 0:8918a71cdbe9 736 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 737 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 738 config |= GMAC_NCFGR_FD;
Sergunb 0:8918a71cdbe9 739 else
Sergunb 0:8918a71cdbe9 740 config &= ~GMAC_NCFGR_FD;
Sergunb 0:8918a71cdbe9 741
Sergunb 0:8918a71cdbe9 742 //Write configuration value back to NCFGR register
Sergunb 0:8918a71cdbe9 743 GMAC0->GMAC_NCFGR = config;
Sergunb 0:8918a71cdbe9 744
Sergunb 0:8918a71cdbe9 745 //Successful processing
Sergunb 0:8918a71cdbe9 746 return NO_ERROR;
Sergunb 0:8918a71cdbe9 747 }
Sergunb 0:8918a71cdbe9 748
Sergunb 0:8918a71cdbe9 749
Sergunb 0:8918a71cdbe9 750 /**
Sergunb 0:8918a71cdbe9 751 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 752 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 753 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 754 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 755 **/
Sergunb 0:8918a71cdbe9 756
Sergunb 0:8918a71cdbe9 757 void sama5d2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 758 {
Sergunb 0:8918a71cdbe9 759 uint32_t value;
Sergunb 0:8918a71cdbe9 760
Sergunb 0:8918a71cdbe9 761 //Set up a write operation
Sergunb 0:8918a71cdbe9 762 value = GMAC_MAN_CLTTO | GMAC_MAN_OP(1) | GMAC_MAN_WTN(2);
Sergunb 0:8918a71cdbe9 763 //PHY address
Sergunb 0:8918a71cdbe9 764 value |= GMAC_MAN_PHYA(phyAddr);
Sergunb 0:8918a71cdbe9 765 //Register address
Sergunb 0:8918a71cdbe9 766 value |= GMAC_MAN_REGA(regAddr);
Sergunb 0:8918a71cdbe9 767 //Register value
Sergunb 0:8918a71cdbe9 768 value |= GMAC_MAN_DATA(data);
Sergunb 0:8918a71cdbe9 769
Sergunb 0:8918a71cdbe9 770 //Start a write operation
Sergunb 0:8918a71cdbe9 771 GMAC0->GMAC_MAN = value;
Sergunb 0:8918a71cdbe9 772 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 773 while(!(GMAC0->GMAC_NSR & GMAC_NSR_IDLE));
Sergunb 0:8918a71cdbe9 774 }
Sergunb 0:8918a71cdbe9 775
Sergunb 0:8918a71cdbe9 776
Sergunb 0:8918a71cdbe9 777 /**
Sergunb 0:8918a71cdbe9 778 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 779 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 780 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 781 * @return Register value
Sergunb 0:8918a71cdbe9 782 **/
Sergunb 0:8918a71cdbe9 783
Sergunb 0:8918a71cdbe9 784 uint16_t sama5d2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 785 {
Sergunb 0:8918a71cdbe9 786 uint32_t value;
Sergunb 0:8918a71cdbe9 787
Sergunb 0:8918a71cdbe9 788 //Set up a read operation
Sergunb 0:8918a71cdbe9 789 value = GMAC_MAN_CLTTO | GMAC_MAN_OP(2) | GMAC_MAN_WTN(2);
Sergunb 0:8918a71cdbe9 790 //PHY address
Sergunb 0:8918a71cdbe9 791 value |= GMAC_MAN_PHYA(phyAddr);
Sergunb 0:8918a71cdbe9 792 //Register address
Sergunb 0:8918a71cdbe9 793 value |= GMAC_MAN_REGA(regAddr);
Sergunb 0:8918a71cdbe9 794
Sergunb 0:8918a71cdbe9 795 //Start a read operation
Sergunb 0:8918a71cdbe9 796 GMAC0->GMAC_MAN = value;
Sergunb 0:8918a71cdbe9 797 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 798 while(!(GMAC0->GMAC_NSR & GMAC_NSR_IDLE));
Sergunb 0:8918a71cdbe9 799
Sergunb 0:8918a71cdbe9 800 //Return PHY register contents
Sergunb 0:8918a71cdbe9 801 return GMAC0->GMAC_MAN & GMAC_MAN_DATA_Msk;
Sergunb 0:8918a71cdbe9 802 }
Sergunb 0:8918a71cdbe9 803