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cyclone_tcp/drivers/s7g2_eth.h@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file s7g2_eth.h
Sergunb 0:8918a71cdbe9 3 * @brief Renesas Synergy S7G2 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 #ifndef _S7G2_ETH_H
Sergunb 0:8918a71cdbe9 30 #define _S7G2_ETH_H
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "core/nic.h"
Sergunb 0:8918a71cdbe9 34
Sergunb 0:8918a71cdbe9 35 //Number of TX buffers
Sergunb 0:8918a71cdbe9 36 #ifndef S7G2_ETH_TX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 37 #define S7G2_ETH_TX_BUFFER_COUNT 3
Sergunb 0:8918a71cdbe9 38 #elif (S7G2_ETH_TX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 39 #error S7G2_ETH_TX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 40 #endif
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //TX buffer size
Sergunb 0:8918a71cdbe9 43 #ifndef S7G2_ETH_TX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 44 #define S7G2_ETH_TX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 45 #elif (S7G2_ETH_TX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 46 #error S7G2_ETH_TX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 47 #endif
Sergunb 0:8918a71cdbe9 48
Sergunb 0:8918a71cdbe9 49 //Number of RX buffers
Sergunb 0:8918a71cdbe9 50 #ifndef S7G2_ETH_RX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 51 #define S7G2_ETH_RX_BUFFER_COUNT 6
Sergunb 0:8918a71cdbe9 52 #elif (S7G2_ETH_RX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 53 #error S7G2_ETH_RX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 54 #endif
Sergunb 0:8918a71cdbe9 55
Sergunb 0:8918a71cdbe9 56 //RX buffer size
Sergunb 0:8918a71cdbe9 57 #ifndef S7G2_ETH_RX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 58 #define S7G2_ETH_RX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 59 #elif (S7G2_ETH_RX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 60 #error S7G2_ETH_RX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 61 #endif
Sergunb 0:8918a71cdbe9 62
Sergunb 0:8918a71cdbe9 63 //Interrupt priority grouping
Sergunb 0:8918a71cdbe9 64 #ifndef S7G2_ETH_IRQ_PRIORITY_GROUPING
Sergunb 0:8918a71cdbe9 65 #define S7G2_ETH_IRQ_PRIORITY_GROUPING 3
Sergunb 0:8918a71cdbe9 66 #elif (S7G2_ETH_IRQ_PRIORITY_GROUPING < 0)
Sergunb 0:8918a71cdbe9 67 #error S7G2_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
Sergunb 0:8918a71cdbe9 68 #endif
Sergunb 0:8918a71cdbe9 69
Sergunb 0:8918a71cdbe9 70 //Ethernet interrupt group priority
Sergunb 0:8918a71cdbe9 71 #ifndef S7G2_ETH_IRQ_GROUP_PRIORITY
Sergunb 0:8918a71cdbe9 72 #define S7G2_ETH_IRQ_GROUP_PRIORITY 12
Sergunb 0:8918a71cdbe9 73 #elif (S7G2_ETH_IRQ_GROUP_PRIORITY < 0)
Sergunb 0:8918a71cdbe9 74 #error S7G2_ETH_IRQ_GROUP_PRIORITY parameter is not valid
Sergunb 0:8918a71cdbe9 75 #endif
Sergunb 0:8918a71cdbe9 76
Sergunb 0:8918a71cdbe9 77 //Ethernet interrupt subpriority
Sergunb 0:8918a71cdbe9 78 #ifndef S7G2_ETH_IRQ_SUB_PRIORITY
Sergunb 0:8918a71cdbe9 79 #define S7G2_ETH_IRQ_SUB_PRIORITY 0
Sergunb 0:8918a71cdbe9 80 #elif (S7G2_ETH_IRQ_SUB_PRIORITY < 0)
Sergunb 0:8918a71cdbe9 81 #error S7G2_ETH_IRQ_SUB_PRIORITY parameter is not valid
Sergunb 0:8918a71cdbe9 82 #endif
Sergunb 0:8918a71cdbe9 83
Sergunb 0:8918a71cdbe9 84 //EESR register
Sergunb 0:8918a71cdbe9 85 #define EDMAC_EESR_TWB 0x40000000
Sergunb 0:8918a71cdbe9 86 #define EDMAC_EESR_TABT 0x04000000
Sergunb 0:8918a71cdbe9 87 #define EDMAC_EESR_RABT 0x02000000
Sergunb 0:8918a71cdbe9 88 #define EDMAC_EESR_RFCOF 0x01000000
Sergunb 0:8918a71cdbe9 89 #define EDMAC_EESR_ADE 0x00800000
Sergunb 0:8918a71cdbe9 90 #define EDMAC_EESR_ECI 0x00400000
Sergunb 0:8918a71cdbe9 91 #define EDMAC_EESR_TC 0x00200000
Sergunb 0:8918a71cdbe9 92 #define EDMAC_EESR_TDE 0x00100000
Sergunb 0:8918a71cdbe9 93 #define EDMAC_EESR_TFUF 0x00080000
Sergunb 0:8918a71cdbe9 94 #define EDMAC_EESR_FR 0x00040000
Sergunb 0:8918a71cdbe9 95 #define EDMAC_EESR_RDE 0x00020000
Sergunb 0:8918a71cdbe9 96 #define EDMAC_EESR_RFOF 0x00010000
Sergunb 0:8918a71cdbe9 97 #define EDMAC_EESR_CND 0x00000800
Sergunb 0:8918a71cdbe9 98 #define EDMAC_EESR_DLC 0x00000400
Sergunb 0:8918a71cdbe9 99 #define EDMAC_EESR_CD 0x00000200
Sergunb 0:8918a71cdbe9 100 #define EDMAC_EESR_TRO 0x00000100
Sergunb 0:8918a71cdbe9 101 #define EDMAC_EESR_RMAF 0x00000080
Sergunb 0:8918a71cdbe9 102 #define EDMAC_EESR_RRF 0x00000010
Sergunb 0:8918a71cdbe9 103 #define EDMAC_EESR_RTLF 0x00000008
Sergunb 0:8918a71cdbe9 104 #define EDMAC_EESR_RTSF 0x00000004
Sergunb 0:8918a71cdbe9 105 #define EDMAC_EESR_PRE 0x00000002
Sergunb 0:8918a71cdbe9 106 #define EDMAC_EESR_CERF 0x00000001
Sergunb 0:8918a71cdbe9 107
Sergunb 0:8918a71cdbe9 108 //Transmit DMA descriptor flags
Sergunb 0:8918a71cdbe9 109 #define EDMAC_TD0_TACT 0x80000000
Sergunb 0:8918a71cdbe9 110 #define EDMAC_TD0_TDLE 0x40000000
Sergunb 0:8918a71cdbe9 111 #define EDMAC_TD0_TFP_SOF 0x20000000
Sergunb 0:8918a71cdbe9 112 #define EDMAC_TD0_TFP_EOF 0x10000000
Sergunb 0:8918a71cdbe9 113 #define EDMAC_TD0_TFE 0x08000000
Sergunb 0:8918a71cdbe9 114 #define EDMAC_TD0_TWBI 0x04000000
Sergunb 0:8918a71cdbe9 115 #define EDMAC_TD0_TFS_MASK 0x0000010F
Sergunb 0:8918a71cdbe9 116 #define EDMAC_TD0_TFS_TABT 0x00000100
Sergunb 0:8918a71cdbe9 117 #define EDMAC_TD0_TFS_CND 0x00000008
Sergunb 0:8918a71cdbe9 118 #define EDMAC_TD0_TFS_DLC 0x00000004
Sergunb 0:8918a71cdbe9 119 #define EDMAC_TD0_TFS_CD 0x00000002
Sergunb 0:8918a71cdbe9 120 #define EDMAC_TD0_TFS_TRO 0x00000001
Sergunb 0:8918a71cdbe9 121 #define EDMAC_TD1_TBL 0xFFFF0000
Sergunb 0:8918a71cdbe9 122 #define EDMAC_TD2_TBA 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 123
Sergunb 0:8918a71cdbe9 124 //Receive DMA descriptor flags
Sergunb 0:8918a71cdbe9 125 #define EDMAC_RD0_RACT 0x80000000
Sergunb 0:8918a71cdbe9 126 #define EDMAC_RD0_RDLE 0x40000000
Sergunb 0:8918a71cdbe9 127 #define EDMAC_RD0_RFP_SOF 0x20000000
Sergunb 0:8918a71cdbe9 128 #define EDMAC_RD0_RFP_EOF 0x10000000
Sergunb 0:8918a71cdbe9 129 #define EDMAC_RD0_RFE 0x08000000
Sergunb 0:8918a71cdbe9 130 #define EDMAC_RD0_RFS_MASK 0x0000039F
Sergunb 0:8918a71cdbe9 131 #define EDMAC_RD0_RFS_RFOF 0x00000200
Sergunb 0:8918a71cdbe9 132 #define EDMAC_RD0_RFS_RABT 0x00000100
Sergunb 0:8918a71cdbe9 133 #define EDMAC_RD0_RFS_RMAF 0x00000080
Sergunb 0:8918a71cdbe9 134 #define EDMAC_RD0_RFS_RRF 0x00000010
Sergunb 0:8918a71cdbe9 135 #define EDMAC_RD0_RFS_RTLF 0x00000008
Sergunb 0:8918a71cdbe9 136 #define EDMAC_RD0_RFS_RTSF 0x00000004
Sergunb 0:8918a71cdbe9 137 #define EDMAC_RD0_RFS_PRE 0x00000002
Sergunb 0:8918a71cdbe9 138 #define EDMAC_RD0_RFS_CERF 0x00000001
Sergunb 0:8918a71cdbe9 139 #define EDMAC_RD1_RBL 0xFFFF0000
Sergunb 0:8918a71cdbe9 140 #define EDMAC_RD1_RFL 0x0000FFFF
Sergunb 0:8918a71cdbe9 141 #define EDMAC_RD2_RBA 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 142
Sergunb 0:8918a71cdbe9 143 //Serial Management Interface
Sergunb 0:8918a71cdbe9 144 #define SMI_SYNC 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 145 #define SMI_START 0x00000001
Sergunb 0:8918a71cdbe9 146 #define SMI_WRITE 0x00000001
Sergunb 0:8918a71cdbe9 147 #define SMI_READ 0x00000002
Sergunb 0:8918a71cdbe9 148 #define SMI_TA 0x00000002
Sergunb 0:8918a71cdbe9 149
Sergunb 0:8918a71cdbe9 150
Sergunb 0:8918a71cdbe9 151 /**
Sergunb 0:8918a71cdbe9 152 * @brief Transmit DMA descriptor
Sergunb 0:8918a71cdbe9 153 **/
Sergunb 0:8918a71cdbe9 154
Sergunb 0:8918a71cdbe9 155 typedef struct
Sergunb 0:8918a71cdbe9 156 {
Sergunb 0:8918a71cdbe9 157 uint32_t td0;
Sergunb 0:8918a71cdbe9 158 uint32_t td1;
Sergunb 0:8918a71cdbe9 159 uint32_t td2;
Sergunb 0:8918a71cdbe9 160 uint32_t padding;
Sergunb 0:8918a71cdbe9 161 } S7g2TxDmaDesc;
Sergunb 0:8918a71cdbe9 162
Sergunb 0:8918a71cdbe9 163
Sergunb 0:8918a71cdbe9 164 /**
Sergunb 0:8918a71cdbe9 165 * @brief Receive DMA descriptor
Sergunb 0:8918a71cdbe9 166 **/
Sergunb 0:8918a71cdbe9 167
Sergunb 0:8918a71cdbe9 168 typedef struct
Sergunb 0:8918a71cdbe9 169 {
Sergunb 0:8918a71cdbe9 170 uint32_t rd0;
Sergunb 0:8918a71cdbe9 171 uint32_t rd1;
Sergunb 0:8918a71cdbe9 172 uint32_t rd2;
Sergunb 0:8918a71cdbe9 173 uint32_t padding;
Sergunb 0:8918a71cdbe9 174 } S7g2RxDmaDesc;
Sergunb 0:8918a71cdbe9 175
Sergunb 0:8918a71cdbe9 176
Sergunb 0:8918a71cdbe9 177 //S7G2 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 178 extern const NicDriver s7g2EthDriver;
Sergunb 0:8918a71cdbe9 179
Sergunb 0:8918a71cdbe9 180 //S7G2 Ethernet MAC related functions
Sergunb 0:8918a71cdbe9 181 error_t s7g2EthInit(NetInterface *interface);
Sergunb 0:8918a71cdbe9 182 void s7g2EthInitGpio(NetInterface *interface);
Sergunb 0:8918a71cdbe9 183 void s7g2EthInitDmaDesc(NetInterface *interface);
Sergunb 0:8918a71cdbe9 184
Sergunb 0:8918a71cdbe9 185 void s7g2EthTick(NetInterface *interface);
Sergunb 0:8918a71cdbe9 186
Sergunb 0:8918a71cdbe9 187 void s7g2EthEnableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 188 void s7g2EthDisableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 189 void s7g2EthEventHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 190
Sergunb 0:8918a71cdbe9 191 error_t s7g2EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 192 const NetBuffer *buffer, size_t offset);
Sergunb 0:8918a71cdbe9 193
Sergunb 0:8918a71cdbe9 194 error_t s7g2EthReceivePacket(NetInterface *interface);
Sergunb 0:8918a71cdbe9 195
Sergunb 0:8918a71cdbe9 196 error_t s7g2EthSetMulticastFilter(NetInterface *interface);
Sergunb 0:8918a71cdbe9 197 error_t s7g2EthUpdateMacConfig(NetInterface *interface);
Sergunb 0:8918a71cdbe9 198
Sergunb 0:8918a71cdbe9 199 void s7g2EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
Sergunb 0:8918a71cdbe9 200 uint16_t s7g2EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
Sergunb 0:8918a71cdbe9 201
Sergunb 0:8918a71cdbe9 202 void s7g2EthWriteSmi(uint32_t data, uint_t length);
Sergunb 0:8918a71cdbe9 203 uint32_t s7g2EthReadSmi(uint_t length);
Sergunb 0:8918a71cdbe9 204
Sergunb 0:8918a71cdbe9 205 #endif
Sergunb 0:8918a71cdbe9 206