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cyclone_tcp/drivers/omapl138_eth.h@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
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Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file omapl138_eth.h
Sergunb 0:8918a71cdbe9 3 * @brief OMAP-L138 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 #ifndef _OMAPL138_ETH_H
Sergunb 0:8918a71cdbe9 30 #define _OMAPL138_ETH_H
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "core/nic.h"
Sergunb 0:8918a71cdbe9 34
Sergunb 0:8918a71cdbe9 35 //Number of TX buffers
Sergunb 0:8918a71cdbe9 36 #ifndef OMAPL138_ETH_TX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 37 #define OMAPL138_ETH_TX_BUFFER_COUNT 8
Sergunb 0:8918a71cdbe9 38 #elif (OMAPL138_ETH_TX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 39 #error OMAPL138_ETH_TX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 40 #endif
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //TX buffer size
Sergunb 0:8918a71cdbe9 43 #ifndef OMAPL138_ETH_TX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 44 #define OMAPL138_ETH_TX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 45 #elif (OMAPL138_ETH_TX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 46 #error OMAPL138_ETH_TX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 47 #endif
Sergunb 0:8918a71cdbe9 48
Sergunb 0:8918a71cdbe9 49 //Number of RX buffers
Sergunb 0:8918a71cdbe9 50 #ifndef OMAPL138_ETH_RX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 51 #define OMAPL138_ETH_RX_BUFFER_COUNT 8
Sergunb 0:8918a71cdbe9 52 #elif (OMAPL138_ETH_RX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 53 #error OMAPL138_ETH_RX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 54 #endif
Sergunb 0:8918a71cdbe9 55
Sergunb 0:8918a71cdbe9 56 //RX buffer size
Sergunb 0:8918a71cdbe9 57 #ifndef OMAPL138_ETH_RX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 58 #define OMAPL138_ETH_RX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 59 #elif (OMAPL138_ETH_RX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 60 #error OMAPL138_ETH_RX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 61 #endif
Sergunb 0:8918a71cdbe9 62
Sergunb 0:8918a71cdbe9 63 //Channel number for the TX interrupt
Sergunb 0:8918a71cdbe9 64 #ifndef OMAPL138_ETH_TX_IRQ_CHANNEL
Sergunb 0:8918a71cdbe9 65 #define OMAPL138_ETH_TX_IRQ_CHANNEL 3
Sergunb 0:8918a71cdbe9 66 #elif (OMAPL138_ETH_TX_IRQ_CHANNEL < 0 || OMAPL138_ETH_TX_IRQ_CHANNEL > 31)
Sergunb 0:8918a71cdbe9 67 #error OMAPL138_ETH_TX_IRQ_CHANNEL parameter is not valid
Sergunb 0:8918a71cdbe9 68 #endif
Sergunb 0:8918a71cdbe9 69
Sergunb 0:8918a71cdbe9 70 //Channel number for the RX interrupt
Sergunb 0:8918a71cdbe9 71 #ifndef OMAPL138_ETH_RX_IRQ_CHANNEL
Sergunb 0:8918a71cdbe9 72 #define OMAPL138_ETH_RX_IRQ_CHANNEL 3
Sergunb 0:8918a71cdbe9 73 #elif (OMAPL138_ETH_RX_IRQ_CHANNEL < 0 || OMAPL138_ETH_RX_IRQ_CHANNEL > 31)
Sergunb 0:8918a71cdbe9 74 #error OMAPL138_ETH_RX_IRQ_CHANNEL parameter is not valid
Sergunb 0:8918a71cdbe9 75 #endif
Sergunb 0:8918a71cdbe9 76
Sergunb 0:8918a71cdbe9 77 //EMAC cores
Sergunb 0:8918a71cdbe9 78 #define EMAC_CORE0 0
Sergunb 0:8918a71cdbe9 79 #define EMAC_CORE1 1
Sergunb 0:8918a71cdbe9 80 #define EMAC_CORE2 2
Sergunb 0:8918a71cdbe9 81
Sergunb 0:8918a71cdbe9 82 //EMAC channels
Sergunb 0:8918a71cdbe9 83 #define EMAC_CH0 0
Sergunb 0:8918a71cdbe9 84 #define EMAC_CH1 1
Sergunb 0:8918a71cdbe9 85 #define EMAC_CH2 2
Sergunb 0:8918a71cdbe9 86 #define EMAC_CH3 3
Sergunb 0:8918a71cdbe9 87 #define EMAC_CH4 4
Sergunb 0:8918a71cdbe9 88 #define EMAC_CH5 5
Sergunb 0:8918a71cdbe9 89 #define EMAC_CH6 6
Sergunb 0:8918a71cdbe9 90 #define EMAC_CH7 7
Sergunb 0:8918a71cdbe9 91
Sergunb 0:8918a71cdbe9 92 //SYSCFG0 registers
Sergunb 0:8918a71cdbe9 93 #define SYSCFG0_PINMUX_R(n) HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_PINMUX(n))
Sergunb 0:8918a71cdbe9 94 #define SYSCFG0_CFGCHIP3_R HWREG(SOC_SYSCFG_0_REGS + SYSCFG0_CFGCHIP3)
Sergunb 0:8918a71cdbe9 95
Sergunb 0:8918a71cdbe9 96 //EMAC registers
Sergunb 0:8918a71cdbe9 97 #define EMAC_TXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXREVID)
Sergunb 0:8918a71cdbe9 98 #define EMAC_TXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCONTROL)
Sergunb 0:8918a71cdbe9 99 #define EMAC_TXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXTEARDOWN)
Sergunb 0:8918a71cdbe9 100 #define EMAC_RXREVID_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXREVID)
Sergunb 0:8918a71cdbe9 101 #define EMAC_RXCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCONTROL)
Sergunb 0:8918a71cdbe9 102 #define EMAC_RXTEARDOWN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXTEARDOWN)
Sergunb 0:8918a71cdbe9 103 #define EMAC_TXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATRAW)
Sergunb 0:8918a71cdbe9 104 #define EMAC_TXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTSTATMASKED)
Sergunb 0:8918a71cdbe9 105 #define EMAC_TXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKSET)
Sergunb 0:8918a71cdbe9 106 #define EMAC_TXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXINTMASKCLEAR)
Sergunb 0:8918a71cdbe9 107 #define EMAC_MACINVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINVECTOR)
Sergunb 0:8918a71cdbe9 108 #define EMAC_MACEOIVECTOR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACEOIVECTOR)
Sergunb 0:8918a71cdbe9 109 #define EMAC_RXINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATRAW)
Sergunb 0:8918a71cdbe9 110 #define EMAC_RXINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTSTATMASKED)
Sergunb 0:8918a71cdbe9 111 #define EMAC_RXINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKSET)
Sergunb 0:8918a71cdbe9 112 #define EMAC_RXINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXINTMASKCLEAR)
Sergunb 0:8918a71cdbe9 113 #define EMAC_MACINTSTATRAW_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATRAW)
Sergunb 0:8918a71cdbe9 114 #define EMAC_MACINTSTATMASKED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTSTATMASKED)
Sergunb 0:8918a71cdbe9 115 #define EMAC_MACINTMASKSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKSET)
Sergunb 0:8918a71cdbe9 116 #define EMAC_MACINTMASKCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINTMASKCLEAR)
Sergunb 0:8918a71cdbe9 117 #define EMAC_RXMBPENABLE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMBPENABLE)
Sergunb 0:8918a71cdbe9 118 #define EMAC_RXUNICASTSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTSET)
Sergunb 0:8918a71cdbe9 119 #define EMAC_RXUNICASTCLEAR_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNICASTCLEAR)
Sergunb 0:8918a71cdbe9 120 #define EMAC_RXMAXLEN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMAXLEN)
Sergunb 0:8918a71cdbe9 121 #define EMAC_RXBUFFEROFFSET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBUFFEROFFSET)
Sergunb 0:8918a71cdbe9 122 #define EMAC_RXFILTERLOWTHRESH_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERLOWTHRESH)
Sergunb 0:8918a71cdbe9 123 #define EMAC_RXFLOWTHRESH_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFLOWTHRESH(n))
Sergunb 0:8918a71cdbe9 124 #define EMAC_RXFREEBUFFER_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFREEBUFFER(n))
Sergunb 0:8918a71cdbe9 125 #define EMAC_MACCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONTROL)
Sergunb 0:8918a71cdbe9 126 #define EMAC_MACSTATUS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSTATUS)
Sergunb 0:8918a71cdbe9 127 #define EMAC_EMCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_EMCONTROL)
Sergunb 0:8918a71cdbe9 128 #define EMAC_FIFOCONTROL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FIFOCONTROL)
Sergunb 0:8918a71cdbe9 129 #define EMAC_MACCONFIG_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACCONFIG)
Sergunb 0:8918a71cdbe9 130 #define EMAC_SOFTRESET_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_SOFTRESET)
Sergunb 0:8918a71cdbe9 131 #define EMAC_MACSRCADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRLO)
Sergunb 0:8918a71cdbe9 132 #define EMAC_MACSRCADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACSRCADDRHI)
Sergunb 0:8918a71cdbe9 133 #define EMAC_MACHASH1_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH1)
Sergunb 0:8918a71cdbe9 134 #define EMAC_MACHASH2_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACHASH2)
Sergunb 0:8918a71cdbe9 135 #define EMAC_BOFFTEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_BOFFTEST)
Sergunb 0:8918a71cdbe9 136 #define EMAC_TPACETEST_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TPACETEST)
Sergunb 0:8918a71cdbe9 137 #define EMAC_RXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSE)
Sergunb 0:8918a71cdbe9 138 #define EMAC_TXPAUSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSE)
Sergunb 0:8918a71cdbe9 139 #define EMAC_RXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXGOODFRAMES)
Sergunb 0:8918a71cdbe9 140 #define EMAC_RXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXBCASTFRAMES)
Sergunb 0:8918a71cdbe9 141 #define EMAC_RXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMCASTFRAMES)
Sergunb 0:8918a71cdbe9 142 #define EMAC_RXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXPAUSEFRAMES)
Sergunb 0:8918a71cdbe9 143 #define EMAC_RXCRCERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCRCERRORS)
Sergunb 0:8918a71cdbe9 144 #define EMAC_RXALIGNCODEERRORS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMACEMAC_RXOVERSIZED)
Sergunb 0:8918a71cdbe9 145 #define EMAC_RXJABBER_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXJABBER)
Sergunb 0:8918a71cdbe9 146 #define EMAC_RXUNDERSIZED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXUNDERSIZED)
Sergunb 0:8918a71cdbe9 147 #define EMAC_RXFRAGMENTS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFRAGMENTS)
Sergunb 0:8918a71cdbe9 148 #define EMAC_RXFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXFILTERED)
Sergunb 0:8918a71cdbe9 149 #define EMAC_RXQOSFILTERED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXQOSFILTERED)
Sergunb 0:8918a71cdbe9 150 #define EMAC_RXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXOCTETS)
Sergunb 0:8918a71cdbe9 151 #define EMAC_TXGOODFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXGOODFRAMES)
Sergunb 0:8918a71cdbe9 152 #define EMAC_TXBCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXBCASTFRAMES)
Sergunb 0:8918a71cdbe9 153 #define EMAC_TXMCASTFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMCASTFRAMES)
Sergunb 0:8918a71cdbe9 154 #define EMAC_TXPAUSEFRAMES_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXPAUSEFRAMES)
Sergunb 0:8918a71cdbe9 155 #define EMAC_TXDEFERRED_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXDEFERRED)
Sergunb 0:8918a71cdbe9 156 #define EMAC_TXCOLLISION_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCOLLISION)
Sergunb 0:8918a71cdbe9 157 #define EMAC_TXSINGLECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXSINGLECOLL)
Sergunb 0:8918a71cdbe9 158 #define EMAC_TXMULTICOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXMULTICOLL)
Sergunb 0:8918a71cdbe9 159 #define EMAC_TXEXCESSIVECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXEXCESSIVECOLL)
Sergunb 0:8918a71cdbe9 160 #define EMAC_TXLATECOLL_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXLATECOLL)
Sergunb 0:8918a71cdbe9 161 #define EMAC_TXUNDERRUN_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXUNDERRUN)
Sergunb 0:8918a71cdbe9 162 #define EMAC_TXCARRIERSENSE_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCARRIERSENSE)
Sergunb 0:8918a71cdbe9 163 #define EMAC_TXOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXOCTETS)
Sergunb 0:8918a71cdbe9 164 #define EMAC_FRAME64_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME64)
Sergunb 0:8918a71cdbe9 165 #define EMAC_FRAME65T127_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME65T127)
Sergunb 0:8918a71cdbe9 166 #define EMAC_FRAME128T255_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME128T255)
Sergunb 0:8918a71cdbe9 167 #define EMAC_FRAME256T511_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME256T511)
Sergunb 0:8918a71cdbe9 168 #define EMAC_FRAME512T1023_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME512T1023)
Sergunb 0:8918a71cdbe9 169 #define EMAC_FRAME1024TUP_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_FRAME1024TUP)
Sergunb 0:8918a71cdbe9 170 #define EMAC_NETOCTETS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_NETOCTETS)
Sergunb 0:8918a71cdbe9 171 #define EMAC_RXSOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXSOFOVERRUNS)
Sergunb 0:8918a71cdbe9 172 #define EMAC_RXMOFOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXMOFOVERRUNS)
Sergunb 0:8918a71cdbe9 173 #define EMAC_RXDMAOVERRUNS_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXDMAOVERRUNS)
Sergunb 0:8918a71cdbe9 174 #define EMAC_MACADDRLO_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRLO)
Sergunb 0:8918a71cdbe9 175 #define EMAC_MACADDRHI_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACADDRHI)
Sergunb 0:8918a71cdbe9 176 #define EMAC_MACINDEX_R HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_MACINDEX)
Sergunb 0:8918a71cdbe9 177 #define EMAC_TXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXHDP(n))
Sergunb 0:8918a71cdbe9 178 #define EMAC_RXHDP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXHDP(n))
Sergunb 0:8918a71cdbe9 179 #define EMAC_TXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_TXCP(n))
Sergunb 0:8918a71cdbe9 180 #define EMAC_RXCP_R(n) HWREG(SOC_EMAC_DSC_CONTROL_REG + EMAC_RXCP(n))
Sergunb 0:8918a71cdbe9 181
Sergunb 0:8918a71cdbe9 182 //EMAC control registers
Sergunb 0:8918a71cdbe9 183 #define EMAC_CTRL_REVID_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_REVID)
Sergunb 0:8918a71cdbe9 184 #define EMAC_CTRL_SOFTRESET_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_SOFTRESET)
Sergunb 0:8918a71cdbe9 185 #define EMAC_CTRL_INTCONTRO_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_INTCONTROL)
Sergunb 0:8918a71cdbe9 186 #define EMAC_CTRL_C0RXTHRESHEN_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHEN)
Sergunb 0:8918a71cdbe9 187 #define EMAC_CTRL_CnRXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXEN(n))
Sergunb 0:8918a71cdbe9 188 #define EMAC_CTRL_CnTXEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnTXEN(n))
Sergunb 0:8918a71cdbe9 189 #define EMAC_CTRL_CnMISCEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnMISCEN(n))
Sergunb 0:8918a71cdbe9 190 #define EMAC_CTRL_CnRXTHRESHEN_R(n) HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_CnRXTHRESHEN(n))
Sergunb 0:8918a71cdbe9 191 #define EMAC_CTRL_C0RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXTHRESHSTAT)
Sergunb 0:8918a71cdbe9 192 #define EMAC_CTRL_C0RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXSTAT)
Sergunb 0:8918a71cdbe9 193 #define EMAC_CTRL_C0TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXSTAT)
Sergunb 0:8918a71cdbe9 194 #define EMAC_CTRL_C0MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0MISCSTAT)
Sergunb 0:8918a71cdbe9 195 #define EMAC_CTRL_C1RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT)
Sergunb 0:8918a71cdbe9 196 #define EMAC_CTRL_C1RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXTHRESHSTAT)
Sergunb 0:8918a71cdbe9 197 #define EMAC_CTRL_C1TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXSTAT)
Sergunb 0:8918a71cdbe9 198 #define EMAC_CTRL_C1MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1MISCSTAT)
Sergunb 0:8918a71cdbe9 199 #define EMAC_CTRL_C2RXTHRESHSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXTHRESHSTAT)
Sergunb 0:8918a71cdbe9 200 #define EMAC_CTRL_C2RXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXSTAT)
Sergunb 0:8918a71cdbe9 201 #define EMAC_CTRL_C2TXSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXSTAT)
Sergunb 0:8918a71cdbe9 202 #define EMAC_CTRL_C2MISCSTAT_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2MISCSTAT)
Sergunb 0:8918a71cdbe9 203 #define EMAC_CTRL_C0RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0RXIMAX)
Sergunb 0:8918a71cdbe9 204 #define EMAC_CTRL_C0TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C0TXIMAX)
Sergunb 0:8918a71cdbe9 205 #define EMAC_CTRL_C1RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1RXIMAX)
Sergunb 0:8918a71cdbe9 206 #define EMAC_CTRL_C1TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C1TXIMAX)
Sergunb 0:8918a71cdbe9 207 #define EMAC_CTRL_C2RXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2RXIMAX)
Sergunb 0:8918a71cdbe9 208 #define EMAC_CTRL_C2TXIMAX_R HWREG(SOC_EMAC_DSC_CTRL_MOD_REG + EMAC_CTRL_C2TXIMAX)
Sergunb 0:8918a71cdbe9 209
Sergunb 0:8918a71cdbe9 210 //MDIO registers
Sergunb 0:8918a71cdbe9 211 #define MDIO_REVID_R HWREG(SOC_MDIO_0_REGS + MDIO_REVID)
Sergunb 0:8918a71cdbe9 212 #define MDIO_CONTROL_R HWREG(SOC_MDIO_0_REGS + MDIO_CONTROL)
Sergunb 0:8918a71cdbe9 213 #define MDIO_ALIVE_R HWREG(SOC_MDIO_0_REGS + MDIO_ALIVE)
Sergunb 0:8918a71cdbe9 214 #define MDIO_LINK_R HWREG(SOC_MDIO_0_REGS + MDIO_LINK)
Sergunb 0:8918a71cdbe9 215 #define MDIO_LINKINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTRAW)
Sergunb 0:8918a71cdbe9 216 #define MDIO_LINKINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_LINKINTMASKED)
Sergunb 0:8918a71cdbe9 217 #define MDIO_USERINTRAW_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTRAW)
Sergunb 0:8918a71cdbe9 218 #define MDIO_USERINTMASKED_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKED)
Sergunb 0:8918a71cdbe9 219 #define MDIO_USERINTMASKSET_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKSET)
Sergunb 0:8918a71cdbe9 220 #define MDIO_USERINTMASKCLEAR_R HWREG(SOC_MDIO_0_REGS + MDIO_USERINTMASKCLEAR)
Sergunb 0:8918a71cdbe9 221 #define MDIO_USERACCESS0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS0)
Sergunb 0:8918a71cdbe9 222 #define MDIO_USERPHYSEL0_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL0)
Sergunb 0:8918a71cdbe9 223 #define MDIO_USERACCESS1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERACCESS1)
Sergunb 0:8918a71cdbe9 224 #define MDIO_USERPHYSEL1_R HWREG(SOC_MDIO_0_REGS + MDIO_USERPHYSEL1)
Sergunb 0:8918a71cdbe9 225
Sergunb 0:8918a71cdbe9 226 //MACEOIVECTOR register
Sergunb 0:8918a71cdbe9 227 #define EMAC_MACEOIVECTOR_C0RXTHRESH 0x00000000
Sergunb 0:8918a71cdbe9 228 #define EMAC_MACEOIVECTOR_C0RX 0x00000001
Sergunb 0:8918a71cdbe9 229 #define EMAC_MACEOIVECTOR_C0TX 0x00000002
Sergunb 0:8918a71cdbe9 230 #define EMAC_MACEOIVECTOR_C0MISC 0x00000003
Sergunb 0:8918a71cdbe9 231 #define EMAC_MACEOIVECTOR_C1RXTHRESH 0x00000004
Sergunb 0:8918a71cdbe9 232 #define EMAC_MACEOIVECTOR_C1RX 0x00000005
Sergunb 0:8918a71cdbe9 233 #define EMAC_MACEOIVECTOR_C1TX 0x00000006
Sergunb 0:8918a71cdbe9 234 #define EMAC_MACEOIVECTOR_C1MISC 0x00000007
Sergunb 0:8918a71cdbe9 235 #define EMAC_MACEOIVECTOR_C2RXTHRESH 0x00000008
Sergunb 0:8918a71cdbe9 236 #define EMAC_MACEOIVECTOR_C2RX 0x00000009
Sergunb 0:8918a71cdbe9 237 #define EMAC_MACEOIVECTOR_C2TX 0x0000000A
Sergunb 0:8918a71cdbe9 238 #define EMAC_MACEOIVECTOR_C2MISC 0x0000000B
Sergunb 0:8918a71cdbe9 239
Sergunb 0:8918a71cdbe9 240 //TX buffer descriptor flags
Sergunb 0:8918a71cdbe9 241 #define EMAC_TX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 242 #define EMAC_TX_WORD1_BUFFER_POINTER 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 243 #define EMAC_TX_WORD2_BUFFER_OFFSET 0xFFFF0000
Sergunb 0:8918a71cdbe9 244 #define EMAC_TX_WORD2_BUFFER_LENGTH 0x0000FFFF
Sergunb 0:8918a71cdbe9 245 #define EMAC_TX_WORD3_SOP 0x80000000
Sergunb 0:8918a71cdbe9 246 #define EMAC_TX_WORD3_EOP 0x40000000
Sergunb 0:8918a71cdbe9 247 #define EMAC_TX_WORD3_OWNER 0x20000000
Sergunb 0:8918a71cdbe9 248 #define EMAC_TX_WORD3_EOQ 0x10000000
Sergunb 0:8918a71cdbe9 249 #define EMAC_TX_WORD3_TDOWNCMPLT 0x08000000
Sergunb 0:8918a71cdbe9 250 #define EMAC_TX_WORD3_PASSCRC 0x04000000
Sergunb 0:8918a71cdbe9 251 #define EMAC_TX_WORD3_PACKET_LENGTH 0x0000FFFF
Sergunb 0:8918a71cdbe9 252
Sergunb 0:8918a71cdbe9 253 //RX buffer descriptor flags
Sergunb 0:8918a71cdbe9 254 #define EMAC_RX_WORD0_NEXT_DESC_POINTER 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 255 #define EMAC_RX_WORD1_BUFFER_POINTER 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 256 #define EMAC_RX_WORD2_BUFFER_OFFSET 0x07FF0000
Sergunb 0:8918a71cdbe9 257 #define EMAC_RX_WORD2_BUFFER_LENGTH 0x000007FF
Sergunb 0:8918a71cdbe9 258 #define EMAC_RX_WORD3_SOP 0x80000000
Sergunb 0:8918a71cdbe9 259 #define EMAC_RX_WORD3_EOP 0x40000000
Sergunb 0:8918a71cdbe9 260 #define EMAC_RX_WORD3_OWNER 0x20000000
Sergunb 0:8918a71cdbe9 261 #define EMAC_RX_WORD3_EOQ 0x10000000
Sergunb 0:8918a71cdbe9 262 #define EMAC_RX_WORD3_TDOWNCMPLT 0x08000000
Sergunb 0:8918a71cdbe9 263 #define EMAC_RX_WORD3_PASSCRC 0x04000000
Sergunb 0:8918a71cdbe9 264 #define EMAC_RX_WORD3_ERROR_MASK 0x03FF0000
Sergunb 0:8918a71cdbe9 265 #define EMAC_RX_WORD3_JABBER 0x02000000
Sergunb 0:8918a71cdbe9 266 #define EMAC_RX_WORD3_OVERSIZE 0x01000000
Sergunb 0:8918a71cdbe9 267 #define EMAC_RX_WORD3_FRAGMENT 0x00800000
Sergunb 0:8918a71cdbe9 268 #define EMAC_RX_WORD3_UNDERSIZED 0x00400000
Sergunb 0:8918a71cdbe9 269 #define EMAC_RX_WORD3_CONTROL 0x00200000
Sergunb 0:8918a71cdbe9 270 #define EMAC_RX_WORD3_OVERRUN 0x00100000
Sergunb 0:8918a71cdbe9 271 #define EMAC_RX_WORD3_CODEERROR 0x00080000
Sergunb 0:8918a71cdbe9 272 #define EMAC_RX_WORD3_ALIGNERROR 0x00040000
Sergunb 0:8918a71cdbe9 273 #define EMAC_RX_WORD3_CRCERROR 0x00020000
Sergunb 0:8918a71cdbe9 274 #define EMAC_RX_WORD3_NOMATCH 0x00010000
Sergunb 0:8918a71cdbe9 275 #define EMAC_RX_WORD3_PACKET_LENGTH 0x0000FFFF
Sergunb 0:8918a71cdbe9 276
Sergunb 0:8918a71cdbe9 277
Sergunb 0:8918a71cdbe9 278 /**
Sergunb 0:8918a71cdbe9 279 * @brief TX buffer descriptor
Sergunb 0:8918a71cdbe9 280 **/
Sergunb 0:8918a71cdbe9 281
Sergunb 0:8918a71cdbe9 282 typedef struct _Omapl138TxBufferDesc
Sergunb 0:8918a71cdbe9 283 {
Sergunb 0:8918a71cdbe9 284 uint32_t word0;
Sergunb 0:8918a71cdbe9 285 uint32_t word1;
Sergunb 0:8918a71cdbe9 286 uint32_t word2;
Sergunb 0:8918a71cdbe9 287 uint32_t word3;
Sergunb 0:8918a71cdbe9 288 struct _Omapl138TxBufferDesc *next;
Sergunb 0:8918a71cdbe9 289 struct _Omapl138TxBufferDesc *prev;
Sergunb 0:8918a71cdbe9 290 } Omapl138TxBufferDesc;
Sergunb 0:8918a71cdbe9 291
Sergunb 0:8918a71cdbe9 292
Sergunb 0:8918a71cdbe9 293 /**
Sergunb 0:8918a71cdbe9 294 * @brief RX buffer descriptor
Sergunb 0:8918a71cdbe9 295 **/
Sergunb 0:8918a71cdbe9 296
Sergunb 0:8918a71cdbe9 297 typedef struct _Omapl138RxBufferDesc
Sergunb 0:8918a71cdbe9 298 {
Sergunb 0:8918a71cdbe9 299 uint32_t word0;
Sergunb 0:8918a71cdbe9 300 uint32_t word1;
Sergunb 0:8918a71cdbe9 301 uint32_t word2;
Sergunb 0:8918a71cdbe9 302 uint32_t word3;
Sergunb 0:8918a71cdbe9 303 struct _Omapl138RxBufferDesc *next;
Sergunb 0:8918a71cdbe9 304 struct _Omapl138RxBufferDesc *prev;
Sergunb 0:8918a71cdbe9 305 } Omapl138RxBufferDesc;
Sergunb 0:8918a71cdbe9 306
Sergunb 0:8918a71cdbe9 307
Sergunb 0:8918a71cdbe9 308 //AM335x Ethernet MAC driver
Sergunb 0:8918a71cdbe9 309 extern const NicDriver omapl138EthDriver;
Sergunb 0:8918a71cdbe9 310
Sergunb 0:8918a71cdbe9 311 //AM335x Ethernet MAC related functions
Sergunb 0:8918a71cdbe9 312 error_t omapl138EthInit(NetInterface *interface);
Sergunb 0:8918a71cdbe9 313 void omapl138EthInitGpio(NetInterface *interface);
Sergunb 0:8918a71cdbe9 314 void omapl138EthInitBufferDesc(NetInterface *interface);
Sergunb 0:8918a71cdbe9 315
Sergunb 0:8918a71cdbe9 316 void omapl138EthTick(NetInterface *interface);
Sergunb 0:8918a71cdbe9 317
Sergunb 0:8918a71cdbe9 318 void omapl138EthEnableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 319 void omapl138EthDisableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 320 void omapl138EthTxIrqHandler(void);
Sergunb 0:8918a71cdbe9 321 void omapl138EthRxIrqHandler(void);
Sergunb 0:8918a71cdbe9 322 void omapl138EthEventHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 323
Sergunb 0:8918a71cdbe9 324 error_t omapl138EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 325 const NetBuffer *buffer, size_t offset);
Sergunb 0:8918a71cdbe9 326
Sergunb 0:8918a71cdbe9 327 error_t omapl138EthReceivePacket(NetInterface *interface);
Sergunb 0:8918a71cdbe9 328
Sergunb 0:8918a71cdbe9 329 error_t omapl138EthSetMulticastFilter(NetInterface *interface);
Sergunb 0:8918a71cdbe9 330 error_t omapl138EthUpdateMacConfig(NetInterface *interface);
Sergunb 0:8918a71cdbe9 331
Sergunb 0:8918a71cdbe9 332 void omapl138EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
Sergunb 0:8918a71cdbe9 333 uint16_t omapl138EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
Sergunb 0:8918a71cdbe9 334
Sergunb 0:8918a71cdbe9 335 #endif
Sergunb 0:8918a71cdbe9 336