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cyclone_tcp/drivers/lpc18xx_eth.h@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file lpc18xx_eth.h
Sergunb 0:8918a71cdbe9 3 * @brief LPC1800 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 #ifndef _LPC18XX_ETH_H
Sergunb 0:8918a71cdbe9 30 #define _LPC18XX_ETH_H
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "core/nic.h"
Sergunb 0:8918a71cdbe9 34
Sergunb 0:8918a71cdbe9 35 //Number of TX buffers
Sergunb 0:8918a71cdbe9 36 #ifndef LPC18XX_ETH_TX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 37 #define LPC18XX_ETH_TX_BUFFER_COUNT 3
Sergunb 0:8918a71cdbe9 38 #elif (LPC18XX_ETH_TX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 39 #error LPC18XX_ETH_TX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 40 #endif
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //TX buffer size
Sergunb 0:8918a71cdbe9 43 #ifndef LPC18XX_ETH_TX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 44 #define LPC18XX_ETH_TX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 45 #elif (LPC18XX_ETH_TX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 46 #error LPC18XX_ETH_TX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 47 #endif
Sergunb 0:8918a71cdbe9 48
Sergunb 0:8918a71cdbe9 49 //Number of RX buffers
Sergunb 0:8918a71cdbe9 50 #ifndef LPC18XX_ETH_RX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 51 #define LPC18XX_ETH_RX_BUFFER_COUNT 6
Sergunb 0:8918a71cdbe9 52 #elif (LPC18XX_ETH_RX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 53 #error LPC18XX_ETH_RX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 54 #endif
Sergunb 0:8918a71cdbe9 55
Sergunb 0:8918a71cdbe9 56 //RX buffer size
Sergunb 0:8918a71cdbe9 57 #ifndef LPC18XX_ETH_RX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 58 #define LPC18XX_ETH_RX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 59 #elif (LPC18XX_ETH_RX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 60 #error LPC18XX_ETH_RX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 61 #endif
Sergunb 0:8918a71cdbe9 62
Sergunb 0:8918a71cdbe9 63 //Interrupt priority grouping
Sergunb 0:8918a71cdbe9 64 #ifndef LPC18XX_ETH_IRQ_PRIORITY_GROUPING
Sergunb 0:8918a71cdbe9 65 #define LPC18XX_ETH_IRQ_PRIORITY_GROUPING 4
Sergunb 0:8918a71cdbe9 66 #elif (LPC18XX_ETH_IRQ_PRIORITY_GROUPING < 0)
Sergunb 0:8918a71cdbe9 67 #error LPC18XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid
Sergunb 0:8918a71cdbe9 68 #endif
Sergunb 0:8918a71cdbe9 69
Sergunb 0:8918a71cdbe9 70 //Ethernet interrupt group priority
Sergunb 0:8918a71cdbe9 71 #ifndef LPC18XX_ETH_IRQ_GROUP_PRIORITY
Sergunb 0:8918a71cdbe9 72 #define LPC18XX_ETH_IRQ_GROUP_PRIORITY 6
Sergunb 0:8918a71cdbe9 73 #elif (LPC18XX_ETH_IRQ_GROUP_PRIORITY < 0)
Sergunb 0:8918a71cdbe9 74 #error LPC18XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid
Sergunb 0:8918a71cdbe9 75 #endif
Sergunb 0:8918a71cdbe9 76
Sergunb 0:8918a71cdbe9 77 //Ethernet interrupt subpriority
Sergunb 0:8918a71cdbe9 78 #ifndef LPC18XX_ETH_IRQ_SUB_PRIORITY
Sergunb 0:8918a71cdbe9 79 #define LPC18XX_ETH_IRQ_SUB_PRIORITY 0
Sergunb 0:8918a71cdbe9 80 #elif (LPC18XX_ETH_IRQ_SUB_PRIORITY < 0)
Sergunb 0:8918a71cdbe9 81 #error LPC18XX_ETH_IRQ_SUB_PRIORITY parameter is not valid
Sergunb 0:8918a71cdbe9 82 #endif
Sergunb 0:8918a71cdbe9 83
Sergunb 0:8918a71cdbe9 84 //CREG6 register
Sergunb 0:8918a71cdbe9 85 #define CREG6_ETHMODE_MII (0 << CREG_CREG6_ETHMODE_Pos)
Sergunb 0:8918a71cdbe9 86 #define CREG6_ETHMODE_RMII (4 << CREG_CREG6_ETHMODE_Pos)
Sergunb 0:8918a71cdbe9 87
Sergunb 0:8918a71cdbe9 88 //MAC_MII_ADDR register
Sergunb 0:8918a71cdbe9 89 #define ETHERNET_MAC_MII_ADDR_CR_DIV42 (0 << ETHERNET_MAC_MII_ADDR_CR_Pos)
Sergunb 0:8918a71cdbe9 90 #define ETHERNET_MAC_MII_ADDR_CR_DIV62 (1 << ETHERNET_MAC_MII_ADDR_CR_Pos)
Sergunb 0:8918a71cdbe9 91 #define ETHERNET_MAC_MII_ADDR_CR_DIV16 (2 << ETHERNET_MAC_MII_ADDR_CR_Pos)
Sergunb 0:8918a71cdbe9 92 #define ETHERNET_MAC_MII_ADDR_CR_DIV26 (3 << ETHERNET_MAC_MII_ADDR_CR_Pos)
Sergunb 0:8918a71cdbe9 93 #define ETHERNET_MAC_MII_ADDR_CR_DIV102 (4 << ETHERNET_MAC_MII_ADDR_CR_Pos)
Sergunb 0:8918a71cdbe9 94 #define ETHERNET_MAC_MII_ADDR_CR_DIV124 (5 << ETHERNET_MAC_MII_ADDR_CR_Pos)
Sergunb 0:8918a71cdbe9 95
Sergunb 0:8918a71cdbe9 96 //DMA_BUS_MODE register
Sergunb 0:8918a71cdbe9 97 #define ETHERNET_DMA_BUS_MODE_RPBL_1 (1 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 98 #define ETHERNET_DMA_BUS_MODE_RPBL_2 (2 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 99 #define ETHERNET_DMA_BUS_MODE_RPBL_4 (4 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 100 #define ETHERNET_DMA_BUS_MODE_RPBL_8 (8 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 101 #define ETHERNET_DMA_BUS_MODE_RPBL_16 (16 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 102 #define ETHERNET_DMA_BUS_MODE_RPBL_32 (32 << ETHERNET_DMA_BUS_MODE_RPBL_Pos)
Sergunb 0:8918a71cdbe9 103
Sergunb 0:8918a71cdbe9 104 #define ETHERNET_DMA_BUS_MODE_PR_1_1 (0 << ETHERNET_DMA_BUS_MODE_PR_Pos)
Sergunb 0:8918a71cdbe9 105 #define ETHERNET_DMA_BUS_MODE_PR_2_1 (1 << ETHERNET_DMA_BUS_MODE_PR_Pos)
Sergunb 0:8918a71cdbe9 106 #define ETHERNET_DMA_BUS_MODE_PR_3_1 (2 << ETHERNET_DMA_BUS_MODE_PR_Pos)
Sergunb 0:8918a71cdbe9 107 #define ETHERNET_DMA_BUS_MODE_PR_4_1 (3 << ETHERNET_DMA_BUS_MODE_PR_Pos)
Sergunb 0:8918a71cdbe9 108
Sergunb 0:8918a71cdbe9 109 #define ETHERNET_DMA_BUS_MODE_PBL_1 (1 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 110 #define ETHERNET_DMA_BUS_MODE_PBL_2 (2 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 111 #define ETHERNET_DMA_BUS_MODE_PBL_4 (4 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 112 #define ETHERNET_DMA_BUS_MODE_PBL_8 (8 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 113 #define ETHERNET_DMA_BUS_MODE_PBL_16 (16 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 114 #define ETHERNET_DMA_BUS_MODE_PBL_32 (32 << ETHERNET_DMA_BUS_MODE_PBL_Pos)
Sergunb 0:8918a71cdbe9 115
Sergunb 0:8918a71cdbe9 116 //DMA_OP_MODE register
Sergunb 0:8918a71cdbe9 117 #define ETHERNET_DMA_OP_MODE_TTC_64 (0 << ETHERNET_DMA_OP_MODE_TTC_Pos)
Sergunb 0:8918a71cdbe9 118 #define ETHERNET_DMA_OP_MODE_TTC_128 (1 << ETHERNET_DMA_OP_MODE_TTC_Pos)
Sergunb 0:8918a71cdbe9 119 #define ETHERNET_DMA_OP_MODE_TTC_192 (2 << ETHERNET_DMA_OP_MODE_TTC_Pos)
Sergunb 0:8918a71cdbe9 120 #define ETHERNET_DMA_OP_MODE_TTC_256 (3 << ETHERNET_DMA_OP_MODE_TTC_Pos)
Sergunb 0:8918a71cdbe9 121 #define ETHERNET_DMA_OP_MODE_TTC_40 (4 << ETHERNET_DMA_OP_MODE_TTC_Pos)
Sergunb 0:8918a71cdbe9 122 #define ETHERNET_DMA_OP_MODE_TTC_32 (5 << ETHERNET_DMA_OP_MODE_TTC_Pos)
Sergunb 0:8918a71cdbe9 123 #define ETHERNET_DMA_OP_MODE_TTC_24 (6 << ETHERNET_DMA_OP_MODE_TTC_Pos)
Sergunb 0:8918a71cdbe9 124 #define ETHERNET_DMA_OP_MODE_TTC_16 (7 << ETHERNET_DMA_OP_MODE_TTC_Pos)
Sergunb 0:8918a71cdbe9 125
Sergunb 0:8918a71cdbe9 126 #define ETHERNET_DMA_OP_MODE_RTC_64 (0 << ETHERNET_DMA_OP_MODE_RTC_Pos)
Sergunb 0:8918a71cdbe9 127 #define ETHERNET_DMA_OP_MODE_RTC_32 (1 << ETHERNET_DMA_OP_MODE_RTC_Pos)
Sergunb 0:8918a71cdbe9 128 #define ETHERNET_DMA_OP_MODE_RTC_96 (2 << ETHERNET_DMA_OP_MODE_RTC_Pos)
Sergunb 0:8918a71cdbe9 129 #define ETHERNET_DMA_OP_MODE_RTC_128 (3 << ETHERNET_DMA_OP_MODE_RTC_Pos)
Sergunb 0:8918a71cdbe9 130
Sergunb 0:8918a71cdbe9 131 //Transmit DMA descriptor flags
Sergunb 0:8918a71cdbe9 132 #define ETH_TDES0_OWN 0x80000000
Sergunb 0:8918a71cdbe9 133 #define ETH_TDES0_IC 0x40000000
Sergunb 0:8918a71cdbe9 134 #define ETH_TDES0_LS 0x20000000
Sergunb 0:8918a71cdbe9 135 #define ETH_TDES0_FS 0x10000000
Sergunb 0:8918a71cdbe9 136 #define ETH_TDES0_DC 0x08000000
Sergunb 0:8918a71cdbe9 137 #define ETH_TDES0_DP 0x04000000
Sergunb 0:8918a71cdbe9 138 #define ETH_TDES0_TTSE 0x02000000
Sergunb 0:8918a71cdbe9 139 #define ETH_TDES0_TER 0x00200000
Sergunb 0:8918a71cdbe9 140 #define ETH_TDES0_TCH 0x00100000
Sergunb 0:8918a71cdbe9 141 #define ETH_TDES0_TTSS 0x00020000
Sergunb 0:8918a71cdbe9 142 #define ETH_TDES0_IHE 0x00010000
Sergunb 0:8918a71cdbe9 143 #define ETH_TDES0_ES 0x00008000
Sergunb 0:8918a71cdbe9 144 #define ETH_TDES0_JT 0x00004000
Sergunb 0:8918a71cdbe9 145 #define ETH_TDES0_FF 0x00002000
Sergunb 0:8918a71cdbe9 146 #define ETH_TDES0_IPE 0x00001000
Sergunb 0:8918a71cdbe9 147 #define ETH_TDES0_LCA 0x00000800
Sergunb 0:8918a71cdbe9 148 #define ETH_TDES0_NC 0x00000400
Sergunb 0:8918a71cdbe9 149 #define ETH_TDES0_LCO 0x00000200
Sergunb 0:8918a71cdbe9 150 #define ETH_TDES0_EC 0x00000100
Sergunb 0:8918a71cdbe9 151 #define ETH_TDES0_VF 0x00000080
Sergunb 0:8918a71cdbe9 152 #define ETH_TDES0_CC 0x00000078
Sergunb 0:8918a71cdbe9 153 #define ETH_TDES0_ED 0x00000004
Sergunb 0:8918a71cdbe9 154 #define ETH_TDES0_UF 0x00000002
Sergunb 0:8918a71cdbe9 155 #define ETH_TDES0_DB 0x00000001
Sergunb 0:8918a71cdbe9 156 #define ETH_TDES1_TBS2 0x1FFF0000
Sergunb 0:8918a71cdbe9 157 #define ETH_TDES1_TBS1 0x00001FFF
Sergunb 0:8918a71cdbe9 158 #define ETH_TDES2_B1ADD 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 159 #define ETH_TDES3_B2ADD 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 160 #define ETH_TDES6_TTSL 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 161 #define ETH_TDES7_TTSH 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 162
Sergunb 0:8918a71cdbe9 163 //Receive DMA descriptor flags
Sergunb 0:8918a71cdbe9 164 #define ETH_RDES0_OWN 0x80000000
Sergunb 0:8918a71cdbe9 165 #define ETH_RDES0_AFM 0x40000000
Sergunb 0:8918a71cdbe9 166 #define ETH_RDES0_FL 0x3FFF0000
Sergunb 0:8918a71cdbe9 167 #define ETH_RDES0_ES 0x00008000
Sergunb 0:8918a71cdbe9 168 #define ETH_RDES0_DE 0x00004000
Sergunb 0:8918a71cdbe9 169 #define ETH_RDES0_SAF 0x00002000
Sergunb 0:8918a71cdbe9 170 #define ETH_RDES0_LE 0x00001000
Sergunb 0:8918a71cdbe9 171 #define ETH_RDES0_OE 0x00000800
Sergunb 0:8918a71cdbe9 172 #define ETH_RDES0_VLAN 0x00000400
Sergunb 0:8918a71cdbe9 173 #define ETH_RDES0_FS 0x00000200
Sergunb 0:8918a71cdbe9 174 #define ETH_RDES0_LS 0x00000100
Sergunb 0:8918a71cdbe9 175 #define ETH_RDES0_TSA 0x00000080
Sergunb 0:8918a71cdbe9 176 #define ETH_RDES0_LCO 0x00000040
Sergunb 0:8918a71cdbe9 177 #define ETH_RDES0_FT 0x00000020
Sergunb 0:8918a71cdbe9 178 #define ETH_RDES0_RWT 0x00000010
Sergunb 0:8918a71cdbe9 179 #define ETH_RDES0_RE 0x00000008
Sergunb 0:8918a71cdbe9 180 #define ETH_RDES0_DBE 0x00000004
Sergunb 0:8918a71cdbe9 181 #define ETH_RDES0_CE 0x00000002
Sergunb 0:8918a71cdbe9 182 #define ETH_RDES0_ESA 0x00000001
Sergunb 0:8918a71cdbe9 183 #define ETH_RDES1_RBS2 0x1FFF0000
Sergunb 0:8918a71cdbe9 184 #define ETH_RDES1_RER 0x00008000
Sergunb 0:8918a71cdbe9 185 #define ETH_RDES1_RCH 0x00004000
Sergunb 0:8918a71cdbe9 186 #define ETH_RDES1_RBS1 0x00001FFF
Sergunb 0:8918a71cdbe9 187 #define ETH_RDES2_B1ADD 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 188 #define ETH_RDES3_B2ADD 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 189 #define ETH_RDES4_PTPVERSION 0x00002000
Sergunb 0:8918a71cdbe9 190 #define ETH_RDES4_PTPTYPE 0x00001000
Sergunb 0:8918a71cdbe9 191 #define ETH_RDES4_MT 0x00000F00
Sergunb 0:8918a71cdbe9 192 #define ETH_RDES4_IPV6 0x00000080
Sergunb 0:8918a71cdbe9 193 #define ETH_RDES4_IPV4 0x00000040
Sergunb 0:8918a71cdbe9 194 #define ETH_RDES6_RTSL 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 195 #define ETH_RDES7_RTSH 0xFFFFFFFF
Sergunb 0:8918a71cdbe9 196
Sergunb 0:8918a71cdbe9 197
Sergunb 0:8918a71cdbe9 198 /**
Sergunb 0:8918a71cdbe9 199 * @brief Enhanced TX DMA descriptor
Sergunb 0:8918a71cdbe9 200 **/
Sergunb 0:8918a71cdbe9 201
Sergunb 0:8918a71cdbe9 202 typedef struct
Sergunb 0:8918a71cdbe9 203 {
Sergunb 0:8918a71cdbe9 204 uint32_t tdes0;
Sergunb 0:8918a71cdbe9 205 uint32_t tdes1;
Sergunb 0:8918a71cdbe9 206 uint32_t tdes2;
Sergunb 0:8918a71cdbe9 207 uint32_t tdes3;
Sergunb 0:8918a71cdbe9 208 uint32_t tdes4;
Sergunb 0:8918a71cdbe9 209 uint32_t tdes5;
Sergunb 0:8918a71cdbe9 210 uint32_t tdes6;
Sergunb 0:8918a71cdbe9 211 uint32_t tdes7;
Sergunb 0:8918a71cdbe9 212 } Lpc18xxTxDmaDesc;
Sergunb 0:8918a71cdbe9 213
Sergunb 0:8918a71cdbe9 214
Sergunb 0:8918a71cdbe9 215 /**
Sergunb 0:8918a71cdbe9 216 * @brief Enhanced RX DMA descriptor
Sergunb 0:8918a71cdbe9 217 **/
Sergunb 0:8918a71cdbe9 218
Sergunb 0:8918a71cdbe9 219 typedef struct
Sergunb 0:8918a71cdbe9 220 {
Sergunb 0:8918a71cdbe9 221 uint32_t rdes0;
Sergunb 0:8918a71cdbe9 222 uint32_t rdes1;
Sergunb 0:8918a71cdbe9 223 uint32_t rdes2;
Sergunb 0:8918a71cdbe9 224 uint32_t rdes3;
Sergunb 0:8918a71cdbe9 225 uint32_t rdes4;
Sergunb 0:8918a71cdbe9 226 uint32_t rdes5;
Sergunb 0:8918a71cdbe9 227 uint32_t rdes6;
Sergunb 0:8918a71cdbe9 228 uint32_t rdes7;
Sergunb 0:8918a71cdbe9 229 } Lpc18xxRxDmaDesc;
Sergunb 0:8918a71cdbe9 230
Sergunb 0:8918a71cdbe9 231
Sergunb 0:8918a71cdbe9 232 //LPC18xx Ethernet MAC driver
Sergunb 0:8918a71cdbe9 233 extern const NicDriver lpc18xxEthDriver;
Sergunb 0:8918a71cdbe9 234
Sergunb 0:8918a71cdbe9 235 //LPC18xx Ethernet MAC related functions
Sergunb 0:8918a71cdbe9 236 error_t lpc18xxEthInit(NetInterface *interface);
Sergunb 0:8918a71cdbe9 237 void lpc18xxEthInitGpio(NetInterface *interface);
Sergunb 0:8918a71cdbe9 238 void lpc18xxEthInitDmaDesc(NetInterface *interface);
Sergunb 0:8918a71cdbe9 239
Sergunb 0:8918a71cdbe9 240 void lpc18xxEthTick(NetInterface *interface);
Sergunb 0:8918a71cdbe9 241
Sergunb 0:8918a71cdbe9 242 void lpc18xxEthEnableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 243 void lpc18xxEthDisableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 244 void lpc18xxEthEventHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 245
Sergunb 0:8918a71cdbe9 246 error_t lpc18xxEthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 247 const NetBuffer *buffer, size_t offset);
Sergunb 0:8918a71cdbe9 248
Sergunb 0:8918a71cdbe9 249 error_t lpc18xxEthReceivePacket(NetInterface *interface);
Sergunb 0:8918a71cdbe9 250
Sergunb 0:8918a71cdbe9 251 error_t lpc18xxEthSetMulticastFilter(NetInterface *interface);
Sergunb 0:8918a71cdbe9 252 error_t lpc18xxEthUpdateMacConfig(NetInterface *interface);
Sergunb 0:8918a71cdbe9 253
Sergunb 0:8918a71cdbe9 254 void lpc18xxEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
Sergunb 0:8918a71cdbe9 255 uint16_t lpc18xxEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
Sergunb 0:8918a71cdbe9 256
Sergunb 0:8918a71cdbe9 257 uint32_t lpc18xxEthCalcCrc(const void *data, size_t length);
Sergunb 0:8918a71cdbe9 258
Sergunb 0:8918a71cdbe9 259 #endif
Sergunb 0:8918a71cdbe9 260