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Dependents:   Nucleo

cyclone_tcp/drivers/f28m35x_eth.c@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file f28m35x_eth.c
Sergunb 0:8918a71cdbe9 3 * @brief F28M35x Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 //Switch to the appropriate trace level
Sergunb 0:8918a71cdbe9 30 #define TRACE_LEVEL NIC_TRACE_LEVEL
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "inc/hw_ethernet.h"
Sergunb 0:8918a71cdbe9 34 #include "inc/hw_ints.h"
Sergunb 0:8918a71cdbe9 35 #include "inc/hw_memmap.h"
Sergunb 0:8918a71cdbe9 36 #include "inc/hw_types.h"
Sergunb 0:8918a71cdbe9 37 #include "driverlib/gpio.h"
Sergunb 0:8918a71cdbe9 38 #include "driverlib/interrupt.h"
Sergunb 0:8918a71cdbe9 39 #include "driverlib/sysctl.h"
Sergunb 0:8918a71cdbe9 40 #include "core/net.h"
Sergunb 0:8918a71cdbe9 41 #include "drivers/f28m35x_eth.h"
Sergunb 0:8918a71cdbe9 42 #include "debug.h"
Sergunb 0:8918a71cdbe9 43
Sergunb 0:8918a71cdbe9 44 //Underlying network interface
Sergunb 0:8918a71cdbe9 45 static NetInterface *nicDriverInterface;
Sergunb 0:8918a71cdbe9 46
Sergunb 0:8918a71cdbe9 47 //IAR EWARM compiler?
Sergunb 0:8918a71cdbe9 48 #if defined(__ICCARM__)
Sergunb 0:8918a71cdbe9 49
Sergunb 0:8918a71cdbe9 50 //Transmit buffer
Sergunb 0:8918a71cdbe9 51 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 52 static uint8_t txBuffer[ETH_MAX_FRAME_SIZE + 2];
Sergunb 0:8918a71cdbe9 53 //Receive buffer
Sergunb 0:8918a71cdbe9 54 #pragma data_alignment = 4
Sergunb 0:8918a71cdbe9 55 static uint8_t rxBuffer[ETH_MAX_FRAME_SIZE];
Sergunb 0:8918a71cdbe9 56
Sergunb 0:8918a71cdbe9 57 //Keil MDK-ARM or GCC compiler?
Sergunb 0:8918a71cdbe9 58 #else
Sergunb 0:8918a71cdbe9 59
Sergunb 0:8918a71cdbe9 60 //Transmit buffer
Sergunb 0:8918a71cdbe9 61 static uint8_t txBuffer[ETH_MAX_FRAME_SIZE + 2] __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 62 //Receive buffer
Sergunb 0:8918a71cdbe9 63 static uint8_t rxBuffer[ETH_MAX_FRAME_SIZE] __attribute__((aligned(4)));
Sergunb 0:8918a71cdbe9 64
Sergunb 0:8918a71cdbe9 65 #endif
Sergunb 0:8918a71cdbe9 66
Sergunb 0:8918a71cdbe9 67
Sergunb 0:8918a71cdbe9 68 /**
Sergunb 0:8918a71cdbe9 69 * @brief F28M35x Ethernet MAC driver
Sergunb 0:8918a71cdbe9 70 **/
Sergunb 0:8918a71cdbe9 71
Sergunb 0:8918a71cdbe9 72 const NicDriver f28m35xEthDriver =
Sergunb 0:8918a71cdbe9 73 {
Sergunb 0:8918a71cdbe9 74 NIC_TYPE_ETHERNET,
Sergunb 0:8918a71cdbe9 75 ETH_MTU,
Sergunb 0:8918a71cdbe9 76 f28m35xEthInit,
Sergunb 0:8918a71cdbe9 77 f28m35xEthTick,
Sergunb 0:8918a71cdbe9 78 f28m35xEthEnableIrq,
Sergunb 0:8918a71cdbe9 79 f28m35xEthDisableIrq,
Sergunb 0:8918a71cdbe9 80 f28m35xEthEventHandler,
Sergunb 0:8918a71cdbe9 81 f28m35xEthSendPacket,
Sergunb 0:8918a71cdbe9 82 f28m35xEthSetMulticastFilter,
Sergunb 0:8918a71cdbe9 83 f28m35xEthUpdateMacConfig,
Sergunb 0:8918a71cdbe9 84 f28m35xEthWritePhyReg,
Sergunb 0:8918a71cdbe9 85 f28m35xEthReadPhyReg,
Sergunb 0:8918a71cdbe9 86 TRUE,
Sergunb 0:8918a71cdbe9 87 TRUE,
Sergunb 0:8918a71cdbe9 88 TRUE,
Sergunb 0:8918a71cdbe9 89 FALSE
Sergunb 0:8918a71cdbe9 90 };
Sergunb 0:8918a71cdbe9 91
Sergunb 0:8918a71cdbe9 92
Sergunb 0:8918a71cdbe9 93 /**
Sergunb 0:8918a71cdbe9 94 * @brief F28M35x Ethernet MAC controller initialization
Sergunb 0:8918a71cdbe9 95 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 96 * @return Error code
Sergunb 0:8918a71cdbe9 97 **/
Sergunb 0:8918a71cdbe9 98
Sergunb 0:8918a71cdbe9 99 error_t f28m35xEthInit(NetInterface *interface)
Sergunb 0:8918a71cdbe9 100 {
Sergunb 0:8918a71cdbe9 101 error_t error;
Sergunb 0:8918a71cdbe9 102 uint_t div;
Sergunb 0:8918a71cdbe9 103 #ifdef ti_sysbios_BIOS___VERS
Sergunb 0:8918a71cdbe9 104 Hwi_Params hwiParams;
Sergunb 0:8918a71cdbe9 105 #endif
Sergunb 0:8918a71cdbe9 106
Sergunb 0:8918a71cdbe9 107 //Debug message
Sergunb 0:8918a71cdbe9 108 TRACE_INFO("Initializing F28M35x Ethernet MAC controller...\r\n");
Sergunb 0:8918a71cdbe9 109
Sergunb 0:8918a71cdbe9 110 //Save underlying network interface
Sergunb 0:8918a71cdbe9 111 nicDriverInterface = interface;
Sergunb 0:8918a71cdbe9 112
Sergunb 0:8918a71cdbe9 113 //Enable Ethernet controller clock
Sergunb 0:8918a71cdbe9 114 SysCtlPeripheralEnable(SYSCTL_PERIPH_ETH);
Sergunb 0:8918a71cdbe9 115 //Reset Ethernet controller
Sergunb 0:8918a71cdbe9 116 SysCtlPeripheralReset(SYSCTL_PERIPH_ETH);
Sergunb 0:8918a71cdbe9 117
Sergunb 0:8918a71cdbe9 118 //GPIO configuration
Sergunb 0:8918a71cdbe9 119 f28m35xEthInitGpio(interface);
Sergunb 0:8918a71cdbe9 120
Sergunb 0:8918a71cdbe9 121 //The MDC clock frequency cannot exceed 2.5MHz
Sergunb 0:8918a71cdbe9 122 div = SysCtlClockGet(20000000) / (2 * 2500000) - 1;
Sergunb 0:8918a71cdbe9 123 //Adjust MDC clock frequency
Sergunb 0:8918a71cdbe9 124 MAC_MDV_R = div & MAC_MDV_DIV_M;
Sergunb 0:8918a71cdbe9 125
Sergunb 0:8918a71cdbe9 126 //PHY transceiver initialization
Sergunb 0:8918a71cdbe9 127 error = interface->phyDriver->init(interface);
Sergunb 0:8918a71cdbe9 128 //Failed to initialize PHY transceiver?
Sergunb 0:8918a71cdbe9 129 if(error)
Sergunb 0:8918a71cdbe9 130 return error;
Sergunb 0:8918a71cdbe9 131
Sergunb 0:8918a71cdbe9 132 //Set the MAC address
Sergunb 0:8918a71cdbe9 133 MAC_IA0_R = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16);
Sergunb 0:8918a71cdbe9 134 MAC_IA1_R = interface->macAddr.w[2];
Sergunb 0:8918a71cdbe9 135
Sergunb 0:8918a71cdbe9 136 //Enable automatic CRC generation and packet padding
Sergunb 0:8918a71cdbe9 137 MAC_TCTL_R = MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN;
Sergunb 0:8918a71cdbe9 138 //Flush the receive FIFO and enable CRC verification
Sergunb 0:8918a71cdbe9 139 MAC_RCTL_R = MAC_RCTL_RSTFIFO | MAC_RCTL_BADCRC;
Sergunb 0:8918a71cdbe9 140
Sergunb 0:8918a71cdbe9 141 //Configure Ethernet interrupts
Sergunb 0:8918a71cdbe9 142 MAC_IM_R = MAC_IM_TXEMPM | MAC_IM_RXINTM;
Sergunb 0:8918a71cdbe9 143
Sergunb 0:8918a71cdbe9 144 #ifdef ti_sysbios_BIOS___VERS
Sergunb 0:8918a71cdbe9 145 //Configure Ethernet interrupt
Sergunb 0:8918a71cdbe9 146 Hwi_Params_init(&hwiParams);
Sergunb 0:8918a71cdbe9 147 hwiParams.enableInt = FALSE;
Sergunb 0:8918a71cdbe9 148 hwiParams.priority = F28M35X_ETH_IRQ_PRIORITY;
Sergunb 0:8918a71cdbe9 149
Sergunb 0:8918a71cdbe9 150 //Register interrupt handler
Sergunb 0:8918a71cdbe9 151 Hwi_create(INT_ETH, (Hwi_FuncPtr) f28m35xEthIrqHandler, &hwiParams, NULL);
Sergunb 0:8918a71cdbe9 152 #else
Sergunb 0:8918a71cdbe9 153 //Register interrupt handler
Sergunb 0:8918a71cdbe9 154 IntRegister(INT_ETH, f28m35xEthIrqHandler);
Sergunb 0:8918a71cdbe9 155
Sergunb 0:8918a71cdbe9 156 //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority)
Sergunb 0:8918a71cdbe9 157 IntPriorityGroupingSet(F28M35X_ETH_IRQ_PRIORITY_GROUPING);
Sergunb 0:8918a71cdbe9 158 //Configure Ethernet interrupt priority
Sergunb 0:8918a71cdbe9 159 IntPrioritySet(INT_ETH, F28M35X_ETH_IRQ_PRIORITY);
Sergunb 0:8918a71cdbe9 160 #endif
Sergunb 0:8918a71cdbe9 161
Sergunb 0:8918a71cdbe9 162 //Enable transmitter
Sergunb 0:8918a71cdbe9 163 MAC_TCTL_R |= MAC_TCTL_TXEN;
Sergunb 0:8918a71cdbe9 164 //Enable receiver
Sergunb 0:8918a71cdbe9 165 MAC_RCTL_R |= MAC_RCTL_RXEN;
Sergunb 0:8918a71cdbe9 166
Sergunb 0:8918a71cdbe9 167 //Accept any packets from the upper layer
Sergunb 0:8918a71cdbe9 168 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 169
Sergunb 0:8918a71cdbe9 170 //Successful initialization
Sergunb 0:8918a71cdbe9 171 return NO_ERROR;
Sergunb 0:8918a71cdbe9 172 }
Sergunb 0:8918a71cdbe9 173
Sergunb 0:8918a71cdbe9 174
Sergunb 0:8918a71cdbe9 175 //TMDXCNCDH52C1 evaluation board?
Sergunb 0:8918a71cdbe9 176 #if defined(USE_TMDXCNCDH52C1)
Sergunb 0:8918a71cdbe9 177
Sergunb 0:8918a71cdbe9 178 /**
Sergunb 0:8918a71cdbe9 179 * @brief GPIO configuration
Sergunb 0:8918a71cdbe9 180 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 181 **/
Sergunb 0:8918a71cdbe9 182
Sergunb 0:8918a71cdbe9 183 void f28m35xEthInitGpio(NetInterface *interface)
Sergunb 0:8918a71cdbe9 184 {
Sergunb 0:8918a71cdbe9 185 //Enable GPIO clocks
Sergunb 0:8918a71cdbe9 186 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
Sergunb 0:8918a71cdbe9 187 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
Sergunb 0:8918a71cdbe9 188 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
Sergunb 0:8918a71cdbe9 189 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOG);
Sergunb 0:8918a71cdbe9 190 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOH);
Sergunb 0:8918a71cdbe9 191 SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOJ);
Sergunb 0:8918a71cdbe9 192
Sergunb 0:8918a71cdbe9 193 //Configure MII_TXD3 (PC4)
Sergunb 0:8918a71cdbe9 194 GPIODirModeSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 195 GPIOPadConfigSet(GPIO_PORTC_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 196 GPIOPinConfigure(GPIO_PC4_MIITXD3);
Sergunb 0:8918a71cdbe9 197
Sergunb 0:8918a71cdbe9 198 //Configure MII_MDIO (PE6)
Sergunb 0:8918a71cdbe9 199 GPIODirModeSet(GPIO_PORTE_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 200 GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 201 GPIOPinConfigure(GPIO_PE6_MIIMDIO);
Sergunb 0:8918a71cdbe9 202
Sergunb 0:8918a71cdbe9 203 //Configure MII_RXD3 (PF5)
Sergunb 0:8918a71cdbe9 204 GPIODirModeSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 205 GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 206 GPIOPinConfigure(GPIO_PF5_MIIRXD3);
Sergunb 0:8918a71cdbe9 207
Sergunb 0:8918a71cdbe9 208 //Configure MII_RXD2 (PG0)
Sergunb 0:8918a71cdbe9 209 GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_0, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 210 GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_0, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 211 GPIOPinConfigure(GPIO_PG0_MIIRXD2);
Sergunb 0:8918a71cdbe9 212
Sergunb 0:8918a71cdbe9 213 //Configure MII_RXD1 (PG1)
Sergunb 0:8918a71cdbe9 214 GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_1, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 215 GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_1, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 216 GPIOPinConfigure(GPIO_PG1_MIIRXD1);
Sergunb 0:8918a71cdbe9 217
Sergunb 0:8918a71cdbe9 218 //Configure MII_RXDV (PG3)
Sergunb 0:8918a71cdbe9 219 GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_3, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 220 GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_3, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 221 GPIOPinConfigure(GPIO_PG3_MIIRXDV);
Sergunb 0:8918a71cdbe9 222
Sergunb 0:8918a71cdbe9 223 //Configure MII_TXER (PG7)
Sergunb 0:8918a71cdbe9 224 GPIODirModeSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 225 GPIOPadConfigSet(GPIO_PORTG_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 226 GPIOPinConfigure(GPIO_PG7_MIITXER);
Sergunb 0:8918a71cdbe9 227
Sergunb 0:8918a71cdbe9 228 //Configure MII_RXD0 (PH1)
Sergunb 0:8918a71cdbe9 229 GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_1, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 230 GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_1, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 231 GPIOPinConfigure(GPIO_PH1_MIIRXD0);
Sergunb 0:8918a71cdbe9 232
Sergunb 0:8918a71cdbe9 233 //Configure MII_TXD2 (PH3)
Sergunb 0:8918a71cdbe9 234 GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_3, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 235 GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_3, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 236 GPIOPinConfigure(GPIO_PH3_MIITXD2);
Sergunb 0:8918a71cdbe9 237
Sergunb 0:8918a71cdbe9 238 //Configure MII_TXD1 (PH4)
Sergunb 0:8918a71cdbe9 239 GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 240 GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 241 GPIOPinConfigure(GPIO_PH4_MIITXD1);
Sergunb 0:8918a71cdbe9 242
Sergunb 0:8918a71cdbe9 243 //Configure MII_TXD0 (PH5)
Sergunb 0:8918a71cdbe9 244 GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 245 GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 246 GPIOPinConfigure(GPIO_PH5_MIITXD0);
Sergunb 0:8918a71cdbe9 247
Sergunb 0:8918a71cdbe9 248 //Configure MII_TXEN (PH6)
Sergunb 0:8918a71cdbe9 249 GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 250 GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 251 GPIOPinConfigure(GPIO_PH6_MIITXEN);
Sergunb 0:8918a71cdbe9 252
Sergunb 0:8918a71cdbe9 253 //Configure MII_TXCK (PH7)
Sergunb 0:8918a71cdbe9 254 GPIODirModeSet(GPIO_PORTH_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 255 GPIOPadConfigSet(GPIO_PORTH_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 256 GPIOPinConfigure(GPIO_PH7_MIITXCK);
Sergunb 0:8918a71cdbe9 257
Sergunb 0:8918a71cdbe9 258 //Configure MII_RXER (PJ0)
Sergunb 0:8918a71cdbe9 259 GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_0, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 260 GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_0, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 261 GPIOPinConfigure(GPIO_PJ0_MIIRXER);
Sergunb 0:8918a71cdbe9 262
Sergunb 0:8918a71cdbe9 263 //Configure MII_RXCK (PJ2)
Sergunb 0:8918a71cdbe9 264 GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_2, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 265 GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_2, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 266 GPIOPinConfigure(GPIO_PJ2_MIIRXCK);
Sergunb 0:8918a71cdbe9 267
Sergunb 0:8918a71cdbe9 268 //Configure MII_MDC (PJ3)
Sergunb 0:8918a71cdbe9 269 GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_3, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 270 GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_3, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 271 GPIOPinConfigure(GPIO_PJ3_MIIMDC);
Sergunb 0:8918a71cdbe9 272
Sergunb 0:8918a71cdbe9 273 //Configure MII_COL (PJ4)
Sergunb 0:8918a71cdbe9 274 GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_4, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 275 GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_4, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 276 GPIOPinConfigure(GPIO_PJ4_MIICOL);
Sergunb 0:8918a71cdbe9 277
Sergunb 0:8918a71cdbe9 278 //Configure MII_CRS (PJ5)
Sergunb 0:8918a71cdbe9 279 GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_5, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 280 GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_5, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 281 GPIOPinConfigure(GPIO_PJ5_MIICRS);
Sergunb 0:8918a71cdbe9 282
Sergunb 0:8918a71cdbe9 283 //Configure MII_PHYINTR (PJ6)
Sergunb 0:8918a71cdbe9 284 GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_6, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 285 GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_6, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 286 GPIOPinConfigure(GPIO_PJ6_MIIPHYINTRn);
Sergunb 0:8918a71cdbe9 287
Sergunb 0:8918a71cdbe9 288 //Configure MII_PHYRSTn (PJ7)
Sergunb 0:8918a71cdbe9 289 GPIODirModeSet(GPIO_PORTJ_BASE, GPIO_PIN_7, GPIO_DIR_MODE_HW);
Sergunb 0:8918a71cdbe9 290 GPIOPadConfigSet(GPIO_PORTJ_BASE, GPIO_PIN_7, GPIO_PIN_TYPE_STD);
Sergunb 0:8918a71cdbe9 291 GPIOPinConfigure(GPIO_PJ7_MIIPHYRSTn);
Sergunb 0:8918a71cdbe9 292 }
Sergunb 0:8918a71cdbe9 293
Sergunb 0:8918a71cdbe9 294 #endif
Sergunb 0:8918a71cdbe9 295
Sergunb 0:8918a71cdbe9 296
Sergunb 0:8918a71cdbe9 297 /**
Sergunb 0:8918a71cdbe9 298 * @brief F28M35x Ethernet MAC timer handler
Sergunb 0:8918a71cdbe9 299 *
Sergunb 0:8918a71cdbe9 300 * This routine is periodically called by the TCP/IP stack to
Sergunb 0:8918a71cdbe9 301 * handle periodic operations such as polling the link state
Sergunb 0:8918a71cdbe9 302 *
Sergunb 0:8918a71cdbe9 303 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 304 **/
Sergunb 0:8918a71cdbe9 305
Sergunb 0:8918a71cdbe9 306 void f28m35xEthTick(NetInterface *interface)
Sergunb 0:8918a71cdbe9 307 {
Sergunb 0:8918a71cdbe9 308 //Handle periodic operations
Sergunb 0:8918a71cdbe9 309 interface->phyDriver->tick(interface);
Sergunb 0:8918a71cdbe9 310 }
Sergunb 0:8918a71cdbe9 311
Sergunb 0:8918a71cdbe9 312
Sergunb 0:8918a71cdbe9 313 /**
Sergunb 0:8918a71cdbe9 314 * @brief Enable interrupts
Sergunb 0:8918a71cdbe9 315 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 316 **/
Sergunb 0:8918a71cdbe9 317
Sergunb 0:8918a71cdbe9 318 void f28m35xEthEnableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 319 {
Sergunb 0:8918a71cdbe9 320 #ifdef ti_sysbios_BIOS___VERS
Sergunb 0:8918a71cdbe9 321 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 322 Hwi_enableInterrupt(INT_ETH);
Sergunb 0:8918a71cdbe9 323 #else
Sergunb 0:8918a71cdbe9 324 //Enable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 325 IntEnable(INT_ETH);
Sergunb 0:8918a71cdbe9 326 #endif
Sergunb 0:8918a71cdbe9 327
Sergunb 0:8918a71cdbe9 328 //Enable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 329 interface->phyDriver->enableIrq(interface);
Sergunb 0:8918a71cdbe9 330 }
Sergunb 0:8918a71cdbe9 331
Sergunb 0:8918a71cdbe9 332
Sergunb 0:8918a71cdbe9 333 /**
Sergunb 0:8918a71cdbe9 334 * @brief Disable interrupts
Sergunb 0:8918a71cdbe9 335 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 336 **/
Sergunb 0:8918a71cdbe9 337
Sergunb 0:8918a71cdbe9 338 void f28m35xEthDisableIrq(NetInterface *interface)
Sergunb 0:8918a71cdbe9 339 {
Sergunb 0:8918a71cdbe9 340 #ifdef ti_sysbios_BIOS___VERS
Sergunb 0:8918a71cdbe9 341 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 342 Hwi_disableInterrupt(INT_ETH);
Sergunb 0:8918a71cdbe9 343 #else
Sergunb 0:8918a71cdbe9 344 //Disable Ethernet MAC interrupts
Sergunb 0:8918a71cdbe9 345 IntDisable(INT_ETH);
Sergunb 0:8918a71cdbe9 346 #endif
Sergunb 0:8918a71cdbe9 347
Sergunb 0:8918a71cdbe9 348 //Disable Ethernet PHY interrupts
Sergunb 0:8918a71cdbe9 349 interface->phyDriver->disableIrq(interface);
Sergunb 0:8918a71cdbe9 350 }
Sergunb 0:8918a71cdbe9 351
Sergunb 0:8918a71cdbe9 352
Sergunb 0:8918a71cdbe9 353 /**
Sergunb 0:8918a71cdbe9 354 * @brief F28M35x Ethernet MAC interrupt service routine
Sergunb 0:8918a71cdbe9 355 **/
Sergunb 0:8918a71cdbe9 356
Sergunb 0:8918a71cdbe9 357 void f28m35xEthIrqHandler(void)
Sergunb 0:8918a71cdbe9 358 {
Sergunb 0:8918a71cdbe9 359 bool_t flag;
Sergunb 0:8918a71cdbe9 360 uint32_t status;
Sergunb 0:8918a71cdbe9 361
Sergunb 0:8918a71cdbe9 362 //Enter interrupt service routine
Sergunb 0:8918a71cdbe9 363 osEnterIsr();
Sergunb 0:8918a71cdbe9 364
Sergunb 0:8918a71cdbe9 365 //This flag will be set if a higher priority task must be woken
Sergunb 0:8918a71cdbe9 366 flag = FALSE;
Sergunb 0:8918a71cdbe9 367
Sergunb 0:8918a71cdbe9 368 //Read interrupt status register
Sergunb 0:8918a71cdbe9 369 status = MAC_RIS_R;
Sergunb 0:8918a71cdbe9 370
Sergunb 0:8918a71cdbe9 371 //Transmit FIFO empty?
Sergunb 0:8918a71cdbe9 372 if(status & MAC_RIS_TXEMP)
Sergunb 0:8918a71cdbe9 373 {
Sergunb 0:8918a71cdbe9 374 //Acknowledge TXEMP interrupt
Sergunb 0:8918a71cdbe9 375 MAC_IACK_R = MAC_IACK_TXEMP;
Sergunb 0:8918a71cdbe9 376
Sergunb 0:8918a71cdbe9 377 //Check whether the transmit FIFO is available for writing
Sergunb 0:8918a71cdbe9 378 if(!(MAC_TR_R & MAC_TR_NEWTX))
Sergunb 0:8918a71cdbe9 379 {
Sergunb 0:8918a71cdbe9 380 //Notify the TCP/IP stack that the transmitter is ready to send
Sergunb 0:8918a71cdbe9 381 flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent);
Sergunb 0:8918a71cdbe9 382 }
Sergunb 0:8918a71cdbe9 383 }
Sergunb 0:8918a71cdbe9 384
Sergunb 0:8918a71cdbe9 385 //Packet received?
Sergunb 0:8918a71cdbe9 386 if(status & MAC_RIS_RXINT)
Sergunb 0:8918a71cdbe9 387 {
Sergunb 0:8918a71cdbe9 388 //Disable RXINT interrupt
Sergunb 0:8918a71cdbe9 389 MAC_IM_R &= ~MAC_IM_RXINTM;
Sergunb 0:8918a71cdbe9 390
Sergunb 0:8918a71cdbe9 391 //Set event flag
Sergunb 0:8918a71cdbe9 392 nicDriverInterface->nicEvent = TRUE;
Sergunb 0:8918a71cdbe9 393 //Notify the TCP/IP stack of the event
Sergunb 0:8918a71cdbe9 394 flag |= osSetEventFromIsr(&netEvent);
Sergunb 0:8918a71cdbe9 395 }
Sergunb 0:8918a71cdbe9 396
Sergunb 0:8918a71cdbe9 397 //Leave interrupt service routine
Sergunb 0:8918a71cdbe9 398 osExitIsr(flag);
Sergunb 0:8918a71cdbe9 399 }
Sergunb 0:8918a71cdbe9 400
Sergunb 0:8918a71cdbe9 401
Sergunb 0:8918a71cdbe9 402 /**
Sergunb 0:8918a71cdbe9 403 * @brief F28M35x Ethernet MAC event handler
Sergunb 0:8918a71cdbe9 404 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 405 **/
Sergunb 0:8918a71cdbe9 406
Sergunb 0:8918a71cdbe9 407 void f28m35xEthEventHandler(NetInterface *interface)
Sergunb 0:8918a71cdbe9 408 {
Sergunb 0:8918a71cdbe9 409 //Packet received?
Sergunb 0:8918a71cdbe9 410 if(MAC_RIS_R & MAC_RIS_RXINT)
Sergunb 0:8918a71cdbe9 411 {
Sergunb 0:8918a71cdbe9 412 //Acknowledge RXINT interrupt
Sergunb 0:8918a71cdbe9 413 MAC_IACK_R = MAC_IACK_RXINT;
Sergunb 0:8918a71cdbe9 414
Sergunb 0:8918a71cdbe9 415 //Process all the pending packets
Sergunb 0:8918a71cdbe9 416 while(MAC_NP_R & MAC_NP_NPR_M)
Sergunb 0:8918a71cdbe9 417 {
Sergunb 0:8918a71cdbe9 418 //Read incoming packet
Sergunb 0:8918a71cdbe9 419 f28m35xEthReceivePacket(interface);
Sergunb 0:8918a71cdbe9 420 }
Sergunb 0:8918a71cdbe9 421 }
Sergunb 0:8918a71cdbe9 422
Sergunb 0:8918a71cdbe9 423 //Re-enable Ethernet interrupts
Sergunb 0:8918a71cdbe9 424 MAC_IM_R = MAC_IM_TXEMPM | MAC_IM_RXINTM;
Sergunb 0:8918a71cdbe9 425 }
Sergunb 0:8918a71cdbe9 426
Sergunb 0:8918a71cdbe9 427
Sergunb 0:8918a71cdbe9 428 /**
Sergunb 0:8918a71cdbe9 429 * @brief Send a packet
Sergunb 0:8918a71cdbe9 430 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 431 * @param[in] buffer Multi-part buffer containing the data to send
Sergunb 0:8918a71cdbe9 432 * @param[in] offset Offset to the first data byte
Sergunb 0:8918a71cdbe9 433 * @return Error code
Sergunb 0:8918a71cdbe9 434 **/
Sergunb 0:8918a71cdbe9 435
Sergunb 0:8918a71cdbe9 436 error_t f28m35xEthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 437 const NetBuffer *buffer, size_t offset)
Sergunb 0:8918a71cdbe9 438 {
Sergunb 0:8918a71cdbe9 439 size_t i;
Sergunb 0:8918a71cdbe9 440 size_t length;
Sergunb 0:8918a71cdbe9 441 uint32_t *p;
Sergunb 0:8918a71cdbe9 442
Sergunb 0:8918a71cdbe9 443 //Retrieve the length of the packet
Sergunb 0:8918a71cdbe9 444 length = netBufferGetLength(buffer) - offset;
Sergunb 0:8918a71cdbe9 445
Sergunb 0:8918a71cdbe9 446 //Check the frame length
Sergunb 0:8918a71cdbe9 447 if(length < sizeof(EthHeader) || length > ETH_MAX_FRAME_SIZE)
Sergunb 0:8918a71cdbe9 448 {
Sergunb 0:8918a71cdbe9 449 //The transmitter can accept another packet
Sergunb 0:8918a71cdbe9 450 osSetEvent(&interface->nicTxEvent);
Sergunb 0:8918a71cdbe9 451 //Report an error
Sergunb 0:8918a71cdbe9 452 return ERROR_INVALID_LENGTH;
Sergunb 0:8918a71cdbe9 453 }
Sergunb 0:8918a71cdbe9 454
Sergunb 0:8918a71cdbe9 455 //Make sure the transmit FIFO is available for writing
Sergunb 0:8918a71cdbe9 456 if(MAC_TR_R & MAC_TR_NEWTX)
Sergunb 0:8918a71cdbe9 457 return ERROR_FAILURE;
Sergunb 0:8918a71cdbe9 458
Sergunb 0:8918a71cdbe9 459 //Copy user data
Sergunb 0:8918a71cdbe9 460 netBufferRead(txBuffer + 2, buffer, offset, length);
Sergunb 0:8918a71cdbe9 461
Sergunb 0:8918a71cdbe9 462 //The packet is preceded by a 16-bit length field
Sergunb 0:8918a71cdbe9 463 txBuffer[0] = LSB(length - sizeof(EthHeader));
Sergunb 0:8918a71cdbe9 464 txBuffer[1] = MSB(length - sizeof(EthHeader));
Sergunb 0:8918a71cdbe9 465
Sergunb 0:8918a71cdbe9 466 //Point to the beginning of the packet
Sergunb 0:8918a71cdbe9 467 p = (uint32_t *) txBuffer;
Sergunb 0:8918a71cdbe9 468 //Compute the length of the packet in 32-bit words
Sergunb 0:8918a71cdbe9 469 length = (length + 5) / 4;
Sergunb 0:8918a71cdbe9 470
Sergunb 0:8918a71cdbe9 471 //Copy packet to transmit FIFO
Sergunb 0:8918a71cdbe9 472 for(i = 0; i < length; i++)
Sergunb 0:8918a71cdbe9 473 MAC_DATA_R = p[i];
Sergunb 0:8918a71cdbe9 474
Sergunb 0:8918a71cdbe9 475 //Start transmitting
Sergunb 0:8918a71cdbe9 476 MAC_TR_R = MAC_TR_NEWTX;
Sergunb 0:8918a71cdbe9 477
Sergunb 0:8918a71cdbe9 478 //Data successfully written
Sergunb 0:8918a71cdbe9 479 return NO_ERROR;
Sergunb 0:8918a71cdbe9 480 }
Sergunb 0:8918a71cdbe9 481
Sergunb 0:8918a71cdbe9 482
Sergunb 0:8918a71cdbe9 483 /**
Sergunb 0:8918a71cdbe9 484 * @brief Receive a packet
Sergunb 0:8918a71cdbe9 485 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 486 * @return Error code
Sergunb 0:8918a71cdbe9 487 **/
Sergunb 0:8918a71cdbe9 488
Sergunb 0:8918a71cdbe9 489 error_t f28m35xEthReceivePacket(NetInterface *interface)
Sergunb 0:8918a71cdbe9 490 {
Sergunb 0:8918a71cdbe9 491 error_t error;
Sergunb 0:8918a71cdbe9 492 size_t i;
Sergunb 0:8918a71cdbe9 493 size_t n;
Sergunb 0:8918a71cdbe9 494 size_t length;
Sergunb 0:8918a71cdbe9 495 uint32_t data;
Sergunb 0:8918a71cdbe9 496 uint16_t *p;
Sergunb 0:8918a71cdbe9 497
Sergunb 0:8918a71cdbe9 498 //Make sure the FIFO is not empty
Sergunb 0:8918a71cdbe9 499 if(MAC_NP_R & MAC_NP_NPR_M)
Sergunb 0:8918a71cdbe9 500 {
Sergunb 0:8918a71cdbe9 501 //Read the first word
Sergunb 0:8918a71cdbe9 502 data = MAC_DATA_R;
Sergunb 0:8918a71cdbe9 503 //Retrieve the total length of the packet
Sergunb 0:8918a71cdbe9 504 length = data & 0xFFFF;
Sergunb 0:8918a71cdbe9 505
Sergunb 0:8918a71cdbe9 506 //Make sure the length field is valid
Sergunb 0:8918a71cdbe9 507 if(length > 2)
Sergunb 0:8918a71cdbe9 508 {
Sergunb 0:8918a71cdbe9 509 //Point to the beginning of the buffer
Sergunb 0:8918a71cdbe9 510 p = (uint16_t *) rxBuffer;
Sergunb 0:8918a71cdbe9 511
Sergunb 0:8918a71cdbe9 512 //Retrieve the length of the frame
Sergunb 0:8918a71cdbe9 513 length -= 2;
Sergunb 0:8918a71cdbe9 514 //Limit the number of data to be read
Sergunb 0:8918a71cdbe9 515 n = MIN(length, ETH_MAX_FRAME_SIZE);
Sergunb 0:8918a71cdbe9 516
Sergunb 0:8918a71cdbe9 517 //Copy the first half word
Sergunb 0:8918a71cdbe9 518 if(n > 0)
Sergunb 0:8918a71cdbe9 519 *(p++) = (uint16_t) (data >> 16);
Sergunb 0:8918a71cdbe9 520
Sergunb 0:8918a71cdbe9 521 //Copy data from receive FIFO
Sergunb 0:8918a71cdbe9 522 for(i = 2; i < n; i += 4)
Sergunb 0:8918a71cdbe9 523 {
Sergunb 0:8918a71cdbe9 524 //Read a 32-bit word from the FIFO
Sergunb 0:8918a71cdbe9 525 data = MAC_DATA_R;
Sergunb 0:8918a71cdbe9 526 //Write the 32-bit to the receive buffer
Sergunb 0:8918a71cdbe9 527 *(p++) = (uint16_t) data;
Sergunb 0:8918a71cdbe9 528 *(p++) = (uint16_t) (data >> 16);
Sergunb 0:8918a71cdbe9 529 }
Sergunb 0:8918a71cdbe9 530
Sergunb 0:8918a71cdbe9 531 //Skip the remaining bytes
Sergunb 0:8918a71cdbe9 532 while(i < length)
Sergunb 0:8918a71cdbe9 533 {
Sergunb 0:8918a71cdbe9 534 //Read a 32-bit word from the FIFO
Sergunb 0:8918a71cdbe9 535 data = MAC_DATA_R;
Sergunb 0:8918a71cdbe9 536 //Increment byte counter
Sergunb 0:8918a71cdbe9 537 i += 4;
Sergunb 0:8918a71cdbe9 538 }
Sergunb 0:8918a71cdbe9 539
Sergunb 0:8918a71cdbe9 540 //Valid packet received
Sergunb 0:8918a71cdbe9 541 error = NO_ERROR;
Sergunb 0:8918a71cdbe9 542 }
Sergunb 0:8918a71cdbe9 543 else
Sergunb 0:8918a71cdbe9 544 {
Sergunb 0:8918a71cdbe9 545 //Disable receiver
Sergunb 0:8918a71cdbe9 546 MAC_RCTL_R &= ~MAC_RCTL_RXEN;
Sergunb 0:8918a71cdbe9 547 //Flush the receive FIFO
Sergunb 0:8918a71cdbe9 548 MAC_RCTL_R |= MAC_RCTL_RSTFIFO;
Sergunb 0:8918a71cdbe9 549 //Re-enable receiver
Sergunb 0:8918a71cdbe9 550 MAC_RCTL_R |= MAC_RCTL_RXEN;
Sergunb 0:8918a71cdbe9 551
Sergunb 0:8918a71cdbe9 552 //The packet is not valid
Sergunb 0:8918a71cdbe9 553 error = ERROR_INVALID_PACKET;
Sergunb 0:8918a71cdbe9 554 }
Sergunb 0:8918a71cdbe9 555 }
Sergunb 0:8918a71cdbe9 556 else
Sergunb 0:8918a71cdbe9 557 {
Sergunb 0:8918a71cdbe9 558 //No more data in the receive buffer
Sergunb 0:8918a71cdbe9 559 error = ERROR_BUFFER_EMPTY;
Sergunb 0:8918a71cdbe9 560 }
Sergunb 0:8918a71cdbe9 561
Sergunb 0:8918a71cdbe9 562 //Check whether a valid packet has been received
Sergunb 0:8918a71cdbe9 563 if(!error)
Sergunb 0:8918a71cdbe9 564 {
Sergunb 0:8918a71cdbe9 565 //Pass the packet to the upper layer
Sergunb 0:8918a71cdbe9 566 nicProcessPacket(interface, rxBuffer, n);
Sergunb 0:8918a71cdbe9 567 }
Sergunb 0:8918a71cdbe9 568
Sergunb 0:8918a71cdbe9 569 //Return status code
Sergunb 0:8918a71cdbe9 570 return error;
Sergunb 0:8918a71cdbe9 571 }
Sergunb 0:8918a71cdbe9 572
Sergunb 0:8918a71cdbe9 573
Sergunb 0:8918a71cdbe9 574 /**
Sergunb 0:8918a71cdbe9 575 * @brief Configure multicast MAC address filtering
Sergunb 0:8918a71cdbe9 576 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 577 * @return Error code
Sergunb 0:8918a71cdbe9 578 **/
Sergunb 0:8918a71cdbe9 579
Sergunb 0:8918a71cdbe9 580 error_t f28m35xEthSetMulticastFilter(NetInterface *interface)
Sergunb 0:8918a71cdbe9 581 {
Sergunb 0:8918a71cdbe9 582 uint_t i;
Sergunb 0:8918a71cdbe9 583 bool_t acceptMulticast;
Sergunb 0:8918a71cdbe9 584
Sergunb 0:8918a71cdbe9 585 //This flag will be set if multicast addresses should be accepted
Sergunb 0:8918a71cdbe9 586 acceptMulticast = FALSE;
Sergunb 0:8918a71cdbe9 587
Sergunb 0:8918a71cdbe9 588 //The MAC filter table contains the multicast MAC addresses
Sergunb 0:8918a71cdbe9 589 //to accept when receiving an Ethernet frame
Sergunb 0:8918a71cdbe9 590 for(i = 0; i < MAC_MULTICAST_FILTER_SIZE; i++)
Sergunb 0:8918a71cdbe9 591 {
Sergunb 0:8918a71cdbe9 592 //Valid entry?
Sergunb 0:8918a71cdbe9 593 if(interface->macMulticastFilter[i].refCount > 0)
Sergunb 0:8918a71cdbe9 594 {
Sergunb 0:8918a71cdbe9 595 //Accept multicast addresses
Sergunb 0:8918a71cdbe9 596 acceptMulticast = TRUE;
Sergunb 0:8918a71cdbe9 597 //We are done
Sergunb 0:8918a71cdbe9 598 break;
Sergunb 0:8918a71cdbe9 599 }
Sergunb 0:8918a71cdbe9 600 }
Sergunb 0:8918a71cdbe9 601
Sergunb 0:8918a71cdbe9 602 //Enable the reception of multicast frames if necessary
Sergunb 0:8918a71cdbe9 603 if(acceptMulticast)
Sergunb 0:8918a71cdbe9 604 MAC_RCTL_R |= MAC_RCTL_AMUL;
Sergunb 0:8918a71cdbe9 605 else
Sergunb 0:8918a71cdbe9 606 MAC_RCTL_R &= ~MAC_RCTL_AMUL;
Sergunb 0:8918a71cdbe9 607
Sergunb 0:8918a71cdbe9 608 //Successful processing
Sergunb 0:8918a71cdbe9 609 return NO_ERROR;
Sergunb 0:8918a71cdbe9 610 }
Sergunb 0:8918a71cdbe9 611
Sergunb 0:8918a71cdbe9 612
Sergunb 0:8918a71cdbe9 613 /**
Sergunb 0:8918a71cdbe9 614 * @brief Adjust MAC configuration parameters for proper operation
Sergunb 0:8918a71cdbe9 615 * @param[in] interface Underlying network interface
Sergunb 0:8918a71cdbe9 616 * @return Error code
Sergunb 0:8918a71cdbe9 617 **/
Sergunb 0:8918a71cdbe9 618
Sergunb 0:8918a71cdbe9 619 error_t f28m35xEthUpdateMacConfig(NetInterface *interface)
Sergunb 0:8918a71cdbe9 620 {
Sergunb 0:8918a71cdbe9 621 //Half-duplex or full-duplex mode?
Sergunb 0:8918a71cdbe9 622 if(interface->duplexMode == NIC_FULL_DUPLEX_MODE)
Sergunb 0:8918a71cdbe9 623 MAC_TCTL_R |= MAC_TCTL_DUPLEX;
Sergunb 0:8918a71cdbe9 624 else
Sergunb 0:8918a71cdbe9 625 MAC_TCTL_R &= ~MAC_TCTL_DUPLEX;
Sergunb 0:8918a71cdbe9 626
Sergunb 0:8918a71cdbe9 627 //Successful processing
Sergunb 0:8918a71cdbe9 628 return NO_ERROR;
Sergunb 0:8918a71cdbe9 629 }
Sergunb 0:8918a71cdbe9 630
Sergunb 0:8918a71cdbe9 631
Sergunb 0:8918a71cdbe9 632 /**
Sergunb 0:8918a71cdbe9 633 * @brief Write PHY register
Sergunb 0:8918a71cdbe9 634 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 635 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 636 * @param[in] data Register value
Sergunb 0:8918a71cdbe9 637 **/
Sergunb 0:8918a71cdbe9 638
Sergunb 0:8918a71cdbe9 639 void f28m35xEthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data)
Sergunb 0:8918a71cdbe9 640 {
Sergunb 0:8918a71cdbe9 641 //Set PHY address
Sergunb 0:8918a71cdbe9 642 MAC_MAR_R = phyAddr;
Sergunb 0:8918a71cdbe9 643 //Data to be written in the PHY register
Sergunb 0:8918a71cdbe9 644 MAC_MTXD_R = data & MAC_MTXD_MDTX_M;
Sergunb 0:8918a71cdbe9 645 //Start a write operation
Sergunb 0:8918a71cdbe9 646 MAC_MCTL_R = (regAddr << 3) | MAC_MCTL_WRITE | MAC_MCTL_START;
Sergunb 0:8918a71cdbe9 647
Sergunb 0:8918a71cdbe9 648 //Wait for the write to complete
Sergunb 0:8918a71cdbe9 649 while(MAC_MCTL_R & MAC_MCTL_START);
Sergunb 0:8918a71cdbe9 650 }
Sergunb 0:8918a71cdbe9 651
Sergunb 0:8918a71cdbe9 652
Sergunb 0:8918a71cdbe9 653 /**
Sergunb 0:8918a71cdbe9 654 * @brief Read PHY register
Sergunb 0:8918a71cdbe9 655 * @param[in] phyAddr PHY address
Sergunb 0:8918a71cdbe9 656 * @param[in] regAddr Register address
Sergunb 0:8918a71cdbe9 657 * @return Register value
Sergunb 0:8918a71cdbe9 658 **/
Sergunb 0:8918a71cdbe9 659
Sergunb 0:8918a71cdbe9 660 uint16_t f28m35xEthReadPhyReg(uint8_t phyAddr, uint8_t regAddr)
Sergunb 0:8918a71cdbe9 661 {
Sergunb 0:8918a71cdbe9 662 //Set PHY address
Sergunb 0:8918a71cdbe9 663 MAC_MAR_R = phyAddr;
Sergunb 0:8918a71cdbe9 664 //Start a read operation
Sergunb 0:8918a71cdbe9 665 MAC_MCTL_R = (regAddr << 3) | MAC_MCTL_START;
Sergunb 0:8918a71cdbe9 666
Sergunb 0:8918a71cdbe9 667 //Wait for the read to complete
Sergunb 0:8918a71cdbe9 668 while(MAC_MCTL_R & MAC_MCTL_START);
Sergunb 0:8918a71cdbe9 669
Sergunb 0:8918a71cdbe9 670 //Return PHY register contents
Sergunb 0:8918a71cdbe9 671 return MAC_MRXD_R & MAC_MRXD_MDRX_M;
Sergunb 0:8918a71cdbe9 672 }
Sergunb 0:8918a71cdbe9 673