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cyclone_tcp/drivers/enc28j60.h@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file enc28j60.h
Sergunb 0:8918a71cdbe9 3 * @brief ENC28J60 Ethernet controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 #ifndef _ENC28J60_H
Sergunb 0:8918a71cdbe9 30 #define _ENC28J60_H
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Full-duplex support
Sergunb 0:8918a71cdbe9 33 #ifndef ENC28J60_FULL_DUPLEX_SUPPORT
Sergunb 0:8918a71cdbe9 34 #define ENC28J60_FULL_DUPLEX_SUPPORT ENABLED
Sergunb 0:8918a71cdbe9 35 #elif (ENC28J60_FULL_DUPLEX_SUPPORT != ENABLED && ENC28J60_FULL_DUPLEX_SUPPORT != DISABLED)
Sergunb 0:8918a71cdbe9 36 #error ENC28J60_FULL_DUPLEX_SUPPORT parameter is not valid
Sergunb 0:8918a71cdbe9 37 #endif
Sergunb 0:8918a71cdbe9 38
Sergunb 0:8918a71cdbe9 39 //Silicon revision identifiers
Sergunb 0:8918a71cdbe9 40 #define ENC28J60_REV_B1 0x02
Sergunb 0:8918a71cdbe9 41 #define ENC28J60_REV_B4 0x04
Sergunb 0:8918a71cdbe9 42 #define ENC28J60_REV_B5 0x05
Sergunb 0:8918a71cdbe9 43 #define ENC28J60_REV_B7 0x06
Sergunb 0:8918a71cdbe9 44
Sergunb 0:8918a71cdbe9 45 //Receive and transmit buffers
Sergunb 0:8918a71cdbe9 46 #define ENC28J60_RX_BUFFER_START 0x0000
Sergunb 0:8918a71cdbe9 47 #define ENC28J60_RX_BUFFER_STOP 0x17FF
Sergunb 0:8918a71cdbe9 48 #define ENC28J60_TX_BUFFER_START 0x1800
Sergunb 0:8918a71cdbe9 49 #define ENC28J60_TX_BUFFER_STOP 0x1FFF
Sergunb 0:8918a71cdbe9 50
Sergunb 0:8918a71cdbe9 51 //SPI command set
Sergunb 0:8918a71cdbe9 52 #define ENC28J60_CMD_RCR 0x00
Sergunb 0:8918a71cdbe9 53 #define ENC28J60_CMD_RBM 0x3A
Sergunb 0:8918a71cdbe9 54 #define ENC28J60_CMD_WCR 0x40
Sergunb 0:8918a71cdbe9 55 #define ENC28J60_CMD_WBM 0x7A
Sergunb 0:8918a71cdbe9 56 #define ENC28J60_CMD_BFS 0x80
Sergunb 0:8918a71cdbe9 57 #define ENC28J60_CMD_BFC 0xA0
Sergunb 0:8918a71cdbe9 58 #define ENC28J60_CMD_SRC 0xFF
Sergunb 0:8918a71cdbe9 59
Sergunb 0:8918a71cdbe9 60 //ENC28J60 register types
Sergunb 0:8918a71cdbe9 61 #define ETH_REG_TYPE 0x0000
Sergunb 0:8918a71cdbe9 62 #define MAC_REG_TYPE 0x1000
Sergunb 0:8918a71cdbe9 63 #define MII_REG_TYPE 0x2000
Sergunb 0:8918a71cdbe9 64 #define PHY_REG_TYPE 0x3000
Sergunb 0:8918a71cdbe9 65
Sergunb 0:8918a71cdbe9 66 //ENC28J60 banks
Sergunb 0:8918a71cdbe9 67 #define BANK_0 0x0000
Sergunb 0:8918a71cdbe9 68 #define BANK_1 0x0100
Sergunb 0:8918a71cdbe9 69 #define BANK_2 0x0200
Sergunb 0:8918a71cdbe9 70 #define BANK_3 0x0300
Sergunb 0:8918a71cdbe9 71
Sergunb 0:8918a71cdbe9 72 //Related masks
Sergunb 0:8918a71cdbe9 73 #define REG_TYPE_MASK 0xF000
Sergunb 0:8918a71cdbe9 74 #define REG_BANK_MASK 0x0F00
Sergunb 0:8918a71cdbe9 75 #define REG_ADDR_MASK 0x001F
Sergunb 0:8918a71cdbe9 76
Sergunb 0:8918a71cdbe9 77 //Bank 0 registers
Sergunb 0:8918a71cdbe9 78 #define ENC28J60_REG_ERDPTL (ETH_REG_TYPE | BANK_0 | 0x00)
Sergunb 0:8918a71cdbe9 79 #define ENC28J60_REG_ERDPTH (ETH_REG_TYPE | BANK_0 | 0x01)
Sergunb 0:8918a71cdbe9 80 #define ENC28J60_REG_EWRPTL (ETH_REG_TYPE | BANK_0 | 0x02)
Sergunb 0:8918a71cdbe9 81 #define ENC28J60_REG_EWRPTH (ETH_REG_TYPE | BANK_0 | 0x03)
Sergunb 0:8918a71cdbe9 82 #define ENC28J60_REG_ETXSTL (ETH_REG_TYPE | BANK_0 | 0x04)
Sergunb 0:8918a71cdbe9 83 #define ENC28J60_REG_ETXSTH (ETH_REG_TYPE | BANK_0 | 0x05)
Sergunb 0:8918a71cdbe9 84 #define ENC28J60_REG_ETXNDL (ETH_REG_TYPE | BANK_0 | 0x06)
Sergunb 0:8918a71cdbe9 85 #define ENC28J60_REG_ETXNDH (ETH_REG_TYPE | BANK_0 | 0x07)
Sergunb 0:8918a71cdbe9 86 #define ENC28J60_REG_ERXSTL (ETH_REG_TYPE | BANK_0 | 0x08)
Sergunb 0:8918a71cdbe9 87 #define ENC28J60_REG_ERXSTH (ETH_REG_TYPE | BANK_0 | 0x09)
Sergunb 0:8918a71cdbe9 88 #define ENC28J60_REG_ERXNDL (ETH_REG_TYPE | BANK_0 | 0x0A)
Sergunb 0:8918a71cdbe9 89 #define ENC28J60_REG_ERXNDH (ETH_REG_TYPE | BANK_0 | 0x0B)
Sergunb 0:8918a71cdbe9 90 #define ENC28J60_REG_ERXRDPTL (ETH_REG_TYPE | BANK_0 | 0x0C)
Sergunb 0:8918a71cdbe9 91 #define ENC28J60_REG_ERXRDPTH (ETH_REG_TYPE | BANK_0 | 0x0D)
Sergunb 0:8918a71cdbe9 92 #define ENC28J60_REG_ERXWRPTL (ETH_REG_TYPE | BANK_0 | 0x0E)
Sergunb 0:8918a71cdbe9 93 #define ENC28J60_REG_ERXWRPTH (ETH_REG_TYPE | BANK_0 | 0x0F)
Sergunb 0:8918a71cdbe9 94 #define ENC28J60_REG_EDMASTL (ETH_REG_TYPE | BANK_0 | 0x10)
Sergunb 0:8918a71cdbe9 95 #define ENC28J60_REG_EDMASTH (ETH_REG_TYPE | BANK_0 | 0x11)
Sergunb 0:8918a71cdbe9 96 #define ENC28J60_REG_EDMANDL (ETH_REG_TYPE | BANK_0 | 0x12)
Sergunb 0:8918a71cdbe9 97 #define ENC28J60_REG_EDMANDH (ETH_REG_TYPE | BANK_0 | 0x13)
Sergunb 0:8918a71cdbe9 98 #define ENC28J60_REG_EDMADSTL (ETH_REG_TYPE | BANK_0 | 0x14)
Sergunb 0:8918a71cdbe9 99 #define ENC28J60_REG_EDMADSTH (ETH_REG_TYPE | BANK_0 | 0x15)
Sergunb 0:8918a71cdbe9 100 #define ENC28J60_REG_EDMACSL (ETH_REG_TYPE | BANK_0 | 0x16)
Sergunb 0:8918a71cdbe9 101 #define ENC28J60_REG_EDMACSH (ETH_REG_TYPE | BANK_0 | 0x17)
Sergunb 0:8918a71cdbe9 102 #define ENC28J60_REG_EIE (ETH_REG_TYPE | BANK_0 | 0x1B)
Sergunb 0:8918a71cdbe9 103 #define ENC28J60_REG_EIR (ETH_REG_TYPE | BANK_0 | 0x1C)
Sergunb 0:8918a71cdbe9 104 #define ENC28J60_REG_ESTAT (ETH_REG_TYPE | BANK_0 | 0x1D)
Sergunb 0:8918a71cdbe9 105 #define ENC28J60_REG_ECON2 (ETH_REG_TYPE | BANK_0 | 0x1E)
Sergunb 0:8918a71cdbe9 106 #define ENC28J60_REG_ECON1 (ETH_REG_TYPE | BANK_0 | 0x1F)
Sergunb 0:8918a71cdbe9 107
Sergunb 0:8918a71cdbe9 108 //Bank 1 registers
Sergunb 0:8918a71cdbe9 109 #define ENC28J60_REG_EHT0 (ETH_REG_TYPE | BANK_1 | 0x00)
Sergunb 0:8918a71cdbe9 110 #define ENC28J60_REG_EHT1 (ETH_REG_TYPE | BANK_1 | 0x01)
Sergunb 0:8918a71cdbe9 111 #define ENC28J60_REG_EHT2 (ETH_REG_TYPE | BANK_1 | 0x02)
Sergunb 0:8918a71cdbe9 112 #define ENC28J60_REG_EHT3 (ETH_REG_TYPE | BANK_1 | 0x03)
Sergunb 0:8918a71cdbe9 113 #define ENC28J60_REG_EHT4 (ETH_REG_TYPE | BANK_1 | 0x04)
Sergunb 0:8918a71cdbe9 114 #define ENC28J60_REG_EHT5 (ETH_REG_TYPE | BANK_1 | 0x05)
Sergunb 0:8918a71cdbe9 115 #define ENC28J60_REG_EHT6 (ETH_REG_TYPE | BANK_1 | 0x06)
Sergunb 0:8918a71cdbe9 116 #define ENC28J60_REG_EHT7 (ETH_REG_TYPE | BANK_1 | 0x07)
Sergunb 0:8918a71cdbe9 117 #define ENC28J60_REG_EPMM0 (ETH_REG_TYPE | BANK_1 | 0x08)
Sergunb 0:8918a71cdbe9 118 #define ENC28J60_REG_EPMM1 (ETH_REG_TYPE | BANK_1 | 0x09)
Sergunb 0:8918a71cdbe9 119 #define ENC28J60_REG_EPMM2 (ETH_REG_TYPE | BANK_1 | 0x0A)
Sergunb 0:8918a71cdbe9 120 #define ENC28J60_REG_EPMM3 (ETH_REG_TYPE | BANK_1 | 0x0B)
Sergunb 0:8918a71cdbe9 121 #define ENC28J60_REG_EPMM4 (ETH_REG_TYPE | BANK_1 | 0x0C)
Sergunb 0:8918a71cdbe9 122 #define ENC28J60_REG_EPMM5 (ETH_REG_TYPE | BANK_1 | 0x0D)
Sergunb 0:8918a71cdbe9 123 #define ENC28J60_REG_EPMM6 (ETH_REG_TYPE | BANK_1 | 0x0E)
Sergunb 0:8918a71cdbe9 124 #define ENC28J60_REG_EPMM7 (ETH_REG_TYPE | BANK_1 | 0x0F)
Sergunb 0:8918a71cdbe9 125 #define ENC28J60_REG_EPMCSL (ETH_REG_TYPE | BANK_1 | 0x10)
Sergunb 0:8918a71cdbe9 126 #define ENC28J60_REG_EPMCSH (ETH_REG_TYPE | BANK_1 | 0x11)
Sergunb 0:8918a71cdbe9 127 #define ENC28J60_REG_EPMOL (ETH_REG_TYPE | BANK_1 | 0x14)
Sergunb 0:8918a71cdbe9 128 #define ENC28J60_REG_EPMOH (ETH_REG_TYPE | BANK_1 | 0x15)
Sergunb 0:8918a71cdbe9 129 #define ENC28J60_REG_EWOLIE (ETH_REG_TYPE | BANK_1 | 0x16)
Sergunb 0:8918a71cdbe9 130 #define ENC28J60_REG_EWOLIR (ETH_REG_TYPE | BANK_1 | 0x17)
Sergunb 0:8918a71cdbe9 131 #define ENC28J60_REG_ERXFCON (ETH_REG_TYPE | BANK_1 | 0x18)
Sergunb 0:8918a71cdbe9 132 #define ENC28J60_REG_EPKTCNT (ETH_REG_TYPE | BANK_1 | 0x19)
Sergunb 0:8918a71cdbe9 133
Sergunb 0:8918a71cdbe9 134 //Bank 2 registers
Sergunb 0:8918a71cdbe9 135 #define ENC28J60_REG_MACON1 (MAC_REG_TYPE | BANK_2 | 0x00)
Sergunb 0:8918a71cdbe9 136 #define ENC28J60_REG_MACON2 (MAC_REG_TYPE | BANK_2 | 0x01)
Sergunb 0:8918a71cdbe9 137 #define ENC28J60_REG_MACON3 (MAC_REG_TYPE | BANK_2 | 0x02)
Sergunb 0:8918a71cdbe9 138 #define ENC28J60_REG_MACON4 (MAC_REG_TYPE | BANK_2 | 0x03)
Sergunb 0:8918a71cdbe9 139 #define ENC28J60_REG_MABBIPG (MAC_REG_TYPE | BANK_2 | 0x04)
Sergunb 0:8918a71cdbe9 140 #define ENC28J60_REG_MAIPGL (MAC_REG_TYPE | BANK_2 | 0x06)
Sergunb 0:8918a71cdbe9 141 #define ENC28J60_REG_MAIPGH (MAC_REG_TYPE | BANK_2 | 0x07)
Sergunb 0:8918a71cdbe9 142 #define ENC28J60_REG_MACLCON1 (MAC_REG_TYPE | BANK_2 | 0x08)
Sergunb 0:8918a71cdbe9 143 #define ENC28J60_REG_MACLCON2 (MAC_REG_TYPE | BANK_2 | 0x09)
Sergunb 0:8918a71cdbe9 144 #define ENC28J60_REG_MAMXFLL (MAC_REG_TYPE | BANK_2 | 0x0A)
Sergunb 0:8918a71cdbe9 145 #define ENC28J60_REG_MAMXFLH (MAC_REG_TYPE | BANK_2 | 0x0B)
Sergunb 0:8918a71cdbe9 146 #define ENC28J60_REG_MAPHSUP (MAC_REG_TYPE | BANK_2 | 0x0D)
Sergunb 0:8918a71cdbe9 147 #define ENC28J60_REG_MICON (MII_REG_TYPE | BANK_2 | 0x11)
Sergunb 0:8918a71cdbe9 148 #define ENC28J60_REG_MICMD (MII_REG_TYPE | BANK_2 | 0x12)
Sergunb 0:8918a71cdbe9 149 #define ENC28J60_REG_MIREGADR (MII_REG_TYPE | BANK_2 | 0x14)
Sergunb 0:8918a71cdbe9 150 #define ENC28J60_REG_MIWRL (MII_REG_TYPE | BANK_2 | 0x16)
Sergunb 0:8918a71cdbe9 151 #define ENC28J60_REG_MIWRH (MII_REG_TYPE | BANK_2 | 0x17)
Sergunb 0:8918a71cdbe9 152 #define ENC28J60_REG_MIRDL (MII_REG_TYPE | BANK_2 | 0x18)
Sergunb 0:8918a71cdbe9 153 #define ENC28J60_REG_MIRDH (MII_REG_TYPE | BANK_2 | 0x19)
Sergunb 0:8918a71cdbe9 154
Sergunb 0:8918a71cdbe9 155 //Bank 3 registers
Sergunb 0:8918a71cdbe9 156 #define ENC28J60_REG_MAADR5 (MAC_REG_TYPE | BANK_3 | 0x00)
Sergunb 0:8918a71cdbe9 157 #define ENC28J60_REG_MAADR6 (MAC_REG_TYPE | BANK_3 | 0x01)
Sergunb 0:8918a71cdbe9 158 #define ENC28J60_REG_MAADR3 (MAC_REG_TYPE | BANK_3 | 0x02)
Sergunb 0:8918a71cdbe9 159 #define ENC28J60_REG_MAADR4 (MAC_REG_TYPE | BANK_3 | 0x03)
Sergunb 0:8918a71cdbe9 160 #define ENC28J60_REG_MAADR1 (MAC_REG_TYPE | BANK_3 | 0x04)
Sergunb 0:8918a71cdbe9 161 #define ENC28J60_REG_MAADR2 (MAC_REG_TYPE | BANK_3 | 0x05)
Sergunb 0:8918a71cdbe9 162 #define ENC28J60_REG_EBSTSD (ETH_REG_TYPE | BANK_3 | 0x06)
Sergunb 0:8918a71cdbe9 163 #define ENC28J60_REG_EBSTCON (ETH_REG_TYPE | BANK_3 | 0x07)
Sergunb 0:8918a71cdbe9 164 #define ENC28J60_REG_EBSTCSL (ETH_REG_TYPE | BANK_3 | 0x08)
Sergunb 0:8918a71cdbe9 165 #define ENC28J60_REG_EBSTCSH (ETH_REG_TYPE | BANK_3 | 0x09)
Sergunb 0:8918a71cdbe9 166 #define ENC28J60_REG_MISTAT (MII_REG_TYPE | BANK_3 | 0x0A)
Sergunb 0:8918a71cdbe9 167 #define ENC28J60_REG_EREVID (ETH_REG_TYPE | BANK_3 | 0x12)
Sergunb 0:8918a71cdbe9 168 #define ENC28J60_REG_ECOCON (ETH_REG_TYPE | BANK_3 | 0x15)
Sergunb 0:8918a71cdbe9 169 #define ENC28J60_REG_EFLOCON (ETH_REG_TYPE | BANK_3 | 0x17)
Sergunb 0:8918a71cdbe9 170 #define ENC28J60_REG_EPAUSL (ETH_REG_TYPE | BANK_3 | 0x18)
Sergunb 0:8918a71cdbe9 171 #define ENC28J60_REG_EPAUSH (ETH_REG_TYPE | BANK_3 | 0x19)
Sergunb 0:8918a71cdbe9 172
Sergunb 0:8918a71cdbe9 173 //PHY registers
Sergunb 0:8918a71cdbe9 174 #define ENC28J60_PHY_REG_PHCON1 (PHY_REG_TYPE | 0x00)
Sergunb 0:8918a71cdbe9 175 #define ENC28J60_PHY_REG_PHSTAT1 (PHY_REG_TYPE | 0x01)
Sergunb 0:8918a71cdbe9 176 #define ENC28J60_PHY_REG_PHID1 (PHY_REG_TYPE | 0x02)
Sergunb 0:8918a71cdbe9 177 #define ENC28J60_PHY_REG_PHID2 (PHY_REG_TYPE | 0x03)
Sergunb 0:8918a71cdbe9 178 #define ENC28J60_PHY_REG_PHCON2 (PHY_REG_TYPE | 0x10)
Sergunb 0:8918a71cdbe9 179 #define ENC28J60_PHY_REG_PHSTAT2 (PHY_REG_TYPE | 0x11)
Sergunb 0:8918a71cdbe9 180 #define ENC28J60_PHY_REG_PHIE (PHY_REG_TYPE | 0x12)
Sergunb 0:8918a71cdbe9 181 #define ENC28J60_PHY_REG_PHIR (PHY_REG_TYPE | 0x13)
Sergunb 0:8918a71cdbe9 182 #define ENC28J60_PHY_REG_PHLCON (PHY_REG_TYPE | 0x14)
Sergunb 0:8918a71cdbe9 183
Sergunb 0:8918a71cdbe9 184 //EIE register
Sergunb 0:8918a71cdbe9 185 #define EIE_INTIE (1 << 7)
Sergunb 0:8918a71cdbe9 186 #define EIE_PKTIE (1 << 6)
Sergunb 0:8918a71cdbe9 187 #define EIE_DMAIE (1 << 5)
Sergunb 0:8918a71cdbe9 188 #define EIE_LINKIE (1 << 4)
Sergunb 0:8918a71cdbe9 189 #define EIE_TXIE (1 << 3)
Sergunb 0:8918a71cdbe9 190 #define EIE_WOLIE (1 << 2)
Sergunb 0:8918a71cdbe9 191 #define EIE_TXERIE (1 << 1)
Sergunb 0:8918a71cdbe9 192 #define EIE_RXERIE (1 << 0)
Sergunb 0:8918a71cdbe9 193
Sergunb 0:8918a71cdbe9 194 //EIR register
Sergunb 0:8918a71cdbe9 195 #define EIR_PKTIF (1 << 6)
Sergunb 0:8918a71cdbe9 196 #define EIR_DMAIF (1 << 5)
Sergunb 0:8918a71cdbe9 197 #define EIR_LINKIF (1 << 4)
Sergunb 0:8918a71cdbe9 198 #define EIR_TXIF (1 << 3)
Sergunb 0:8918a71cdbe9 199 #define EIR_WOLIF (1 << 2)
Sergunb 0:8918a71cdbe9 200 #define EIR_TXERIF (1 << 1)
Sergunb 0:8918a71cdbe9 201 #define EIR_RXERIF (1 << 0)
Sergunb 0:8918a71cdbe9 202
Sergunb 0:8918a71cdbe9 203 //ESTAT register
Sergunb 0:8918a71cdbe9 204 #define ESTAT_INT (1 << 7)
Sergunb 0:8918a71cdbe9 205 #define ESTAT_LATECOL (1 << 4)
Sergunb 0:8918a71cdbe9 206 #define ESTAT_RXBUSY (1 << 2)
Sergunb 0:8918a71cdbe9 207 #define ESTAT_TXABRT (1 << 1)
Sergunb 0:8918a71cdbe9 208 #define ESTAT_CLKRDY (1 << 0)
Sergunb 0:8918a71cdbe9 209
Sergunb 0:8918a71cdbe9 210 //ECON2 register
Sergunb 0:8918a71cdbe9 211 #define ECON2_AUTOINC (1 << 7)
Sergunb 0:8918a71cdbe9 212 #define ECON2_PKTDEC (1 << 6)
Sergunb 0:8918a71cdbe9 213 #define ECON2_PWRSV (1 << 5)
Sergunb 0:8918a71cdbe9 214 #define ECON2_VRPS (1 << 3)
Sergunb 0:8918a71cdbe9 215
Sergunb 0:8918a71cdbe9 216 //ECON1 register
Sergunb 0:8918a71cdbe9 217 #define ECON1_TXRST (1 << 7)
Sergunb 0:8918a71cdbe9 218 #define ECON1_RXRST (1 << 6)
Sergunb 0:8918a71cdbe9 219 #define ECON1_DMAST (1 << 5)
Sergunb 0:8918a71cdbe9 220 #define ECON1_CSUMEN (1 << 4)
Sergunb 0:8918a71cdbe9 221 #define ECON1_TXRTS (1 << 3)
Sergunb 0:8918a71cdbe9 222 #define ECON1_RXEN (1 << 2)
Sergunb 0:8918a71cdbe9 223 #define ECON1_BSEL1 (1 << 1)
Sergunb 0:8918a71cdbe9 224 #define ECON1_BSEL0 (1 << 0)
Sergunb 0:8918a71cdbe9 225
Sergunb 0:8918a71cdbe9 226 //ERXFCON register
Sergunb 0:8918a71cdbe9 227 #define ERXFCON_UCEN (1 << 7)
Sergunb 0:8918a71cdbe9 228 #define ERXFCON_ANDOR (1 << 6)
Sergunb 0:8918a71cdbe9 229 #define ERXFCON_CRCEN (1 << 5)
Sergunb 0:8918a71cdbe9 230 #define ERXFCON_PMEN (1 << 4)
Sergunb 0:8918a71cdbe9 231 #define ERXFCON_MPEN (1 << 3)
Sergunb 0:8918a71cdbe9 232 #define ERXFCON_HTEN (1 << 2)
Sergunb 0:8918a71cdbe9 233 #define ERXFCON_MCEN (1 << 1)
Sergunb 0:8918a71cdbe9 234 #define ERXFCON_BCEN (1 << 0)
Sergunb 0:8918a71cdbe9 235
Sergunb 0:8918a71cdbe9 236 //MACON1 register
Sergunb 0:8918a71cdbe9 237 #define MACON1_LOOPBK (1 << 4)
Sergunb 0:8918a71cdbe9 238 #define MACON1_TXPAUS (1 << 3)
Sergunb 0:8918a71cdbe9 239 #define MACON1_RXPAUS (1 << 2)
Sergunb 0:8918a71cdbe9 240 #define MACON1_PASSALL (1 << 1)
Sergunb 0:8918a71cdbe9 241 #define MACON1_MARXEN (1 << 0)
Sergunb 0:8918a71cdbe9 242
Sergunb 0:8918a71cdbe9 243 //MACON2 register
Sergunb 0:8918a71cdbe9 244 #define MACON2_MARST (1 << 7)
Sergunb 0:8918a71cdbe9 245 #define MACON2_RNDRST (1 << 6)
Sergunb 0:8918a71cdbe9 246 #define MACON2_MARXRST (1 << 3)
Sergunb 0:8918a71cdbe9 247 #define MACON2_RFUNRST (1 << 2)
Sergunb 0:8918a71cdbe9 248 #define MACON2_MATXRST (1 << 1)
Sergunb 0:8918a71cdbe9 249 #define MACON2_TFUNRST (1 << 0)
Sergunb 0:8918a71cdbe9 250
Sergunb 0:8918a71cdbe9 251 //MACON3 register
Sergunb 0:8918a71cdbe9 252 #define MACON3_PADCFG2 (1 << 7)
Sergunb 0:8918a71cdbe9 253 #define MACON3_PADCFG1 (1 << 6)
Sergunb 0:8918a71cdbe9 254 #define MACON3_PADCFG0 (1 << 5)
Sergunb 0:8918a71cdbe9 255 #define MACON3_TXCRCEN (1 << 4)
Sergunb 0:8918a71cdbe9 256 #define MACON3_PHDRLEN (1 << 3)
Sergunb 0:8918a71cdbe9 257 #define MACON3_HFRMLEN (1 << 2)
Sergunb 0:8918a71cdbe9 258 #define MACON3_FRMLNEN (1 << 1)
Sergunb 0:8918a71cdbe9 259 #define MACON3_FULDPX (1 << 0)
Sergunb 0:8918a71cdbe9 260
Sergunb 0:8918a71cdbe9 261 #define MACON3_PADCFG(x) ((x) << 5)
Sergunb 0:8918a71cdbe9 262
Sergunb 0:8918a71cdbe9 263 //MACON4 register
Sergunb 0:8918a71cdbe9 264 #define MACON4_DEFER (1 << 6)
Sergunb 0:8918a71cdbe9 265 #define MACON4_BPEN (1 << 5)
Sergunb 0:8918a71cdbe9 266 #define MACON4_NOBKOFF (1 << 4)
Sergunb 0:8918a71cdbe9 267 #define MACON4_LONGPRE (1 << 1)
Sergunb 0:8918a71cdbe9 268 #define MACON4_PUREPRE (1 << 0)
Sergunb 0:8918a71cdbe9 269
Sergunb 0:8918a71cdbe9 270 //MAPHSUP register
Sergunb 0:8918a71cdbe9 271 #define MAPHSUP_RSTINTFC (1 << 7)
Sergunb 0:8918a71cdbe9 272 #define MAPHSUP_RSTRMII (1 << 3)
Sergunb 0:8918a71cdbe9 273
Sergunb 0:8918a71cdbe9 274 //MICON register
Sergunb 0:8918a71cdbe9 275 #define MICON_RSTMII (1 << 7)
Sergunb 0:8918a71cdbe9 276
Sergunb 0:8918a71cdbe9 277 //MICMD register
Sergunb 0:8918a71cdbe9 278 #define MICMD_MIISCAN (1 << 1)
Sergunb 0:8918a71cdbe9 279 #define MICMD_MIIRD (1 << 0)
Sergunb 0:8918a71cdbe9 280
Sergunb 0:8918a71cdbe9 281 //EBSTCON register
Sergunb 0:8918a71cdbe9 282 #define EBSTCON_PSV2 (1 << 7)
Sergunb 0:8918a71cdbe9 283 #define EBSTCON_PSV1 (1 << 6)
Sergunb 0:8918a71cdbe9 284 #define EBSTCON_PSV0 (1 << 5)
Sergunb 0:8918a71cdbe9 285 #define EBSTCON_PSEL (1 << 4)
Sergunb 0:8918a71cdbe9 286 #define EBSTCON_TMSEL1 (1 << 3)
Sergunb 0:8918a71cdbe9 287 #define EBSTCON_TMSEL0 (1 << 2)
Sergunb 0:8918a71cdbe9 288 #define EBSTCON_TME (1 << 1)
Sergunb 0:8918a71cdbe9 289 #define EBSTCON_BISTST (1 << 0)
Sergunb 0:8918a71cdbe9 290
Sergunb 0:8918a71cdbe9 291 //MISTAT register
Sergunb 0:8918a71cdbe9 292 #define MISTAT_NVALID (1 << 2)
Sergunb 0:8918a71cdbe9 293 #define MISTAT_SCAN (1 << 1)
Sergunb 0:8918a71cdbe9 294 #define MISTAT_BUSY (1 << 0)
Sergunb 0:8918a71cdbe9 295
Sergunb 0:8918a71cdbe9 296 //ECOCON register
Sergunb 0:8918a71cdbe9 297 #define ECOCON_COCON2 (1 << 2)
Sergunb 0:8918a71cdbe9 298 #define ECOCON_COCON1 (1 << 1)
Sergunb 0:8918a71cdbe9 299 #define ECOCON_COCON0 (1 << 0)
Sergunb 0:8918a71cdbe9 300
Sergunb 0:8918a71cdbe9 301 //EFLOCON register
Sergunb 0:8918a71cdbe9 302 #define EFLOCON_FULDPXS (1 << 2)
Sergunb 0:8918a71cdbe9 303 #define EFLOCON_FCEN1 (1 << 1)
Sergunb 0:8918a71cdbe9 304 #define EFLOCON_FCEN0 (1 << 0)
Sergunb 0:8918a71cdbe9 305
Sergunb 0:8918a71cdbe9 306 //PHCON1 register
Sergunb 0:8918a71cdbe9 307 #define PHCON1_PRST (1 << 15)
Sergunb 0:8918a71cdbe9 308 #define PHCON1_PLOOPBK (1 << 14)
Sergunb 0:8918a71cdbe9 309 #define PHCON1_PPWRSV (1 << 11)
Sergunb 0:8918a71cdbe9 310 #define PHCON1_PDPXMD (1 << 8)
Sergunb 0:8918a71cdbe9 311
Sergunb 0:8918a71cdbe9 312 //PHSTAT1 register
Sergunb 0:8918a71cdbe9 313 #define PHSTAT1_PFDPX (1 << 12)
Sergunb 0:8918a71cdbe9 314 #define PHSTAT1_PHDPX (1 << 11)
Sergunb 0:8918a71cdbe9 315 #define PHSTAT1_LLSTAT (1 << 2)
Sergunb 0:8918a71cdbe9 316 #define PHSTAT1_JBSTAT (1 << 1)
Sergunb 0:8918a71cdbe9 317
Sergunb 0:8918a71cdbe9 318 //PHCON2 register
Sergunb 0:8918a71cdbe9 319 #define PHCON2_FRCLINK (1 << 14)
Sergunb 0:8918a71cdbe9 320 #define PHCON2_TXDIS (1 << 13)
Sergunb 0:8918a71cdbe9 321 #define PHCON2_JABBER (1 << 10)
Sergunb 0:8918a71cdbe9 322 #define PHCON2_HDLDIS (1 << 8)
Sergunb 0:8918a71cdbe9 323
Sergunb 0:8918a71cdbe9 324 //PHSTAT2 register
Sergunb 0:8918a71cdbe9 325 #define PHSTAT2_TXSTAT (1 << 13)
Sergunb 0:8918a71cdbe9 326 #define PHSTAT2_RXSTAT (1 << 12)
Sergunb 0:8918a71cdbe9 327 #define PHSTAT2_COLSTAT (1 << 11)
Sergunb 0:8918a71cdbe9 328 #define PHSTAT2_LSTAT (1 << 10)
Sergunb 0:8918a71cdbe9 329 #define PHSTAT2_DPXSTAT (1 << 9)
Sergunb 0:8918a71cdbe9 330 #define PHSTAT2_PLRITY (1 << 4)
Sergunb 0:8918a71cdbe9 331
Sergunb 0:8918a71cdbe9 332 //PHIE register
Sergunb 0:8918a71cdbe9 333 #define PHIE_PLNKIE (1 << 4)
Sergunb 0:8918a71cdbe9 334 #define PHIE_PGEIE (1 << 1)
Sergunb 0:8918a71cdbe9 335
Sergunb 0:8918a71cdbe9 336 //PHIR register
Sergunb 0:8918a71cdbe9 337 #define PHIR_PLNKIF (1 << 4)
Sergunb 0:8918a71cdbe9 338 #define PHIR_PGIF (1 << 2)
Sergunb 0:8918a71cdbe9 339
Sergunb 0:8918a71cdbe9 340 //PHLCON register
Sergunb 0:8918a71cdbe9 341 #define PHLCON_LACFG3 (1 << 11)
Sergunb 0:8918a71cdbe9 342 #define PHLCON_LACFG2 (1 << 10)
Sergunb 0:8918a71cdbe9 343 #define PHLCON_LACFG1 (1 << 9)
Sergunb 0:8918a71cdbe9 344 #define PHLCON_LACFG0 (1 << 8)
Sergunb 0:8918a71cdbe9 345 #define PHLCON_LBCFG3 (1 << 7)
Sergunb 0:8918a71cdbe9 346 #define PHLCON_LBCFG2 (1 << 6)
Sergunb 0:8918a71cdbe9 347 #define PHLCON_LBCFG1 (1 << 5)
Sergunb 0:8918a71cdbe9 348 #define PHLCON_LBCFG0 (1 << 4)
Sergunb 0:8918a71cdbe9 349 #define PHLCON_LFRQ1 (1 << 3)
Sergunb 0:8918a71cdbe9 350 #define PHLCON_LFRQ0 (1 << 2)
Sergunb 0:8918a71cdbe9 351 #define PHLCON_STRCH (1 << 1)
Sergunb 0:8918a71cdbe9 352
Sergunb 0:8918a71cdbe9 353 #define PHLCON_LACFG(x) ((x) << 8)
Sergunb 0:8918a71cdbe9 354 #define PHLCON_LBCFG(x) ((x) << 4)
Sergunb 0:8918a71cdbe9 355 #define PHLCON_LFRQ(x) ((x) << 2)
Sergunb 0:8918a71cdbe9 356
Sergunb 0:8918a71cdbe9 357 //Per-packet control byte
Sergunb 0:8918a71cdbe9 358 #define TX_CTRL_PHUGEEN (1 << 3)
Sergunb 0:8918a71cdbe9 359 #define TX_CTRL_PPADEN (1 << 2)
Sergunb 0:8918a71cdbe9 360 #define TX_CTRL_PCRCEN (1 << 1)
Sergunb 0:8918a71cdbe9 361 #define TX_CTRL_POVERRIDE (1 << 0)
Sergunb 0:8918a71cdbe9 362
Sergunb 0:8918a71cdbe9 363 //Receive status vector
Sergunb 0:8918a71cdbe9 364 #define RSV_VLAN_TYPE 0x4000
Sergunb 0:8918a71cdbe9 365 #define RSV_UNKNOWN_OPCODE 0x2000
Sergunb 0:8918a71cdbe9 366 #define RSV_PAUSE_CONTROL_FRAME 0x1000
Sergunb 0:8918a71cdbe9 367 #define RSV_CONTROL_FRAME 0x0800
Sergunb 0:8918a71cdbe9 368 #define RSV_DRIBBLE_NIBBLE 0x0400
Sergunb 0:8918a71cdbe9 369 #define RSV_BROADCAST_PACKET 0x0200
Sergunb 0:8918a71cdbe9 370 #define RSV_MULTICAST_PACKET 0x0100
Sergunb 0:8918a71cdbe9 371 #define RSV_RECEIVED_OK 0x0080
Sergunb 0:8918a71cdbe9 372 #define RSV_LENGTH_OUT_OF_RANGE 0x0040
Sergunb 0:8918a71cdbe9 373 #define RSV_LENGTH_CHECK_ERROR 0x0020
Sergunb 0:8918a71cdbe9 374 #define RSV_CRC_ERROR 0x0010
Sergunb 0:8918a71cdbe9 375 #define RSV_CARRIER_EVENT 0x0004
Sergunb 0:8918a71cdbe9 376 #define RSV_DROP_EVENT 0x0001
Sergunb 0:8918a71cdbe9 377
Sergunb 0:8918a71cdbe9 378
Sergunb 0:8918a71cdbe9 379 /**
Sergunb 0:8918a71cdbe9 380 * @brief ENC28J60 driver context
Sergunb 0:8918a71cdbe9 381 **/
Sergunb 0:8918a71cdbe9 382
Sergunb 0:8918a71cdbe9 383 typedef struct
Sergunb 0:8918a71cdbe9 384 {
Sergunb 0:8918a71cdbe9 385 uint16_t currentBank; ///<Current bank
Sergunb 0:8918a71cdbe9 386 uint16_t nextPacket; ///<Next packet in the receive buffer
Sergunb 0:8918a71cdbe9 387 uint8_t *rxBuffer; ///<Receive buffer
Sergunb 0:8918a71cdbe9 388 } Enc28j60Context;
Sergunb 0:8918a71cdbe9 389
Sergunb 0:8918a71cdbe9 390
Sergunb 0:8918a71cdbe9 391 //ENC28J60 driver
Sergunb 0:8918a71cdbe9 392 extern const NicDriver enc28j60Driver;
Sergunb 0:8918a71cdbe9 393
Sergunb 0:8918a71cdbe9 394 //ENC28J60 related functions
Sergunb 0:8918a71cdbe9 395 error_t enc28j60Init(NetInterface *interface);
Sergunb 0:8918a71cdbe9 396
Sergunb 0:8918a71cdbe9 397 void enc28j60Tick(NetInterface *interface);
Sergunb 0:8918a71cdbe9 398
Sergunb 0:8918a71cdbe9 399 void enc28j60EnableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 400 void enc28j60DisableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 401 bool_t enc28j60IrqHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 402 void enc28j60EventHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 403
Sergunb 0:8918a71cdbe9 404 error_t enc28j60SendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 405 const NetBuffer *buffer, size_t offset);
Sergunb 0:8918a71cdbe9 406
Sergunb 0:8918a71cdbe9 407 error_t enc28j60ReceivePacket(NetInterface *interface);
Sergunb 0:8918a71cdbe9 408
Sergunb 0:8918a71cdbe9 409 error_t enc28j60SetMulticastFilter(NetInterface *interface);
Sergunb 0:8918a71cdbe9 410
Sergunb 0:8918a71cdbe9 411 void enc28j60SoftReset(NetInterface *interface);
Sergunb 0:8918a71cdbe9 412 void enc28j60SelectBank(NetInterface *interface, uint16_t address);
Sergunb 0:8918a71cdbe9 413
Sergunb 0:8918a71cdbe9 414 void enc28j60WriteReg(NetInterface *interface, uint16_t address, uint8_t data);
Sergunb 0:8918a71cdbe9 415 uint8_t enc28j60ReadReg(NetInterface *interface, uint16_t address);
Sergunb 0:8918a71cdbe9 416
Sergunb 0:8918a71cdbe9 417 void enc28j60WritePhyReg(NetInterface *interface, uint16_t address, uint16_t data);
Sergunb 0:8918a71cdbe9 418 uint16_t enc28j60ReadPhyReg(NetInterface *interface, uint16_t address);
Sergunb 0:8918a71cdbe9 419
Sergunb 0:8918a71cdbe9 420 void enc28j60WriteBuffer(NetInterface *interface,
Sergunb 0:8918a71cdbe9 421 const NetBuffer *buffer, size_t offset);
Sergunb 0:8918a71cdbe9 422
Sergunb 0:8918a71cdbe9 423 void enc28j60ReadBuffer(NetInterface *interface,
Sergunb 0:8918a71cdbe9 424 uint8_t *data, size_t length);
Sergunb 0:8918a71cdbe9 425
Sergunb 0:8918a71cdbe9 426 void enc28j60SetBit(NetInterface *interface, uint16_t address, uint16_t mask);
Sergunb 0:8918a71cdbe9 427 void enc28j60ClearBit(NetInterface *interface, uint16_t address, uint16_t mask);
Sergunb 0:8918a71cdbe9 428
Sergunb 0:8918a71cdbe9 429 uint32_t enc28j60CalcCrc(const void *data, size_t length);
Sergunb 0:8918a71cdbe9 430
Sergunb 0:8918a71cdbe9 431 void enc28j60DumpReg(NetInterface *interface);
Sergunb 0:8918a71cdbe9 432 void enc28j60DumpPhyReg(NetInterface *interface);
Sergunb 0:8918a71cdbe9 433
Sergunb 0:8918a71cdbe9 434 #endif
Sergunb 0:8918a71cdbe9 435