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cyclone_tcp/drivers/dp83848.h@0:8918a71cdbe9, 2017-02-04 (annotated)

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
nothing else

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file dp83848.h
Sergunb 0:8918a71cdbe9 3 * @brief DP83848 Ethernet PHY transceiver
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 #ifndef _DP83848_H
Sergunb 0:8918a71cdbe9 30 #define _DP83848_H
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Dependencies
Sergunb 0:8918a71cdbe9 33 #include "core/nic.h"
Sergunb 0:8918a71cdbe9 34
Sergunb 0:8918a71cdbe9 35 //PHY address
Sergunb 0:8918a71cdbe9 36 #ifndef DP83848_PHY_ADDR
Sergunb 0:8918a71cdbe9 37 #define DP83848_PHY_ADDR 1
Sergunb 0:8918a71cdbe9 38 #elif (DP83848_PHY_ADDR < 0 || DP83848_PHY_ADDR > 31)
Sergunb 0:8918a71cdbe9 39 #error DP83848_PHY_ADDR parameter is not valid
Sergunb 0:8918a71cdbe9 40 #endif
Sergunb 0:8918a71cdbe9 41
Sergunb 0:8918a71cdbe9 42 //DP83848 registers
Sergunb 0:8918a71cdbe9 43 #define DP83848_PHY_REG_BMCR 0x00
Sergunb 0:8918a71cdbe9 44 #define DP83848_PHY_REG_BMSR 0x01
Sergunb 0:8918a71cdbe9 45 #define DP83848_PHY_REG_PHYIDR1 0x02
Sergunb 0:8918a71cdbe9 46 #define DP83848_PHY_REG_PHYIDR2 0x03
Sergunb 0:8918a71cdbe9 47 #define DP83848_PHY_REG_ANAR 0x04
Sergunb 0:8918a71cdbe9 48 #define DP83848_PHY_REG_ANLPAR 0x05
Sergunb 0:8918a71cdbe9 49 #define DP83848_PHY_REG_ANER 0x06
Sergunb 0:8918a71cdbe9 50 #define DP83848_PHY_REG_ANNPTR 0x07
Sergunb 0:8918a71cdbe9 51 #define DP83848_PHY_REG_PHYSTS 0x10
Sergunb 0:8918a71cdbe9 52 #define DP83848_PHY_REG_MICR 0x11
Sergunb 0:8918a71cdbe9 53 #define DP83848_PHY_REG_MISR 0x12
Sergunb 0:8918a71cdbe9 54 #define DP83848_PHY_REG_FCSCR 0x14
Sergunb 0:8918a71cdbe9 55 #define DP83848_PHY_REG_RECR 0x15
Sergunb 0:8918a71cdbe9 56 #define DP83848_PHY_REG_PCSR 0x16
Sergunb 0:8918a71cdbe9 57 #define DP83848_PHY_REG_RBR 0x17
Sergunb 0:8918a71cdbe9 58 #define DP83848_PHY_REG_LEDCR 0x18
Sergunb 0:8918a71cdbe9 59 #define DP83848_PHY_REG_PHYCR 0x19
Sergunb 0:8918a71cdbe9 60 #define DP83848_PHY_REG_10BTSCR 0x1A
Sergunb 0:8918a71cdbe9 61 #define DP83848_PHY_REG_CDCTRL1 0x1B
Sergunb 0:8918a71cdbe9 62 #define DP83848_PHY_REG_EDCR 0x1D
Sergunb 0:8918a71cdbe9 63
Sergunb 0:8918a71cdbe9 64 //BMCR register
Sergunb 0:8918a71cdbe9 65 #define BMCR_RESET (1 << 15)
Sergunb 0:8918a71cdbe9 66 #define BMCR_LOOPBACK (1 << 14)
Sergunb 0:8918a71cdbe9 67 #define BMCR_SPEED_SEL (1 << 13)
Sergunb 0:8918a71cdbe9 68 #define BMCR_AN_EN (1 << 12)
Sergunb 0:8918a71cdbe9 69 #define BMCR_POWER_DOWN (1 << 11)
Sergunb 0:8918a71cdbe9 70 #define BMCR_ISOLATE (1 << 10)
Sergunb 0:8918a71cdbe9 71 #define BMCR_RESTART_AN (1 << 9)
Sergunb 0:8918a71cdbe9 72 #define BMCR_DUPLEX_MODE (1 << 8)
Sergunb 0:8918a71cdbe9 73 #define BMCR_COL_TEST (1 << 7)
Sergunb 0:8918a71cdbe9 74
Sergunb 0:8918a71cdbe9 75 //BMSR register
Sergunb 0:8918a71cdbe9 76 #define BMSR_100BT4 (1 << 15)
Sergunb 0:8918a71cdbe9 77 #define BMSR_100BTX_FD (1 << 14)
Sergunb 0:8918a71cdbe9 78 #define BMSR_100BTX (1 << 13)
Sergunb 0:8918a71cdbe9 79 #define BMSR_10BT_FD (1 << 12)
Sergunb 0:8918a71cdbe9 80 #define BMSR_10BT (1 << 11)
Sergunb 0:8918a71cdbe9 81 #define BMSR_NO_PREAMBLE (1 << 6)
Sergunb 0:8918a71cdbe9 82 #define BMSR_AN_COMPLETE (1 << 5)
Sergunb 0:8918a71cdbe9 83 #define BMSR_REMOTE_FAULT (1 << 4)
Sergunb 0:8918a71cdbe9 84 #define BMSR_AN_ABLE (1 << 3)
Sergunb 0:8918a71cdbe9 85 #define BMSR_LINK_STATUS (1 << 2)
Sergunb 0:8918a71cdbe9 86 #define BMSR_JABBER_DETECT (1 << 1)
Sergunb 0:8918a71cdbe9 87 #define BMSR_EXTENDED_CAP (1 << 0)
Sergunb 0:8918a71cdbe9 88
Sergunb 0:8918a71cdbe9 89 //ANAR register
Sergunb 0:8918a71cdbe9 90 #define ANAR_NP (1 << 15)
Sergunb 0:8918a71cdbe9 91 #define ANAR_RF (1 << 13)
Sergunb 0:8918a71cdbe9 92 #define ANAR_ASM_DIR (1 << 11)
Sergunb 0:8918a71cdbe9 93 #define ANAR_PAUSE (1 << 10)
Sergunb 0:8918a71cdbe9 94 #define ANAR_100BT4 (1 << 9)
Sergunb 0:8918a71cdbe9 95 #define ANAR_100BTX_FD (1 << 8)
Sergunb 0:8918a71cdbe9 96 #define ANAR_100BTX (1 << 7)
Sergunb 0:8918a71cdbe9 97 #define ANAR_10BT_FD (1 << 6)
Sergunb 0:8918a71cdbe9 98 #define ANAR_10BT (1 << 5)
Sergunb 0:8918a71cdbe9 99 #define ANAR_SELECTOR4 (1 << 4)
Sergunb 0:8918a71cdbe9 100 #define ANAR_SELECTOR3 (1 << 3)
Sergunb 0:8918a71cdbe9 101 #define ANAR_SELECTOR2 (1 << 2)
Sergunb 0:8918a71cdbe9 102 #define ANAR_SELECTOR1 (1 << 1)
Sergunb 0:8918a71cdbe9 103 #define ANAR_SELECTOR0 (1 << 0)
Sergunb 0:8918a71cdbe9 104
Sergunb 0:8918a71cdbe9 105 //ANLPAR register
Sergunb 0:8918a71cdbe9 106 #define ANLPAR_NP (1 << 15)
Sergunb 0:8918a71cdbe9 107 #define ANLPAR_ACK (1 << 14)
Sergunb 0:8918a71cdbe9 108 #define ANLPAR_RF (1 << 13)
Sergunb 0:8918a71cdbe9 109 #define ANLPAR_ASM_DIR (1 << 11)
Sergunb 0:8918a71cdbe9 110 #define ANLPAR_PAUSE (1 << 10)
Sergunb 0:8918a71cdbe9 111 #define ANLPAR_100BT4 (1 << 9)
Sergunb 0:8918a71cdbe9 112 #define ANLPAR_100BTX_FD (1 << 8)
Sergunb 0:8918a71cdbe9 113 #define ANLPAR_100BTX (1 << 7)
Sergunb 0:8918a71cdbe9 114 #define ANLPAR_10BT_FD (1 << 6)
Sergunb 0:8918a71cdbe9 115 #define ANLPAR_10BT (1 << 5)
Sergunb 0:8918a71cdbe9 116 #define ANLPAR_SELECTOR4 (1 << 4)
Sergunb 0:8918a71cdbe9 117 #define ANLPAR_SELECTOR3 (1 << 3)
Sergunb 0:8918a71cdbe9 118 #define ANLPAR_SELECTOR2 (1 << 2)
Sergunb 0:8918a71cdbe9 119 #define ANLPAR_SELECTOR1 (1 << 1)
Sergunb 0:8918a71cdbe9 120 #define ANLPAR_SELECTOR0 (1 << 0)
Sergunb 0:8918a71cdbe9 121
Sergunb 0:8918a71cdbe9 122 //ANER register
Sergunb 0:8918a71cdbe9 123 #define ANER_PDF (1 << 4)
Sergunb 0:8918a71cdbe9 124 #define ANER_LP_NP_ABLE (1 << 3)
Sergunb 0:8918a71cdbe9 125 #define ANER_NP_ABLE (1 << 2)
Sergunb 0:8918a71cdbe9 126 #define ANER_PAGE_RX (1 << 1)
Sergunb 0:8918a71cdbe9 127 #define ANER_LP_AN_ABLE (1 << 0)
Sergunb 0:8918a71cdbe9 128
Sergunb 0:8918a71cdbe9 129 //ANNPTR register
Sergunb 0:8918a71cdbe9 130 #define ANNPTR_NP (1 << 15)
Sergunb 0:8918a71cdbe9 131 #define ANNPTR_MP (1 << 13)
Sergunb 0:8918a71cdbe9 132 #define ANNPTR_ACK2 (1 << 12)
Sergunb 0:8918a71cdbe9 133 #define ANNPTR_TOG_TX (1 << 11)
Sergunb 0:8918a71cdbe9 134 #define ANNPTR_CODE10 (1 << 10)
Sergunb 0:8918a71cdbe9 135 #define ANNPTR_CODE9 (1 << 9)
Sergunb 0:8918a71cdbe9 136 #define ANNPTR_CODE8 (1 << 8)
Sergunb 0:8918a71cdbe9 137 #define ANNPTR_CODE7 (1 << 7)
Sergunb 0:8918a71cdbe9 138 #define ANNPTR_CODE6 (1 << 6)
Sergunb 0:8918a71cdbe9 139 #define ANNPTR_CODE5 (1 << 5)
Sergunb 0:8918a71cdbe9 140 #define ANNPTR_CODE4 (1 << 4)
Sergunb 0:8918a71cdbe9 141 #define ANNPTR_CODE3 (1 << 3)
Sergunb 0:8918a71cdbe9 142 #define ANNPTR_CODE2 (1 << 2)
Sergunb 0:8918a71cdbe9 143 #define ANNPTR_CODE1 (1 << 1)
Sergunb 0:8918a71cdbe9 144 #define ANNPTR_CODE0 (1 << 0)
Sergunb 0:8918a71cdbe9 145
Sergunb 0:8918a71cdbe9 146 //PHYSTS register
Sergunb 0:8918a71cdbe9 147 #define PHYSTS_MDIX_MODE (1 << 14)
Sergunb 0:8918a71cdbe9 148 #define PHYSTS_RX_ERROR_LATCH (1 << 13)
Sergunb 0:8918a71cdbe9 149 #define PHYSTS_POLARITY_STATUS (1 << 12)
Sergunb 0:8918a71cdbe9 150 #define PHYSTS_FALSE_CARRIER_SENSE (1 << 11)
Sergunb 0:8918a71cdbe9 151 #define PHYSTS_SIGNAL_DETECT (1 << 10)
Sergunb 0:8918a71cdbe9 152 #define PHYSTS_DESCRAMBLER_LOCK (1 << 9)
Sergunb 0:8918a71cdbe9 153 #define PHYSTS_PAGE_RECEIVED (1 << 8)
Sergunb 0:8918a71cdbe9 154 #define PHYSTS_MII_INTERRUPT (1 << 7)
Sergunb 0:8918a71cdbe9 155 #define PHYSTS_REMOTE_FAULT (1 << 6)
Sergunb 0:8918a71cdbe9 156 #define PHYSTS_JABBER_DETECT (1 << 5)
Sergunb 0:8918a71cdbe9 157 #define PHYSTS_AN_COMPLETE (1 << 4)
Sergunb 0:8918a71cdbe9 158 #define PHYSTS_LOOPBACK_STATUS (1 << 3)
Sergunb 0:8918a71cdbe9 159 #define PHYSTS_DUPLEX_STATUS (1 << 2)
Sergunb 0:8918a71cdbe9 160 #define PHYSTS_SPEED_STATUS (1 << 1)
Sergunb 0:8918a71cdbe9 161 #define PHYSTS_LINK_STATUS (1 << 0)
Sergunb 0:8918a71cdbe9 162
Sergunb 0:8918a71cdbe9 163 //MICR register
Sergunb 0:8918a71cdbe9 164 #define MICR_TINT (1 << 2)
Sergunb 0:8918a71cdbe9 165 #define MICR_INTEN (1 << 1)
Sergunb 0:8918a71cdbe9 166 #define MICR_INT_OE (1 << 0)
Sergunb 0:8918a71cdbe9 167
Sergunb 0:8918a71cdbe9 168 //MISR register
Sergunb 0:8918a71cdbe9 169 #define MISR_ED_INT (1 << 14)
Sergunb 0:8918a71cdbe9 170 #define MISR_LINK_INT (1 << 13)
Sergunb 0:8918a71cdbe9 171 #define MISR_SPD_INT (1 << 12)
Sergunb 0:8918a71cdbe9 172 #define MISR_DUP_INT (1 << 11)
Sergunb 0:8918a71cdbe9 173 #define MISR_ANC_INT (1 << 10)
Sergunb 0:8918a71cdbe9 174 #define MISR_FHF_INT (1 << 9)
Sergunb 0:8918a71cdbe9 175 #define MISR_RHF_INT (1 << 8)
Sergunb 0:8918a71cdbe9 176 #define MISR_ED_INT_EN (1 << 6)
Sergunb 0:8918a71cdbe9 177 #define MISR_LINK_INT_EN (1 << 5)
Sergunb 0:8918a71cdbe9 178 #define MISR_SPD_INT_EN (1 << 4)
Sergunb 0:8918a71cdbe9 179 #define MISR_DUP_INT_EN (1 << 3)
Sergunb 0:8918a71cdbe9 180 #define MISR_ANC_INT_EN (1 << 2)
Sergunb 0:8918a71cdbe9 181 #define MISR_FHF_INT_EN (1 << 1)
Sergunb 0:8918a71cdbe9 182 #define MISR_RHF_INT_EN (1 << 0)
Sergunb 0:8918a71cdbe9 183
Sergunb 0:8918a71cdbe9 184 //FCSCR register
Sergunb 0:8918a71cdbe9 185 #define FCSCR_FCSCNT7 (1 << 7)
Sergunb 0:8918a71cdbe9 186 #define FCSCR_FCSCNT6 (1 << 6)
Sergunb 0:8918a71cdbe9 187 #define FCSCR_FCSCNT5 (1 << 5)
Sergunb 0:8918a71cdbe9 188 #define FCSCR_FCSCNT4 (1 << 4)
Sergunb 0:8918a71cdbe9 189 #define FCSCR_FCSCNT3 (1 << 3)
Sergunb 0:8918a71cdbe9 190 #define FCSCR_FCSCNT2 (1 << 2)
Sergunb 0:8918a71cdbe9 191 #define FCSCR_FCSCNT1 (1 << 1)
Sergunb 0:8918a71cdbe9 192 #define FCSCR_FCSCNT0 (1 << 0)
Sergunb 0:8918a71cdbe9 193
Sergunb 0:8918a71cdbe9 194 //RECR register
Sergunb 0:8918a71cdbe9 195 #define RECR_RXERCNT7 (1 << 7)
Sergunb 0:8918a71cdbe9 196 #define RECR_RXERCNT6 (1 << 6)
Sergunb 0:8918a71cdbe9 197 #define RECR_RXERCNT5 (1 << 5)
Sergunb 0:8918a71cdbe9 198 #define RECR_RXERCNT4 (1 << 4)
Sergunb 0:8918a71cdbe9 199 #define RECR_RXERCNT3 (1 << 3)
Sergunb 0:8918a71cdbe9 200 #define RECR_RXERCNT2 (1 << 2)
Sergunb 0:8918a71cdbe9 201 #define RECR_RXERCNT1 (1 << 1)
Sergunb 0:8918a71cdbe9 202 #define RECR_RXERCNT0 (1 << 0)
Sergunb 0:8918a71cdbe9 203
Sergunb 0:8918a71cdbe9 204 //PCSR register
Sergunb 0:8918a71cdbe9 205 #define PCSR_TQ_EN (1 << 10)
Sergunb 0:8918a71cdbe9 206 #define PCSR_SD_FORCE_PMA (1 << 9)
Sergunb 0:8918a71cdbe9 207 #define PCSR_SD_OPTION (1 << 8)
Sergunb 0:8918a71cdbe9 208 #define PCSR_DESC_TIME (1 << 7)
Sergunb 0:8918a71cdbe9 209 #define PCSR_FORCE_100_OK (1 << 5)
Sergunb 0:8918a71cdbe9 210 #define PCSR_NRZI_BYPASS (1 << 2)
Sergunb 0:8918a71cdbe9 211
Sergunb 0:8918a71cdbe9 212 //RBR register
Sergunb 0:8918a71cdbe9 213 #define RBR_RMII_MODE (1 << 5)
Sergunb 0:8918a71cdbe9 214 #define RBR_RMII_REV1_0 (1 << 4)
Sergunb 0:8918a71cdbe9 215 #define RBR_RX_OVF_STS (1 << 3)
Sergunb 0:8918a71cdbe9 216 #define RBR_RX_UNF_STS (1 << 2)
Sergunb 0:8918a71cdbe9 217 #define RBR_ELAST_BUF1 (1 << 1)
Sergunb 0:8918a71cdbe9 218 #define RBR_ELAST_BUF0 (1 << 0)
Sergunb 0:8918a71cdbe9 219
Sergunb 0:8918a71cdbe9 220 //LEDCR register
Sergunb 0:8918a71cdbe9 221 #define LEDCR_DRV_SPDLED (1 << 5)
Sergunb 0:8918a71cdbe9 222 #define LEDCR_DRV_LNKLED (1 << 4)
Sergunb 0:8918a71cdbe9 223 #define LEDCR_DRV_ACTLED (1 << 3)
Sergunb 0:8918a71cdbe9 224 #define LEDCR_SPDLED (1 << 2)
Sergunb 0:8918a71cdbe9 225 #define LEDCR_LNKLED (1 << 1)
Sergunb 0:8918a71cdbe9 226 #define LEDCR_ACTLED (1 << 0)
Sergunb 0:8918a71cdbe9 227
Sergunb 0:8918a71cdbe9 228 //PHYCR register
Sergunb 0:8918a71cdbe9 229 #define PHYCR_MDIX_EN (1 << 15)
Sergunb 0:8918a71cdbe9 230 #define PHYCR_FORCE_MDIX (1 << 14)
Sergunb 0:8918a71cdbe9 231 #define PHYCR_PAUSE_RX (1 << 13)
Sergunb 0:8918a71cdbe9 232 #define PHYCR_PAUSE_TX (1 << 12)
Sergunb 0:8918a71cdbe9 233 #define PHYCR_BIST_FE (1 << 11)
Sergunb 0:8918a71cdbe9 234 #define PHYCR_PSR_15 (1 << 10)
Sergunb 0:8918a71cdbe9 235 #define PHYCR_BIST_STATUS (1 << 9)
Sergunb 0:8918a71cdbe9 236 #define PHYCR_BIST_START (1 << 8)
Sergunb 0:8918a71cdbe9 237 #define PHYCR_BP_STRETCH (1 << 7)
Sergunb 0:8918a71cdbe9 238 #define PHYCR_LED_CNFG1 (1 << 6)
Sergunb 0:8918a71cdbe9 239 #define PHYCR_LED_CNFG0 (1 << 5)
Sergunb 0:8918a71cdbe9 240 #define PHYCR_PHYADDR4 (1 << 4)
Sergunb 0:8918a71cdbe9 241 #define PHYCR_PHYADDR3 (1 << 3)
Sergunb 0:8918a71cdbe9 242 #define PHYCR_PHYADDR2 (1 << 2)
Sergunb 0:8918a71cdbe9 243 #define PHYCR_PHYADDR1 (1 << 1)
Sergunb 0:8918a71cdbe9 244 #define PHYCR_PHYADDR0 (1 << 0)
Sergunb 0:8918a71cdbe9 245
Sergunb 0:8918a71cdbe9 246 //10BTSCR register
Sergunb 0:8918a71cdbe9 247 #define _10BTSCR_10BT_SERIAL (1 << 15)
Sergunb 0:8918a71cdbe9 248 #define _10BTSCR_SQUELCH2 (1 << 11)
Sergunb 0:8918a71cdbe9 249 #define _10BTSCR_SQUELCH1 (1 << 10)
Sergunb 0:8918a71cdbe9 250 #define _10BTSCR_SQUELCH0 (1 << 9)
Sergunb 0:8918a71cdbe9 251 #define _10BTSCR_LOOPBACK_10_DIS (1 << 8)
Sergunb 0:8918a71cdbe9 252 #define _10BTSCR_LP_DIS (1 << 7)
Sergunb 0:8918a71cdbe9 253 #define _10BTSCR_FORCE_LINK_10 (1 << 6)
Sergunb 0:8918a71cdbe9 254 #define _10BTSCR_POLARITY (1 << 4)
Sergunb 0:8918a71cdbe9 255 #define _10BTSCR_HEARTBEAT_DIS (1 << 1)
Sergunb 0:8918a71cdbe9 256 #define _10BTSCR_JABBER_DIS (1 << 0)
Sergunb 0:8918a71cdbe9 257
Sergunb 0:8918a71cdbe9 258 //CDCTRL1 register
Sergunb 0:8918a71cdbe9 259 #define CDCTRL1_BIST_ERROR_COUNT7 (1 << 15)
Sergunb 0:8918a71cdbe9 260 #define CDCTRL1_BIST_ERROR_COUNT6 (1 << 14)
Sergunb 0:8918a71cdbe9 261 #define CDCTRL1_BIST_ERROR_COUNT5 (1 << 13)
Sergunb 0:8918a71cdbe9 262 #define CDCTRL1_BIST_ERROR_COUNT4 (1 << 12)
Sergunb 0:8918a71cdbe9 263 #define CDCTRL1_BIST_ERROR_COUNT3 (1 << 11)
Sergunb 0:8918a71cdbe9 264 #define CDCTRL1_BIST_ERROR_COUNT2 (1 << 10)
Sergunb 0:8918a71cdbe9 265 #define CDCTRL1_BIST_ERROR_COUNT1 (1 << 9)
Sergunb 0:8918a71cdbe9 266 #define CDCTRL1_BIST_ERROR_COUNT0 (1 << 8)
Sergunb 0:8918a71cdbe9 267 #define CDCTRL1_BIST_CONT_MODE (1 << 5)
Sergunb 0:8918a71cdbe9 268 #define CDCTRL1_CDPATTEN_10 (1 << 4)
Sergunb 0:8918a71cdbe9 269 #define CDCTRL1_10MEG_PATT_GAP (1 << 2)
Sergunb 0:8918a71cdbe9 270 #define CDCTRL1_CDPATTSEL1 (1 << 1)
Sergunb 0:8918a71cdbe9 271 #define CDCTRL1_CDPATTSEL0 (1 << 0)
Sergunb 0:8918a71cdbe9 272
Sergunb 0:8918a71cdbe9 273 //EDCR register
Sergunb 0:8918a71cdbe9 274 #define EDCR_ED_EN (1 << 15)
Sergunb 0:8918a71cdbe9 275 #define EDCR_ED_AUTO_UP (1 << 14)
Sergunb 0:8918a71cdbe9 276 #define EDCR_ED_AUTO_DOWN (1 << 13)
Sergunb 0:8918a71cdbe9 277 #define EDCR_ED_MAN (1 << 12)
Sergunb 0:8918a71cdbe9 278 #define EDCR_ED_BURST_DIS (1 << 11)
Sergunb 0:8918a71cdbe9 279 #define EDCR_ED_PWR_STATE (1 << 10)
Sergunb 0:8918a71cdbe9 280 #define EDCR_ED_ERR_MET (1 << 9)
Sergunb 0:8918a71cdbe9 281 #define EDCR_ED_DATA_MET (1 << 8)
Sergunb 0:8918a71cdbe9 282 #define EDCR_ED_ERR_COUNT3 (1 << 7)
Sergunb 0:8918a71cdbe9 283 #define EDCR_ED_ERR_COUNT2 (1 << 6)
Sergunb 0:8918a71cdbe9 284 #define EDCR_ED_ERR_COUNT1 (1 << 5)
Sergunb 0:8918a71cdbe9 285 #define EDCR_ED_ERR_COUNT0 (1 << 4)
Sergunb 0:8918a71cdbe9 286 #define EDCR_ED_DATA_COUNT3 (1 << 3)
Sergunb 0:8918a71cdbe9 287 #define EDCR_ED_DATA_COUNT2 (1 << 2)
Sergunb 0:8918a71cdbe9 288 #define EDCR_ED_DATA_COUNT1 (1 << 1)
Sergunb 0:8918a71cdbe9 289 #define EDCR_ED_DATA_COUNT0 (1 << 0)
Sergunb 0:8918a71cdbe9 290
Sergunb 0:8918a71cdbe9 291 //DP83848 Ethernet PHY driver
Sergunb 0:8918a71cdbe9 292 extern const PhyDriver dp83848PhyDriver;
Sergunb 0:8918a71cdbe9 293
Sergunb 0:8918a71cdbe9 294 //DP83848 related functions
Sergunb 0:8918a71cdbe9 295 error_t dp83848Init(NetInterface *interface);
Sergunb 0:8918a71cdbe9 296
Sergunb 0:8918a71cdbe9 297 void dp83848Tick(NetInterface *interface);
Sergunb 0:8918a71cdbe9 298
Sergunb 0:8918a71cdbe9 299 void dp83848EnableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 300 void dp83848DisableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 301
Sergunb 0:8918a71cdbe9 302 void dp83848EventHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 303
Sergunb 0:8918a71cdbe9 304 void dp83848WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data);
Sergunb 0:8918a71cdbe9 305 uint16_t dp83848ReadPhyReg(NetInterface *interface, uint8_t address);
Sergunb 0:8918a71cdbe9 306
Sergunb 0:8918a71cdbe9 307 void dp83848DumpPhyReg(NetInterface *interface);
Sergunb 0:8918a71cdbe9 308
Sergunb 0:8918a71cdbe9 309 #endif
Sergunb 0:8918a71cdbe9 310