Webserver+3d print

Dependents:   Nucleo

Committer:
Sergunb
Date:
Sat Feb 04 18:15:49 2017 +0000
Revision:
0:8918a71cdbe9
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Sergunb 0:8918a71cdbe9 1 /**
Sergunb 0:8918a71cdbe9 2 * @file avr32_eth.h
Sergunb 0:8918a71cdbe9 3 * @brief AVR32 Ethernet MAC controller
Sergunb 0:8918a71cdbe9 4 *
Sergunb 0:8918a71cdbe9 5 * @section License
Sergunb 0:8918a71cdbe9 6 *
Sergunb 0:8918a71cdbe9 7 * Copyright (C) 2010-2017 Oryx Embedded SARL. All rights reserved.
Sergunb 0:8918a71cdbe9 8 *
Sergunb 0:8918a71cdbe9 9 * This file is part of CycloneTCP Open.
Sergunb 0:8918a71cdbe9 10 *
Sergunb 0:8918a71cdbe9 11 * This program is free software; you can redistribute it and/or
Sergunb 0:8918a71cdbe9 12 * modify it under the terms of the GNU General Public License
Sergunb 0:8918a71cdbe9 13 * as published by the Free Software Foundation; either version 2
Sergunb 0:8918a71cdbe9 14 * of the License, or (at your option) any later version.
Sergunb 0:8918a71cdbe9 15 *
Sergunb 0:8918a71cdbe9 16 * This program is distributed in the hope that it will be useful,
Sergunb 0:8918a71cdbe9 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Sergunb 0:8918a71cdbe9 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
Sergunb 0:8918a71cdbe9 19 * GNU General Public License for more details.
Sergunb 0:8918a71cdbe9 20 *
Sergunb 0:8918a71cdbe9 21 * You should have received a copy of the GNU General Public License
Sergunb 0:8918a71cdbe9 22 * along with this program; if not, write to the Free Software Foundation,
Sergunb 0:8918a71cdbe9 23 * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
Sergunb 0:8918a71cdbe9 24 *
Sergunb 0:8918a71cdbe9 25 * @author Oryx Embedded SARL (www.oryx-embedded.com)
Sergunb 0:8918a71cdbe9 26 * @version 1.7.6
Sergunb 0:8918a71cdbe9 27 **/
Sergunb 0:8918a71cdbe9 28
Sergunb 0:8918a71cdbe9 29 #ifndef _AVR32_ETH_H
Sergunb 0:8918a71cdbe9 30 #define _AVR32_ETH_H
Sergunb 0:8918a71cdbe9 31
Sergunb 0:8918a71cdbe9 32 //Number of TX buffers
Sergunb 0:8918a71cdbe9 33 #ifndef AVR32_ETH_TX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 34 #define AVR32_ETH_TX_BUFFER_COUNT 2
Sergunb 0:8918a71cdbe9 35 #elif (AVR32_ETH_TX_BUFFER_COUNT < 1)
Sergunb 0:8918a71cdbe9 36 #error AVR32_ETH_TX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 37 #endif
Sergunb 0:8918a71cdbe9 38
Sergunb 0:8918a71cdbe9 39 //TX buffer size
Sergunb 0:8918a71cdbe9 40 #ifndef AVR32_ETH_TX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 41 #define AVR32_ETH_TX_BUFFER_SIZE 1536
Sergunb 0:8918a71cdbe9 42 #elif (AVR32_ETH_TX_BUFFER_SIZE != 1536)
Sergunb 0:8918a71cdbe9 43 #error AVR32_ETH_TX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 44 #endif
Sergunb 0:8918a71cdbe9 45
Sergunb 0:8918a71cdbe9 46 //Number of RX buffers
Sergunb 0:8918a71cdbe9 47 #ifndef AVR32_ETH_RX_BUFFER_COUNT
Sergunb 0:8918a71cdbe9 48 #define AVR32_ETH_RX_BUFFER_COUNT 48
Sergunb 0:8918a71cdbe9 49 #elif (AVR32_ETH_RX_BUFFER_COUNT < 12)
Sergunb 0:8918a71cdbe9 50 #error AVR32_ETH_RX_BUFFER_COUNT parameter is not valid
Sergunb 0:8918a71cdbe9 51 #endif
Sergunb 0:8918a71cdbe9 52
Sergunb 0:8918a71cdbe9 53 //RX buffer size
Sergunb 0:8918a71cdbe9 54 #ifndef AVR32_ETH_RX_BUFFER_SIZE
Sergunb 0:8918a71cdbe9 55 #define AVR32_ETH_RX_BUFFER_SIZE 128
Sergunb 0:8918a71cdbe9 56 #elif (AVR32_ETH_RX_BUFFER_SIZE != 128)
Sergunb 0:8918a71cdbe9 57 #error AVR32_ETH_RX_BUFFER_SIZE parameter is not valid
Sergunb 0:8918a71cdbe9 58 #endif
Sergunb 0:8918a71cdbe9 59
Sergunb 0:8918a71cdbe9 60 //Ethernet interrupt priority
Sergunb 0:8918a71cdbe9 61 #ifndef AVR32_ETH_IRQ_PRIORITY
Sergunb 0:8918a71cdbe9 62 #define AVR32_ETH_IRQ_PRIORITY 2
Sergunb 0:8918a71cdbe9 63 #elif (AVR32_ETH_IRQ_PRIORITY < 0 || AVR32_ETH_IRQ_PRIORITY > 3)
Sergunb 0:8918a71cdbe9 64 #error AVR32_ETH_IRQ_PRIORITY parameter is not valid
Sergunb 0:8918a71cdbe9 65 #endif
Sergunb 0:8918a71cdbe9 66
Sergunb 0:8918a71cdbe9 67 //RMII pin definition
Sergunb 0:8918a71cdbe9 68 #define MACB_RMII_EREFCK_MASK (1 << (AVR32_MACB_TX_CLK_0_PIN - 32))
Sergunb 0:8918a71cdbe9 69 #define MACB_RMII_ETXEN_MASK (1 << (AVR32_MACB_TX_EN_0_PIN - 32))
Sergunb 0:8918a71cdbe9 70 #define MACB_RMII_ETX0_MASK (1 << (AVR32_MACB_TXD_0_PIN - 32))
Sergunb 0:8918a71cdbe9 71 #define MACB_RMII_ETX1_MASK (1 << (AVR32_MACB_TXD_1_PIN - 32))
Sergunb 0:8918a71cdbe9 72 #define MACB_RMII_ERX0_MASK (1 << (AVR32_MACB_RXD_0_PIN - 32))
Sergunb 0:8918a71cdbe9 73 #define MACB_RMII_ERX1_MASK (1 << (AVR32_MACB_RXD_1_PIN - 32))
Sergunb 0:8918a71cdbe9 74 #define MACB_RMII_ERXER_MASK (1 << (AVR32_MACB_RX_ER_0_PIN - 32))
Sergunb 0:8918a71cdbe9 75 #define MACB_RMII_ECRSDV_MASK (1 << (AVR32_MACB_RX_DV_0_PIN - 32))
Sergunb 0:8918a71cdbe9 76 #define MACB_RMII_MDC_MASK (1 << (AVR32_MACB_MDC_0_PIN - 32))
Sergunb 0:8918a71cdbe9 77 #define MACB_RMII_MDIO_MASK (1 << (AVR32_MACB_MDIO_0_PIN - 32))
Sergunb 0:8918a71cdbe9 78
Sergunb 0:8918a71cdbe9 79 //RMII signals
Sergunb 0:8918a71cdbe9 80 #define MACB_RMII_MASK (MACB_RMII_EREFCK_MASK | MACB_RMII_ETXEN_MASK | \
Sergunb 0:8918a71cdbe9 81 MACB_RMII_ETX0_MASK | MACB_RMII_ETX1_MASK | MACB_RMII_ERX0_MASK | MACB_RMII_ERX1_MASK | \
Sergunb 0:8918a71cdbe9 82 MACB_RMII_ERXER_MASK | MACB_RMII_ECRSDV_MASK | MACB_RMII_MDC_MASK | MACB_RMII_MDIO_MASK)
Sergunb 0:8918a71cdbe9 83
Sergunb 0:8918a71cdbe9 84 //PHY maintenance register (MAN)
Sergunb 0:8918a71cdbe9 85 #define MACB_MAN_SOF_01 (1 << AVR32_MACB_MAN_SOF_OFFSET)
Sergunb 0:8918a71cdbe9 86 #define MACB_MAN_RW_01 (1 << AVR32_MACB_MAN_RW_OFFSET)
Sergunb 0:8918a71cdbe9 87 #define MACB_MAN_RW_10 (2 << AVR32_MACB_MAN_RW_OFFSET)
Sergunb 0:8918a71cdbe9 88 #define MACB_MAN_CODE_10 (2 << AVR32_MACB_MAN_CODE_OFFSET)
Sergunb 0:8918a71cdbe9 89
Sergunb 0:8918a71cdbe9 90 //TX buffer descriptor flags
Sergunb 0:8918a71cdbe9 91 #define MACB_TX_USED 0x80000000
Sergunb 0:8918a71cdbe9 92 #define MACB_TX_WRAP 0x40000000
Sergunb 0:8918a71cdbe9 93 #define MACB_TX_ERROR 0x20000000
Sergunb 0:8918a71cdbe9 94 #define MACB_TX_UNDERRUN 0x10000000
Sergunb 0:8918a71cdbe9 95 #define MACB_TX_EXHAUSTED 0x08000000
Sergunb 0:8918a71cdbe9 96 #define MACB_TX_NO_CRC 0x00010000
Sergunb 0:8918a71cdbe9 97 #define MACB_TX_LAST 0x00008000
Sergunb 0:8918a71cdbe9 98 #define MACB_TX_LENGTH 0x000007FF
Sergunb 0:8918a71cdbe9 99
Sergunb 0:8918a71cdbe9 100 //RX buffer descriptor flags
Sergunb 0:8918a71cdbe9 101 #define MACB_RX_ADDRESS 0xFFFFFFFC
Sergunb 0:8918a71cdbe9 102 #define MACB_RX_WRAP 0x00000002
Sergunb 0:8918a71cdbe9 103 #define MACB_RX_OWNERSHIP 0x00000001
Sergunb 0:8918a71cdbe9 104 #define MACB_RX_BROADCAST 0x80000000
Sergunb 0:8918a71cdbe9 105 #define MACB_RX_MULTICAST_HASH 0x40000000
Sergunb 0:8918a71cdbe9 106 #define MACB_RX_UNICAST_HASH 0x20000000
Sergunb 0:8918a71cdbe9 107 #define MACB_RX_EXT_ADDR 0x10000000
Sergunb 0:8918a71cdbe9 108 #define MACB_RX_SAR1 0x04000000
Sergunb 0:8918a71cdbe9 109 #define MACB_RX_SAR2 0x02000000
Sergunb 0:8918a71cdbe9 110 #define MACB_RX_SAR3 0x01000000
Sergunb 0:8918a71cdbe9 111 #define MACB_RX_SAR4 0x00800000
Sergunb 0:8918a71cdbe9 112 #define MACB_RX_TYPE_ID 0x00400000
Sergunb 0:8918a71cdbe9 113 #define MACB_RX_VLAN_TAG 0x00200000
Sergunb 0:8918a71cdbe9 114 #define MACB_RX_PRIORITY_TAG 0x00100000
Sergunb 0:8918a71cdbe9 115 #define MACB_RX_VLAN_PRIORITY 0x000E0000
Sergunb 0:8918a71cdbe9 116 #define MACB_RX_CFI 0x00010000
Sergunb 0:8918a71cdbe9 117 #define MACB_RX_EOF 0x00008000
Sergunb 0:8918a71cdbe9 118 #define MACB_RX_SOF 0x00004000
Sergunb 0:8918a71cdbe9 119 #define MACB_RX_OFFSET 0x00003000
Sergunb 0:8918a71cdbe9 120 #define MACB_RX_LENGTH 0x00000FFF
Sergunb 0:8918a71cdbe9 121
Sergunb 0:8918a71cdbe9 122
Sergunb 0:8918a71cdbe9 123 /**
Sergunb 0:8918a71cdbe9 124 * @brief Transmit buffer descriptor
Sergunb 0:8918a71cdbe9 125 **/
Sergunb 0:8918a71cdbe9 126
Sergunb 0:8918a71cdbe9 127 typedef struct
Sergunb 0:8918a71cdbe9 128 {
Sergunb 0:8918a71cdbe9 129 uint32_t address;
Sergunb 0:8918a71cdbe9 130 uint32_t status;
Sergunb 0:8918a71cdbe9 131 } Avr32TxBufferDesc;
Sergunb 0:8918a71cdbe9 132
Sergunb 0:8918a71cdbe9 133
Sergunb 0:8918a71cdbe9 134 /**
Sergunb 0:8918a71cdbe9 135 * @brief Receive buffer descriptor
Sergunb 0:8918a71cdbe9 136 **/
Sergunb 0:8918a71cdbe9 137
Sergunb 0:8918a71cdbe9 138 typedef struct
Sergunb 0:8918a71cdbe9 139 {
Sergunb 0:8918a71cdbe9 140 uint32_t address;
Sergunb 0:8918a71cdbe9 141 uint32_t status;
Sergunb 0:8918a71cdbe9 142 } Avr32RxBufferDesc;
Sergunb 0:8918a71cdbe9 143
Sergunb 0:8918a71cdbe9 144
Sergunb 0:8918a71cdbe9 145 //AVR32 Ethernet MAC driver
Sergunb 0:8918a71cdbe9 146 extern const NicDriver avr32EthDriver;
Sergunb 0:8918a71cdbe9 147
Sergunb 0:8918a71cdbe9 148 //AVR32 Ethernet MAC related functions
Sergunb 0:8918a71cdbe9 149 error_t avr32EthInit(NetInterface *interface);
Sergunb 0:8918a71cdbe9 150 void avr32EthInitGpio(NetInterface *interface);
Sergunb 0:8918a71cdbe9 151 void avr32EthInitBufferDesc(NetInterface *interface);
Sergunb 0:8918a71cdbe9 152
Sergunb 0:8918a71cdbe9 153 void avr32EthTick(NetInterface *interface);
Sergunb 0:8918a71cdbe9 154
Sergunb 0:8918a71cdbe9 155 void avr32EthEnableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 156 void avr32EthDisableIrq(NetInterface *interface);
Sergunb 0:8918a71cdbe9 157 void avr32EthIrqWrapper(void);
Sergunb 0:8918a71cdbe9 158 bool_t avr32EthIrqHandler(void);
Sergunb 0:8918a71cdbe9 159 void avr32EthEventHandler(NetInterface *interface);
Sergunb 0:8918a71cdbe9 160
Sergunb 0:8918a71cdbe9 161 error_t avr32EthSendPacket(NetInterface *interface,
Sergunb 0:8918a71cdbe9 162 const NetBuffer *buffer, size_t offset);
Sergunb 0:8918a71cdbe9 163
Sergunb 0:8918a71cdbe9 164 error_t avr32EthReceivePacket(NetInterface *interface);
Sergunb 0:8918a71cdbe9 165
Sergunb 0:8918a71cdbe9 166 error_t avr32EthSetMulticastFilter(NetInterface *interface);
Sergunb 0:8918a71cdbe9 167 error_t avr32EthUpdateMacConfig(NetInterface *interface);
Sergunb 0:8918a71cdbe9 168
Sergunb 0:8918a71cdbe9 169 void avr32EthWritePhyReg(uint8_t phyAddr, uint8_t regAddr, uint16_t data);
Sergunb 0:8918a71cdbe9 170 uint16_t avr32EthReadPhyReg(uint8_t phyAddr, uint8_t regAddr);
Sergunb 0:8918a71cdbe9 171
Sergunb 0:8918a71cdbe9 172 #endif
Sergunb 0:8918a71cdbe9 173