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Watchdog
Fork of Watchdog_sample_nocoverage by
KL25Z_SystemInit.c@6:1a6af3f79bb0, 2018-03-09 (annotated)
- Committer:
- Sarang
- Date:
- Fri Mar 09 23:04:00 2018 +0000
- Revision:
- 6:1a6af3f79bb0
- Parent:
- 1:159a09ac60ba
Watchdog_sample;
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Manel_Marin | 0:5ce3cfc57999 | 1 | /* |
Manel_Marin | 0:5ce3cfc57999 | 2 | ** ################################################################### |
Manel_Marin | 0:5ce3cfc57999 | 3 | ** Processor: MKL25Z128VLK4 |
Manel_Marin | 0:5ce3cfc57999 | 4 | ** Compilers: ARM Compiler |
Manel_Marin | 0:5ce3cfc57999 | 5 | ** Freescale C/C++ for Embedded ARM |
Manel_Marin | 0:5ce3cfc57999 | 6 | ** GNU C Compiler |
Manel_Marin | 0:5ce3cfc57999 | 7 | ** IAR ANSI C/C++ Compiler for ARM |
Manel_Marin | 0:5ce3cfc57999 | 8 | ** |
Manel_Marin | 0:5ce3cfc57999 | 9 | ** Reference manual: KL25RM, Rev.1, Jun 2012 |
Manel_Marin | 0:5ce3cfc57999 | 10 | ** Version: rev. 1.1, 2012-06-21 |
Manel_Marin | 0:5ce3cfc57999 | 11 | ** |
Manel_Marin | 0:5ce3cfc57999 | 12 | ** Abstract: |
Manel_Marin | 0:5ce3cfc57999 | 13 | ** Provides a system configuration function and a global variable that |
Manel_Marin | 0:5ce3cfc57999 | 14 | ** contains the system frequency. It configures the device and initializes |
Manel_Marin | 0:5ce3cfc57999 | 15 | ** the oscillator (PLL) that is part of the microcontroller device. |
Manel_Marin | 0:5ce3cfc57999 | 16 | ** |
Manel_Marin | 0:5ce3cfc57999 | 17 | ** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved. |
Manel_Marin | 0:5ce3cfc57999 | 18 | ** |
Manel_Marin | 0:5ce3cfc57999 | 19 | ** http: www.freescale.com |
Manel_Marin | 0:5ce3cfc57999 | 20 | ** mail: support@freescale.com |
Manel_Marin | 0:5ce3cfc57999 | 21 | ** |
Manel_Marin | 0:5ce3cfc57999 | 22 | ** Revisions: |
Manel_Marin | 0:5ce3cfc57999 | 23 | ** - rev. 1.0 (2012-06-13) |
Manel_Marin | 0:5ce3cfc57999 | 24 | ** Initial version. |
Manel_Marin | 0:5ce3cfc57999 | 25 | ** - rev. 1.1 (2012-06-21) |
Manel_Marin | 0:5ce3cfc57999 | 26 | ** Update according to reference manual rev. 1. |
Manel_Marin | 0:5ce3cfc57999 | 27 | ** |
Manel_Marin | 0:5ce3cfc57999 | 28 | ** ################################################################### |
Manel_Marin | 0:5ce3cfc57999 | 29 | */ |
Manel_Marin | 0:5ce3cfc57999 | 30 | |
Manel_Marin | 0:5ce3cfc57999 | 31 | /** |
Manel_Marin | 0:5ce3cfc57999 | 32 | * @file MKL25Z4 |
Manel_Marin | 0:5ce3cfc57999 | 33 | * @version 1.1 |
Manel_Marin | 0:5ce3cfc57999 | 34 | * @date 2012-06-21 |
Manel_Marin | 0:5ce3cfc57999 | 35 | * @brief Device specific configuration file for MKL25Z4 (implementation file) |
Manel_Marin | 0:5ce3cfc57999 | 36 | * |
Manel_Marin | 0:5ce3cfc57999 | 37 | * Provides a system configuration function and a global variable that contains |
Manel_Marin | 0:5ce3cfc57999 | 38 | * the system frequency. It configures the device and initializes the oscillator |
Manel_Marin | 0:5ce3cfc57999 | 39 | * (PLL) that is part of the microcontroller device. |
Manel_Marin | 0:5ce3cfc57999 | 40 | */ |
Manel_Marin | 0:5ce3cfc57999 | 41 | |
Manel_Marin | 0:5ce3cfc57999 | 42 | #include <stdint.h> |
Manel_Marin | 0:5ce3cfc57999 | 43 | #include "MKL25Z4.h" |
Manel_Marin | 0:5ce3cfc57999 | 44 | |
Manel_Marin | 0:5ce3cfc57999 | 45 | //MODIFICATION: We DO want watchdog, uC default after reset is enabled with timeout=1024ms (2^10*LPO=1KHz) |
Manel_Marin | 0:5ce3cfc57999 | 46 | //#define DISABLE_WDOG 1 |
Manel_Marin | 0:5ce3cfc57999 | 47 | |
Manel_Marin | 0:5ce3cfc57999 | 48 | #define CLOCK_SETUP 1 |
Manel_Marin | 0:5ce3cfc57999 | 49 | /* Predefined clock setups |
Manel_Marin | 0:5ce3cfc57999 | 50 | 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode |
Manel_Marin | 0:5ce3cfc57999 | 51 | Reference clock source for MCG module is the slow internal clock source 32.768kHz |
Manel_Marin | 0:5ce3cfc57999 | 52 | Core clock = 41.94MHz, BusClock = 13.98MHz |
Manel_Marin | 0:5ce3cfc57999 | 53 | 1 ... Multipurpose Clock Generator (MCG) in PLL Engaged External (PEE) mode |
Manel_Marin | 0:5ce3cfc57999 | 54 | Reference clock source for MCG module is an external crystal 8MHz |
Manel_Marin | 0:5ce3cfc57999 | 55 | Core clock = 48MHz, BusClock = 24MHz |
Manel_Marin | 0:5ce3cfc57999 | 56 | 2 ... Multipurpose Clock Generator (MCG) in Bypassed Low Power External (BLPE) mode |
Manel_Marin | 0:5ce3cfc57999 | 57 | Core clock/Bus clock derived directly from an external crystal 8MHz with no multiplication |
Manel_Marin | 0:5ce3cfc57999 | 58 | Core clock = 8MHz, BusClock = 8MHz |
Manel_Marin | 0:5ce3cfc57999 | 59 | 3 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode |
Manel_Marin | 0:5ce3cfc57999 | 60 | Reference clock source for MCG module is an external crystal 32.768kHz |
Manel_Marin | 0:5ce3cfc57999 | 61 | Core clock = 47.97MHz, BusClock = 23.98MHz |
Manel_Marin | 0:5ce3cfc57999 | 62 | This setup sets the RTC to be driven by the MCU clock directly without the need of an external source. |
Manel_Marin | 0:5ce3cfc57999 | 63 | RTC register values are retained when MCU is reset although there will be a slight (mSec's)loss of time |
Manel_Marin | 0:5ce3cfc57999 | 64 | accuracy durring the reset period. RTC will reset on power down. |
Manel_Marin | 0:5ce3cfc57999 | 65 | */ |
Manel_Marin | 0:5ce3cfc57999 | 66 | |
Manel_Marin | 0:5ce3cfc57999 | 67 | /*---------------------------------------------------------------------------- |
Manel_Marin | 0:5ce3cfc57999 | 68 | Define clock source values |
Manel_Marin | 0:5ce3cfc57999 | 69 | *----------------------------------------------------------------------------*/ |
Manel_Marin | 0:5ce3cfc57999 | 70 | #if (CLOCK_SETUP == 0) |
Manel_Marin | 0:5ce3cfc57999 | 71 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 72 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 73 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 74 | #define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */ |
Manel_Marin | 0:5ce3cfc57999 | 75 | #elif (CLOCK_SETUP == 1) |
Manel_Marin | 0:5ce3cfc57999 | 76 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 77 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 78 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 79 | #define DEFAULT_SYSTEM_CLOCK 48000000u /* Default System clock value */ |
Manel_Marin | 0:5ce3cfc57999 | 80 | #elif (CLOCK_SETUP == 2) |
Manel_Marin | 0:5ce3cfc57999 | 81 | #define CPU_XTAL_CLK_HZ 8000000u /* Value of the external crystal or oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 82 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 83 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 84 | #define DEFAULT_SYSTEM_CLOCK 8000000u /* Default System clock value */ |
Manel_Marin | 0:5ce3cfc57999 | 85 | #elif (CLOCK_SETUP == 3) |
Manel_Marin | 0:5ce3cfc57999 | 86 | #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 87 | #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 88 | #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ |
Manel_Marin | 0:5ce3cfc57999 | 89 | #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */ |
Manel_Marin | 0:5ce3cfc57999 | 90 | #endif /* (CLOCK_SETUP == 3) */ |
Manel_Marin | 0:5ce3cfc57999 | 91 | |
Manel_Marin | 0:5ce3cfc57999 | 92 | /* ---------------------------------------------------------------------------- |
Manel_Marin | 0:5ce3cfc57999 | 93 | -- Core clock |
Manel_Marin | 0:5ce3cfc57999 | 94 | ---------------------------------------------------------------------------- */ |
Manel_Marin | 0:5ce3cfc57999 | 95 | |
Manel_Marin | 0:5ce3cfc57999 | 96 | //MODIFICATION: That vartiable already exists |
Manel_Marin | 0:5ce3cfc57999 | 97 | // uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; |
Manel_Marin | 0:5ce3cfc57999 | 98 | |
Manel_Marin | 0:5ce3cfc57999 | 99 | /* ---------------------------------------------------------------------------- |
Manel_Marin | 0:5ce3cfc57999 | 100 | -- SystemInit() |
Manel_Marin | 0:5ce3cfc57999 | 101 | ---------------------------------------------------------------------------- */ |
Manel_Marin | 0:5ce3cfc57999 | 102 | |
Manel_Marin | 0:5ce3cfc57999 | 103 | void $Sub$$SystemInit (void) { |
Manel_Marin | 0:5ce3cfc57999 | 104 | |
Manel_Marin | 0:5ce3cfc57999 | 105 | //MODIFICATION: |
Manel_Marin | 0:5ce3cfc57999 | 106 | // That variable already exists, we set it here |
Manel_Marin | 0:5ce3cfc57999 | 107 | SystemCoreClock = DEFAULT_SYSTEM_CLOCK; |
Manel_Marin | 0:5ce3cfc57999 | 108 | // We want visual indication of boot time with red LED on |
Manel_Marin | 0:5ce3cfc57999 | 109 | //TODO |
Manel_Marin | 0:5ce3cfc57999 | 110 | |
Manel_Marin | 0:5ce3cfc57999 | 111 | #if (DISABLE_WDOG) |
Manel_Marin | 0:5ce3cfc57999 | 112 | /* Disable the WDOG module */ |
Manel_Marin | 0:5ce3cfc57999 | 113 | /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 114 | SIM->COPC = (uint32_t)0x00u; |
Manel_Marin | 0:5ce3cfc57999 | 115 | #endif /* (DISABLE_WDOG) */ |
Manel_Marin | 0:5ce3cfc57999 | 116 | #if (CLOCK_SETUP == 0) |
WilliamMarshQMUL | 1:159a09ac60ba | 117 | /* SIM->CLKDIV1: OUTDIV1=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 118 | SIM->CLKDIV1 = (uint32_t)0x00020000UL; /* Update system prescalers */ |
Manel_Marin | 0:5ce3cfc57999 | 119 | /* Switch to FEI Mode */ |
Manel_Marin | 0:5ce3cfc57999 | 120 | /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 121 | MCG->C1 = (uint8_t)0x06U; |
WilliamMarshQMUL | 1:159a09ac60ba | 122 | /* MCG_C2: LOCRE0=0, =0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 123 | MCG->C2 = (uint8_t)0x00U; |
Manel_Marin | 0:5ce3cfc57999 | 124 | /* MCG->C4: DMX32=0,DRST_DRS=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 125 | MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)0xC0U) | (uint8_t)0x20U); |
WilliamMarshQMUL | 1:159a09ac60ba | 126 | /* OSC0->CR: ERCLKEN=1,=0,EREFSTEN=0,=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 127 | OSC0->CR = (uint8_t)0x80U; |
WilliamMarshQMUL | 1:159a09ac60ba | 128 | /* MCG->C5: =0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 129 | MCG->C5 = (uint8_t)0x00U; |
Manel_Marin | 0:5ce3cfc57999 | 130 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 131 | MCG->C6 = (uint8_t)0x00U; |
Manel_Marin | 0:5ce3cfc57999 | 132 | while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ |
Manel_Marin | 0:5ce3cfc57999 | 133 | } |
Manel_Marin | 0:5ce3cfc57999 | 134 | while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ |
Manel_Marin | 0:5ce3cfc57999 | 135 | } |
Manel_Marin | 0:5ce3cfc57999 | 136 | #elif (CLOCK_SETUP == 1) |
Manel_Marin | 0:5ce3cfc57999 | 137 | /* SIM->SCGC5: PORTA=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 138 | SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */ |
WilliamMarshQMUL | 1:159a09ac60ba | 139 | /* SIM->CLKDIV1: OUTDIV1=1,OUTDIV4=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 140 | SIM->CLKDIV1 = (uint32_t)0x10010000UL; /* Update system prescalers */ |
Manel_Marin | 0:5ce3cfc57999 | 141 | /* PORTA->PCR18: ISF=0,MUX=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 142 | PORTA->PCR[18] &= (uint32_t)~0x01000700UL; |
Manel_Marin | 0:5ce3cfc57999 | 143 | /* PORTA->PCR19: ISF=0,MUX=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 144 | PORTA->PCR[19] &= (uint32_t)~0x01000700UL; |
Manel_Marin | 0:5ce3cfc57999 | 145 | /* Switch to FBE Mode */ |
WilliamMarshQMUL | 1:159a09ac60ba | 146 | /* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 147 | OSC0->CR = (uint8_t)0x89U; |
WilliamMarshQMUL | 1:159a09ac60ba | 148 | /* MCG->C2: LOCRE0=0, RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 149 | MCG->C2 = (uint8_t)0x24U; |
Manel_Marin | 0:5ce3cfc57999 | 150 | /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 151 | MCG->C1 = (uint8_t)0x9AU; |
Manel_Marin | 0:5ce3cfc57999 | 152 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 153 | MCG->C4 &= (uint8_t)~(uint8_t)0xE0U; |
WilliamMarshQMUL | 1:159a09ac60ba | 154 | /* MCG->C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 155 | MCG->C5 = (uint8_t)0x01U; |
Manel_Marin | 0:5ce3cfc57999 | 156 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 157 | MCG->C6 = (uint8_t)0x00U; |
Manel_Marin | 0:5ce3cfc57999 | 158 | while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
Manel_Marin | 0:5ce3cfc57999 | 159 | } |
Manel_Marin | 0:5ce3cfc57999 | 160 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
Manel_Marin | 0:5ce3cfc57999 | 161 | } |
Manel_Marin | 0:5ce3cfc57999 | 162 | /* Switch to PBE Mode */ |
Manel_Marin | 0:5ce3cfc57999 | 163 | /* MCG->C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 164 | MCG->C6 = (uint8_t)0x40U; |
Manel_Marin | 0:5ce3cfc57999 | 165 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
Manel_Marin | 0:5ce3cfc57999 | 166 | } |
Manel_Marin | 0:5ce3cfc57999 | 167 | while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */ |
Manel_Marin | 0:5ce3cfc57999 | 168 | } |
Manel_Marin | 0:5ce3cfc57999 | 169 | /* Switch to PEE Mode */ |
Manel_Marin | 0:5ce3cfc57999 | 170 | /* MCG->C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 171 | MCG->C1 = (uint8_t)0x1AU; |
Manel_Marin | 0:5ce3cfc57999 | 172 | while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */ |
Manel_Marin | 0:5ce3cfc57999 | 173 | } |
Manel_Marin | 0:5ce3cfc57999 | 174 | #elif (CLOCK_SETUP == 2) |
Manel_Marin | 0:5ce3cfc57999 | 175 | /* SIM->SCGC5: PORTA=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 176 | SIM->SCGC5 |= (uint32_t)0x0200UL; /* Enable clock gate for ports to enable pin routing */ |
WilliamMarshQMUL | 1:159a09ac60ba | 177 | /* SIM->CLKDIV1: OUTDIV1=0,OUTDIV4=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 178 | SIM->CLKDIV1 = (uint32_t)0x00000000UL; /* Update system prescalers */ |
Manel_Marin | 0:5ce3cfc57999 | 179 | /* PORTA->PCR18: ISF=0,MUX=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 180 | PORTA->PCR[18] &= (uint32_t)~0x01000700UL; |
Manel_Marin | 0:5ce3cfc57999 | 181 | /* PORTA->PCR19: ISF=0,MUX=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 182 | PORTA->PCR[19] &= (uint32_t)~0x01000700UL; |
Manel_Marin | 0:5ce3cfc57999 | 183 | /* Switch to FBE Mode */ |
WilliamMarshQMUL | 1:159a09ac60ba | 184 | /* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=1,SC4P=0,SC8P=0,SC16P=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 185 | OSC0->CR = (uint8_t)0x89U; |
WilliamMarshQMUL | 1:159a09ac60ba | 186 | /* MCG->C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 187 | MCG->C2 = (uint8_t)0x24U; |
Manel_Marin | 0:5ce3cfc57999 | 188 | /* MCG->C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 189 | MCG->C1 = (uint8_t)0x9AU; |
Manel_Marin | 0:5ce3cfc57999 | 190 | /* MCG->C4: DMX32=0,DRST_DRS=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 191 | MCG->C4 &= (uint8_t)~(uint8_t)0xE0U; |
WilliamMarshQMUL | 1:159a09ac60ba | 192 | /* MCG->C5: PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 193 | MCG->C5 = (uint8_t)0x00U; |
Manel_Marin | 0:5ce3cfc57999 | 194 | /* MCG->C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 195 | MCG->C6 = (uint8_t)0x00U; |
Manel_Marin | 0:5ce3cfc57999 | 196 | while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
Manel_Marin | 0:5ce3cfc57999 | 197 | } |
Manel_Marin | 0:5ce3cfc57999 | 198 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
Manel_Marin | 0:5ce3cfc57999 | 199 | } |
Manel_Marin | 0:5ce3cfc57999 | 200 | /* Switch to BLPE Mode */ |
WilliamMarshQMUL | 1:159a09ac60ba | 201 | /* MCG->C2: LOCRE0=0,RANGE0=2,HGO0=0,EREFS0=1,LP=1,IRCS=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 202 | MCG->C2 = (uint8_t)0x26U; |
Manel_Marin | 0:5ce3cfc57999 | 203 | while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */ |
Manel_Marin | 0:5ce3cfc57999 | 204 | } |
Manel_Marin | 0:5ce3cfc57999 | 205 | #elif (CLOCK_SETUP == 3) |
Manel_Marin | 0:5ce3cfc57999 | 206 | /* SIM->SCGC5: PORTA=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 207 | SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */ |
WilliamMarshQMUL | 1:159a09ac60ba | 208 | /* SIM->CLKDIV1: OUTDIV1=0, OUTDIV4=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 209 | SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */ |
Manel_Marin | 0:5ce3cfc57999 | 210 | /* PORTA->PCR[3]: ISF=0,MUX=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 211 | PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); |
Manel_Marin | 0:5ce3cfc57999 | 212 | /* PORTA->PCR[4]: ISF=0,MUX=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 213 | PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07))); |
Manel_Marin | 0:5ce3cfc57999 | 214 | /* Switch to FEE Mode */ |
WilliamMarshQMUL | 1:159a09ac60ba | 215 | /* MCG->C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 216 | MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK); |
WilliamMarshQMUL | 1:159a09ac60ba | 217 | /* OSC0->CR: ERCLKEN=1,EREFSTEN=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 218 | OSC0->CR = OSC_CR_ERCLKEN_MASK | OSC_CR_SC16P_MASK | OSC_CR_SC4P_MASK | OSC_CR_SC2P_MASK; |
Manel_Marin | 0:5ce3cfc57999 | 219 | /* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */ |
Manel_Marin | 0:5ce3cfc57999 | 220 | MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK); |
Manel_Marin | 0:5ce3cfc57999 | 221 | /* MCG->C4: DMX32=1,DRST_DRS=1 */ |
Manel_Marin | 0:5ce3cfc57999 | 222 | MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)( |
Manel_Marin | 0:5ce3cfc57999 | 223 | MCG_C4_DRST_DRS(0x02) |
Manel_Marin | 0:5ce3cfc57999 | 224 | )) | (uint8_t)( |
Manel_Marin | 0:5ce3cfc57999 | 225 | MCG_C4_DMX32_MASK | |
Manel_Marin | 0:5ce3cfc57999 | 226 | MCG_C4_DRST_DRS(0x01) |
Manel_Marin | 0:5ce3cfc57999 | 227 | )); |
Manel_Marin | 0:5ce3cfc57999 | 228 | while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */ |
Manel_Marin | 0:5ce3cfc57999 | 229 | } |
Manel_Marin | 0:5ce3cfc57999 | 230 | while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ |
Manel_Marin | 0:5ce3cfc57999 | 231 | } |
Manel_Marin | 0:5ce3cfc57999 | 232 | #endif /* (CLOCK_SETUP == 3) */ |
Manel_Marin | 0:5ce3cfc57999 | 233 | } |