Sam Shi
customized font for Unyte
Dependencies: Adafruit_GFX_customizedfont BLE_API USBDevice mbed
Fork of
mbed-os-example-mbed5-blinky
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mbed-os-examples
Revision 32:a1b2391b0c35, committed 2017-07-18
- Comitter:
- SamShiSS
- Date:
- Tue Jul 18 14:57:27 2017 +0000
- Parent:
- 31:d960851a7d2c
- Commit message:
- customized Unyte font
Changed in this revision
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/Adafruit_GFX.lib Tue Jul 18 14:57:27 2017 +0000 @@ -0,0 +1,1 @@ +https://developer.mbed.org/users/SamShiSS/code/Adafruit_GFX_customizedfont/#5aab2bc95fa6
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/BLE_API.lib Tue Jul 18 14:57:27 2017 +0000 @@ -0,0 +1,1 @@ +http://developer.mbed.org/teams/Bluetooth-Low-Energy/code/BLE_API/#65474dc93927
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/USBDevice.lib Tue Jul 18 14:57:27 2017 +0000 @@ -0,0 +1,1 @@ +http://developer.mbed.org/users/mbed_official/code/USBDevice/#01321bd6ff89
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/clkman.h Tue Jul 18 14:57:27 2017 +0000
@@ -0,0 +1,268 @@
+/*******************************************************************************
+* Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of Maxim Integrated
+* Products, Inc. shall not be used except as stated in the Maxim Integrated
+* Products, Inc. Branding Policy.
+*
+* The mere transfer of this software does not imply any licenses
+* of trade secrets, proprietary technology, copyrights, patents,
+* trademarks, maskwork rights, or any other form of intellectual
+* property whatsoever. Maxim Integrated Products, Inc. retains all
+* ownership rights.
+*******************************************************************************
+*/
+
+/* $Revision: 3581 $ $Date: 2014-11-18 11:46:39 -0600 (Tue, 18 Nov 2014) $ */
+
+#ifndef _CLKMAN_H
+#define _CLKMAN_H
+
+#include "clkman_regs.h"
+#include "adc_regs.h"
+
+/**
+ * @file clkman.h
+ * @addtogroup clkman CLKMAN
+ * @{
+ * @brief This is the high level API for the clock management module
+ * of the MAX32600 family of ARM Cortex based embedded microcontrollers.
+ */
+
+/**
+ * @brief Selects an internal module clock for clock scaling configuration.
+ */
+typedef enum {
+ /** Main System clock */
+ MXC_E_CLKMAN_CLK_SYS = 0,
+ /** GPIO module clock */
+ MXC_E_CLKMAN_CLK_GPIO,
+ /** Pulse Train engine clock */
+ MXC_E_CLKMAN_CLK_PT,
+ /** SPI instance 0 module clock */
+ MXC_E_CLKMAN_CLK_SPI0,
+ /** SPI instance 1 module clock */
+ MXC_E_CLKMAN_CLK_SPI1,
+ /** SPI instance 2 module clock */
+ MXC_E_CLKMAN_CLK_SPI2,
+ /** I2C Master module clock (for all instances) */
+ MXC_E_CLKMAN_CLK_I2CM,
+ /** I2C Slave module clock */
+ MXC_E_CLKMAN_CLK_I2CS,
+ /** LCD Charge pump clock */
+ MXC_E_CLKMAN_CLK_LCD_CHPUMP,
+ /** Reserved */
+ MXC_E_CLKMAN_CLK_PUF,
+ /** PRNG module clock */
+ MXC_E_CLKMAN_CLK_PRNG,
+ /** Watchdog Timer 0 clock */
+ MXC_E_CLKMAN_CLK_WDT0,
+ /** Watchdog Timer 1 clock */
+ MXC_E_CLKMAN_CLK_WDT1,
+ /** RTC synchronizer clock (required for cross-clock-domain register updates) */
+ MXC_E_CLKMAN_CLK_RTC_INT_SYNC,
+ /** Clock for DAC 0 */
+ MXC_E_CLKMAN_CLK_DAC0,
+ /** Clock for DAC 1 */
+ MXC_E_CLKMAN_CLK_DAC1,
+ /** Clock for DAC 2 */
+ MXC_E_CLKMAN_CLK_DAC2,
+ /** Clock for DAC 3 */
+ MXC_E_CLKMAN_CLK_DAC3
+} mxc_clkman_clk_t;
+
+/**
+ * @brief Selects a TPU module clock for crypto ring-oscillator clock scaling configuration
+ */
+typedef enum {
+ /** AES engine clock */
+ MXC_E_CLKMAN_CRYPT_CLK_AES = 0,
+ /** Modular Arithmetic Accelerator (MAA) clock */
+ MXC_E_CLKMAN_CRYPT_CLK_MAA,
+ /** Pseudo-random number Generator (PRNG) clock */
+ MXC_E_CLKMAN_CRYPT_CLK_PRNG
+} mxc_clkman_crypt_clk_t;
+
+/**
+ * @brief Configures but does not enable the high frequency external oscillator circuitry.
+ *
+ * @param hfx_bypass 1 for crystal receiver bypass, 0 for no bypass.
+ * @param hfx_gm_adjust High frequency crystal gain adjust.
+ * @param hfx_dc_control High frequency crystal dc control.
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t CLKMAN_HFXConfig(uint8_t hfx_bypass, uint8_t hfx_gm_adjust, uint8_t hfx_dc_control);
+
+/**
+ * @brief Enables the high frequency crystal receiver. Make sure HFX is stable before switching system clock.
+ */
+void CLKMAN_HFXEnable(void);
+
+/**
+ * @brief Disables the high frequency crystal receiver.
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t CLKMAN_HFXDisable(void);
+
+/**
+ * @brief Configures but does not enable the phase locked loop circuitry.
+ *
+ * @param pll_input_select Phase locked loop clock input.
+ * @param pll_divisor_select Input clock frequency for the phase locked loop.
+ * @param pll_stability_count Number of clocks before phase locked loop is stable.
+ * @param pll_bypass 1 for high frequency oscillator output for 48MHz clock, 0 for phase locked loop output.
+ * @param pll_8mhz_enable 1 for enable 8MHz phase locked loop output, 0 for disable.
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t CLKMAN_PLLConfig(mxc_clkman_pll_input_select_t pll_input_select,
+ mxc_clkman_pll_divisor_select_t pll_divisor_select,
+ mxc_clkman_stability_count_t pll_stability_count,
+ uint8_t pll_bypass, uint8_t pll_8mhz_enable);
+
+/**
+ * @brief Enables the phase locked loop circuitry.
+ */
+void CLKMAN_PLLEnable(void);
+
+/**
+ * @brief Disables the phase locked loop circuitry.
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t CLKMAN_PLLDisable(void);
+
+/**
+ * @brief Starts the Trim calibration of the relaxation oscillator off the 32kHz crystal for use with USB.
+ */
+void CLKMAN_TrimRO_Start(void);
+
+/**
+ * @brief Stops the Trim calibration of the relaxation oscillator off the 32kHz crystal for use with USB.
+ */
+void CLKMAN_TrimRO_Stop(void);
+
+/**
+ * @brief Sets the system clock source if the source is valid. Make sure HFX is stable before switching system clock.
+ *
+ * @param system_source_select System clock source.
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t CLKMAN_SetSystemClock(mxc_clkman_system_source_select_t system_source_select);
+
+/**
+ * @brief Polls on the clock stable flags until all are stable.
+ */
+void CLKMAN_WaitForSystemClockStable(void);
+
+/**
+ * @brief Enables the USB clock.
+ */
+void CLKMAN_USBClockEnable(void);
+
+/**
+ * @brief Disables the USB clock.
+ */
+void CLKMAN_USBClockDisable(void);
+
+/**
+ * @brief Configures but does not enable the crypto clock.
+ *
+ * @param crypto_stability_count Number of clocks before crypto clock is stable.
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t CLKMAN_CryptoClockConfig(mxc_clkman_stability_count_t crypto_stability_count);
+
+/**
+ * @brief Enables the crypto clock.
+ */
+void CLKMAN_CryptoClockEnable(void);
+
+/**
+ * @brief Disables the crypto clock.
+ */
+void CLKMAN_CryptoClockDisable(void);
+
+/**
+ * @brief Sets the analog to digital converter clock source if the source is valid.
+ *
+ * @param adc_source_select Analog to digital converter clock source.
+ * @param adc_clk_mode Divide the clock source into the ADC if source is too high.
+ * ADC must run at 8MHz.
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t CLKMAN_SetADCClock(mxc_clkman_adc_source_select_t adc_source_select, mxc_adc_clk_mode adc_clk_mode);
+
+/**
+ * @brief Disables the analog to digital converter clock source.
+ */
+void CLKMAN_ADCClockDisable(void);
+
+/**
+ * @brief Sets the watchdog clock source if the source is valid for the watchdog specified.
+ *
+ * @param index Index of watchdog to set clock.
+ * @param watchdog_source_select Watchdog clock source.
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t CLKMAN_SetWatchdogClock(uint8_t index, mxc_clkman_wdt_source_select_t watchdog_source_select);
+
+/**
+ * @brief Disable the watchdog clock source for the watchdog specified.
+ *
+ * @param index Index of watchdog to disable.
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t CLKMAN_WatchdogClockDisable(uint8_t index);
+
+/**
+ * @brief Set the system clock scale.
+ * @param device_clk device enum for clock scale setup
+ * @param clk_scale System clock scale.
+ */
+void CLKMAN_SetClkScale(mxc_clkman_clk_t device_clk, mxc_clkman_clk_scale_t clk_scale);
+
+/**
+ * @brief Set the TPU clock scale.
+ * @param device_clk device enum for clock scale setup
+ * @param clk_scale System clock scale.
+ */
+void CLKMAN_SetCryptClkScale(mxc_clkman_crypt_clk_t device_clk, mxc_clkman_clk_scale_t clk_scale);
+
+/**
+ * @brief Set RTC clock for systick counter, allowing systick to operate in full clockgating powersaving mode
+ * @param enable 1 enable 0 disable
+ */
+void CLKMAN_SetRTOSMode(uint8_t enable);
+
+/**
+ * @}
+ */
+
+#endif /* _CLKMAN_H */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/flc.c Tue Jul 18 14:57:27 2017 +0000
@@ -0,0 +1,125 @@
+/*******************************************************************************
+ * Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+ * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Except as contained in this notice, the name of Maxim Integrated
+ * Products, Inc. shall not be used except as stated in the Maxim Integrated
+ * Products, Inc. Branding Policy.
+ *
+ * The mere transfer of this software does not imply any licenses
+ * of trade secrets, proprietary technology, copyrights, patents,
+ * trademarks, maskwork rights, or any other form of intellectual
+ * property whatsoever. Maxim Integrated Products, Inc. retains all
+ * ownership rights.
+ *******************************************************************************
+ */
+
+/* $Revision: 3277 $ $Date: 2014-10-02 13:39:01 -0500 (Thu, 02 Oct 2014) $ */
+
+#include "./mxc_config.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#include "./flc.h"
+#include "./icc_regs.h"
+
+
+int32_t FLC_Erase(uint32_t address, uint8_t erase_code, uint8_t unlock_key)
+{
+ if(!MXC_ICC->ctrl_stat_f.enable) {
+ return -1;
+ }
+
+ mxc_flc_ctrl_t fcntl = MXC_FLC->ctrl_f;
+ fcntl.erase_code = 0; /* clear erase code */
+ fcntl.auto_incre_mode = 0; /* clear burst */
+ MXC_FLC->ctrl_f = fcntl;
+
+ fcntl.flsh_unlock = unlock_key;
+ fcntl.erase_code = erase_code;
+ MXC_FLC->ctrl_f = fcntl;
+
+ MXC_FLC->faddr = (address & MXC_FLC_PAGE_ERASE_MSK); /* set bank address */
+
+ fcntl = MXC_FLC->ctrl_f;
+ fcntl.page_erase = 1; /* set and start erase operation */
+ MXC_FLC->ctrl_f = fcntl;
+
+ do {
+ fcntl = MXC_FLC->ctrl_f;
+ } while (fcntl.pending); /* wait until done */
+
+ fcntl = MXC_FLC->ctrl_f;
+ fcntl.erase_code = 0; /* lock flash */
+ fcntl.flsh_unlock = 0;
+ MXC_FLC->ctrl_f = fcntl;
+
+ return 0;
+}
+
+int32_t FLC_WriteBlock(uint32_t address, const void *data, uint32_t length, uint8_t unlock_key)
+{
+ uint32_t *word = (uint32_t *) data;
+
+ if(!MXC_ICC->ctrl_stat_f.enable) {
+ return -1;
+ }
+
+ if(address & 3) { /* address needs to be aligned with word */
+ return -1;
+ }
+
+ length = length & 0xfffffffc;
+
+ mxc_flc_ctrl_t fcntl = MXC_FLC->ctrl_f;
+ fcntl.erase_code = 0; /* clear erase code */
+ fcntl.auto_incre_mode = 0; /* clear burst */
+ MXC_FLC->ctrl_f = fcntl;
+
+ fcntl.flsh_unlock = unlock_key; /* set unlock */
+ MXC_FLC->ctrl_f = fcntl;
+
+ while (length)
+ {
+ MXC_FLC->faddr = address;
+ MXC_FLC->fdata = *word;
+
+ fcntl = MXC_FLC->ctrl_f;
+ fcntl.write = 1;
+ MXC_FLC->ctrl_f = fcntl;
+
+ address += 4;
+ word++;
+ length -= 4;
+
+ do {
+ fcntl = MXC_FLC->ctrl_f;
+ } while (fcntl.pending);
+ }
+
+ fcntl = MXC_FLC->ctrl_f;
+ fcntl.erase_code = 0; /* lock flash */
+ fcntl.flsh_unlock = 0;
+ MXC_FLC->ctrl_f = fcntl;
+
+ return 0;
+}
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/flc.h Tue Jul 18 14:57:27 2017 +0000
@@ -0,0 +1,86 @@
+/*******************************************************************************
+* Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of Maxim Integrated
+* Products, Inc. shall not be used except as stated in the Maxim Integrated
+* Products, Inc. Branding Policy.
+*
+* The mere transfer of this software does not imply any licenses
+* of trade secrets, proprietary technology, copyrights, patents,
+* trademarks, maskwork rights, or any other form of intellectual
+* property whatsoever. Maxim Integrated Products, Inc. retains all
+* ownership rights.
+*******************************************************************************
+*/
+
+/* $Revision: 2905 $ $Date: 2014-08-05 17:18:09 -0500 (Tue, 05 Aug 2014) $ */
+
+#ifndef _FLASH_H
+#define _FLASH_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "flc_regs.h"
+
+/**
+ * @file flc.h
+ * @addtogroup flash Flash Controller
+ * @{
+ * @brief This is the high level API for the internal flash controller module
+ * of the MAX32600 family of ARM Cortex based embedded microcontrollers.
+ */
+
+/**
+ * @brief This function will erase a single page of flash, 1 page is
+ * 2K bytes. Keys needed for flash are in the hardware specific
+ * register file "flc_regs.h"
+ *
+ * @param address Start address that needs to be erased, must be aligned with 0x800
+ * @param erase_code Flash erase code; defined as 'MXC_V_FLC_ERASE_CODE_PAGE_ERASE' for page erase
+ * @param unlock_key Key necessary for accessing flash; defined as 'MXC_V_FLC_FLSH_UNLOCK_KEY'
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t FLC_Erase(uint32_t address, uint8_t erase_code, uint8_t unlock_key);
+
+/**
+ * @brief This function writes data to the flash device through flash controller
+ *
+ * @param address Start address that needs to be written, must be aligned with 4 bytes
+ * @param data Pointer to the buffer containing data to write
+ * @param length Size of the data to write in bytes, must be multiple of 4 bytes
+ * @param unlock_key Key necessary for accessing flash; defined as 'MXC_V_FLC_FLSH_UNLOCK_KEY'
+ *
+ * @return 0 => Success. Non zero => error condition.
+ */
+int32_t FLC_WriteBlock(uint32_t address, const void *data, uint32_t length, uint8_t unlock_key);
+
+/**
+ * @}
+ */
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/flc_regs.h Tue Jul 18 14:57:27 2017 +0000
@@ -0,0 +1,282 @@
+/*******************************************************************************
+* Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of Maxim Integrated
+* Products, Inc. shall not be used except as stated in the Maxim Integrated
+* Products, Inc. Branding Policy.
+*
+* The mere transfer of this software does not imply any licenses
+* of trade secrets, proprietary technology, copyrights, patents,
+* trademarks, maskwork rights, or any other form of intellectual
+* property whatsoever. Maxim Integrated Products, Inc. retains all
+* ownership rights.
+*******************************************************************************
+*/
+
+/* $Revision: 3550 $ $Date: 2014-11-12 11:45:23 -0600 (Wed, 12 Nov 2014) $ */
+
+#ifndef _MXC_FLC_REGS_H
+#define _MXC_FLC_REGS_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+
+/*
+ Bitfield structs for registers in this module
+*/
+
+
+typedef struct
+{
+ uint32_t faddr : 18;
+ uint32_t : 14;
+} mxc_flc_faddr_t;
+
+typedef struct
+{
+ uint32_t fckdiv : 5;
+ uint32_t : 27;
+} mxc_flc_fckdiv_t;
+
+typedef struct
+{
+ uint32_t write : 1;
+ uint32_t mass_erase : 1;
+ uint32_t page_erase : 1;
+ uint32_t : 5;
+ uint32_t erase_code : 8;
+ uint32_t info_block_unlock : 1;
+ uint32_t write_enable : 1;
+ uint32_t : 6;
+ uint32_t pending : 1;
+ uint32_t info_block_valid : 1;
+ uint32_t : 1;
+ uint32_t auto_incre_mode : 1;
+ uint32_t flsh_unlock : 4;
+} mxc_flc_ctrl_t;
+
+typedef struct
+{
+ uint32_t write_erase : 1;
+ uint32_t flsh_fail : 1;
+ uint32_t : 6;
+ uint32_t done : 1;
+ uint32_t failed : 1;
+ uint32_t : 22;
+} mxc_flc_intr_t;
+
+typedef struct
+{
+ uint32_t delay_se_en : 1;
+ uint32_t : 7;
+ uint32_t fast_read_mode_en : 1;
+ uint32_t : 23;
+} mxc_flc_perform_t;
+
+typedef struct
+{
+ uint32_t jtag_lock_window : 1;
+ uint32_t jtag_lock_static : 1;
+ uint32_t : 1;
+ uint32_t auto_lock : 1;
+ uint32_t : 25;
+ uint32_t trim_update_done : 1;
+ uint32_t info_block_valid : 1;
+ uint32_t : 1;
+} mxc_flc_status_t;
+
+typedef struct
+{
+ uint32_t debug_disable : 1;
+ uint32_t : 7;
+ uint32_t mass_erase_lock : 1;
+ uint32_t : 22;
+ uint32_t security_lock : 1;
+} mxc_flc_security_t;
+
+typedef struct
+{
+ uint32_t destruct_bypass_erase : 1;
+ uint32_t superwipe_erase : 1;
+ uint32_t destruct_bypass_complete : 1;
+ uint32_t superwipe_complete : 1;
+ uint32_t : 28;
+} mxc_flc_bypass_t;
+
+typedef struct
+{
+ uint32_t flash_lve : 1;
+ uint32_t : 7;
+ uint32_t bypass_ahb_fail : 1;
+ uint32_t : 23;
+} mxc_flc_ctrl2_t;
+
+typedef struct
+{
+ uint32_t sram_addr_wrapped : 1;
+ uint32_t invalid_flash_addr : 1;
+ uint32_t flash_read_locked : 1;
+ uint32_t trim_update_done : 1;
+ uint32_t : 28;
+} mxc_flc_intfl1_t;
+
+typedef struct
+{
+ uint32_t sram_addr_wrapped : 1;
+ uint32_t invalid_flash_addr : 1;
+ uint32_t flash_read_locked : 1;
+ uint32_t trim_update_done : 1;
+ uint32_t : 28;
+} mxc_flc_inten1_t;
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ register access along with union access to bit/bitfield struct (where defined).
+*/
+
+/* Offset Register Description
+ ====== ======================================================= */
+typedef struct {
+ union {
+ __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
+ __IO mxc_flc_faddr_t faddr_f;
+ };
+ union {
+ __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */
+ __IO mxc_flc_fckdiv_t fckdiv_f;
+ };
+ union {
+ __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
+ __IO mxc_flc_ctrl_t ctrl_f;
+ };
+ __R uint32_t rsv000C[6]; /* 0x000C */
+ union {
+ __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
+ __IO mxc_flc_intr_t intr_f;
+ };
+ __R uint32_t rsv0028[2]; /* 0x0028 */
+
+ __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
+
+ __R uint32_t rsv0034[7]; /* 0x0034 */
+ union {
+ __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
+ __IO mxc_flc_perform_t perform_f;
+ };
+ __R uint32_t rsv0054[11]; /* 0x0054 */
+ union {
+ __IO uint32_t status; /* 0x0080 Security Status Flags */
+ __IO mxc_flc_status_t status_f;
+ };
+ __R uint32_t rsv0084; /* 0x0084 */
+ union {
+ __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
+ __IO mxc_flc_security_t security_f;
+ };
+ __R uint32_t rsv008C[4]; /* 0x008C */
+ union {
+ __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
+ __IO mxc_flc_bypass_t bypass_f;
+ };
+
+ __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
+ __R uint32_t rsv0104[15]; /* 0x0104 */
+ union {
+ __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
+ __IO mxc_flc_ctrl2_t ctrl2_f;
+ };
+ union {
+ __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
+ __IO mxc_flc_intfl1_t intfl1_f;
+ };
+ union {
+ __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
+ __IO mxc_flc_inten1_t inten1_f;
+ };
+ __R uint32_t rsv014C; /* 0x014C */
+ __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */
+ __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */
+ __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */
+ __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */
+ __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */
+ __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */
+ __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */
+ __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */
+} mxc_flc_regs_t;
+
+
+/*
+ Register offsets for module FLC.
+*/
+#define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
+#define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
+#define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
+#define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
+#define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
+#define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
+#define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
+#define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
+#define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
+#define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
+#define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
+#define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
+#define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL)
+#define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL)
+#define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL)
+#define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL)
+
+#define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
+#define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
+
+#define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MXC_FLC_REGS_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/icc_regs.h Tue Jul 18 14:57:27 2017 +0000
@@ -0,0 +1,125 @@
+/*******************************************************************************
+* Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of Maxim Integrated
+* Products, Inc. shall not be used except as stated in the Maxim Integrated
+* Products, Inc. Branding Policy.
+*
+* The mere transfer of this software does not imply any licenses
+* of trade secrets, proprietary technology, copyrights, patents,
+* trademarks, maskwork rights, or any other form of intellectual
+* property whatsoever. Maxim Integrated Products, Inc. retains all
+* ownership rights.
+*******************************************************************************
+*/
+
+/* $Revision: 3545 $ $Date: 2014-11-11 18:20:37 -0600 (Tue, 11 Nov 2014) $ */
+
+#ifndef _MXC_ICC_REGS_H_
+#define _MXC_ICC_REGS_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/*
+ If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+/*
+ Bitfield structs for registers in this module
+*/
+typedef struct
+{
+ uint32_t rtl_version : 6;
+ uint32_t part_num : 4;
+ uint32_t cache_id : 6;
+ uint32_t : 16;
+} mxc_icc_id_t;
+
+typedef struct
+{
+ uint32_t cache_size : 16;
+ uint32_t main_memory_size : 16;
+} mxc_icc_mem_cfg_t;
+
+typedef struct
+{
+ uint32_t enable : 1;
+ uint32_t : 15;
+ uint32_t ready : 1;
+ uint32_t : 15;
+} mxc_icc_ctrl_stat_t;
+
+
+/*
+ Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
+ register access along with union access to bit/bitfield struct (where defined).
+*/
+/* Offset Register Description
+ ====== =================================================== */
+typedef struct {
+ union {
+ __IO uint32_t id; /* 0x0000 Device ID Register */
+ __IO mxc_icc_id_t id_f;
+ };
+ union {
+ __IO uint32_t mem_cfg; /* 0x0004 Memory Configuration */
+ __IO mxc_icc_mem_cfg_t mem_cfg_f;
+ };
+ __R uint32_t rsv0008[62]; /* 0x0008 */
+ union {
+ __IO uint32_t ctrl_stat; /* 0x0100 Control and Status */
+ __IO mxc_icc_ctrl_stat_t ctrl_stat_f;
+ };
+ __R uint32_t rsv0104[383]; /* 0x0104 */
+ __IO uint32_t invdt_all; /* 0x0700 Invalidate (Clear) Cache Control */
+} mxc_icc_regs_t;
+
+
+/*
+ Register offsets for module ICC.
+*/
+#define MXC_R_ICC_OFFS_ID ((uint32_t)0x00000000UL)
+#define MXC_R_ICC_OFFS_MEM_CFG ((uint32_t)0x00000004UL)
+#define MXC_R_ICC_OFFS_CTRL_STAT ((uint32_t)0x00000100UL)
+#define MXC_R_ICC_OFFS_INVDT_ALL ((uint32_t)0x00000700UL)
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
--- a/main.cpp Tue Mar 14 14:00:04 2017 +0000
+++ b/main.cpp Tue Jul 18 14:57:27 2017 +0000
@@ -1,12 +1,239 @@
+#include <USBHID/USBHID_Types.h>
#include "mbed.h"
+#include "USBHID.h"
+#include "rtos.h"
+#include "flc.h"
+#include "mbed_application.h"
+#include "Adafruit_SSD1306.h"
+#include "Adafruit_GFX.h"
-DigitalOut led1(LED1);
-
+DigitalOut led3(LED3);
+USBHID hid(64,64,0x1234,0x0006,0x0001,false);
+HID_REPORT recv;
// main() runs in its own thread in the OS
+Thread thd_hid;
+
+I2C I2c_oled(P2_6,P2_7);
+//SPI,DC,RST,CS
+Adafruit_SSD1306_I2c oled(I2c_oled,P2_6);
+
+const unsigned char unyte[128][8] = {
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x80,0xFC,0x0E,0x0E,0xFC,0x80,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0x98,0x30,0x60,0xE0,0xC0,0x00,0x00,0x00,
+0x1F,0xF4,0x80,0x80,0xF4,0x1F,0x00,0x00,0x00,0xC0,0xE0,0x60,0x30,0x98,0xF8,0xF8,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x0F,0x1C,0x18,0x19,0x33,0x3F,0x3C,
+0x30,0x01,0x03,0x03,0x01,0x30,0x3C,0x3F,0x33,0x19,0x18,0x1C,0x0F,0x03,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF8,0xF0,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+
+0x00,0x00,0x00,0x00,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0x00,0x00,0x00,
+0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xF0,0xF8,0xF8,0xFC,0xFC,0xFE,0xFE,0xFE,
+0xFE,0xFE,0xFC,0xFC,0xF8,0xF0,0xE0,0x84,0x3C,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,
+0xF8,0xC0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xF0,0xFC,0xFC,0xFC,0xFC,0xFC,0xFC,
+0xFC,0x7C,0x0C,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0xFC,0xFC,
+0xFC,0xFC,0xFC,0x00,0x00,0x80,0xC0,0xE0,0xF0,0xF8,0xFC,0xFC,0xFC,0xFE,0x7E,0x7E,
+0x7E,0x7E,0x7E,0xFE,0xFC,0xFC,0xFC,0xF8,0xF0,0xE0,0xC0,0x80,0x00,0x00,0x00,0x00,
+
+0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x0F,0x03,0x01,0x00,0x00,0x00,0x01,0x03,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x07,0x1F,0xFF,0xFF,0xFF,0xFF,
+0xFF,0xFF,0xFE,0xF0,0x80,0x00,0xC0,0xF8,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x0F,
+0x01,0x00,0x00,0x00,0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,
+0x00,0x00,0x00,0xF0,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF9,0xF8,0xF8,0xF8,
+0xF8,0xF8,0xF8,0xF8,0xF9,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0x00,0x00,0x00,
+
+0x00,0x00,0x00,0x00,0x0F,0x3F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xF8,0xF8,0xF0,
+0xF0,0xF0,0xF8,0xF8,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x3F,0x0F,0x00,0x00,0x00,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00,0x00,0x00,0x00,0x00,0x03,0x1F,0x7F,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x1F,0x03,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xF0,0xF0,0xE0,
+0xE0,0xF0,0x00,0x00,0x0F,0x3F,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xF9,0xF1,0xF1,0xE1,
+0xE1,0xE1,0xE1,0xE1,0xF1,0xF9,0xF9,0xF9,0xF1,0xF1,0xE1,0x61,0x01,0x00,0x00,0x00,
+
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x03,0x03,0x07,0x07,0x07,0x07,0x07,
+0x07,0x07,0x07,0x07,0x07,0x07,0x03,0x03,0x01,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x0F,0x7F,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFC,0xF0,0xF0,0xE0,0xE0,0xE0,0xF0,0xF8,
+0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x7F,0x3F,0x07,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x03,0x03,0x07,0x07,0x07,0x07,0x07,0x07,0x07,
+0x07,0x07,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x03,0x03,0x03,0x07,0x07,0x07,0x07,
+0x07,0x07,0x07,0x07,0x07,0x07,0x03,0x03,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,
+
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x01,0x03,0x07,0x0F,0x0F,0x1F,0x1F,0x1F,0x3F,0x3F,0x3F,0x3F,0x1F,
+0x1F,0x1F,0x1F,0x0F,0x0F,0x07,0x03,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
+};
+
+const unsigned char blank[128][8] = {
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
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+
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+
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+
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+
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+
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+};
+
int main() {
- while (true) {
- led1 = !led1;
- wait(0.5);
- }
+
+int width=16, space=4;
+double t=0.5;
+
+while(true){
+ oled.drawBitmap(0,0,*unyte,128,64,1);
+ oled.display();
+ wait(3);
+ oled.clearDisplay();
+
+ oled.drawBitmap(0,0,*blank,128,64,1);
+ oled.display();
+ wait(1);
+
+ oled.drawChar(21,10,'G',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(36,10,'u',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(50,10,'i',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(58,10,'d',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(72,10,'i',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(80,10,'n',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(94,10,'g',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(107,10,' ',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(40,35,'Y',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(55,35,'o',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(69,35,'u',1,1,1);
+ oled.display();
+ wait(t);
+
+ oled.drawChar(83,35,'.',1,1,1);
+ oled.display();
+ wait(3);
+
+ // oled.fillRect(21,10,80,40,BLACK);
+ // wait(2);
+
+ oled.clearDisplay();
+
+
}
+}
\ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/max32600.h Tue Jul 18 14:57:27 2017 +0000
@@ -0,0 +1,646 @@
+/*******************************************************************************
+* Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
+* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+* Except as contained in this notice, the name of Maxim Integrated
+* Products, Inc. shall not be used except as stated in the Maxim Integrated
+* Products, Inc. Branding Policy.
+*
+* The mere transfer of this software does not imply any licenses
+* of trade secrets, proprietary technology, copyrights, patents,
+* trademarks, maskwork rights, or any other form of intellectual
+* property whatsoever. Maxim Integrated Products, Inc. retains all
+* ownership rights.
+*******************************************************************************
+*/
+
+/* $Revision: 4395 $ $Date: 2015-02-17 15:52:32 -0600 (Tue, 17 Feb 2015) $ */
+
+#include <stdint.h>
+
+#ifndef _MAX32600_H_
+#define _MAX32600_H_
+
+#ifndef FALSE
+#define FALSE (0)
+#endif
+
+#ifndef TRUE
+#define TRUE (1)
+#endif
+
+#define __NVIC_PRIO_BITS 3
+
+typedef enum IRQn_Type {
+ NonMaskableInt_IRQn = -14,
+ HardFault_IRQn = -13,
+ MemoryManagement_IRQn = -12,
+ BusFault_IRQn = -11,
+ UsageFault_IRQn = -10,
+ SVCall_IRQn = -5,
+ DebugMonitor_IRQn = -4,
+ PendSV_IRQn = -2,
+ SysTick_IRQn = -1,
+
+ /* Maxim 32600 Externals interrupts */
+ UART0_IRQn = 0, /* 16:01 UART0 */
+ UART1_IRQn, /* 17: 2 UART1 */
+ I2CM0_IRQn, /* 18: 3 I2C Master 0 */
+ I2CS_IRQn, /* 19: 4 I2C Slave */
+ USB_IRQn, /* 20: 5 USB */
+ PMU_IRQn, /* 21: 6 DMA */
+ AFE_IRQn, /* 22: 7 AFE */
+ MAA_IRQn, /* 23: 8 MAA */
+ AES_IRQn, /* 24: 9 AES */
+ SPI0_IRQn, /* 25:10 SPI0 */
+ SPI1_IRQn, /* 26:11 SPI1 */
+ SPI2_IRQn, /* 27:12 SPI2 */
+ TMR0_IRQn, /* 28:13 Timer32-0 */
+ TMR1_IRQn, /* 29:14 Timer32-1 */
+ TMR2_IRQn, /* 30:15 Timer32-1 */
+ TMR3_IRQn, /* 31:16 Timer32-2 */
+ RSVD0_IRQn, /* 32:17 RSVD */
+ RSVD1_IRQn, /* 33:18 RSVD */
+ DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */
+ DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */
+ DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */
+ DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */
+ ADC_IRQn, /* 38:23 ADC */
+ FLC_IRQn, /* 39:24 Flash Controller */
+ PWRMAN_IRQn, /* 40:25 PWRMAN */
+ CLKMAN_IRQn, /* 41:26 CLKMAN */
+ RTC0_IRQn, /* 42:27 RTC INT0 */
+ RTC1_IRQn, /* 43:28 RTC INT1 */
+ RTC2_IRQn, /* 44:29 RTC INT2 */
+ RTC3_IRQn, /* 45:30 RTC INT3 */
+ WDT0_IRQn, /* 46:31 WATCHDOG0 */
+ WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */
+ WDT1_IRQn, /* 48:33 WATCHDOG1 */
+ WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */
+ GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */
+ GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */
+ GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */
+ GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */
+ GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */
+ GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */
+ GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */
+ GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */
+ TMR16_0_IRQn, /* 58:43 Timer16-s0 */
+ TMR16_1_IRQn, /* 59:44 Timer16-s1 */
+ TMR16_2_IRQn, /* 60:45 Timer16-s2 */
+ TMR16_3_IRQn, /* 61:46 Timer16-s3 */
+ I2CM1_IRQn, /* 62:47 I2C Master 1 */
+ MXC_IRQ_EXT_COUNT,
+} IRQn_Type;
+
+#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
+
+#include "core_cm3.h"
+#include "system_max32600.h"
+
+/*
+ Base addresses and configuration settings for all MAX32600 peripheral modules.
+*/
+
+/*******************************************************************************/
+/* General Purpose I/O Ports (GPIO) */
+
+
+#define MXC_BASE_GPIO ((uint32_t)0x40000000UL)
+#define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
+#define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL)
+
+
+/*******************************************************************************/
+/* Pulse Train Generation */
+
+#define MXC_CFG_PT_INSTANCES (13)
+
+#define MXC_BASE_PTG ((uint32_t)0x40001000UL)
+#define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
+#define MXC_BASE_PT ((uint32_t)0x40001008UL)
+#define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT)
+#define MXC_BASE_PT0 ((uint32_t)0x40001008UL)
+#define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
+#define MXC_BASE_PT1 ((uint32_t)0x40001010UL)
+#define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
+#define MXC_BASE_PT2 ((uint32_t)0x40001018UL)
+#define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
+#define MXC_BASE_PT3 ((uint32_t)0x40001020UL)
+#define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
+#define MXC_BASE_PT4 ((uint32_t)0x40001028UL)
+#define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
+#define MXC_BASE_PT5 ((uint32_t)0x40001030UL)
+#define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
+#define MXC_BASE_PT6 ((uint32_t)0x40001038UL)
+#define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
+#define MXC_BASE_PT7 ((uint32_t)0x40001040UL)
+#define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
+#define MXC_BASE_PT8 ((uint32_t)0x40001048UL)
+#define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
+#define MXC_BASE_PT9 ((uint32_t)0x40001050UL)
+#define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
+#define MXC_BASE_PT10 ((uint32_t)0x40001058UL)
+#define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
+#define MXC_BASE_PT11 ((uint32_t)0x40001060UL)
+#define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
+
+/* PT12, PT13, PT14 are not used */
+
+/*******************************************************************************/
+/* CRC-16/CRC-32 Engine */
+
+#define MXC_BASE_CRC ((uint32_t)0x40010000UL)
+#define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC)
+
+#define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL)
+#define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
+
+/*******************************************************************************/
+/* Trust Protection Unit (TPU) */
+
+#define MXC_BASE_TPU ((uint32_t)0x40011000UL)
+#define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
+
+#define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL)
+#define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
+
+/*******************************************************************************/
+/* AES Cryptographic Engine */
+
+#define MXC_BASE_AES ((uint32_t)0x40011400UL)
+#define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
+
+#define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL)
+#define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
+
+
+/*******************************************************************************/
+/* MAA Cryptographic Engine */
+
+#define MXC_BASE_MAA ((uint32_t)0x40011800UL)
+#define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
+
+#define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL)
+#define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
+
+/*******************************************************************************/
+/* 32-Bit PWM Timer/Counter */
+
+#define MXC_CFG_TMR_INSTANCES (4)
+
+#define MXC_BASE_TMR0 ((uint32_t)0x40012000UL)
+#define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL)
+#define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
+
+#define MXC_BASE_TMR1 ((uint32_t)0x40013000UL)
+#define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL)
+#define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
+
+#define MXC_BASE_TMR2 ((uint32_t)0x40014000UL)
+#define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL)
+#define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
+
+#define MXC_BASE_TMR3 ((uint32_t)0x40015000UL)
+#define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL)
+#define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
+
+
+#define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \
+ (i) == 1 ? TMR1_IRQn : \
+ (i) == 2 ? TMR2_IRQn : \
+ (i) == 3 ? TMR3_IRQn : 0)
+
+#define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \
+ (i) == 1 ? TMR1_IRQn : \
+ (i) == 2 ? TMR2_IRQn : \
+ (i) == 3 ? TMR3_IRQn : \
+ (i) == 4 ? TMR16_0_IRQn : \
+ (i) == 5 ? TMR16_1_IRQn : \
+ (i) == 6 ? TMR16_2_IRQn : \
+ (i) == 7 ? TMR16_3_IRQn : 0)
+
+#define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
+ (i) == 1 ? MXC_BASE_TMR1 : \
+ (i) == 2 ? MXC_BASE_TMR2 : \
+ (i) == 3 ? MXC_BASE_TMR3 : 0)
+
+#define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
+ (i) == 1 ? MXC_TMR1 : \
+ (i) == 2 ? MXC_TMR2 : \
+ (i) == 3 ? MXC_TMR3 : 0)
+/*******************************************************************************/
+/* Watchdog Timer */
+
+#define MXC_CFG_WDT_INSTANCES (2)
+
+#define MXC_BASE_WDT0 ((uint32_t)0x40021000UL)
+#define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL)
+#define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
+
+#define MXC_BASE_WDT1 ((uint32_t)0x40022000UL)
+#define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL)
+#define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
+
+#define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \
+ (i) == 1 ? WDT1_IRQn : 0)
+
+#define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \
+ (i) == 1 ? WDT1_P_IRQn : 0)
+
+#define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
+ (i) == 1 ? MXC_BASE_WDT1 : 0)
+
+#define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
+ (i) == 1 ? MXC_WDT1 : 0)
+
+/*******************************************************************************/
+/* SPI Interface */
+
+#define MXC_CFG_SPI_INSTANCES (3)
+#define MXC_CFG_SPI_FIFO_DEPTH (16)
+
+
+#define MXC_BASE_SPI0 ((uint32_t)0x40030000UL)
+#define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
+
+#define MXC_BASE_SPI0_FIFO ((uint32_t)0x40100000UL)
+#define MXC_SPI0_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI0_FIFO)
+
+#define MXC_BASE_SPI1 ((uint32_t)0x40031000UL)
+#define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
+
+#define MXC_BASE_SPI1_FIFO ((uint32_t)0x40101000UL)
+#define MXC_SPI1_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI1_FIFO)
+
+#define MXC_BASE_SPI2 ((uint32_t)0x40032000UL)
+#define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
+
+#define MXC_BASE_SPI2_FIFO ((uint32_t)0x40102000UL)
+#define MXC_SPI2_FIFO ((mxc_spi_fifo_regs_t *)MXC_BASE_SPI2_FIFO)
+
+
+#define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \
+ (i) == 1 ? SPI1_IRQn : \
+ (i) == 2 ? SPI2_IRQn : 0)
+
+#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
+ (i) == 1 ? MXC_BASE_SPI1 : \
+ (i) == 2 ? MXC_BASE_SPI2 : 0)
+
+#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
+ (i) == 1 ? MXC_SPI1 : \
+ (i) == 2 ? MXC_SPI2 : 0)
+
+#define MXC_SPI_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPI0_FIFO : \
+ (i) == 1 ? MXC_BASE_SPI1_FIFO : \
+ (i) == 2 ? MXC_BASE_SPI2_FIFO : 0)
+
+#define MXC_SPI_GET_SPI_FIFO(i) ((i) == 0 ? MXC_SPI0_FIFO : \
+ (i) == 1 ? MXC_SPI1_FIFO : \
+ (i) == 2 ? MXC_SPI2_FIFO : 0)
+
+
+/*******************************************************************************/
+/* UART Interface */
+
+#define MXC_CFG_UART_INSTANCES (2)
+
+#define MXC_BASE_UART0 ((uint32_t)0x40038000UL)
+#define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL)
+#define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
+
+#define MXC_BASE_UART1 ((uint32_t)0x40039000UL)
+#define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL)
+#define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
+
+
+#define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \
+ (i) == 1 ? UART1_IRQn : 0)
+
+#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
+ (i) == 1 ? MXC_BASE_UART1 : 0)
+
+#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
+ (i) == 1 ? MXC_UART1 : 0)
+
+#define MXC_CFG_UART_FIFO_DEPTH (8)
+
+
+/*******************************************************************************/
+/* I2C Master Interface */
+
+#define MXC_CFG_I2CM_INSTANCES (2)
+
+#define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL)
+#define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL)
+#define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
+
+#define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40103000UL)
+
+#define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL)
+#define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL)
+#define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
+
+#define MXC_BASE_I2CM1_FIFO ((uint32_t)0x4010D000UL)
+
+
+#define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \
+ (i) == 1 ? I2CM1_IRQn : 0)
+
+#define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
+ (i) == 1 ? MXC_BASE_I2CM1 : 0)
+
+#define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
+ (i) == 1 ? MXC_I2CM1 : 0)
+
+#define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
+ (i) == 1 ? MXC_BASE_I2CM1_FIFO : 0)
+
+
+/*******************************************************************************/
+/* I2C Slave Interface */
+
+#define MXC_CFG_I2CS_INSTANCES (1)
+
+#define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL)
+#define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL)
+#define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
+
+#define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL)
+#define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
+
+
+
+/*******************************************************************************/
+/* DACs */
+
+#define MXC_CFG_DAC_INSTANCES (4)
+#define MXC_CFG_DAC_FIFO_DEPTH (32)
+
+#define MXC_BASE_DAC0 ((uint32_t)0x40050000UL)
+#define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0)
+#define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL)
+#define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
+#define MXC_DAC0_WIDTH ((uint8_t)(2))
+
+#define MXC_BASE_DAC1 ((uint32_t)0x40051000UL)
+#define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1)
+#define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL)
+#define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
+#define MXC_DAC1_WIDTH ((uint8_t)(2))
+
+#define MXC_BASE_DAC2 ((uint32_t)0x40052000UL)
+#define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2)
+#define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL)
+#define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
+#define MXC_DAC2_WIDTH ((uint8_t)(1))
+
+#define MXC_BASE_DAC3 ((uint32_t)0x40053000UL)
+#define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3)
+#define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL)
+#define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
+#define MXC_DAC3_WIDTH ((uint8_t)(1))
+
+
+#define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \
+ (i) == 1 ? DAC1_IRQn : \
+ (i) == 2 ? DAC2_IRQn : \
+ (i) == 3 ? DAC3_IRQn : 0)
+
+
+#define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
+ i == 1 ? MXC_BASE_DAC1 : \
+ i == 2 ? MXC_BASE_DAC2 : \
+ i == 3 ? MXC_BASE_DAC3 : 0)
+
+#define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
+ i == 1 ? MXC_BASE_DAC1_FIFO : \
+ i == 2 ? MXC_BASE_DAC2_FIFO : \
+ i == 3 ? MXC_BASE_DAC3_FIFO : 0)
+
+#define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
+ i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
+ i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \
+ i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0)
+
+#define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \
+ i == 1 ? MXC_DAC1 : \
+ i == 2 ? MXC_DAC2 : \
+ i == 3 ? MXC_DAC3 : 0)
+
+#define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \
+ i == 1 ? MXC_DAC1_WIDTH : \
+ i == 2 ? MXC_DAC2_WIDTH : \
+ i == 3 ? MXC_DAC3_WIDTH : 0)
+
+
+/*******************************************************************************/
+/* Analog Front End */
+
+#define MXC_BASE_AFE ((uint32_t)0x4005401CUL)
+#define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE)
+
+
+
+/*******************************************************************************/
+/* ADC */
+
+#define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32))
+
+#define MXC_BASE_ADC ((uint32_t)0x40054000UL)
+#define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
+
+#define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL)
+#define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
+
+#define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL)
+
+
+
+/*******************************************************************************/
+/* LCD */
+#define MXC_BASE_LCD ((uint32_t)0x40060000)
+#define MXC_LCD ((mxc_lcd_regs_t *)MXC_BASE_LCD)
+
+/*******************************************************************************/
+/* Peripheral Management Unit (PMU) - formerly DMA Controller */
+
+#define MXC_CFG_PMU_CHANNELS (6)
+
+#define MXC_BASE_PMU0 ((uint32_t)0x40070000UL)
+#define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
+#define MXC_BASE_PMU1 ((uint32_t)0x40070020UL)
+#define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
+#define MXC_BASE_PMU2 ((uint32_t)0x40070040UL)
+#define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
+#define MXC_BASE_PMU3 ((uint32_t)0x40070060UL)
+#define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
+#define MXC_BASE_PMU4 ((uint32_t)0x40070080UL)
+#define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
+#define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL)
+#define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
+
+#define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL)
+#define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL)
+/*******************************************************************************/
+
+typedef enum {
+ PMU_IRQ_DAC0_FIFO_AE,
+ PMU_IRQ_DAC1_FIFO_AE,
+ PMU_IRQ_DAC2_FIFO_AE,
+ PMU_IRQ_DAC3_FIFO_AE,
+ PMU_IRQ_DAC0_DONE,
+ PMU_IRQ_DAC1_DONE,
+ PMU_IRQ_DAC2_DONE,
+ PMU_IRQ_DAC3_DONE,
+ PMU_IRQ_ADC_FIFO_AF,
+ PMU_IRQ_ADC_DONE,
+ PMU_IRQ_I2C_MST0_DONE,
+ PMU_IRQ_I2C_MST1_DONE,
+ PMU_IRQ_SPI0_RSLTS_DONE,
+ PMU_IRQ_SPI1_RSLTS_DONE,
+ PMU_IRQ_SPI2_RSLTS_DONE,
+ PMU_IRQ_MAA_DONE,
+ PMU_IRQ_SPI0_TX_FIFO_AE,
+ PMU_IRQ_SPI0_RSLTS_FIFO_AF,
+ PMU_IRQ_SPI1_TX_FIFO_AE,
+ PMU_IRQ_SPI1_RSLTS_FIFO_AF,
+ PMU_IRQ_SPI2_TX_FIFO_AE,
+ PMU_IRQ_SPI3_RSLTS_FIFO_AF,
+ PMU_IRQ_I2C_MST0_TRANS_FIFO,
+ PMU_IRQ_I2C_MST0_RSLT_FIFO,
+ PMU_IRQ_I2C_MST1_TRANS_FIFO,
+ PMU_IRQ_I2C_MST2_RSLT_FIFO,
+ PMU_IRQ_I2C_SLV_TRANS_FIFO,
+ PMU_IRQ_I2C_SLV_RSLT_FIFO,
+ PMU_IRQ_UART0_TX_FIFO,
+ PMU_IRQ_UART0_RX_FIFO,
+ PMU_IRQ_UART1_TX_FIFO,
+ PMU_IRQ_UART1_RX_FIFO,
+ PMU_IRQ_SPI0_EXCP,
+ PMU_IRQ_SPI1_EXCP,
+ PMU_IRQ_SPI2_EXCP,
+ PMU_IRQ_RSVD0,
+ PMU_IRQ_I2C_MST0_EXCP,
+ PMU_IRQ_I2C_MST1_EXCP,
+ PMU_IRQ_I2C_SLV_EXCP,
+ PMU_IRQ_RSVD1,
+ PMU_IRQ_GPIO0,
+ PMU_IRQ_GPIO1,
+ PMU_IRQ_GPIO2,
+ PMU_IRQ_GPIO3,
+ PMU_IRQ_GPIO4,
+ PMU_IRQ_GPIO5,
+ PMU_IRQ_GPIO6,
+ PMU_IRQ_GPIO7,
+ PMU_IRQ_GPIO8,
+ PMU_IRQ_AFE_COMP_NMI,
+ PMU_IRQ_AES_ENGINE,
+} pmu_int_mask_t;
+
+/*******************************************************************************/
+/* USB */
+
+#define MXC_BASE_USB ((uint32_t)0x4010C000UL)
+#define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
+
+#define MXC_USB_MAX_PACKET (64)
+#define MXC_USB_NUM_EP (8)
+
+
+/*******************************************************************************/
+/* Instruction Cache Controller */
+
+#define MXC_BASE_ICC ((uint32_t)0x40080000UL)
+#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
+
+/* System Manager */
+
+#define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL)
+
+/*******************************************************************************/
+/* Clock Manager */
+
+#define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL)
+#define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
+
+
+/*******************************************************************************/
+/* Power Manager */
+
+#define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL)
+#define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
+
+/*******************************************************************************/
+/* I/O Manager */
+
+#define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL)
+#define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
+
+
+/*******************************************************************************/
+/* RTC: Timer/Alarms */
+
+#define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL)
+#define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
+
+#define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \
+ i == 1 ? RTC1_IRQn : \
+ i == 2 ? RTC2_IRQn : \
+ i == 3 ? RTC3_IRQn : 0)
+
+#define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL)
+#define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
+/*******************************************************************************/
+/* RTC: Power Sequencer */
+
+#define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL)
+#define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
+
+/*******************************************************************************/
+
+/* Trim Shadow Registers */
+
+#define MXC_BASE_TRIM ((uint32_t)0x400E0000UL)
+#define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
+
+
+/*******************************************************************************/
+/* Flash Memory Controller / Security */
+
+#define MXC_BASE_FLC ((uint32_t)0x400F0000UL)
+#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
+#define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL)
+#define MXC_FLC_PAGE_SIZE_SHIFT 11
+#define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
+#define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
+
+
+/*******************************************************************************/
+
+#define BITBAND(reg, bit) ((0xf0000000 & reg) + 0x2000000 + ((reg & 0x0fffffff) << 5) + (bit << 2))
+#define BITBAND_ClrBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 0;
+#define BITBAND_SetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit) = 1;
+#define BITBAND_GetBit(reg, bit) *(volatile uint32_t *)BITBAND(reg, bit)
+
+/*******************************************************************************/
+#endif /* _MAX32600_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mbed.bld Tue Jul 18 14:57:27 2017 +0000 @@ -0,0 +1,1 @@ +https://mbed.org/users/mbed_official/code/mbed/builds/794e51388b66 \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/mxc_config.h Tue Jul 18 14:57:27 2017 +0000 @@ -0,0 +1,45 @@ +/******************************************************************************* +* Copyright (C) 2014 Maxim Integrated Products, Inc., All Rights Reserved. +* +* Permission is hereby granted, free of charge, to any person obtaining a +* copy of this software and associated documentation files (the "Software"), +* to deal in the Software without restriction, including without limitation +* the rights to use, copy, modify, merge, publish, distribute, sublicense, +* and/or sell copies of the Software, and to permit persons to whom the +* Software is furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included +* in all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS +* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +* IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES +* OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +* OTHER DEALINGS IN THE SOFTWARE. +* +* Except as contained in this notice, the name of Maxim Integrated +* Products, Inc. shall not be used except as stated in the Maxim Integrated +* Products, Inc. Branding Policy. +* +* The mere transfer of this software does not imply any licenses +* of trade secrets, proprietary technology, copyrights, patents, +* trademarks, maskwork rights, or any other form of intellectual +* property whatsoever. Maxim Integrated Products, Inc. retains all +* ownership rights. +******************************************************************************* +*/ + +/* $Revision: 3166 $ $Date: 2014-09-09 14:11:31 -0500 (Tue, 09 Sep 2014) $ */ + +#ifndef _MXC_CONFIG_H +#define _MXC_CONFIG_H + +/* include 'device' file */ +#include "max32600.h" + +/* application specific defines */ + +#endif /* _CONFIG_H */ +